Semiconductor Devices

Abstract

To provide a semiconductor device to suppress increasing in an area of a clamp element that determines a read potential in a variable resistance nonvolatile memory including an OTP cell.SOLUTION: A clamp element 46 applies a fixed potential to a bit line BL during a read operation. A reference current source RCS generates a reference current Iref. An offset current source OSC1 is activated during a read operation for an OTP cell OTPC and generates an offset current Iof1 to be subtracted from a cell current Icel when activated. A sense amplifier SA detects a magnitude relationship between the read current Ird obtained by subtracting the offset current Iof1 from the cell current Icel and the reference current Iref during the read operation to the OTP cell OTPC.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a resistance change type memory element such as an MRAM (Magnetoresistive Random Access Memory). [Background technology]

[0002] For example, Non-Patent Document 1 shows an example of the configuration of a read circuit in an STT (Spin Transfer Torque)-MRAM. The read circuit includes a clamp element that applies a read potential to a cell resistor and a reference resistor, a pMOS cross-coupled sense amplifier, and a precharge element that precharges a differential pair node of the sense amplifier. After precharging, the sense amplifier amplifies the potential difference between the differential pair nodes discharged via the cell resistor and the reference resistor. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Yu-Der Chih et al., “13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference”, 2020 ISSCC , pp.222-224 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, MRAM, specifically STT-MRAM, has been attracting attention as an embedded memory in semiconductor devices such as MCUs (Micro Controller Units) and SoCs (System on a Chip). Compared to conventional MRAMs and flash memories, STT-MRAM offers advantages in terms of miniaturization, or in other words, scaling. MRAMs typically have memory cells including rewritable resistance-change memory elements, and store data depending on whether the memory element is in a low-resistance state or a high-resistance state.

[0005] On the other hand, OTP (One Time Programmable) cells are known as memory cells for security purposes. For example, when a large current sufficient to cause dielectric breakdown is passed through an MRAM memory element, the resistance value of the memory element can be irreversibly fixed to a value even lower than the value in the low resistance state. This property can be utilized to realize an OTP cell. Furthermore, during a read operation on an OTP cell, a read potential is applied to the OTP cell using a clamp element, and the cell current flowing through the OTP cell is detected. In this case, a cell current even larger than that in the low resistance state can flow. As a result, there is a risk that the circuit area of ​​the clamp element will increase.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes a bit line, first and second memory cells, a clamp element, a reference current source, a sense amplifier, and an offset current source. The first memory cell is connected to the bit line and includes a first variable resistance memory element. The second memory cell is connected to the bit line and includes a second memory element having the same electrical characteristics as the first memory element, and is used as an OTP cell. The clamp element applies a fixed potential to the bit line during a read operation. The reference current source generates a reference current. The sense amplifier applies a fixed potential to the first or second memory cell during a read operation, thereby detecting the magnitude of a cell current flowing through the bit line using the reference current. The offset current source is activated during a read operation for the second memory cell, and generates an offset current to be subtracted from the cell current when activated. Here, the sense amplifier detects the magnitude relationship between the reference current and the read current, resulting from subtracting the offset current from the cell current, during a read operation for the second memory cell. [Effects of the Invention]

[0008] By using the semiconductor device of one embodiment, it is possible to suppress an increase in the area of ​​a clamp element that determines a read potential in a variable resistance nonvolatile memory including an OTP cell. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a main part of a semiconductor device according to a first embodiment. [Figure 2A] FIG. 2A is a block diagram showing an example of the configuration of a main part of the nonvolatile memory in FIG. [Figure 2B] FIG. 2B is a circuit diagram showing an example of the configuration of the memory cell in FIG. 2A. [Figure 3] FIG. 3 is a schematic diagram showing an example of the configuration of the main part of the readout circuit in FIG. 2A. [Figure 4] FIG. 4 is a circuit diagram showing a detailed configuration example of the read circuit shown in FIG. [Figure 5] FIG. 5 is a diagram illustrating an example of the operation of the read circuit shown in FIG. [Figure 6A] FIG. 6A is a waveform diagram showing an example of a read operation on a memory cell using the read circuit shown in FIGS. [Figure 6B] FIG. 6B is a waveform diagram showing an example of a read operation on an OTP cell using the read circuit shown in FIGS. [Figure 7A] FIG. 7A is a diagram illustrating an example of a prerequisite problem in the semiconductor device according to the second embodiment. [Figure 7B] FIG. 7B is a diagram showing an example of a read current distribution of an OTP cell when the method of the second embodiment is applied to the method of the comparative example in the semiconductor device according to the third embodiment. [Figure 8A] FIG. 8A is a circuit diagram showing a detailed configuration example of the OTP cell shown in FIGS. 3 and 4 in the semiconductor device according to the second embodiment. [Figure 8B] FIG. 8B is a circuit diagram showing a detailed configuration example of a driver circuit when the OTP cell shown in FIG. 8A is used. [Figure 9] FIG. 9 is a diagram illustrating an example of operation when the configuration example shown in FIGS. 8A and 8B is used. [Figure 10] FIG. 10 is a schematic diagram showing a configuration example of a main part of the read circuit in FIG. 2A in a semiconductor device according to the fifth embodiment. [Figure 11] FIG. 11 is a schematic diagram showing a configuration example of the main part of a read circuit in a nonvolatile memory serving as a comparative example. [Figure 12] FIG. 12 is a diagram illustrating an example of the operation of the read circuit shown in FIG. [Figure 13] FIG. 13 is a diagram illustrating an example of operation of the read circuit shown in FIG. 11, which is different from that shown in FIG. [Figure 14A] FIG. 14A is a waveform diagram showing an example of operation when the OTP cell OTPC is operated in the normal MC mode in the semiconductor device according to the fourth embodiment. [Figure 14B]FIG. 14B is a diagram showing the number of select transistor elements that are turned on in each operation mode in the OTP cell in the semiconductor device according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0011] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0012] Furthermore, the circuit elements constituting each functional block of the embodiments are formed on a semiconductor substrate such as single-crystal silicon using integrated circuit technology such as known CMOS (complementary metal-oxide semiconductor transistor). In the embodiments, a MOSFET (metal oxide semiconductor field effect transistor), abbreviated as MOS transistor, is used as an example of a MISFET (metal insulator semiconductor field effect transistor), but this does not exclude non-oxide films as gate insulating films. In the embodiments, a p-channel MOSFET is referred to as a pMOS transistor MP, and an n-channel MOSFET is referred to as an nMOS transistor MN. Although the drawings do not specifically indicate the connection of the substrate potential of the MOS transistor, the connection method is not particularly limited as long as the MOS transistor can operate normally.

[0013] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0014] (Embodiment 1) <Outline of semiconductor device and non-volatile memory> Fig. 1 is a block diagram showing a configuration example of a main part of a semiconductor device according to embodiment 1. The semiconductor device 10 shown in Fig. 1 is configured by one semiconductor chip, and is, for example, an MCU or an SoC. The semiconductor device 10 is used, for example, for IoT (Internet of Things) applications.

[0015] 1 includes a processor 15, RAM 16, nonvolatile memory 17, timer 18, analog-to-digital converter (ADC) 19, digital-to-analog converter (DAC) 20, communication interface 21, various peripheral circuits 22, and a bus 23 connecting these to one another. The processor 15 is a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or the like. The RAM is a volatile memory such as a DRAM or SRAM.

[0016] The communication interface 21 may be, for example, an Ethernet (registered trademark) MAC interface. The nonvolatile memory 17 may be, for example, an STT-MRAM. The nonvolatile memory 17 may be used to store programs executed by the processor 15, or may be used as a work memory for the processor 15. Note that the nonvolatile memory 17 is not limited to an MRAM, and may be any memory including a resistance change type memory element.

[0017] Here, for example, rollback attacks are known that weaken security by rolling back the version of a communication protocol, etc. One countermeasure against such rollback attacks is to install a version counter for managing communication versions in the nonvolatile memory 17. The version counter needs to be realized by an OTP cell that allows one-time writing to prevent rewriting.

[0018] Fig. 2A is a block diagram showing an example of the configuration of the main part of the nonvolatile memory in Fig. 1. Fig. 2B is a circuit diagram showing an example of the configuration of a memory cell in Fig. 2A. Nonvolatile memory 17 shown in Fig. 2A includes a memory array 30, a word line driver 32, a plurality of, here k, read / write circuits 33[1] to 33[k], an address decoder 31, and a control circuit 34.

[0019] The memory array 30 includes a plurality of word lines WL[1] to WL[n], n in this example. The memory array 30 also includes a plurality of bit lines BL[1] to BL[m], m source lines SL[1] to SL[m], and a plurality of memory cells MC11 to MCnm, n×m in this example, corresponding to one read / write circuit, e.g., 33[1]. In this specification, the word lines WL[1] to WL[n] are collectively referred to as word lines WL. The bit lines BL[1] to BL[m] are collectively referred to as bit lines BL. The source lines SL[1] to SL[m] are collectively referred to as source lines SL. The memory cells MC11 to MCnm are collectively referred to as memory cells MC.

[0020] Here, m write source lines SL[1] to SL[m] are provided corresponding to m bit lines BL[1] to BL[m]. However, for higher density, two memory cells MC may share one source line, in which case the number of source lines provided is m / 2. Although not shown in the figure, in detail, m×k bit lines BL are provided corresponding to k read / write circuits 33[1] to 33[k], and n×m×k memory cells MC are provided.

[0021] A plurality of word lines WL[1] to WL[n] are arranged side by side in the row direction and extend in a column direction that intersects, for example, perpendicular to, the row direction. On the other hand, a plurality of bit lines BL[1] to BL[m] are arranged side by side in the column direction and extend in the row direction. A plurality of memory cells MC are arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL. For example, a memory cell MCnm is arranged at the intersection of a word line WL[n] and a bit line BL[m].

[0022] As shown in FIG. 2B, the memory cell MC includes a resistance-change memory element Rcel and a select transistor ST connected in series between a bit line BL and a source line SL. During a read operation, a ground potential Vss, which is a low-potential power supply potential, is applied to the source line SL. The memory element Rcel is connected to the bit line BL and stores different data depending on whether it is in a low-resistance state or a high-resistance state, using, for example, a magnetic tunnel junction (MTJ) as a component.

[0023] Specifically, an MTJ has a fixed layer and a free layer sandwiched between them by a tunnel barrier film. The magnetization direction of the free layer changes depending on the direction of the current flowing during a write operation. A state in which the magnetization directions of the fixed layer and the free layer are the same is called a P state, and a state in which the magnetization directions are opposite is called an AP state. The P state is a low-resistance state, and the AP state is a high-resistance state. The select transistor ST is, for example, an nMOS transistor, and is connected between the source line SL and the memory element Rcel. Furthermore, a control node, for example, the gate, of the select transistor ST is connected to a word line WL, and the on / off state of the select transistor ST is controlled by the word line WL.

[0024] When changing the memory element Rcel from the AP state, which is a high-resistance state, to the P state, which is a low-resistance state, with the select transistor ST in the ON state, a positive write potential, for example, +0.4V is applied to the bit line BL with the source line SL to which the ground potential Vss is applied as a reference, and a write current is passed from the bit line BL to the source line SL via the memory element Rcel. On the other hand, when changing the memory element Rcel from the P state to the AP state, with the select transistor ST in the ON state, a positive write potential, for example, +0.4V is applied to the source line SL with the bit line BL to which the ground potential Vss is applied as a reference, and a write current is passed from the source line SL to the bit line BL via the memory element Rcel.

[0025] During a read operation, the ground potential Vss is applied to the source line SL, and a read potential, such as +0.1 V, lower than that during a write operation is applied to the memory element Rcel via the bit line BL, and the magnitude of the cell current flowing through the memory element Rcel is determined. At this time, for example, a reference current having an intermediate value between the cell current value in the AP state and the cell current value in the P state is generated in advance, and the reference current is compared with the cell current flowing through the memory element Rcel.

[0026] Returning to FIG. 2A, the word line driver 32 selects one of the word lines WL[1] to WL[n] based on the word line selection signal XS from the address decoder 31, and applies a potential to the selected word line WL to turn on the selection transistor ST. Each of the read / write circuits 33[1] to 33[k], representatively 33[1], includes a column selector CSEL, a read circuit, and a write circuit. The read circuit includes a sense amplifier SA and an output buffer OBF. The write circuit includes an input buffer IBF and a write driver WTD.

[0027] During a read operation, the column selector CSEL selects one of the m bit lines BL based on the bit line selection signal YS from the address decoder 31. The column selector CSEL connects the selected bit line BL to the global bit line GBL. The sense amplifier SA detects the current flowing through the global bit line GBL, and therefore the magnitude of the cell current flowing through the selected memory cell MC, using the reference current described above. The output buffer OBF latches the detection signal from the sense amplifier SA and outputs the latched result to the outside as read data DO1.

[0028] On the other hand, during a write operation, the column selector CSEL selects one bit line BL and one source line SL from among the m bit lines BL and m source lines SL based on a selection signal YS from the address decoder 31. The column selector CSEL connects the selected one bit line BL and one source line SL to a global bit line GBL and a global source line GSL, respectively.

[0029] The input buffer IBF latches external write data DI1. The write driver WTD writes the P state, AP state, or the like into the selected memory cell MC via the global bit line GBL and global source line GSL based on the logic level of the data latched by the input buffer IBF. That is, the write driver WTD generates a write current or write potential corresponding to the P state or AP state and applies it to the global bit line GBL and global source line GSL.

[0030] The read / write circuits 33[2] to 33[k] have the same configuration as the read / write circuit 33[1] and perform the same operation. As a result, the read / write circuits 33[2] to 33[k] output data stored in selected memory cells MC on the same word line WL to the outside as read data DO2 to DOk. The read / write circuits 33[2] to 33[k] also write external write data DI2 to DIk to the selected memory cells MC.

[0031] The control circuit 34 controls various timings of the entire nonvolatile memory 17. As part of this, the control circuit 34 controls the timing of activating the sense amplifier SA and write driver WTD, and the latch timing in the output buffer OBF and input buffer IBF. In the specification, the read / write circuits 33[1] to 33[k] are collectively referred to as read / write circuits 33. The read data DO1 to DOk are collectively referred to as read data DO. The write data DI1 to DIk are collectively referred to as write data DI.

[0032] Here, as mentioned above, there are cases where it is required to mount OTP cells in the nonvolatile memory 17. Therefore, it is beneficial to allocate a predetermined portion of the memory cells MC to the OTP cells in the memory array 30. This makes it possible to mount OTP cells in the nonvolatile memory 17 while suppressing an increase in the circuit area, etc., compared to, for example, a case where a separate circuit area dedicated to the OTP cells is provided.

[0033] That is, when a write potential, such as +1.4V, which is much higher than the write potential for the P state, such as +0.4V, is applied to the OTP cell, the memory element undergoes dielectric breakdown, resulting in a state with an even lower resistance than the P state. In this specification, the state of an OTP cell in which such writing has occurred is called the BD (BreakDown) state. Unlike the P state / AP state, the BD state is an irreversible state.

[0034] <Readout circuit details> [Embodiment Method] Fig. 3 is a schematic diagram showing a configuration example of the main part of the read circuit in Fig. 2A. Fig. 3 shows a part of the memory array 30 in Fig. 2A, a part of the word line driver 32, a part of the read circuit in the read / write circuit 33, and a control circuit 34. In Fig. 3, the memory array 30 includes OTP cells OTPC in addition to memory cells MC.

[0035] As shown in FIG. 2B, the memory cell MC is connected to a bit line BL and a source line SL, and includes a resistance-change memory element Rcel and a select transistor ST. Although not shown, during a read operation, a ground potential Vss is applied to the source line SL. The select transistor ST in the memory cell MC forms a current path between the memory element Rcel and the bit line BL when the word line WL1 is activated. Similarly, the OTP cell OTPC is connected to the bit line BL and includes a resistance-change memory element having the same electrical characteristics as the memory element Rcel in the memory cell MC, and a select transistor ST. The select transistor ST in the OTP cell OTPC forms a current path between the memory element and the bit line BL when the word line WL2 is activated.

[0036] The word line driver 32 includes driver circuits DV1 and DV2. The driver circuit DV1 activates the word line WL1 by applying a drive potential to the word line WL1, thereby controlling the select transistor ST in the memory cell MC to be turned on. The driver circuit DV1 also deactivates the word line WL1 by applying a ground potential Vss or the like to the word line WL1, thereby controlling the select transistor ST in the memory cell MC to be turned off. Similarly, the driver circuit DV2 activates / deactivates the word line WL2, thereby controlling the on / off of the select transistor ST in the OTP cell OTPC.

[0037] The read / write circuit 33 includes a column selector CSEL, a clamp element 46, a sense amplifier SA, a reference current source RCS, and an offset current source OCS1. When the column selector CSEL is selected by the bit line selection signal YS described in FIG. 2A, it connects the bit line BL to a node Nq via the clamp element 46.

[0038] The clamp element 46 is connected between the node Nq and the bit line BL, specifically the global bit line GBL, assuming that the column selector CSEL is in a connected state. During a read operation, the clamp element 46 applies a fixed read potential to the bit line BL via the column selector CSEL. That is, when the potential Vq of the node Nq and the bit line potential Vbl satisfy Vq>Vbl, the clamp element 46 clamps the bit line potential Vbl to the read potential regardless of the potential Vq of the node Nq.

[0039] The reference current source RCS generates a reference current Iref and supplies the reference current Iref to the node Nqb. During a read operation, the sense amplifier SA detects the magnitude of the cell current Icel flowing through the bit line BL by applying a read potential to the memory cell MC or the OTP cell OTPC, using the reference current Iref.

[0040] The offset current source OCS1 is connected between the high-side power supply potential Vdd and the global bit line GBL, and is also connected between the high-side power supply potential Vdd and the bit line GBL, assuming that the column selector CSEL is in a connected state. The offset current source OCS1 is activated by an enable signal EN1 during a read operation on the OTP cell OTPC, and when activated, generates an offset current Iof1 to be subtracted from the cell current Icel of the OTP cell OTPC based on a current value setting signal Iset. Accordingly, during a read operation on the OTP cell OTPC, the sense amplifier SA detects the magnitude relationship between the read current Ird, which is the cell current Icel minus the offset current Iof1, and the reference current Iref.

[0041] The control circuit 34 generates a sense amplifier enable signal SAE for controlling activation / deactivation of the sense amplifier SA and outputs it to the sense amplifier SA. The control circuit 34 also generates an enable signal EN1 for controlling activation / deactivation of the offset current source OCS1 and outputs it to the offset current source OCS1. The control circuit 34 also generates a current value setting signal Iset for determining the current value of the offset current Iof1 and outputs it to the offset current source OCS1.

[0042] The offset current source OCS1 is deactivated during a read operation on the memory cell MC. In this case, the read current Ird is equal to the cell current Icel of the memory cell MC. During a read operation on the memory cell MC, the sense amplifier SA detects the magnitude relationship between the read current Ird, which is equal to the cell current Icel, and the reference current Iref.

[0043] Fig. 4 is a circuit diagram showing a detailed configuration example of the read circuit shown in Fig. 3. In Fig. 4, the memory cell MC includes a memory element Rcel and a select transistor STc for the memory cell MC. On the other hand, the OTP cell OTPC includes a memory element Rotp having the same electrical characteristics as the memory element Rcel and a select transistor STo for the OTP cell OTPC.

[0044] A write operation to the OTP cell OTPC requires a larger write current than a write operation to the memory cell MC. Therefore, the select transistor STo may be configured by connecting multiple elements identical to the select transistor STc in parallel. Although not shown, a column selector CSEL is connected between the clamp circuit 46 and the memory cell MC and OTP cell OTPC.

[0045] The reference current source RCS is composed of, for example, a reference memory cell MCr. The reference memory cell MCr includes a reference resistor Rref and a reference select transistor STr. The reference resistor Rref has a resistance value intermediate between the resistance values ​​of the P state and the AP state. The reference select transistor STr is controlled by a reference word line WLr. During a read operation, the reference word line WLr is activated in addition to the word line WL. As a result, a reference current Iref corresponding to the resistance value of the reference resistor Rref flows through the reference bit line BLr.

[0046] The read / write circuit 33 includes a sense amplifier SA, a precharge circuit 45, a clamp element 46, and an offset current source OCS1. The clamp element 46 includes two nMOS transistors MNc1 and MNc2 that function as source followers. During a read operation, the clamp element 46 applies a read potential to the memory element Rcel or the memory element Rotp via the bit line BL, and applies a read potential to the reference resistor Rref via the reference bit line BLr. At this time, the read potential, which is a fixed potential, is determined by a clamp potential Vclp applied to the gates of the nMOS transistors MNc1 and MNc2.

[0047] The offset current source OCS1 includes a p-channel current mirror pair consisting of two pMOS transistors MPm1 and MPm2, and an nMOS transistor MNm1. The offset current source OCS1 is connected between the power supply potential Vdd and the bit line BL. When an enable signal EN1 is activated in the offset current source OCS1, the nMOS transistor MNm1 turns on, and an offset current Iof1 based on a current value setting signal Iset input to the current mirror pair flows through the bit line BL. In this example, a current mirror circuit is configured with the pMOS transistor MPm1 as the mirror destination and the pMOS transistor MPm2 as the mirror source.

[0048] The drains of the nMOS transistors MNc1 and MNc2 that make up the clamp element 46 are connected to nodes Nq and Nqb, respectively. A reference current Iref, which is generated by applying a read potential to the reference resistor Rref, flows through the node Nqb. On the other hand, a read current Ird flows through the node Nq.

[0049] The read current Ird is equal to the cell current Icel during a read operation on the memory cell MC, i.e., when the offset current source OCS1 is inactive. On the other hand, the read current Ird is equal to the current obtained by subtracting the offset current Iof1 from the cell current Icel during a read operation on the OTP cell OTPC, i.e., when the offset current source OCS1 is active. Specifically, the clamp element 46 is connected to the bit line BL and the reference bit line BLr via the column selector CSEL, as shown in FIG. 3 .

[0050] The precharge circuit 45 includes two pMOS transistors MPp1 and MPp2, whose sources are applied with the power supply potential Vdd. The precharge circuit 45 precharges the nodes Nq and Nqb to the power supply potential Vdd. Specifically, the pMOS transistors MPp1 and MPp2 are turned on while the inverted precharge signal / PC is at low level, and precharge the nodes Nqb and Nq connected to their drains, respectively. The inverted precharge signal / PC is generated by the control circuit 34 shown in FIG. 2.

[0051] The sense amplifier SA includes a p-channel transistor pair consisting of two pMOS transistors MPa1 and MPa2, and a pMOS transistor MPa3. The sense amplifier SA amplifies the potential difference between the potential Vq of the node Nq and the potential Vqb of the node Nqb, which occurs after the precharge by the precharge circuit 45 and the discharge period by the read current Ird and the reference current Iref.

[0052] Specifically, the gates of pMOS transistors MPa1 and MPa2 are connected to nodes Nqb and Nq, respectively. The pMOS transistors MPa1 and MPa2 perform differential amplification through a cross-coupled connection in which the gate of one is connected to the drain of the other. The pMOS transistor MPa3 applies the power supply potential Vdd to the sources of the pMOS transistors MPa1 and MPa2 while the sense amplifier enable signal SAE is at a high level, i.e., while the inverted sense amplifier enable signal / SAE is at a low level. This causes the pMOS transistor MPa3 to activate the sense amplifier SA.

[0053] 4, the reference current source RCS is configured by an nMOS transistor MNc2 arranged in the read circuit 33 and a reference memory cell MCr arranged in the memory array 30. However, without being limited to this, the reference current source RCS may also be configured by arranging the reference memory cell MCr in the read circuit 33. Furthermore, the reference current source RCS may also be configured using only nMOS transistors without using the reference resistor Rref.

[0054] 4, the offset current source OCS1 is composed of three transistors: pMOS transistors MPm1 and MPm2, and an nMOS transistor MNm1. However, the offset current source OCS1 may be composed, for example, by arranging the pMOS transistor MPm2, which is the mirror source, in the control circuit 34, and arranging the pMOS transistor MPm2 and nMOS transistor MNm1, which are the mirror destinations, in each of the k read / write circuits 33. This effectively reduces the number of elements in the offset current source OCS1 to two.

[0055] [Comparative Example Method and Its Problems] 11 is a schematic diagram showing an example of the configuration of the main parts of a conventional read circuit in a nonvolatile memory serving as a comparative example. The conventional configuration example shown in FIG. 11 differs from the configuration example of the embodiment shown in FIG. 3 in the following two points. The first difference is that an offset current source OCS1 is not provided. The second difference is that the control circuit 34x does not output a current value setting signal Iset and an enable signal EN1 to the offset current source OCS1.

[0056] 12 is a diagram illustrating an example of the operation of the conventional read circuit shown in FIG. 11. FIG. 12 shows an example of the distribution of the read current Ird detected by the sense amplifier SA. In FIG. 12, during a read operation on a memory cell MC in the AP state, which is a high-resistance state, a distribution 51 of the read current Ird is located in a range representing a small current value. During a read operation on a memory cell MC in the P state, which is a low-resistance state, a distribution 52 of the read current Ird is located in a range representing a larger current value than the distribution 51. On the other hand, during a read operation on an OTP cell OTPC in the BD state, a distribution 53 of the read current Ird is located in a range representing a larger current value than the distribution 52.

[0057] Therefore, during a read operation on a memory cell MC in the AP state or the P state, the sense amplifier SA distinguishes between the AP state and the P state using a reference current Iref set to a current value approximately midway between the current value in the AP state and the current value in the P state. On the other hand, during a read operation on an OTP cell OTPC in the AP state / P state or the BD state, the sense amplifier SA distinguishes between the BD state and the BD state using, for example, a reference current Iref set to a current value approximately midway between the current value in the P state and the current value in the BD state. Therefore, during a read operation on the OTP cell OTPC, the reference current source 55 generates a reference current Iref increased by +α in accordance with the current value setting signal Iset.

[0058] However, when the method shown in FIG. 11 is used, for example, the following three problems may occur. First, the area of ​​the clamp element 46 may increase. Second, the timing control when the control circuit 34x outputs the sense amplifier enable signal SAE or the precharge signal PC in FIG. 4 may become complicated. Third, the reference current Iref needs to be increased during a read operation on the OTP cell OTPC, which may increase the power consumption of the sense amplifier SA.

[0059] Regarding the first problem, if a clamp element 46 having a transistor size sufficient to pass the cell current Icel in the P state is provided, the cell current Icel in the BD state may become smaller than the original value, and the gap between distributions 52 and 53 shown in Fig. 12 may narrow. As a result, erroneous detection may occur in the sense amplifier SA.

[0060] More specifically, the cell current Icel is given by equation (1) based on the characteristics of the nMOS transistor MNc1 in the clamp element 46. In equation (1), β is a constant proportional to the value of W / L, which represents the transistor size, where W is the gate width of the nMOS transistor MNc1 and L is the gate length. Furthermore, Vclp is the clamp potential, Vbl is the bit line potential, and Vth is the threshold voltage of the nMOS transistor MNc1. Icel=β×(Vclp-Vbl-Vth) …(1)

[0061] Furthermore, the bit line potential Vbl is "R × Icel," where R is the combined resistance of the resistance of the memory element and the resistance of the select transistor. As a result, equation (1) is transformed into equation (2). From equation (2), it can be seen that the cell current Icel is given by "(Vclp - Vth) / R" in an ideal state where β is infinite. On the other hand, when β is small, the cell current Icel becomes "1 >> β × R" in the region where R is small, and approaches "β × (Vclp - Vth)." This means that when the transistor size of the clamp element 46 is too small, for example, in FIG. 12, distribution 53 when the resistance is particularly low approaches distribution 52. Icel=β×(Vclp-Vth) / (1+β×R) …(2)

[0062] Regarding the second problem, for example, as in the case of Figure 4, consider a method in which the nodes Nq and Nqb are precharged to the power supply potential Vdd, and then the nodes Nq and Nqb are discharged for a discharge period using the cell current Icel and the reference current Iref, and the potential difference "|Vq-Vqb|" at the end of the discharge period is amplified by the sense amplifier SA. In this case, in the configuration example shown in Figure 11, the range of the discharge current differs between the read operation on the memory cell MC and the read operation on the OTP cell OTPC, so it is necessary to change at least the length of the discharge period accordingly.

[0063] That is, in order for the sense amplifier SA to perform detection correctly, it is necessary to activate the sense amplifier SA before the potentials Vq and Vqb at the nodes Nq and Nqb are discharged to a lower limit, e.g., the read potential. However, the time required for discharging to this lower limit varies depending on the magnitude of the discharge current. To solve the first, second, and third problems described here, it is useful to use the configuration example shown in Figure 3, as described below.

[0064] <Read operation details> Fig. 5 is a diagram illustrating an example of the operation of the read circuit shown in Fig. 3. Fig. 5 shows an example of the distribution of the read current Ird detected by the sense amplifier SA, together with the distribution in the comparative example shown in Fig. 12. As described above, during a read operation on the OTP cell OTPC, the read current Ird obtained by subtracting the offset current Iof1 from the cell current Icel is input to the sense amplifier SA.

[0065] As a result, as shown in Fig. 5, the distribution 52 of the read current Ird in the P state in the comparative example and the distribution 53 of the read current Ird in the BD state are both shifted to a smaller value by the offset current Iof1. As can be seen from Fig. 5, this allows the sense amplifier SA to detect the read current Ird using the same reference current Iref during a read operation on the memory cell MC and during a read operation on the OTP cell OTPC.

[0066] That is, during a read operation on the memory cell MC, the sense amplifier SA performs the same operation as in the comparative example, and uses a certain reference current Iref to distinguish between distribution 51 and distribution 52. On the other hand, during a read operation on the OTP cell OTPC, unlike the comparative example, the sense amplifier SA uses a reference current Iref of the same value as during a read operation on the memory cell MC to distinguish between distribution 52 or distribution 51 and distribution 53.

[0067] In this way, by reducing the read current Ird by the offset current Iof1 during a read operation on the OTP cell OTPC, a first effect is achieved, which is to suppress an increase in the area of ​​the clamp element 46. That is, with regard to the first problem described above, it is only necessary to provide a clamp element 46 having a transistor size sufficient to flow, for example, the cell current Icel in the P state, instead of the cell current Icel in the BD state.

[0068] As a second effect, it is possible to facilitate timing control by the control circuit 34. That is, with regard to the second problem described above, the range of the discharge current during a read operation on the memory cell MC and during a read operation on the OTP cell OTPC can be made equivalent, so the length of the discharge period can also be the same. Furthermore, as a third effect, unlike the comparative example, there is no need to increase the reference current Iref during a read operation on the OTP cell OTPC, so an increase in power consumption in the sense amplifier SA can be suppressed.

[0069] Fig. 6A is a waveform diagram showing an example of a read operation on a memory cell using the read circuit shown in Fig. 3 and Fig. 4. Fig. 6B is a waveform diagram showing an example of a read operation on an OTP cell using the read circuit shown in Fig. 3 and Fig. 4. In Fig. 6A and Fig. 6B, the period from time t0 to time t1 is a precharge period Tpc, the period from time t1 to time t2 is a discharge period Tdc, and the period from time t2 to time t3 is an amplification period Tsae or a detection period by the sense amplifier SA.

[0070] 6A, first, at time t0, word line WL1 for memory cell MC is activated. Then, during a precharge period Tpc, the precharge circuit 45 is activated by the low level of the inverted precharge signal / PC, more specifically, by the AND logic of the word line selection signal XS and the precharge signal PC. As a result, during the precharge period Tpc, the potentials Vq and Vqb of nodes Nq and Nqb change from the ground potential Vss to the power supply potential Vdd.

[0071] Next, at time t1, the inverted precharge signal / PC transitions from low to high, deactivating the precharge circuit 45. During the discharge period Tdc, the potentials Vq and Vqb at the nodes Nq and Nqb gradually decrease due to discharge caused by the cell current Icel and the reference current Iref. After that, at time t2, when the predetermined discharge period Tdc ends, the sense amplifier enable signal SAE transitions from low to high.

[0072] As a result, the sense amplifier SA is activated and amplifies the potential difference between the potentials Vq and Vqb. Then, at time t3 when the amplification period Tsae by the sense amplifier SA ends, the sense amplifier enable signal SAE transitions from high to low. Also at time t3, the word line WL1 is deactivated, and the inverted precharge signal / PC transitions from high to low. In FIG. 6A, the word line WL2 for the OTP cell OTPC is in an inactive state, and the enable signal EN1 for the offset current source OCS1 is also at a disable level, here a low level.

[0073] Figure 6B shows a waveform diagram similar to that of Figure 6A. The difference from Figure 6A is that the word line WL2 for the OTP cell OTPC is activated instead of the word line WL1 for the memory cell MC, and the enable signal EN1 for the offset current source OCS1 is set to an enable level, here a high level. That is, the control circuit 34 activates the offset current source OCS1 using the enable signal EN1 from time t0, when the word line WL2 is activated, to time t3, when the sense amplifier SA is deactivated.

[0074] 3, the timing control of the control circuit 34 can be simplified as shown in FIGS. 6A and 6B. That is, the second effect described above can be obtained. Specifically, for example, the sense amplifier SA can be activated at the same time t2 during a read operation on the memory cell MC shown in FIG. 6A and during a read operation on the OTP cell OTPC shown in FIG. 6B.

[0075] <Major Effects of the First Embodiment> As described above, in the method of the first embodiment, by providing an offset current source OCS1 for subtracting from the cell current Icel of the OTP cell OTPC, it is possible to suppress an increase in the area of ​​the clamp element 46 that determines the read potential. Furthermore, by mixing normal memory cells MC and OTP cells OTPC in the memory array 30, read operations can be performed on both cells using a sense amplifier SA with a common reference current Iref and activation timing. As a result, a nonvolatile memory 17 that is efficient in terms of circuit area, etc. can be realized.

[0076] (Embodiment 2) <Underlying issues> 7A is a diagram illustrating an example of a problem that is a premise of the semiconductor device according to the second embodiment. As described in the first embodiment, for example, the select transistor STo in the OTP cell OTPC shown in FIG. 4 can be configured by connecting multiple elements identical to the select transistor STc in the memory cell MC in parallel so that a write current sufficient for writing to the BD state can flow. When a read operation is performed using such a select transistor STo, the read current distribution can be, for example, as shown in FIG. 7A.

[0077] 7A first shows the current distribution when a read operation is performed on the OTP cell OTPC using the comparative example method shown in FIG. 11, and shows the same current distribution as in FIG. 12. However, when the parallel-configured select transistor STo described above is used, the resistance value of the OTP cell OTPC during the read operation decreases, so the current distribution shifts to a larger value compared to the case of FIG. 12. That is, distribution 52 in the P state shifts to distribution 52a, and distribution 53 in the BD state shifts to distribution 53a.

[0078] As a result, when a read operation is performed on the OTP cell OTPC using the method of the first embodiment shown in Fig. 3, it is necessary to increase the offset current Iof1 by the amount of the shift in the distribution, as shown in Fig. 7A. As a specific example, it is assumed that the value of the offset current is determined so that the maximum current value of the distribution 51 in the AP state in the comparative example matches the maximum current value of the distribution 52 in the P state in the first embodiment.

[0079] In this case, the offset current source OCS1 needs to add a correction current ΔI1 corresponding to the shift from distribution 52 to distribution 52a to the offset current Iof1, which is determined on the assumption that the select transistor STo is composed of a single element. Furthermore, taking into account the shift from distribution 53 to distribution 53a, the offset current source OCS1 needs to add a correction current ΔI2, which is larger than the correction current ΔI1 and corresponds to the shift from distribution 53 to distribution 53a, to the offset current Iof1.

[0080] Therefore, the offset current source OCS1 must be configured to pass an offset current that is larger than the original offset current Iof1 by the correction currents ΔI1 to ΔI2. As a result, the offset current source OCS1 may require an increased area and consume more power. Therefore, it is advantageous to use the configuration examples shown in FIGS. 8A and 8B as follows.

[0081] <Details of the selection transistor and driver circuit> 8A is a circuit diagram showing a detailed configuration example of the OTP cell shown in FIGS. 3 and 4 in the semiconductor device according to the second embodiment. The select transistor STo in the OTP cell OTPC shown in FIG. 8A is composed of j transistor elements connected in parallel, specifically j nMOS transistors MNs[1] to MNs[j], where j is an integer greater than 1. Although not shown, the select transistor STc in the memory cell MC is composed of i transistor elements, for example, one transistor element, out of the j transistor elements, where i is an integer less than j.

[0082] Here, the word line WL2 for the OTP cell OTPC is composed of two split word lines WL21 and WL22 that are each activated individually. The on / off of i nMOS transistors, for example, one nMOS transistor MNs[1], is controlled by the split word line WL21, and the on / off of the remaining ji nMOS transistors, for example, j-1 nMOS transistors MNs[2] to MNs[j], is controlled by the split word line WL22.

[0083] Fig. 8B is a circuit diagram showing a detailed configuration example of a driver circuit when the OTP cell shown in Fig. 8A is used. Fig. 8B shows details of the driver circuit DV2 for the OTP cell OTPC in Fig. 3. The driver circuit DV2 shown in Fig. 8B includes inverter circuits IV1 to IV3 and a NAND operation circuit ND1.

[0084] The two inverter circuits IV1 and IV2 are cascade-connected and drive the divided word line WL21 in response to a word line selection signal XS from the control circuit 34 shown in FIG. 2A. The NAND operation circuit ND1 performs a NAND operation on the word line selection signal XS and a write enable signal BDW-EN for the BD state. The inverter circuit IV3 drives the divided word line WL22 in response to the operation result of the NAND operation circuit ND1. The write enable signal BDW-EN is generated by the control circuit 34. The inverter circuit IV3 may have twice the driving capability of the inverter circuit IV2.

[0085] 9 is a diagram illustrating an example of operation when the configuration examples shown in FIGS. 8A and 8B are used. FIG. 9 shows the number of select transistor elements that are turned on during read and write operations. In FIG. 9, during read and write operations on a memory cell MC, the number of select transistor elements that are turned on is i, where i is an integer greater than or equal to 1 and less than j.

[0086] Also, during a read operation on the OTP cell OTPC, the number of elements of the select transistor STo that are turned on is i. That is, in FIG. 8B, the write enable signal BDW-EN is at a low level, so only one divided word line WL21 of the two divided word lines WL21 and WL22 is activated. On the other hand, during a write operation on the OTP cell OTPC, the number of elements of the select transistor STo that are turned on is j, which is an integer greater than i. That is, in FIG. 8B, the write enable signal BDW-EN is at a high level, so both of the two divided word lines WL21 and WL22 are activated.

[0087] 8A shows an example in which the select transistor STc in the memory cell MC is configured with one transistor element, and the select transistor STo in the OTP cell OTPC is configured with j (j>1) transistor elements. However, in terms of layout design, the select transistor STc may be configured with i transistor elements by dividing one transistor element into multiple elements, where i is an integer greater than or equal to 1. In this case, the select transistor STo may be configured with j transistor elements, where j is an integer greater than i.

[0088] Furthermore, the word line WL2 for the OTP cell OTPC may be configured with a plurality of split word lines that are each individually activated. In this case, the on / off of any one of the j transistor elements is controlled by any one of the split word lines, and the on / off of any other one of the j transistor elements is controlled by any other one of the split word lines. In FIG. 9, the number of transistor elements that are controlled to be on during a write operation to the BD state for the OTP cell OTPC should be greater than the number of transistor elements that are controlled to be on during a read operation for the OTP cell OTPC.

[0089] <Major Effects of the Second Embodiment> As described above, by using the method of the second embodiment based on the first embodiment, it is possible to somewhat alleviate the problems of the first embodiment while maintaining the various effects described in the first embodiment. That is, by configuring the select transistor STo in the OTP cell OTPC, which is composed of multiple transistor elements, so that the number of transistor elements controlled to be turned on can be changed, the need to correct the offset current is eliminated. Specifically, since the number of select transistor elements controlled to be turned on during a read operation on the OTP cell OTPC can be the same as during a read operation on the memory cell MC, the distribution shift shown in FIG. 7A does not occur. Therefore, it is not necessary to add the correction currents ΔI1 and ΔI2. As a result, it is possible to reduce the area and power consumption of the offset current source OCS1.

[0090] (Embodiment 3) In the second embodiment, an example has been described in which the method of the second embodiment shown in Figures 8A, 8B, etc. is applied to the method of the first embodiment shown in Figure 3, but it is also possible to apply the method of the second embodiment to the method of the comparative example shown in Figure 11. This provides the same effects as those described in the first embodiment, albeit to a small extent.

[0091] 7B is a diagram showing an example of a read current distribution of an OTP cell when the method of the second embodiment is applied to the method of the comparative example in the semiconductor device according to the third embodiment. First, the upper part of FIG. 7B shows a read current distribution when a read operation is performed on the OTP cell OTPC using the method of the comparative example shown in FIG. 11. As described in the second embodiment, when the parallel-configured select transistor STo is fully activated, the resistance value of the OTP cell OTPC during the read operation decreases, and therefore the current distribution shifts to a larger value compared to the case of FIG. 12.

[0092] That is, distribution 52 in the P state shown in Fig. 12 shifts to be larger by ΔI1 as shown in distribution 52a in Fig. 7B, and distribution 53 in the BD state shown in Fig. 12 shifts to be larger by ΔI2 as shown in distribution 53a in Fig. 7B. Therefore, the reference current source 55 in the comparative example shown in Fig. 11 not only had to increase the reference current Iref by +α but also had to increase it by the correction current ΔI1 during the read operation on the OTP cell OTPC.

[0093] On the other hand, when the method of the second embodiment is applied to the method of the comparative example, as shown in the lower part of Fig. 7B, it is possible to obtain slight effects similar to those described in the first embodiment. That is, in the OTP cell OTPC shown in Fig. 11, the select transistor STo is configured with a plurality of transistor elements, and further, the number of transistor elements controlled to be turned on is configured to be changeable.

[0094] As a result, distribution 52a in the P state shifts smaller by ΔI1, as shown in distribution 52 in FIG. 7B, and distribution 53a in the BD state shifts smaller by ΔI2, as shown in distribution 53 in FIG. 7B. As a result, it is possible to slightly suppress an increase in the area of ​​clamp element 46 that determines the read potential. Also, in the offset adjustment of reference current Iref in reference current source 55, i.e., in the adjustment of "+α+ΔI1", the correction current ΔI1 is not required. This makes it possible to slightly suppress an increase in power consumption in sense amplifier SA during a read operation for OTP cell OTPC.

[0095] (Fourth embodiment) In the above-described first to third embodiments, a read operation for determining whether or not the memory element Rotp in the OTP cell OTPC shown in FIG. 8A has experienced a dielectric breakdown has been described. In this specification, this read operation mode is referred to as the OTP mode. On the other hand, it is also possible to write the P state or AP state to the memory element Rotp in the OTP cell OTPC and perform a read operation as a normal memory cell MC. In this specification, this read operation mode is referred to as the normal MC mode.

[0096] The semiconductor device according to the fourth embodiment can be set to either an OTP mode in which the OTP cell OTPC is used as an OTP cell, or a normal MC mode in which the OTP cell OTPC is used as a normal memory cell MC. Specifically, for example, which OTP cell OTPC among the multiple OTP cells OTPC is to operate in the normal MC mode is set in advance in the control circuit 34 shown in FIG. 2A. The control circuit 34 controls each unit according to this setting, and the semiconductor device changes the operation content for the OTP cell OTPC as described below.

[0097] 14A is a waveform diagram showing an example of operation when the OTP cell OTPC is operated in the normal MC mode in the semiconductor device according to the fourth embodiment. In FIG. 14A, unlike the case of FIG. 6B, the enable signal EN1 is not activated while the divided word line WL21 is activated. As a result, an operation similar to the read operation on the memory cell MC shown in FIG. 6A is performed in the OTP cell OTPC.

[0098] 14B is a diagram showing the number of select transistor elements that are turned on in each operation mode in an OTP cell in a semiconductor device according to the fourth embodiment. When writing the P state or AP state to a memory element Rotp in an OTP cell OTPC, i.e., when performing a write operation in normal MC mode, the number of select transistors STo that are turned on is i to prevent dielectric breakdown due to application of an overcurrent. Here, i is the same value as the number of elements that constitute the select transistor STc in a normal memory cell MC and is an integer equal to or greater than 1.

[0099] Also, when the OTP cell OTPC is read in the normal MC mode, the number of elements of the select transistor STo that are turned on is i. In this way, when set to the normal MC mode, the number of transistor elements in the OTP cell OTPC that are controlled to be on during a write operation and a read operation to the OTP cell OTPC is the same as the number of transistor elements in the memory cell MC that are controlled to be on during a write operation and a read operation to the normal memory cell MC.

[0100] <Major Effects of the Fourth Embodiment> As shown in FIGS. 14A and 14B, operating the OTP cells OTPC in the normal MC mode provides two added benefits. First, in applications where it is not necessary to use all of the OTP cells OTPC provided in the memory array 30 for OTP purposes, the unnecessary OTP cells OTPC can be allocated to normal memory cells MC. As a result, the normal memory cell area can be increased slightly. Second, before writing to the BD state, read and write operations can be performed on the OTP cells OTPC in the same way as on normal memory cells MC. As a result, the OTP cells OTPC can be used as backup memory for temporarily storing data to be written to the OTP cells OTPC, such as security data.

[0101] (Embodiment 5) <Underlying issues> Fig. 13 is a diagram illustrating an example of operation of the read circuit shown in Fig. 11, which is different from that shown in Fig. 12. Similar to Fig. 12, Fig. 13 shows distributions 51, 52, and 53 of read current Ird when the configuration example of Fig. 11 is used. For example, when testing nonvolatile memory 17 with a test device, it may be desired to measure the distribution of read current Ird, and therefore the cell current Icel and resistance value.

[0102] In this case, for example, using the configuration example shown in Fig. 11, a method can be considered in which the current value of reference current source 55 is variably set within the range of "Iref-ΔIref1" to "Iref+ΔIref2" using current value setting signal Iset, as shown in Fig. 13. However, if the current value of reference current source 55 is variably set in this way, as described in the second problem in Fig. 11, the appropriate discharge period differs for each current value of reference current source 55, which may complicate timing control. Therefore, it is advantageous to use the configuration example shown in Fig. 10.

[0103] <Readout circuit details> 10 is a schematic diagram showing a configuration example of the main part of the read circuit in FIG. 2A in a semiconductor device according to embodiment 5. The configuration example shown in FIG. 10 differs from the configuration example shown in FIG. 3 in the following two points. The first difference is that two offset current sources OCS1v and OCS2v are provided. The second difference is that, in conjunction with the provision of two offset current sources OCS1v and OCS2v, a control circuit 34a different from that in FIG. 3 is provided.

[0104] The offset current source OCS1v is connected between the high-side power supply potential Vdd and the bit line BL, as in the case of FIG. 3. However, unlike the case of FIG. 3, the offset current source OCS1v is a variable current source. The offset current source OCS1v is activated by an enable signal EN1 during a test read operation on the OTP cell OTPC, and when activated, generates an offset current Iof1 to be subtracted from the cell current Icel. The offset current source OCS1v also determines the value of the offset current Iof1 based on a current value setting signal Iset1.

[0105] The offset current source OCS1v is also used when measuring the distribution of the read current Ird in normal memory cells MC, not just OTP cells OTPC. That is, the offset current source OCS1v is activated by the enable signal EN1 even during a test read operation on normal memory cells MC, and when activated, generates an offset current Iof1 to be subtracted from the cell current Icel. The offset current source OCS1v determines the value of the offset current Iof1 based on the current value setting signal Iset1.

[0106] On the other hand, the offset current source OCS2v is connected between the ground potential Vss, which is the low-potential power supply potential, and the bit line BL, and serves as a variable current source. The offset current source OCS2v is activated by an enable signal EN2 during a test read operation on the OTP cell OTPC or a normal memory cell MC, and when activated, generates an offset current Iof2 to be added to the cell current Icel. The offset current source OCS2v determines the value of the offset current Iof2 based on a current value setting signal Iset2.

[0107] The control circuit 34a activates one of the two offset current sources OCS1v, OCS2v by enable signals EN1, EN2 during a test read operation on the OTP cells OTPC or normal memory cells MC. The control circuit 34a also variably controls the value of the offset current Iof1 or Iof2 by current value setting signals Iset1, Iset2.

[0108] With this configuration, during a test read operation on an OTP cell OTPC or a normal memory cell MC, the sense amplifier SA detects the magnitude relationship between the read current Ird, obtained by subtracting the offset current Iof1 from the cell current Icel, and the reference current Iref. Alternatively, the sense amplifier SA detects the magnitude relationship between the read current Ird, obtained by adding the offset current Iof2 to the cell current Icel, and the reference current Iref.

[0109] 10, it is possible to measure the distribution of the read current Ird, and therefore the cell current Icel and resistance value, without changing the value of the reference current Iref. As a result, the problem described in FIG. 13 does not occur, and timing control, and therefore testing, can be simplified. Specifically, the control circuit 34a activates the sense amplifier SA at the same time point during a test read operation on the OTP cell OTPC or the normal memory cell MC, regardless of the values ​​of the offset currents Iof1 and Iof2.

[0110] In detail, the offset current source OCS2v may include a current mirror circuit made up of two nMOS transistors, similar to the offset current source OCS1 shown in Fig. 4. Also, the variable current source may include, for example, a pMOS transistor MPm1 in Fig. 4, n This can be realized by configuring a plurality of elements with different transistor sizes in units and selectively activating the plurality of elements connected in parallel. In other words, the variable current source can be realized by configuring it so that the current mirror ratio can be adjusted sequentially.

[0111] 10, the offset current source OCS2v is connected between the ground potential Vss and the bit line BL. However, because a read potential of, for example, 0.1 V is applied to the bit line BL, it may not be possible to ensure a sufficient source-drain voltage for the nMOS transistor that constitutes the offset current source OCS2v. In this case, the offset current source OCS2v may be connected between the ground potential Vss and the node Nq.

[0112] <Major Effects of the Fifth Embodiment> As described above, the method of embodiment 5 also provides the same effects as those described in embodiments 1, 2, and 4. Furthermore, by providing two variable offset current sources OCS1v and OCS2v, it becomes possible to realize easier testing, etc.

[0113] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0114] 10 Semiconductor devices 15 processors 17 Non-volatile memory 23 Bus 34 Control circuit BL bit line EN1, EN2 enable signals Icel Cell current Iof1, Iof2 offset current Ird Read current Iref Reference Current MC memory cell MN nMOS transistor MP pMOS transistor OCS1, OCS2 offset current sources OTPC OTP Cell RCS reference current source Rcel,Rotp storage element SA Sense Amplifier SAE Sense amplifier enable signal ST Select Transistor Vdd power supply potential Vss Ground potential WL Word Line

Claims

1. A bit line; a first memory cell connected to the bit line and including a first variable resistance memory element; a second memory cell connected to the bit line, including a second memory element having the same electrical characteristics as the first memory element, and used as an OTP (One Time Programmable) cell; a clamp element for applying a fixed potential to the bit line during a read operation; a reference current source for generating a reference current; a sense amplifier that detects, by using the reference current, a magnitude of a cell current flowing through the bit line by applying the fixed potential to the first memory cell or the second memory cell during the read operation; an offset current source that is activated during the read operation on the second memory cell and that generates an offset current to be subtracted from the cell current when activated; Equipped with the sense amplifier detects a magnitude relationship between a read current obtained by subtracting the offset current from the cell current and the reference current during the read operation on the second memory cell; Semiconductor device.

2. 2. The semiconductor device according to claim 1, Further, a first word line and a second word line are provided; the first memory cell includes a first selection transistor that forms a current path between the first storage element and the bit line when the first word line is activated; the second memory cell includes a second selection transistor that forms a current path between the second storage element and the bit line when the second word line is activated; Semiconductor device.

3. 3. The semiconductor device according to claim 2, the first selection transistor is composed of i transistor elements, where i is an integer equal to or greater than 1; the second select transistor is composed of j transistor elements, where j is an integer greater than i; the second word line is composed of a plurality of divided word lines that are individually activated; i transistor elements among the j transistor elements are controlled to be turned on / off by any one of the plurality of divided word lines; j-i transistor elements among the j transistor elements are controlled to be on / off by any other one of the plurality of divided word lines; Semiconductor device.

4. 4. The semiconductor device according to claim 3, the number of transistor elements in the second memory cell that are controlled to be turned on during a write operation on the second memory cell is greater than the number of transistor elements in the second memory cell that are controlled to be turned on during the read operation on the second memory cell; Semiconductor device.

5. 4. The semiconductor device according to claim 3, the semiconductor device can be set to either an OTP mode in which the second memory cell is used as an OTP cell or a normal MC mode in which the second memory cell is used as a normal memory cell, When set to the normal MC mode, the number of transistor elements in the second memory cell that are controlled to be turned on during a write operation and a read operation to the second memory cell is the same as the number of transistor elements in the first memory cell that are controlled to be turned on during a write operation and a read operation to the first memory cell. Semiconductor device.

6. 2. The semiconductor device according to claim 1, Further, a control circuit is provided which activates the sense amplifier at the same time when the read operation is performed on the first memory cell and when the read operation is performed on the second memory cell. Semiconductor device.

7. 3. The semiconductor device according to claim 2, further comprising a control circuit for activating the offset current source during the period from when the second word line is activated to when the sense amplifier is deactivated. Semiconductor device.

8. 2. The semiconductor device according to claim 1, the offset current source is connected between a power supply potential on a high potential side and the bit line; Semiconductor device.

9. A bit line; a first memory cell connected to the bit line and including a first variable resistance memory element; a second memory cell connected to the bit line, including a second memory element having the same electrical characteristics as the first memory element, and used as an OTP (One Time Programmable) cell; a clamp element for applying a fixed potential to the bit line during a read operation; a reference current source for generating a reference current; a sense amplifier that detects, by using the reference current, a magnitude of a cell current flowing through the bit line by applying the fixed potential to the second memory cell during the read operation; a first offset current source that is activated during the read operation on the second memory cell and that, when activated, generates a first offset current to be subtracted from the cell current; a second offset current source that is activated during the read operation on the second memory cell and that, when activated, generates a second offset current to be added to the cell current; a control circuit that activates either the first offset current source or the second offset current source during the read operation on the second memory cell, and variably controls the value of the first offset current or the value of the second offset current; Equipped with the sense amplifier, during the read operation on the second memory cell, detects a magnitude relationship between a read current obtained by subtracting the first offset current from the cell current and the reference current, or detects a magnitude relationship between a read current obtained by adding the second offset current to the cell current and the reference current. Semiconductor device.

10. 10. The semiconductor device according to claim 9, Further, a first word line and a second word line are provided; the first memory cell includes a first selection transistor that forms a current path between the first storage element and the bit line when the first word line is activated; the second memory cell includes a second selection transistor that forms a current path between the second storage element and the bit line when the second word line is activated; Semiconductor device.

11. 10. The semiconductor device according to claim 9, the first offset current source is connected between a power supply potential on a high potential side and the bit line; the second offset current source is connected between a power supply potential on a low potential side and the bit line; Semiconductor device.

12. 10. The semiconductor device according to claim 9, the control circuit activates the sense amplifier at the same time point during the read operation on the second memory cell, regardless of the value of the first offset current and the value of the second offset current; Semiconductor device.

13. A semiconductor device composed of one semiconductor chip, a processor; a non-volatile memory; a bus connecting the processor and the non-volatile memory to each other; and The nonvolatile memory includes: A bit line; a first memory cell connected to the bit line and including a first variable resistance memory element; a second memory cell connected to the bit line, including a second memory element having the same electrical characteristics as the first memory element, and used as an OTP (One Time Programmable) cell; a clamp element for applying a fixed potential to the bit line during a read operation; a reference current source for generating a reference current; a sense amplifier that detects, by using the reference current, a magnitude of a cell current flowing through the bit line by applying the fixed potential to the first memory cell or the second memory cell during the read operation; an offset current source that is activated during the read operation on the second memory cell and that generates an offset current to be subtracted from the cell current when activated; Equipped with the sense amplifier detects a magnitude relationship between a read current obtained by subtracting the offset current from the cell current and the reference current during the read operation on the second memory cell; Semiconductor device.

14. 14. The semiconductor device according to claim 13, Further, a first word line and a second word line are provided; the first memory cell includes a first selection transistor that forms a current path between the first storage element and the bit line when the first word line is activated; the second memory cell includes a second selection transistor that forms a current path between the second storage element and the bit line when the second word line is activated; Semiconductor device.

15. 15. The semiconductor device according to claim 14, the first selection transistor is composed of i transistor elements, where i is an integer equal to or greater than 1; the second select transistor is composed of j transistor elements, where j is an integer greater than i; the second word line is composed of a plurality of divided word lines that are individually activated; i transistor elements among the j transistor elements are controlled to be turned on / off by any one of the plurality of divided word lines; j-i transistor elements among the j transistor elements are controlled to be on / off by any other one of the plurality of divided word lines; Semiconductor device.

16. 14. The semiconductor device according to claim 13, Further, a control circuit is provided which activates the sense amplifier at the same time when the read operation is performed on the first memory cell and when the read operation is performed on the second memory cell. Semiconductor device.

Images