Array substrate and display device

Abstract

To reduce parasitic capacitance and suppress signal delay.SOLUTION: An array substrate 21 comprises: gate wiring 26; source wiring 27 that intersects the gate wiring 26; a switching element 23 provided at an intersection of the gate wiring 26 and the source wiring 27; a semiconductor film 23A provided to the switching element 23; a first insulting film F2 interposed between the gate wiring 26 and the semiconductor film 23A; and a second insulating film F4 interposed between the semiconductor film 23A and the source wiring 27. The source wiring 27 is superimposed on the gate wiring 26 via the first insulating film F2 and the second insulting film F4.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to an array substrate and a display device. [Background technology]

[0002] Patent Document 1 below discloses an array substrate for a liquid crystal display device. In the array substrate described in Patent Document 1, increasing the thickness of the wiring increases the cross-sectional area and reduces the resistance value. When the resistance value decreases, the time constant decreases, and signal delay can be suppressed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4592677 Summary of the Invention [Problem to be solved by the invention]

[0004] The time constant τ of a signal transmission circuit (RC circuit) is expressed as τ = RC, and depends on the resistance value R as well as the electrostatic capacitance (parasitic capacitance) C. Depending on the drive voltage of the transistor to which the signal is input and the resistance value of the surrounding circuit, reducing the parasitic capacitance of the transmission circuit may be more effective in suppressing signal delay than reducing the resistance value of the transmission circuit.

[0005] The technology disclosed in this specification was developed based on the above circumstances, and aims to reduce the parasitic capacitance of wiring and suppress signal delays. [Means for solving the problem]

[0006] (1) An array substrate described in this specification includes a gate wiring, a source wiring intersecting the gate wiring, a switching element provided at an intersection of the gate wiring and the source wiring, a semiconductor film provided in the switching element, a first insulating film disposed in a layer between the gate wiring and the semiconductor film, and a second insulating film disposed in a layer between the semiconductor film and the source wiring. The source wiring overlaps the gate wiring with the first insulating film and the second insulating film interposed therebetween.

[0007] (2) In the array substrate described in (1), the switching element may have a source electrode connected to the semiconductor film, and the source wiring may be connected to the source electrode, thereby being connected to the semiconductor film via the source electrode, and the source electrode may be provided between the first insulating film and the second insulating film.

[0008] (3) In the array substrate described in (1) or (2) above, the source electrode may not overlap the gate line.

[0009] (4) The array substrate according to any one of (1) to (3) above may include a relay electrode, and the switching element may have a drain electrode connected to the semiconductor film. The relay electrode may be connected to the drain electrode, and thereby connected to the semiconductor film via the drain electrode, and the drain electrode may be provided between the first insulating film and the second insulating film.

[0010] (5) A display device according to the technology described in this specification may include the array substrate according to any one of (1) to (4) above, and a counter substrate facing the array substrate. [Effects of the Invention]

[0011] According to the technology described in this specification, it is possible to reduce the parasitic capacitance of wiring and suppress signal delays. [Brief explanation of the drawings]

[0012] [Figure 1] LCD panel plan view [Figure 2] Cross section of a liquid crystal panel [Figure 3] Enlarged plan view of the array substrate [Figure 4] Enlarged view of the TFT area in Figure 3 [Figure 5] Cross section of line AA in Figure 4 [Figure 6] FIG. 10 is a diagram showing the signal waveform of a transmitted grayscale signal. [Figure 7] Cross-sectional view of an array substrate with a conventional structure, taken along line AA DETAILED DESCRIPTION OF THE INVENTION

[0013] <Embodiment> An embodiment of the present invention will be described with reference to Figs. 1 to 6. In this embodiment, a liquid crystal panel 11 (an example of a "display panel") provided in a liquid crystal display device 10 (an example of a "display device") will be described as an example. Some of the drawings show X-axis, Y-axis, and Z-axis, and the directions of these axes are drawn so as to be common to all the drawings. Furthermore, with reference to Fig. 2, the upper side of the drawing is the front side, and the lower side of the drawing is the back side.

[0014] 1. LCD panel overview Fig. 1 is a plan view of a liquid crystal panel 11. As shown in Fig. 1, the liquid crystal panel 11 according to this embodiment has an overall planar shape that is horizontally long and approximately rectangular. The long side direction of this liquid crystal panel 11 coincides with the X-axis direction, the short side direction coincides with the Y-axis direction, and the thickness direction coincides with the Z-axis direction.

[0015] The liquid crystal panel 11 is capable of displaying images using illumination light emitted from a backlight device (illumination device). The central portion of the screen of the liquid crystal panel 11 is a display area (pixel area) AA where an image is displayed. In contrast, the frame-shaped outer peripheral portion of the screen surrounding the display area AA is a non-display area (frame area) NAA where no image is displayed. In FIG. 1, the area surrounded by the dashed line is the display area AA.

[0016] 1, the liquid crystal panel 11 has a pair of substrates 20, 21 made of glass that is nearly transparent and has excellent light-transmitting properties, and of the pair of substrates 20, 21, the substrate disposed on the front side is a counter substrate 20 (CF substrate), and the substrate disposed on the rear side is an array substrate 21 (active matrix substrate, element substrate). Both the counter substrate 20 and the array substrate 21 have various films laminated on the inner surface of the glass substrate.

[0017] The short side dimension of the array substrate 21 is larger than the short side dimension of the counter substrate 20, and one end in the long side direction does not overlap with the counter substrate 20. A driver (signal supply unit, mounted component) 12 and a flexible substrate (mounted component) 13 are mounted in the non-overlapping area. The driver 12 is made of an LSI chip having a drive circuit inside, and is mounted on the mounting area of ​​the array substrate 21 by COG (Chip On Glass). The driver 12 processes various signals transmitted via the flexible substrate 13.

[0018] A driver 12 is mounted on the flexible substrate 13. The driver 12 is made up of an LSI chip having a drive circuit inside. The driver 12 is mounted on the flexible substrate 13 and processes various signals supplied from an external control substrate.

[0019] In the non-display area NAA of the array substrate 21, a pair of gate circuit units 14 are provided at positions adjacent to both sides (left and right sides in FIG. 1) of the display area AA in the X-axis direction. The gate circuit units 14 supply scanning signals to gate wiring 26, which will be described later. The gate circuit units 14 are monolithically provided on the array substrate 21 using metal films that form the gate wiring 26 and source wiring 27. The gate circuit units 14 include a shift register circuit for sequentially supplying scanning signals to the plurality of gate wirings 26.

[0020] The flexible substrate 13 has a configuration in which a large number of wiring patterns (not shown) are formed on a base material made of an insulating and flexible synthetic resin material (such as polyimide resin). One end of the flexible substrate 13 is connected to the array substrate 21, and the other end is connected to an external control substrate (signal supply source). Various signals supplied from the control substrate are transmitted to the liquid crystal panel 11 via the flexible substrate 13.

[0021] Fig. 2 is a schematic cross-sectional view of a display area AA of the liquid crystal panel 11. As shown in Fig. 2, the liquid crystal panel 11 sandwiches, between a pair of substrates 20 and 21, a liquid crystal layer 29 containing liquid crystal molecules whose optical properties change when a voltage is applied.

[0022] Three color filters 30, each representing red (R), green (G), and blue (B), are provided on the inner surface of the counter substrate 20 in the display area AA. These color filters 30 are arranged so as to overlap with each pixel electrode 24 of the array substrate 21 in a plan view. Light-shielding portions 31 are provided between adjacent color filters 30. The light-shielding portions 31 function as partitions between the color filters 30. In the liquid crystal panel 11, the RGB color filters 30 aligned along the X-axis direction and the three pixel electrodes 24 facing each color filter 30 form three-color pixels PX.

[0023] A solid counter electrode 22 extending across the entire display area AA is provided on the counter substrate 20. The counter electrode 22 is made of the same transparent electrode material as the pixel electrodes 24, and is disposed opposite all of the pixel electrodes 24 arranged in the display area AA with a liquid crystal layer 29 sandwiched therebetween.

[0024] An alignment film 32 is provided on the innermost surface of each of the pair of substrates 20 and 21. A polarizing plate 33 is provided on the outermost surface of each of the pair of substrates 20 and 21.

[0025] 2. Wiring and TFT Fig. 3 is an enlarged view of the display area AA of the array substrate 21. On the inner surface of the display area AA of the array substrate 21, as shown in Fig. 3, a large number of gate wirings 26 (wirings, scanning wirings) and source wirings 27 (wirings, image wirings) are provided in a grid pattern.

[0026] The gate lines 26 extend along the X-axis direction across the display area AA. The source lines 27 extend along the Y-axis direction across the display area AA. The gate lines 26 are arranged at intervals in the Y-axis direction. The source lines 27 are arranged at intervals in the X-axis direction. The gate lines 26 and the source lines 27 are made of two metal films arranged in different layers with at least a gate insulating film F2 interposed therebetween (described later).

[0027] The gate lines 26 and source lines 27 intersect when viewed from the Z-axis direction, and a TFT 23 (an example of a "switching element") is formed near each intersection. A rectangular area surrounded by the gate lines 26 and source lines 27 corresponds to the pixel PX described above. A pixel electrode 24 (transparent electrode) is formed inside the pixel PX. Each metal film constituting the gate lines 26 and source lines 27 is conductive.

[0028] The configuration of the TFT 23 and the wirings 26 and 27 will be described with reference to Fig. 4. Fig. 4 is an enlarged plan view of the vicinity of the TFT 23. As shown in Fig. 4, the TFT 23 has a semiconductor film 23A, a gate electrode 23G, a source electrode 23S, and a drain electrode 23D.

[0029] A gate electrode 23G protruding in the Y-axis direction is connected to the gate wiring 26 extending along the X-axis direction. The gate electrode 23G is disposed so that at least a portion thereof overlaps with the semiconductor film 23A.

[0030] A portion of the source wiring 27 extending along the Y-axis direction has a source protrusion 27A protruding in the X-axis direction. The source protrusion 27A is provided at a position where it does not overlap with the gate wiring 26. This reduces the capacitance component that occurs between the source protrusion 27A and the gate wiring 26.

[0031] The source electrode 23S is provided at the tip of the source protrusion 27A so as to overlap at least a portion with the source protrusion 27A. The source protrusion 27A and the source electrode 23S are electrically connected in the Z-axis direction at the overlapping portion and are at the same potential. The source electrode 23S is provided at a position where it does not overlap with the gate wiring 26, thereby suppressing the capacitance component generated between the source electrode 23S and the gate wiring 26.

[0032] The pixel electrode 24 is connected to the drain electrode 23D of the TFT 23 via a contact electrode 34 (an example of a "relay electrode"; see FIG. 5).

[0033] The TFT 23 has a semiconductor film 23A made of a semiconductor material. One end of the semiconductor film 23A is connected to a source electrode 23S, and the other end is connected to a drain electrode 23D. The semiconductor film 23A is superimposed on a gate electrode 23G provided on the back side, with a gate insulating film F2 interposed between them.

[0034] 2.1 About various membranes Next, various films laminated on the glass substrate of the array substrate 21 and constituting the wiring 26, 27, TFT 23, etc. will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view taken along line AA in Fig. 4. Line AA in Fig. 4 is a line that crosses the TFT 23 in the X-axis direction, then bends in the Y-axis direction at point 27B on the source wiring 27, and crosses the intersection of the source wiring 27 and the gate wiring 26 in the Y-axis direction.

[0035] The glass substrate of the array substrate 21 is formed with a first metal film F1, a gate insulating film F2 (an example of a "first insulating film"), a semiconductor film 23A, a second metal film F3, a second insulating film F4, a third metal film F5, a protective film F6, a planarizing film F7, and a transparent electrode film F8 stacked in this order from the lower layer side (glass substrate side).

[0036] The first metal film F1, the second metal film F3, and the third metal film F5 are each made of a metal such as copper or aluminum and are electrically conductive. The first metal film F1 forms the gate line 26, the gate electrode 23G of the TFT 23, etc.

[0037] The second metal film F3 constitutes the source electrode 23S and the drain electrode 23D of the TFT 23. The third metal film F5 constitutes the source line 27, the contact electrode 34, and the like.

[0038] A part of the source wiring 27 extends in a convex shape along the X-axis direction, and overlaps with the source electrode 23S at the end in the X-axis direction. A contact portion 27C that protrudes in the Z-axis direction and comes into contact with the source electrode 23S is formed at the portion of the source wiring 27 that overlaps with the source electrode 23S.

[0039] The source wiring 27 is electrically connected to the source electrode 23S at a contact portion 27C. Similarly, the contact electrode 34 has a contact portion 34A formed at an end of the contact electrode 34, and is connected to the drain electrode 23D at the contact portion 34A.

[0040] The semiconductor film 23A is made of a thin film using a semiconductor material such as an oxide semiconductor or amorphous silicon, and constitutes a channel of the TFT 23. The gate insulating film F2, the second insulating film F4, and the protective film F6 are made of silicon nitride (SiN xThe gate insulating film F2 is made of an inorganic material such as silicon dioxide (SiO2). The gate insulating film F2 is interposed between the first metal film F1 and the semiconductor film 23A to insulate them. More specifically, in the TFT 23, the gate insulating film F2 is interposed between the gate electrode 23G and the semiconductor film 23A to generate an electric field and control the current flowing through the channel. The gate insulating film F2 also extends to an overlapping portion 36 where the gate wiring 26 and the source wiring 27 intersect and overlap. The gate insulating film F2 is interposed between the gate wiring 26 and the source wiring 27 in this overlapping portion to prevent a short circuit.

[0041] The second insulating film F4 is interposed between the second metal film F3 and the third metal film F5 and prevents a short circuit between the second metal film F3 and the third metal film F5. Specifically, it prevents a short circuit in unintended locations except for the contact portion 27C provided at the location where the source electrode 23S and the source wiring 27 overlap, and the contact portion 34A provided at the location where the drain electrode 23D and the contact electrode 34 overlap. The second insulating film F4 also extends to the overlap portion 36 between the gate wiring 26 and the source wiring 27 and is interposed between the gate wiring 26 and the source wiring 27 to prevent a short circuit.

[0042] In order to protect the various films stacked on the rear side of the protective film F6, the protective film F6 is formed in a solid state over almost the entire area of ​​the array substrate 21. In the portions of the protective film F6 and the planarizing film F7 that overlap the contact electrodes 34, contact holes 35 that penetrate the protective film F6 and the planarizing film F7 in the film thickness direction (Z-axis direction) are formed.

[0043] The planarization film F7 is made of an organic material such as PMMA (acrylic resin). The thickness of the planarization film F7 is much greater than that of the other films laminated on the glass substrate, and the planarization film F7 flattens the inner surface of the array substrate 21 (the surface on the liquid crystal layer 29 side).

[0044] The transparent electrode film F8 is formed continuously over the inner periphery and bottom surface of the contact hole 35 and the surface of the planarization film F7. The portion of the transparent electrode film F8 that is formed on the inner surface side of the array substrate 21 is the pixel electrode 24. The transparent electrode film F8 is in contact with the contact electrode 34 at the bottom of the contact hole 35, and the pixel electrode 24 is electrically connected to the contact electrode 34 and the drain electrode 23D that is connected to the contact electrode 34.

[0045] When the TFT 23 is turned on based on the scanning signal transmitted by the gate line 26, the gradation signal (image signal) transmitted by the source line 27 is supplied to the pixel electrode 24 via the source electrode 23S, the semiconductor film 23A, the drain electrode 23D, and the contact electrode 34. At this time, the pixel electrode 24 is charged to a potential based on the gradation signal.

[0046] In the liquid crystal panel 11, a predetermined electric field is applied to the liquid crystal layer 29 based on the potential difference generated between the counter electrode 22 and each pixel electrode 24, thereby enabling each pixel PX to display a predetermined gradation.

[0047] 2.2 Parasitic capacitance and signal delay The grayscale signal input to the TFT 23 through the source line 27 is delayed due to the influence of the time constant τs of the source line. The time constant τs is expressed as τs=RsCs, where Rs is the resistance value [Ω] of the source line 27 and Cs is the parasitic capacitance [F] of the source line 27.

[0048] 5, the gate wiring 26 and the source wiring 27 overlap with insulators (gate insulating film F2 and second insulating film F4) interposed therebetween at the overlapping portion 36. The parasitic capacitance Cs2 is a capacitance component that arises due to the physical structure of the wirings 26 and 27. If the parasitic capacitance Cs2 is large, the time constant τs of the source wiring 27 also becomes large, resulting in a large delay in the grayscale signal that is input to the TFT 23 through the source wiring 27.

[0049] For comparison, an array substrate 121 having a conventional configuration will now be described with reference to Fig. 7. Fig. 7 is a cross-sectional view of the array substrate 121 at a location corresponding to line AA in Fig. 4 (a broken line that crosses the TFT 23 and vertically cuts through the overlapping portion 36 of the gate line 26 and the source line 27). The array substrate 121 includes, on a glass substrate, a first metal film F11, a gate insulating film F12 (first insulating film), a semiconductor film 123A, a second metal film F13, a protective film F14, a planarizing film F15, a transparent conductive film F16, and the like.

[0050] The first metal film F11 and the second metal film F13 are each made of a metal such as copper or aluminum and are conductive. Like the first metal film F1 of the array substrate 21, the first metal film F11 forms the gate wiring 126, the gate electrode 123G, etc. The second metal film F13 forms the source electrode 123S and source wiring 127, which are formed in a continuous manner, and the drain electrode 123D, etc. For convenience, of the source electrode 123S and source wiring 127, which are formed in a continuous manner, the portion extending in the Y-axis direction will be referred to as the source wiring 127, and the portion protruding from the source wiring 127 in the X-axis direction and connected to the semiconductor film 123A will be referred to as the source electrode 123S.

[0051] The source electrode 123S and source wiring 127 of the array substrate 121 are both made of the second metal film F13. This is a different configuration from the array substrate 21 of the present invention, in which the source electrode 23S and source wiring 27 are made of separate metal films (the first metal film F1 and the third metal film F5) and are separated from each other by an insulator (the second insulating film F4).

[0052] Furthermore, a portion of the array substrate 21 corresponding to the contact electrode 34 that is interposed between the drain electrode 23D and the transparent conductive film F16 and connected to both is not provided on the array substrate 121. The drain electrode 123D of the array substrate 121 is directly connected to a contact portion 134A made of the transparent conductive film F16.

[0053] The semiconductor film 123A, the protective film F14, the planarizing film F15, and the transparent conductive film F16 have the same configurations as the semiconductor film 23A, the protective film F6, the planarizing film F7, and the transparent conductive film F8 of the array substrate 21, respectively.

[0054] The gate insulating film F12 is interposed between the semiconductor film 123A and the gate electrode 123G to insulate them from each other. The gate insulating film F12 is also interposed between the gate wiring 126 and the source wiring 127 in an overlapping portion 136 where the gate wiring 126 and the source wiring 127 overlap each other to insulate them from each other.

[0055] In the conventional array substrate 121, the gate insulating film F12 is the only insulator interposed between the gate wiring 126 and the source wiring 127. In the array substrate 121, the distance L1 between the gate wiring 126 and the source wiring 127 depends on the thickness of the gate insulating film F12.

[0056] Increasing the thickness of the gate insulating film F12 is one way to reduce the parasitic capacitance Cs1 of the overlapping portion 136. However, there is a concern that changing the thickness of the gate insulating film F12 may affect the characteristics of the TFT 123.

[0057] 3. Explanation of effects In the array substrate 21 of this embodiment, in order to reduce the parasitic capacitance Cs2 of the overlapping portion 36, it is considered to increase the distance L2 between the gate wiring 26 and the source wiring 27. The array substrate 21 of this embodiment includes a gate wiring 26, a source wiring 27 intersecting with the gate wiring 26, a TFT 23 provided at the intersection of the gate wiring 26 and the source wiring 27, a semiconductor film 23A provided in the TFT 23, a gate insulating film F2 disposed in a layer between the gate wiring 26 and the semiconductor film 23A, and a second insulating film F4 disposed in a layer between the semiconductor film 23A and the source wiring 27, and the source wiring 27 overlaps with the gate wiring 26 via the gate insulating film F2 and the second insulating film F4.

[0058] 5, in addition to the gate insulating film F2, which is an insulator, a second insulating film F4 is interposed between the gate wiring 26 and the source wiring 27. Even if the thickness of the gate insulating film F2 is the same as that of the gate insulating film F12 (see FIG. 7), the distance L2 between the gate wiring 26 and the source wiring 27 is greater than the distance L1 (see FIG. 7) by the thickness of the second insulating film F4. The parasitic capacitance Cs2 in the overlapping portion 36 is reduced compared to the parasitic capacitance Cs1 when the distance is L1. As the parasitic capacitance decreases, the time constant τs decreases, thereby suppressing delays in signals input from the source wiring 27 to the TFT 23.

[0059] The suppression of delay will be described with reference to graph 50 shown in FIG. 6. Graph 50 is a graph that schematically shows the signal waveforms applied to source electrodes 23S and 123S when a rectangular wave (voltage value V0) grayscale signal is input to source wirings 27 and 127. In graph 50, the horizontal axis represents time and the vertical axis represents voltage. Voltage waveform 51 in graph 50 is the voltage waveform of the grayscale signal input to source wiring 27. Voltage waveforms 52 and 53 are waveforms of source voltages transmitted through source wirings 27 and 127 and applied to source electrodes 23S and 123S.

[0060] The application of voltage waveform 51 begins at time t0, and the voltage rises from 0 to V0 at time t0. Furthermore, the voltage V0 is maintained from time t0 to time t3, and at time t3 the voltage drops from V0 to 0. For convenience, it is assumed that the voltage of the gradation signal rises and falls instantaneously.

[0061] Voltage waveform 52 is a waveform that appears at source electrode 123S when a grayscale signal of voltage waveform 51 is applied to source wiring 127 of array substrate 121 having the conventional configuration shown in Fig. 7. A time constant τ1 calculated by using the capacitance C of source wiring 127 as a parasitic capacitance Cs1 is applied to voltage waveform 52.

[0062] As shown in FIG. 6, the voltage waveform 52 rises with the passage of time from time t0 and reaches the voltage V0 at time t2. In the array substrate 121 of the conventional configuration, after the application of the gradation signal (voltage waveform 51), it takes a time of t2 - t0 until the voltage reaches the voltage V0.

[0063] If the delay time is defined as the time (time t2) from the start of application of the gradation signal (time t0) until the voltage V0 is reached, the delay time of the array substrate 121 is t2 - t0.

[0064] The voltage waveform 53 shows the voltage of the source electrode 23S when the gradation signal of the voltage waveform 51 is input to the source wiring 27 of the array substrate 21 of the present embodiment shown in FIG. 5. A time constant τ2 calculated by using the capacitance C of the source wiring 27 as the parasitic capacitance Cs2 is applied to the voltage waveform 53. As described above, since the distance L2 between the gate wiring 26 and the source wiring 27 is in the relation of L1 < L2, the parasitic capacitance Cs2 is smaller than Cs1 (Cs1 > Cs2), and the time constant τ2 is smaller than τ1 (τ1 > τ2).

[0065] As shown in FIG. 6, the voltage of the voltage waveform 53 rises with the passage of time from time t0 and reaches the voltage V0 at time t1. The delay time of the array substrate 21 of the present embodiment is t1 - t0. Since the time constant τ1 > τ2, the delay time t1 - t0 of the array substrate 21 is shorter than the delay time t2 - t0 of the array substrate 121. The array substrate 21 of the present embodiment reaches the voltage V0 with a shorter delay time than the array substrate 121, and the signal delay of the source wiring 27 is suppressed as compared with the array substrate 121.

[0066] The shortening of the delay time means that the time from the application of the gradation signal until the pixel performs a predetermined gradation display is shortened. Thereby, the refresh rate of the liquid crystal panel 11 can be increased to a higher frequency, or the number of pixels in the display area AA can be increased to increase the resolution of the liquid crystal panel 11.

[0067] In the array substrate 21 of this embodiment, the TFT 23 has a source electrode 23S connected to the semiconductor film 23A. The source wiring 27 is connected to the source electrode 23S, and is thereby connected to the semiconductor film 23A via the source electrode 23S, and the source electrode 23S is provided between the gate insulating film F2 and the second insulating film F4.

[0068] 5, the source wiring 27 is connected to the semiconductor film 23A via the source electrode 23S, and there is no direct contact between the source wiring 27 and the semiconductor film 23A. By not making direct contact, there is no need to match the material and formation process (chemical resistance, annealing temperature, etc.) of the source wiring 27 with the material properties of the semiconductor film 23A.

[0069] For example, a material that can be well connected to the source electrode 23S but has low connection reliability with the semiconductor film 23A can be used as the material for the source wiring 27, or a chemical solution that is highly aggressive to the semiconductor film 23A can be used in the process of forming the source wiring 27. This improves the degree of freedom in the material and process of the source wiring 27 relative to the semiconductor film 23A.

[0070] Furthermore, since the source electrode 23S and the source wiring 27 are formed in different layers with the second insulating film F4 in between, they do not need to be made of the same material or formed by the same process, which increases the degree of freedom in the materials and the forming process between the source electrode 23S and the source wiring 27.

[0071] The source wiring 27 is connected to the semiconductor film 23A via the source electrode 23S, which improves the degree of freedom in arranging the source wiring 27 relative to the semiconductor film 23A. For example, even if the semiconductor film 23A is not positioned so as to overlap with the source wiring 27, the semiconductor film 23A and the source wiring 27 can be electrically connected via the source electrode 23S.

[0072] In the array substrate 21 of this embodiment, the source electrode 23S does not overlap with the gate line 26. When the source electrode 23S and the gate line 26 do not overlap, the capacitance component between them is smaller than when they overlap. In the path of a grayscale signal input from the source line 27 to the semiconductor film 23A via the source electrode 23S, the total value of the capacitance between the source line 27 and the source electrode 23S, which are connected to each other and have the same potential, and the gate line 26 is reduced, the time constant τ is reduced, and signal delay can be suppressed.

[0073] In the array substrate 21 of this embodiment, the TFT 23 has a drain electrode 23D connected to the semiconductor film 23A, and the drain electrode 23D is provided between the gate insulating film F2 and the second insulating film F4.

[0074] In this way, similar to the relationship between the source wiring 27 and the semiconductor film 23A described above, the degree of freedom in the material and forming process of the drain electrode 23D can be increased.

[0075] The liquid crystal display device 10 according to this embodiment includes the array substrate 21 described above and a counter substrate 20 disposed opposite the array substrate 21. In this liquid crystal display device 10, the parasitic capacitance Cs2 of the source lines 27 is reduced, so that the signals (grayscale signals) transmitted by the source lines 27 are less likely to be dulled, thereby improving the display quality.

[0076] <Other embodiments> (1) In the above embodiment, a TFT 23 (switching element) having a semiconductor film 23A, a source electrode 23S, and a drain electrode 23D is exemplified. The switching element may not have one or both of the source electrode and the drain electrode. In this case, a portion of the semiconductor film is made conductive by a conductive treatment, and the source wiring or the contact electrode is brought into contact with the conductive portion, thereby electrically connecting the source wiring or the contact electrode to the switching element.

[0077] (2) In the above embodiment, the source electrode 23S does not overlap with the gate wiring 26. However, the source electrode 23S may overlap with the gate wiring 26 in part or in whole.

[0078] (3) In the above embodiment, the TFT 23 is described as a bottom-gate TFT having a gate electrode 23G on the back side of the semiconductor film 23A with the gate insulating film F2 sandwiched therebetween. The TFT is not limited to the bottom-gate type, and may be a top-gate type having a gate electrode on the front side of the semiconductor film. Alternatively, the TFT may be a double-gate type having gate electrodes on both the front and back sides of the semiconductor film.

[0079] (4) In the above embodiment, a TFT is used as an example of a switching element, but the switching element is not limited to a TFT and may be another type of transistor (MOSFET, IGBT, etc.).

[0080] (5) As a driving method for the liquid crystal panel, the SSD method (Source Shared Driving) may be applied, in which the display area AA is divided into multiple areas and a source signal is distributed from one TFT to each divided area. The array substrate of the present invention can shorten the delay time of the TFT, enabling high-speed switching. By using TFTs capable of high-speed switching in an SSD-type liquid crystal panel, the number of divisions of the display area can be increased.

[0081] (6) In the above embodiment, the counter electrode 22 is provided on the counter substrate 20, and the alignment state of the liquid crystal molecules contained in the liquid crystal layer 29 is controlled by utilizing a vertical electric field generated between the pixel electrodes 24 and the counter electrode 22 (vertical electric field liquid crystal mode). However, a horizontal electric field may be generated in the liquid crystal layer 29, and the alignment state of the liquid crystal molecules contained in the liquid crystal layer 29 may be controlled by utilizing the horizontal electric field (horizontal electric field liquid crystal mode). To achieve the horizontal electric field liquid crystal mode, instead of providing the counter electrode 22 on the counter substrate 20, for example, a common electrode may be provided on the array substrate 21 so as to overlap the pixel electrodes 24 via an insulating film, and a horizontal electric field may be generated between the pixel electrodes 24 and the common electrode. [Explanation of symbols]

[0082] 11: liquid crystal panel, 21: array substrate, 22: counter electrode, 23: TFT (an example of a switching element), 23A: semiconductor film, 23D: drain electrode, 23G: gate electrode, 23S: source electrode, 26: gate wiring, 27: source wiring, 36: overlapping portion, F1: first metal film, F2: gate insulating film (an example of a first insulating film), F4: second insulating film

Claims

1. An array substrate, A substrate; The gate wiring, a source wiring that intersects with the gate wiring; a switching element provided at an intersection of the gate wiring and the source wiring; a semiconductor film provided on the switching element; a first insulating film disposed in a layer between the gate wiring and the semiconductor film; a second insulating film disposed in a layer between the semiconductor film and the source wiring; the first insulating film is a gate insulating film, the gate wiring, the gate insulating film, the semiconductor film, the second insulating film, and the source wiring are stacked in this order from the substrate side; the source wiring overlaps the gate wiring with the gate insulating film and the second insulating film interposed therebetween.

2. 2. The array substrate according to claim 1, the switching element has a source electrode connected to the semiconductor film, the source wiring is connected to the source electrode, and is thereby connected to the semiconductor film via the source electrode; the source electrode is formed from a material different from that of the semiconductor film and is provided between the semiconductor film and the second insulating film.

3. 3. The array substrate according to claim 2, The source electrode does not overlap with the gate line.

4. 3. The array substrate according to claim 2, A relay electrode is provided, the switching element has a drain electrode connected to the semiconductor film, the relay electrode is connected to the drain electrode, and thereby connected to the semiconductor film via the drain electrode; the drain electrode is formed from a material different from that of the semiconductor film and is provided between the semiconductor film and the second insulating film.

5. The array substrate according to claim 4, The array substrate, wherein the source electrode and the drain electrode are made of the same conductive film.

6. The array substrate according to any one of claims 1 to 5; a counter substrate facing the array substrate.

Images