Electronic Components

Abstract

An electronic component (102) comprises a semiconductor substrate (1), an insulator layer (2) formed on the top surface layer side of the semiconductor substrate (1), internal electrodes (3A1, 3A2, 3B) formed inside the insulator layer (2), a dielectric layer (4) composed of a thermal oxide film formed on the top surface layer side of the semiconductor substrate (1), extracting electrodes (5A1, 5A2) that are connected to the internal electrodes (3A1, 3A2) and are nearer the top surface layer side than the internal electrodes (3A1, 3A2), extracting electrodes (5B1, 5B2) that are connected to the internal electrode (3B) and are nearer the top surface layer side than the internal electrode (3B), an external electrode (6A) that is connected to the extracting electrodes (5A1, 5A2) and is nearer the top surface layer side than the extraction electrodes (5A1, 5A2), and an external electrode (6B) that is connected to the extracting electrodes (5B1, 5B2) and is nearer the top surface layer side than the extracting electrodes (5B1, 5B2). Viewed in the vertical direction relative to the semiconductor substrate plane, the second extraction electrodes are formed inside of the second internal electrode.

Description

[Technical Field]

[0001] The present invention relates to an electronic component that includes a semiconductor substrate and is configured by providing a capacitor or the like on the semiconductor substrate. [Background technology]

[0002] Patent Document 1 shows the configuration of a MOS capacitor used in an internal voltage generating circuit of a semiconductor memory. Figures 6(A) and 6(B) show a simplified example. This MOS capacitor includes a P-type semiconductor substrate 11, an N-type well 12, an N+ diffusion layer 13, an SiO2 104 for isolation, a gate insulating film 15, a gate 106 made of polycrystalline silicon or metal, an interlayer insulating film 113, a wiring layer 108, a protective layer 115, and a contact hole 116. This capacitor is formed between the gate 106 and the surface of the N-type well 12, with the gate insulating film 15 sandwiched between them, just like a normal MOS capacitor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-110030 Summary of the Invention [Problem to be solved by the invention]

[0004] A significant amount of parasitic impedance occurs in the MOS capacitor having the structure shown in Patent Document 1. For example, parasitic capacitance is formed between the wiring layer 108 and the N-type well 12 or between the wiring layer 108 and the semiconductor substrate 11, and parasitic resistance components and parasitic inductance components occur in the wiring layer 108 itself.

[0005] Figure 7 is an equivalent circuit diagram of the MOS capacitor shown in Figures 6(A) and 6(B). Terminals T1 and T2 shown in Figure 7 correspond to the electrodes to which wiring layer 108 of the electronic component shown in Figures 6(A) and 6(B) is connected, and capacitor C0 shown in Figure 7 is the intended capacitor. Capacitor C1 shown in Figure 7 is the parasitic capacitance. Inductor L1 shown in Figure 7 is the parasitic inductance component, and resistor R1 is the parasitic resistance component.

[0006] An object of the present invention is to provide an electronic component in which a capacitor with low parasitic impedance is formed on a semiconductor substrate. [Means for solving the problem]

[0007] An example electronic component of the present disclosure includes: a semiconductor substrate; an insulator layer formed on a surface side of the semiconductor substrate; an internal electrode formed in the insulator layer; a dielectric layer formed on a surface side of the semiconductor substrate; A lead electrode is disposed on a surface layer side of the internal electrode and is electrically connected to the internal electrode; an external electrode that is electrically connected to the extraction electrode on the surface side of the extraction electrode; Equipped with the internal electrodes include a first internal electrode that is electrically connected to the semiconductor substrate and a second internal electrode that is formed on a surface side of the dielectric layer, the extraction electrode includes a first extraction electrode that is electrically connected to the first internal electrode and a second extraction electrode that is electrically connected to the second internal electrode, the external electrodes include a first external electrode electrically connected to the first extraction electrode and a second external electrode electrically connected to the second extraction electrode; When viewed in a direction perpendicular to the surface of the semiconductor substrate, the second extraction electrode is formed inside the second internal electrode. It is characterized by: [Effects of the Invention]

[0008] According to the present invention, an electronic component is obtained in which a capacitor with low parasitic impedance is formed on a semiconductor substrate. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1(A) is a plan view of an electronic component 101 according to the first embodiment, FIG. 1(B) is a cross-sectional view at the BB portion in FIG. 1(A), and FIG. 1(C) is a cross-sectional view at the CC portion in FIG. 1(A). [Figure 2] FIG. 2(A) is a plan view of an electronic component 102 according to the second embodiment, FIG. 2(B) is a cross-sectional view at the BB portion in FIG. 2(A), and FIG. 2(C) is a cross-sectional view at the CC portion in FIG. 2(A). [Figure 3] FIG. 3(A) is a plan view of an electronic component 103 according to the third embodiment, FIG. 3(B) is a cross-sectional view at the BB portion in FIG. 3(A), and FIG. 3(C) is a cross-sectional view at the CC portion in FIG. 3(A). [Figure 4] FIG. 4(A) is a plan view of an electronic component 104 according to the fourth embodiment, FIG. 4(B) is a cross-sectional view at the BB portion in FIG. 4(A), and FIG. 4(C) is a cross-sectional view at the CC portion in FIG. 4(A). [Figure 5] FIG. 5(A) is a plan view of an electronic component 105 according to the fifth embodiment, FIG. 5(B) is a cross-sectional view at the BB portion in FIG. 5(A), and FIG. 5(C) is a cross-sectional view at the CC portion in FIG. 5(A). [Figure 6] 6(A) and 6(B) are simplified diagrams showing MOS type capacitors used in the internal voltage generating circuit of the semiconductor memory described in Patent Document 1. FIG. [Figure 7] FIG. 7 is an equivalent circuit diagram of the MOS capacitor shown in FIGS. 6(A) and 6(B). DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, several specific examples will be given with reference to the drawings to illustrate several embodiments for carrying out the present invention. The same reference numerals are used for the same parts in each drawing. For the sake of convenience, the embodiments are shown divided into several embodiments, taking into account ease of explanation and understanding of the main points, but partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0011] First Embodiment Fig. 1(A) is a plan view of an electronic component 101 according to a first embodiment, Fig. 1(B) is a cross-sectional view taken along line BB in Fig. 1(A), and Fig. 1(C) is a cross-sectional view taken along line CC in Fig. 1(A). However, Fig. 1(A) is a plan view showing a state before a protective film 10, which will be described later, is formed.

[0012] This electronic component 101 includes a semiconductor substrate 1, an insulator layer 2 formed on the surface side of this semiconductor substrate 1, first internal electrodes 3A1 and 3A2 formed in the insulator layer 2, a second internal electrode 3B formed in the insulator layer 2, a dielectric layer 4 made of a thermal oxide film formed on the surface side of the semiconductor substrate 1, and a second internal electrode 3B electrically connected to the first internal electrodes 3A1 and 3A2 on the surface side of the first internal electrodes 3A1 and 3A2. The semiconductor device is provided with first extraction electrodes 5A1, 5A2, second extraction electrodes 5B1, 5B2 that are on the surface side of the second internal electrode 3B and are electrically connected to the second internal electrode 3B, a first external electrode 6A that is on the surface side of the first extraction electrodes 5A1, 5A2 and is electrically connected to the first extraction electrodes 5A1, 5A2, a second external electrode 6B that is on the surface side of the second extraction electrodes 5B1, 5B2 and is electrically connected to the second extraction electrodes 5B1, 5B2, and a protective film 10.

[0013] The semiconductor substrate 1 is a substrate made of an impurity semiconductor such as a carrier-doped silicon substrate, the insulator layer 2 is, for example, a SiN film, and the dielectric layer 4 is, for example, a SiO2 film, a thermally oxidized film of the semiconductor substrate 1. The first internal electrodes 3A1, 3A2 and the second internal electrode 3B are, for example, Al films, and the first extraction electrodes 5A1, 5A2 and the second extraction electrodes 5B1, 5B2 are, for example, Cu films. The first external electrode 6A and the second external electrode 6B are, for example, metal films with a Ni base and an Au surface. The protective film 10 is, for example, an organic insulating film such as solder resist.

[0014] The second internal electrode 3B constitutes a capacitor electrode formed on the dielectric layer 4. The semiconductor substrate 1 is a substrate made of an impurity semiconductor such as a carrier-doped silicon substrate, and is therefore conductive. Therefore, the semiconductor substrate 1, the dielectric layer 4, and the second internal electrode 3B constitute the main part of the capacitor.

[0015] The first external electrode 6A, the first lead electrodes 5A1 and 5A2, and the first internal electrodes 3A1 and 3A2 are electrically connected to the semiconductor substrate 1, and the second external electrode 6B and the second lead electrodes 5B1 and 5B2 are electrically connected to the second internal electrode 3B.

[0016] The first external electrode 6A and the second external electrode 6B are used as connection pads such as wire bonding pads or surface mounting pads, etc. Therefore, the electronic component 101 functions as a capacitor having the first external electrode 6A and the second external electrode 6B.

[0017] The capacitor formed in electronic component 101 of this embodiment uses a silicon semiconductor substrate as one electrode and a silicon thermal oxide film as a dielectric layer, so that a highly accurate capacitance can be set.

[0018] According to this embodiment, the second extension electrodes 5B1 and 5B2 are formed inside the second internal electrode 3B when viewed in a direction perpendicular to the surface of the semiconductor substrate 1, thereby reducing the parasitic capacitance between the second extension electrodes 5B1 and 5B2 and the semiconductor substrate 1. Furthermore, the second external electrode 6B, which is electrically connected to the second extension electrodes 5B1 and 5B2, is formed on the second extension electrodes 5B1 and 5B2, thereby reducing the parasitic inductance and parasitic resistance caused by the second extension electrodes 5B1 and 5B2. Furthermore, the first extension electrodes 5A1 and 5A2 are formed on the first internal electrodes 3A1 and 3A2, and the first external electrode 6A, which is electrically connected to the first extension electrodes 5A1 and 5A2, is formed on the first extension electrodes 5A1 and 5A2, thereby reducing the parasitic inductance and parasitic resistance caused by the first extension electrodes 5A1 and 5A2.

[0019] As a result, it is possible to construct electronic components equipped with capacitors whose electrical characteristics are close to ideal capacitance elements, and to realize low-loss high-frequency circuits, thereby achieving circuit characteristics as intended by design.

[0020] Second Embodiment In the second embodiment, an electronic component in which the configuration of the internal electrodes and dielectric layers is different from that of the example shown in the first embodiment will be illustrated.

[0021] Fig. 2(A) is a plan view of an electronic component 102 according to a second embodiment, Fig. 2(B) is a cross-sectional view taken along line BB in Fig. 2(A), and Fig. 2(C) is a cross-sectional view taken along line CC in Fig. 2(A). However, Fig. 2(A) is a plan view showing the state before the protective film 10 is formed.

[0022] This electronic component 102 includes a semiconductor substrate 1, an insulator layer 2 formed on the surface side of this semiconductor substrate 1, first internal electrodes 3A1 and 3A2 formed in the insulator layer 2, a second internal electrode 3B formed in the insulator layer 2, a dielectric layer 4 made of a thermal oxide film formed on the surface side of the semiconductor substrate 1, and a second internal electrode 3B electrically connected to the first internal electrodes 3A1 and 3A2 on the surface side of the first internal electrodes 3A1 and 3A2. The semiconductor device is provided with first extraction electrodes 5A1, 5A2, second extraction electrodes 5B1, 5B2 that are on the surface side of the second internal electrode 3B and are electrically connected to the second internal electrode 3B, a first external electrode 6A that is on the surface side of the first extraction electrodes 5A1, 5A2 and is electrically connected to the first extraction electrodes 5A1, 5A2, a second external electrode 6B that is on the surface side of the second extraction electrodes 5B1, 5B2 and is electrically connected to the second extraction electrodes 5B1, 5B2, and a protective film 10.

[0023] The semiconductor substrate 1 is a substrate made of an impurity semiconductor such as a carrier-doped silicon substrate, the insulator layer 2 is, for example, a SiN film, and the dielectric layer 4 is, for example, a SiO2 film, a thermally oxidized film of the semiconductor substrate 1. The first internal electrodes 3A1, 3A2 and the second internal electrode 3B are, for example, Al films, and the first extraction electrodes 5A1, 5A2 and the second extraction electrodes 5B1, 5B2 are, for example, Cu films. The first external electrode 6A and the second external electrode 6B are, for example, metal films with a Ni base and an Au surface. The protective film 10 is, for example, an organic insulating film such as solder resist.

[0024] The electronic component 102 differs from the electronic component 101 shown in FIGS. 1(A), 1(B), and 1(C) in the shapes of the first internal electrodes 3A1 and 3A2, the second internal electrode 3B, and the dielectric layer 4. In the electronic component 102, the dielectric layer 4 is concave when viewed in a direction perpendicular to the surface of the semiconductor substrate 1. Accordingly, the second internal electrode 3B is also concave. On the other hand, the first internal electrodes 3A1 and 3A2 have a convex overall shape, and the opposing portions of the first internal electrodes 3A1 and 3A2 and the second internal electrode 3B face each other in an uneven shape. That is, the first internal electrode 3A1 has a linear portion extending toward the second external electrode 6B, and the second internal electrode 3B is disposed so as to surround the extended portion. Furthermore, as can be seen from Figure 2(A), the first internal electrode 3A1 and the second internal electrode 3B are formed so that the spacing between their sides is constant in the area where they face each other (the distance between the facing sides of the first internal electrode 3A1 and the second internal electrode 3B is constant).

[0025] The second internal electrode 3B constitutes a capacitor electrode formed on the dielectric layer 4. The semiconductor substrate 1, the dielectric layer 4, and the second internal electrode 3B constitute the main part of the capacitor. The other configurations are the same as those of the electronic component 101 shown in the first preferred embodiment.

[0026] According to the second embodiment, the area in which the first internal electrodes 3A1, 3A2 and the second internal electrode 3B face each other is wide, so that the average path length of the current flowing laterally through the semiconductor substrate 1 is short.

[0027] Generally, in a MOS capacitor using a silicon semiconductor substrate as one electrode and a silicon thermal oxide film as a dielectric layer, current flows laterally (along the surface) through the silicon semiconductor substrate. This current, in a high-frequency range, for example, above 1 GHz, concentrates near the surface of the silicon semiconductor substrate due to the current skin effect. This phenomenon increases the ESR (equivalent series resistance), thereby degrading the capacitor characteristics. While the increase in ESR due to the skin effect occurs even in metals with high conductivity, it is more pronounced in semiconductor substrates with lower conductivity than metals. In this embodiment, the average path length of the current flowing laterally through the semiconductor substrate 1 is short, so the ESR caused by the semiconductor substrate 1 is low. This results in a capacitor with low ESR.

[0028] In addition, compared to the electronic component 105 shown in the fifth embodiment described later, the area of ​​the conductive portion between the first internal electrode 3A1 and the semiconductor substrate 1 can be made smaller, so that a capacitor with a higher capacitance density can be formed.

[0029] Third Embodiment In the third embodiment, an electronic component in which the configurations of the internal electrodes and dielectric layers are different from those of the examples shown in the first and second embodiments will be illustrated.

[0030] Fig. 3(A) is a plan view of an electronic component 103 according to a third embodiment, Fig. 3(B) is a cross-sectional view taken along line BB in Fig. 3(A), and Fig. 3(C) is a cross-sectional view taken along line CC in Fig. 3(A). However, Fig. 3(A) is a plan view showing a state before the formation of a protective film 10.

[0031] This electronic component 103 includes a semiconductor substrate 1, an insulator layer 2 formed on the surface side of this semiconductor substrate 1, first internal electrodes 3A1 and 3A2 formed in the insulator layer 2, a second internal electrode 3B formed in the insulator layer 2, a dielectric layer 4 made of a thermal oxide film formed on the surface side of the semiconductor substrate 1, and a second internal electrode 3B electrically connected to the first internal electrodes 3A1 and 3A2 on the surface side of the first internal electrodes 3A1 and 3A2. The semiconductor device is provided with first extraction electrodes 5A1, 5A2, second extraction electrodes 5B1, 5B2 that are on the surface side of the second internal electrode 3B and are electrically connected to the second internal electrode 3B, a first external electrode 6A that is on the surface side of the first extraction electrodes 5A1, 5A2 and is electrically connected to the first extraction electrodes 5A1, 5A2, a second external electrode 6B that is on the surface side of the second extraction electrodes 5B1, 5B2 and is electrically connected to the second extraction electrodes 5B1, 5B2, and a protective film 10.

[0032] 2(A), 2(B), and 2(C) differ from the electronic component 102 shown in Figures 2(A), 2(B), and 2(C) in the shapes of the first internal electrodes 3A1 and 3A2 and the dielectric layer 4. In the electronic component 103, the dielectric layer 4 is also formed on the lower surface of the first internal electrode 3A2 when viewed in a direction perpendicular to the surface of the semiconductor substrate 1. In addition, the first internal electrode 3A1 is formed within an opening in the dielectric layer 4.

[0033] The second internal electrode 3B constitutes a capacitor electrode formed on the dielectric layer 4. The semiconductor substrate 1, the dielectric layer 4, and the second internal electrode 3B constitute the main part of the capacitor. The rest of the configuration is the same as that of the electronic component 102 shown in the second embodiment.

[0034] According to this embodiment, the dielectric layer 4 below the first internal electrode 3A2 acts as a height adjustment layer for this first internal electrode 3A2. In other words, in the process of forming the first internal electrode 3A2, the sagging of this first internal electrode 3A2 toward the semiconductor substrate 1 is suppressed. As a result, the heights of the first external electrode 6A and the second external electrode 6B are easily aligned. As a result, when the electronic component 103 is wire-bonded, the accuracy of wire-bonding to the first external electrode 6A and the second external electrode 6B can be improved. Alternatively, it is possible to prevent the impact when the electronic component 103 is surface-mounted from concentrating on one of the external electrodes.

[0035] In addition, the dielectric layer 4 may be formed so that the part constituting the height adjustment layer of the first internal electrode 3A2, which is used to align the heights of the first external electrode 6A and the second external electrode 6B, and the part constituting the main part of the capacitor are separate bodies.

[0036] Fourth Embodiment In the fourth embodiment, an electronic component having internal electrodes and dielectric layers with different configurations from those of the examples shown so far will be described.

[0037] Fig. 4(A) is a plan view of an electronic component 104 according to a fourth embodiment, Fig. 4(B) is a cross-sectional view taken along line BB in Fig. 4(A), and Fig. 4(C) is a cross-sectional view taken along line CC in Fig. 4(A). However, Fig. 4(A) is a plan view showing the state before the protective film 10 is formed.

[0038] 2(B), the dielectric layer 4 and the second internal electrode 3B are formed in a planar shape on the upper part of the semiconductor substrate 1, but in the electronic component 104 of the fourth embodiment, a plurality of trenches are formed on the upper part of the semiconductor substrate 1. In this example, the trenches are cylindrical rather than groove-shaped. The dielectric layer 4 is formed on the inner surface of these trenches, and a portion of the second internal electrode 3B is buried inside the trenches.

[0039] According to this embodiment, the opposing area between the second internal electrode 3B and the semiconductor substrate 1 via the dielectric layer 4 can be increased, so that the plane area of ​​the capacitor formation region can be saved.

[0040] Fifth Embodiment In the fifth embodiment, an electronic component in which the configurations of the internal electrodes and dielectric layers are different from those of the examples shown in the first and second embodiments will be illustrated.

[0041] Fig. 5(A) is a plan view of an electronic component 105 according to a fifth embodiment, Fig. 5(B) is a cross-sectional view taken along line BB in Fig. 5(A), and Fig. 5(C) is a cross-sectional view taken along line CC in Fig. 5(A). However, Fig. 5(A) is a plan view showing the state before the formation of the protective film 10.

[0042] This electronic component 105 includes a semiconductor substrate 1, an insulator layer 2 formed on the surface side of this semiconductor substrate 1, first internal electrodes 3A1 and 3A2 formed in the insulator layer 2, a second internal electrode 3B formed in the insulator layer 2, a dielectric layer 4 made of a thermal oxide film formed on the surface side of the semiconductor substrate 1, and a second internal electrode 3B electrically connected to the first internal electrodes 3A1 and 3A2 on the surface side of the first internal electrodes 3A1 and 3A2. The semiconductor device is provided with first extraction electrodes 5A1, 5A2, second extraction electrodes 5B1, 5B2 that are on the surface side of the second internal electrode 3B and are electrically connected to the second internal electrode 3B, a first external electrode 6A that is on the surface side of the first extraction electrodes 5A1, 5A2 and is electrically connected to the first extraction electrodes 5A1, 5A2, a second external electrode 6B that is on the surface side of the second extraction electrodes 5B1, 5B2 and is electrically connected to the second extraction electrodes 5B1, 5B2, and a protective film 10.

[0043] 2(A), 2(B), and 2(C), when viewed in a direction perpendicular to the surface of the semiconductor substrate 1, the dielectric layer 4 and the second internal electrode 3B are concave, and the first internal electrodes 3A1 and 3A2 have a convex overall shape. However, in the electronic component 105 according to the fifth embodiment, the dielectric layer 4 and the second internal electrode 3B are convex, and the first internal electrodes 3A1 and 3A2 have a concave overall shape. The opposing portions of the first internal electrodes 3A1 and 3A2 and the second internal electrode 3B face each other in an uneven manner. That is, a portion of the second internal electrode 3B extends linearly toward the first external electrode 6A, and the second internal electrode 3B is disposed so that the first internal electrode 3A1 surrounds the extending portion of the second internal electrode 3B. In addition, in the region where the first internal electrode 3A1 and the second internal electrode 3B face each other, the first internal electrode 3A1 and the second internal electrode 3B are formed so that the spacing between their sides is constant (the distance between the facing sides of the first internal electrode 3A1 and the second internal electrode 3B is constant).

[0044] According to this embodiment, similar to the electronic component 102 shown in the second embodiment, a capacitor with reduced parasitic inductance and parasitic resistance and low ESR can be obtained.

[0045] Finally, the present invention is not limited to the above-described embodiments. Those skilled in the art can make appropriate modifications and variations. The scope of the present invention is defined not by the above-described embodiments but by the claims. Furthermore, the scope of the present invention includes modifications and variations from the embodiments within the scope of the claims and their equivalents.

[0046] In each embodiment, an electronic component including a capacitor and an inductor as a passive component is shown, but the present invention can be similarly applied to an electronic component including both a passive component and an active component.

[0047] In the second to fifth embodiments, examples of electronic components have been shown in which, when viewed in a direction perpendicular to the surface of the semiconductor substrate 1, the opposing portions between the second internal electrode 3B and the first internal electrodes 3A1, 3A2 are opposed in an uneven manner, but the present invention can also be applied to electronic components in which, when viewed in a direction perpendicular to the surface of the semiconductor substrate 1, the opposing portions between the second internal electrode 3B and the first internal electrodes 3A1, 3A2 are opposed in a comb-tooth manner. [Explanation of symbols]

[0048] C0, C1...capacitors L1...inductor R1: Resistor T1, T2...Terminals 1...Semiconductor substrate 2...Insulator layer 3A1,3A2…1st internal electrode 3B…Second internal electrode 4...Dielectric layer 5A1,5A2…1st extraction electrode 5B1,5B2…Second extraction electrode 6A…1st external electrode 6B…Second external electrode 10...Protective film 11...Semiconductor substrate 12...Well 13...Diffusion layer 15...Gate insulating film 101, 102, 103, 104, 105...Electronic components 106...Gate 108...Wiring layer 113...Interlayer insulating film 115...Protective layer 116...Contact hole

Claims

1. a semiconductor substrate; an insulator layer formed on a surface side of the semiconductor substrate; an internal electrode formed in the insulator layer; a dielectric layer formed on a surface layer of the semiconductor substrate; A lead electrode is disposed on a surface layer side of the internal electrode and is electrically connected to the internal electrode; an external electrode that is electrically connected to the extraction electrode on the surface side of the extraction electrode; Equipped with the internal electrodes include a first internal electrode that is electrically connected to the semiconductor substrate and a second internal electrode that is formed on a surface side of the dielectric layer, the extraction electrode includes a first extraction electrode that is electrically connected to the first internal electrode and a second extraction electrode that is electrically connected to the second internal electrode, the external electrodes include a first external electrode electrically connected to the first extraction electrode and a second external electrode electrically connected to the second extraction electrode; the second extraction electrode is formed inside the second internal electrode when viewed in a direction perpendicular to the surface of the semiconductor substrate, the dielectric layer is a thermal oxide film of the semiconductor substrate, The second internal electrode and the semiconductor substrate sandwich the dielectric layer therebetween, and each of the second internal electrode and the semiconductor substrate abuts on the dielectric layer, thereby constituting a capacitor. Electronic components.

2. When viewed in a direction perpendicular to the surface of the semiconductor substrate, the opposing portions of the first internal electrode and the second internal electrode are opposed to each other in an uneven or comb-teeth shape. The electronic component according to claim 1 .

3. The electronic component according to claim 2 , wherein the distance between opposing sides of the first internal electrode and the second internal electrode is constant.

4. 3. The electronic component according to claim 2, wherein the first internal electrode has an extension portion that extends linearly toward the second extraction electrode, and the second internal electrode is arranged to surround the extension portion of the first internal electrode.

5. 3. The electronic component according to claim 2, wherein the second internal electrode has an extension portion that extends linearly toward the first extraction electrode, and the first internal electrode is arranged to surround the extension portion of the second internal electrode.

6. 2. The electronic component according to claim 1, wherein the dielectric layer is also formed in a trench formed in a portion of the semiconductor substrate.

7. the dielectric layer is also formed between the semiconductor substrate and the first internal electrode; The electronic component according to claim 1 .

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