Semiconductor Devices

Abstract

To suppress interference of heat.SOLUTION: A semiconductor device comprises: a source bus bar 22 provided on a first surface of a substrate 10 and overlapping a first via hole 32 penetrating the substrate when viewed from a thickness direction of the substrate; a plurality of first transistors arranged in a second direction crossing a first direction, each of the first transistors including a first source finger 12a, a first drain finger 16a, and a first gate finger 14a which extend in the first direction on the first surface, the first source finger being electrically connected to the source bus bar; and a plurality of second transistors sandwiching the source bus bar with the plurality of first transistors and arranged in the second direction, each of the second transistors including a second source finger 12b, a second drain finger 16b, and a second gate finger 14b which extend in the first direction on the first surface, the second source finger being electrically connected to the source bus bar.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] In a field effect transistor (FET) having a source, a gate, and a drain, it is known to arrange a plurality of unit FETs, each having a source finger, a gate finger, and a drain finger, in the direction in which the fingers extend (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-299351 Summary of the Invention [Problem to be solved by the invention]

[0004] Thermal interference may occur between a plurality of unit FET groups provided in the extension direction of the fingers.

[0005] The present disclosure has been made in consideration of the above-mentioned problems, and aims to suppress thermal interference. [Means for solving the problem]

[0006] According to one embodiment of the present disclosure, there is provided a semiconductor device including: a source bus bar provided on a first surface of a substrate and overlapping with a first via hole penetrating the substrate as viewed in a thickness direction of the substrate; a plurality of first transistors extending in a first direction and including first source fingers, first drain fingers, and first gate fingers provided on the first surface, the first source fingers being electrically connected to the source bus bar and arranged in a second direction intersecting the first direction; and a plurality of second transistors extending in the first direction and including second source fingers, second drain fingers, and second gate fingers provided on the first surface, the second source fingers being electrically connected to the source bus bar, the source bus bar being sandwiched between the plurality of first transistors and arranged in the second direction. The first via hole can suppress thermal interference between the first transistor and the second transistor. [Effects of the Invention]

[0007] According to the present disclosure, thermal interference can be suppressed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along the line BB in FIG. [Figure 4] FIG. 4 is a plan view of a semiconductor device according to a first comparative example. [Figure 5] FIG. 5 is a cross-sectional view showing an example in which a semiconductor chip is mounted on a mounting substrate in the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing another example of a via hole in the first embodiment. [Figure 7] FIG. 7 is a plan view of a semiconductor device according to a first modification of the first embodiment. [Figure 8] FIG. 8 is a plan view of a semiconductor device according to a second embodiment. [Figure 9]FIG. 9 is a plan view of a semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is a plan view of a semiconductor device according to a first modification of the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Details of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a semiconductor device including: a source bus bar provided on a first surface of a substrate and overlapping with a first via hole penetrating the substrate as viewed in a thickness direction of the substrate; a plurality of first transistors extending in a first direction and including first source fingers, first drain fingers, and first gate fingers provided on the first surface, the first source fingers being electrically connected to the source bus bar and arranged in a second direction intersecting the first direction; and a plurality of second transistors extending in the first direction and including second source fingers, second drain fingers, and second gate fingers provided on the first surface, the second source fingers being electrically connected to the source bus bar, the source bus bar being sandwiched between the plurality of first transistors and arranged in the second direction. The first via hole can suppress thermal interference between the first transistor and the second transistor. (2) It is preferable that at least a portion of the first via hole is hollow. (3) It is preferable to provide a first metal layer filled in the first via hole and having a thermal conductivity lower than that of the substrate. (4) It is preferable that a plurality of the first via holes are arranged in the second direction. (5) It is preferable that the width of the first via hole in the second direction is larger than the width of the first via hole in the first direction. (6) It is preferable that the semiconductor device further comprises a first gate bus bar provided on the first surface between the plurality of first transistors and the source bus bar, the first gate fingers being electrically connected thereto, and a second gate bus bar provided on the first surface between the plurality of second transistors and the source bus bar, the second gate fingers being electrically connected thereto. (7) It is preferable that the semiconductor device further comprises a first source wiring that electrically connects the first source finger and the source bus bar and intersects the first gate bus bar without contacting it, and a second source wiring that electrically connects the second source finger and the source bus bar and intersects the second gate bus bar without contacting it. (8) It is preferable to have a first drain bus bar provided on the first surface, sandwiching the plurality of first transistors together with the source bus bar and having the first drain fingers connected thereto, and a second drain bus bar provided on the first surface, sandwiching the plurality of second transistors together with the source bus bar and having the second drain fingers connected thereto. (9) It is preferable that the first source finger overlaps with a second via hole that penetrates the substrate when viewed in the thickness direction of the substrate, and the second source finger overlaps with a third via hole that penetrates the substrate when viewed in the thickness direction of the substrate. (10) It is preferable that a second metal layer is provided on a second surface of the substrate opposite to the first surface, and is electrically connected to the source bus bar through the first via hole.

[0010] Specific examples of semiconductor devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] [Example 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB in FIG. The normal direction to the surface 30 of the substrate 10 is defined as the Z direction, the extension direction of each finger as the X direction, and the extension direction of each bus bar as the Y direction. In the plan views such as FIG. 1, the gate fingers 14a and 14b, the gate bus bars 24a and 24b, and the gate pads 25a and 25b are indicated by cross-hatching.

[0012] 1 to 3, in the semiconductor device 50 of the first embodiment, a plurality of FET groups 36a and 36b are provided on the front surface 30 (first surface) of the substrate 10. The FET groups 36a and 36b are arranged in the X direction. The FET group 36a includes a plurality of unit FETs 35a, and the FET group 36b includes a plurality of unit FETs 35b. The unit FETs 35a are arranged in the Y direction, and the unit FETs 35b are arranged in the Y direction. The number of unit FETs 35a in the FET group 36a and the number of unit FETs 35b in the FET group 36b may be plural.

[0013] The substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. The substrate 10 includes active regions 11a and 11b. The region other than the active regions 11a and 11b is an inactive region 13 in which the semiconductor layer 10b has been inactivated by ion implantation or the like. That is, the active regions 11a and 11b are regions in the substrate 10 in which the semiconductor layer 10b has been activated, and the inactive region is a region in which the semiconductor layer 10b has been inactivated. The FET groups 36a and 36b are provided in the active regions 11a and 11b, respectively.

[0014] In the FET group 36a, source fingers 12a (first source fingers), gate fingers 14a (first gate fingers), and drain fingers 16a (first drain fingers) are provided on an active region 11a on the surface 30 of the substrate 10, extending in the X direction (first direction). The planar shapes of the source fingers 12a, gate fingers 14a, and drain fingers 16a are approximately rectangular and extend in the X direction. That is, the long sides of each finger extend in the X direction, and the short sides extend in the Y direction. The source fingers 12a, gate fingers 14a, and drain fingers 16a are arranged in the Y direction.

[0015] Source fingers 12a and drain fingers 16a are arranged alternately in the Y direction. A gate finger 14a is sandwiched between one source finger 12a and one drain finger 16a. The source finger 12a and the drain finger 16a sandwiching the gate finger 14a form one unit FET 35a. Adjacent unit FETs 35a share the source finger 12a or the drain finger 16a. The multiple unit FETs 35a are arranged in the Y direction (second direction).

[0016] In the FET group 36b, a source finger 12b (second source finger), a gate finger 14b (second gate finger), and a drain finger 16b (second drain finger) are similarly provided on an active region 11b on the surface 30 of the substrate 10. The gate finger 14b and the source finger 12b and drain finger 16b sandwiching the gate finger 14b form one unit FET 35b. The multiple unit FETs 35b are arranged in the Y direction (second direction). The direction in which each finger extends and the direction in which the unit FETs 35a (and 35b) are arranged do not need to be orthogonal, as long as they intersect.

[0017] A source bus bar 22, gate bus bars 24a and 24b, and drain bus bars 26a and 26b are provided on an inactive region 13 on the surface 30 of the substrate 10, extending in the Y direction. The source bus bar 22 is provided between the FET groups 36a and 36b. The gate bus bar 24a is provided between the source bus bar 22 and the FET group 36a, and the gate bus bar 24b is provided between the source bus bar 22 and the FET group 36b. The drain bus bar 26a is provided so as to sandwich the FET group 36a between itself and the gate bus bar 24a, and the drain bus bar 26b is provided so as to sandwich the FET group 36b between itself and the gate bus bar 24b.

[0018] In the FET group 36a, the +X side ends of the multiple source fingers 12a are connected to the source bus bar 22 via source wiring 23a. The +X side ends of the multiple gate fingers 14a are connected to the gate bus bar 24a. The -X side ends of the multiple drain fingers 16a are connected to the drain bus bar 26a. In the FET group 36b, the -X side ends of the multiple source fingers 12b are connected to the source bus bar 22 via source wiring 23b. The -X side ends of the multiple gate fingers 14b are connected to the gate bus bar 24b. The +X side ends of the multiple drain fingers 16b are connected to the drain bus bar 26b. The -Y side ends of the gate bus bars 24a and 24b are connected to gate pads 25a and 25b, respectively.

[0019] Via holes 32 are provided below the source bus bars 22, penetrating the substrate 10. The planar shape of the via holes 32 is, for example, a substantially elliptical shape. The major axis direction of the via holes 32 is the Y direction, and the width Wy of the via holes 32 in the Y direction is larger than the width Wx of the via holes 32 in the X direction. A plurality of via holes 32 are provided in the extension direction of one source bus bar 22.

[0020] FET set 38 includes FETs 36a, 36b, source bus bar 22, gate bus bars 24a, 24b, and drain bus bars 26a and 26b.

[0021] As shown in FIG. 2, in the FET group 36a, source fingers 12a, gate fingers 14a, and drain fingers 16a are provided on a semiconductor layer 10b. The source fingers 12a and drain fingers 16a include an ohmic metal layer 18a and a low-resistance layer 18b provided on the semiconductor layer 10b. The ohmic metal layer 18a makes ohmic contact with the semiconductor layer 10b. The material of the low-resistance layer 18b has a lower resistivity than the material of the ohmic metal layer 18a. The low-resistance layer 18b is thicker than the ohmic metal layer 18a. As a result, the sheet resistance of the low-resistance layer 18b is lower than the sheet resistance of the ohmic metal layer 18a. In the FET group 36b, the source fingers 12b and drain fingers 16b also include an ohmic metal layer 18a and a low-resistance layer 18b. The ohmic metal layers 18a in the source fingers 12a, 12b, drain fingers 16a, 16b, and source bus bar 22 are made of the same material and are formed simultaneously. The source fingers 12a, 12b, drain fingers 16a, 16b, source wirings 23a, 23b, and source bus bar 22 low-resistance layer 18b are formed simultaneously. An insulating layer 28 is provided on the semiconductor layer 10b to cover the source fingers 12a, gate fingers 14a, and drain fingers 16a. A metal layer 34 is provided on the back surface 31 (a second surface opposite to the first surface) of the substrate 10. A reference potential, such as a ground potential, is supplied to the metal layer 34.

[0022] As shown in FIG. 3 , the source bus bar 22 includes an ohmic metal layer 18a and a low-resistance layer 18b. The source wiring 23a connecting the source bus bar 22 to the source finger 12a and the source wiring 23b connecting the source bus bar 22 to the source finger 12b include the low-resistance layer 18b but do not include the ohmic metal layer 18a. The gate bus bars 24a and 24b are made of the same metal layer as the gate fingers 14a and 14b and are provided on the semiconductor layer 10b. The source wiring 23a and 23b cross the gate bus bars 24a and 24b without contacting them, respectively, on the gate bus bars 24a and 24b. An insulating layer 28 is provided between the source wiring 23a and 23b and the gate bus bars 24a and 24b.

[0023] Via holes 32 pass through substrate 10 and are connected to source bus bar 22. When viewed in the thickness direction (Z direction) of substrate 10, the area where via holes 32 are connected to source bus bar 22 is contained within source bus bar 22. In other words, no via holes 32 are provided outside source bus bar 22 on front surface 30. A metal layer 34 is provided on back surface 31 of substrate 10. A metal layer 34a is provided on the side and top surfaces of via hole 32. Metal layer 34a electrically connects and shorts metal layer 34 and source bus bar 22. Metal layer 34a is the same metal layer as metal layer 34 and is formed at the same time. A cavity 33 is provided within metal layer 34a in via hole 32. Cavity 33 is filled with a gas such as air.

[0024] If the semiconductor device is, for example, a nitride semiconductor device, the substrate 10a is, for example, a SiC substrate, a silicon substrate, a GaN substrate, or a sapphire substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a GaN layer, an AlGaN layer, and / or an InGaN layer. If the semiconductor device is, for example, a GaAs-based semiconductor device, the substrate 10a is, for example, a GaAs substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a GaAs layer, an AlGaAs layer, and / or an InGaAs layer. The ohmic metal layer 18a is, for example, an adhesion film (e.g., a titanium film) and an aluminum film from the substrate 10 side. The low-resistance layer 18b is, for example, a gold layer. The gate fingers 14a, 14b and the gate bus bars 24a and 24b are, for example, metal films, for example, an adhesion film (e.g., a nickel film) and a gold film from the substrate 10 side. The metal layers 34 and 34a are, for example, an adhesion layer and a gold layer from the substrate 10 side.

[0025] The length in the Y direction of the gate fingers 14a and 14b is the gate length, and is, for example, 0.05 μm to 5 μm. The width in the X direction of the active regions 11a and 11b is the gate width of the unit FETs 35a and 35b, and is, for example, 50 μm to 1000 μm. The width in the Y direction of the source fingers 12a and 12b is, for example, 50 μm to 200 μm, and the width in the Y direction of the drain fingers 16a and 16b is, for example, 5 μm to 500 μm. The width in the X direction of the source bus bar 22 is, for example, 10 μm to 100 μm. The width in the X direction of the gate bus bars 24a and 24b is, for example, 10 μm to 50 μm. The thickness of the substrate 10 is, for example, 10 μm to 500 μm.

[0026] [Comparative Example 1] Fig. 4 is a plan view of a semiconductor device according to Comparative Example 1. As shown in Fig. 4, in a semiconductor device 58 of Comparative Example 1, no via holes 32 are provided in the source bus bar 22. The other configurations are the same as those in Example 1, and therefore description thereof will be omitted.

[0027] In Comparative Example 1, heat generated in the FET group 36a propagates to the FET group 36b, and heat generated in the FET group 36b propagates to the FET 36a. The FET groups 36a and 36b are designed taking into account the heat generated independently from each other. Therefore, if the heat generated in the FET group 36a and the heat generated in the FET group 36b interfere with each other, the operation of each of the FET groups 36a and 36b may differ from the design.

[0028] 1 , in the semiconductor device 50, a plurality of unit FETs 35a (first transistors) and a plurality of unit FETs 35b (second transistors) sandwich a source bus bar 22, and the source fingers 12a and 12b are electrically connected to and short-circuited with the source bus bar 22. In this structure, the source bus bar 22 overlaps with a via hole 32 (first via hole) that penetrates the substrate 10 when viewed in the thickness direction of the substrate 10. The via hole 32 separates heat between the FET groups 36a and 36b. This makes it possible to suppress interference between the heat generated in the FET group 36a and the heat generated in the FET group 36b. This makes it possible to suppress deviations in the operation of each of the FET groups 36a and 36b from the design.

[0029] 2, at least a portion of the via hole 32 is a cavity 33. When the via hole 32 is thus a cavity 33, the via hole 32 can provide better thermal isolation between the FET groups 36a and 36b.

[0030] The metal layer 34 (second metal layer) is provided on the back surface 31 opposite to the front surface 30 of the substrate 10, and is electrically connected to and short-circuited with the source bus bar 22 through the via hole 32. This reduces the inductance between the source bus bar 22 and the metal layer 34. When a reference potential is supplied to the metal layer 34, the source inductance can be reduced.

[0031] The metal layer 34a is provided on the side surface of the via hole 32 and electrically connects the source bus bar 22 and the metal layer 34. The inside of the metal layer 34a in the via hole 32 is a cavity 33. This allows a portion of the via hole 32 to be made into the cavity 33, electrically connecting and shorting the source bus bar 22 and the metal layer 34. In order to provide the cavity 33 in the via hole 32, the thickness T2 of the metal layer 34a in the via hole 32 is preferably equal to or less than 1 / 2 of the thickness T1 of the substrate 10, and more preferably equal to or less than 1 / 10 of the thickness T1.

[0032] Although one via hole 32 may be provided for one source bus bar 22, it is preferable that a plurality of via holes 32 are arranged in the Y direction as shown in Fig. 1. The plurality of via holes 32 allows for better thermal isolation between the FET groups 36a and 36b.

[0033] The width Wy of the via hole 32 in the Y direction is greater than the width Wx in the X direction. This allows for better thermal isolation between the FET groups 36a and 36b. The width Wy is preferably 1.5 times or more, more preferably 2 times or more, of the width Wx. The planar shape of the via hole 32 may be an ellipse, an oval, a rounded rectangle, or a track shape, in addition to an ellipse.

[0034] When viewed from the X direction, the total length of the via holes 32 in the Y direction on the surface 30 is preferably 1 / 5 or more, and more preferably 1 / 2 or more, of the length of the source bus bar 22 in the Y direction on the surface 30, which makes it possible to better isolate heat between the FET groups 36a and 36b.

[0035] FIG. 5 is a cross-sectional view showing an example in which a semiconductor chip is mounted on a mounting substrate in Example 1. As shown in FIG. 5, the semiconductor device 50 of Example 1 is mounted on a mounting substrate 37a using solder 37. The via holes 32 are filled with solder 37. The thermal conductivities of the SiC substrate and silicon substrate used as the substrate 10a are 200 W / (m·K) to 450 W / (m·K) and 162 W / (m·K), respectively. In contrast, the thermal conductivity of the solder 37 is low. For example, the thermal conductivity of tin-silver-copper solder is 55 W / (m·K). Therefore, even when the cavity 33 in the via holes 32 is filled with solder 37, the via holes 32 enable thermal isolation between the FET groups 36a and 36b.

[0036] FIG. 6 is a cross-sectional view showing another example of a via hole in Example 1. As shown in FIG. 6, a metal layer 39 (first metal layer) is filled in the via hole 32 so that no voids are formed. Even with this via hole 32 structure, if the thermal conductivity of the substrate 10a is higher than that of the metal layer 39, the via hole 32 can separate heat from the FET groups 36a and 36b. For example, the thermal conductivities of copper and gold are 386 W / (m·K) and 295 W / (m·K), respectively, which are lower than that of SiC. The thermal conductivity of the metal layer 39 is preferably 0.9 times or less, more preferably 0.8 times or less, of the thermal conductivity of the substrate 10a.

[0037] By providing the metal layer 34 on the rear surface 31 of the substrate 10 and the lower surface of the metal layer 39, the metal layer 34 and the source bus bar 22 can be electrically connected and short-circuited, thereby suppressing the source inductance.

[0038] The gate bus bar 24a may be provided between the drain bus bar 26a and the FET group 36a, and the gate bus bar 24b may be provided between the drain bus bar 26b and the FET group 36b. In this case, the direction in which a high-frequency signal is input from the gate bus bar 24a to the gate finger 14a is opposite to the direction in which the high-frequency signal is output from the drain finger 16a to the drain bus bar 26a. As a result, the phases of the input and output signals are not aligned in the X direction, degrading the high-frequency characteristics of the FET group 36a. The same applies to the FET group 36b.

[0039] The gate bus bars 24a and 24b may be commonly provided and provided above the source bus bar 22 in a non-contact manner, in which case the source-gate capacitance increases.

[0040] 1, it is preferable that the gate bus bar 24a (first gate bus bar) is provided on the surface 30 between the plurality of unit FETs 35a and the source bus bar 22, and the gate bus bar 24b (second gate bus bar) is provided on the surface 30 between the plurality of unit FETs 35b and the source bus bar 22. This makes it possible to reduce the source-gate capacitance compared to when the gate bus bar is provided above the source bus bar 22.

[0041] In Comparative Example 1 of Fig. 4, electromagnetic coupling occurs between the gate bus bars 24a and 24b, making it easy for oscillation and the like to occur. In Example 1, the source bus bar 22 is short-circuited to the metal layer 34 to which the ground potential is supplied via the via hole 32. This increases the shielding effect of the source bus bar 22. This suppresses electromagnetic coupling between the gate bus bars 24a and 24b, making it possible to suppress oscillation and the like.

[0042] 3, source wiring 23a (first source wiring) connects source finger 12a to source bus bar 22 and intersects gate bus bar 24a without contacting it. Source wiring 23b (second source wiring) connects source finger 12b to source bus bar 22 and intersects gate bus bar 24b without contacting it. This makes it possible to prevent electrical contact between source bus bar 22 and gate bus bars 24a and 24b, even if gate bus bar 24a is provided between source bus bar 22 and FET group 36a and gate bus bar 24b is provided between source bus bar 22 and FET group 36b.

[0043] The drain bus bar 26a (first drain bus bar) sandwiches multiple unit FETs 35a between itself and the source bus bar 22, and the drain bus bar 26b (second drain bus bar) sandwiches multiple unit FETs 35b between itself and the source bus bar 22. This ensures that the direction in which a high-frequency signal is input from the gate bus bar 24a to the gate finger 14a is the same as the direction in which a high-frequency signal is output from the drain finger 16a to the drain bus bar 26a. This ensures that the phases of the input and output signals are aligned in the X direction, preventing degradation of the high-frequency characteristics of the FET group 36a. The same is true for the FET group 36b.

[0044] [Modification 1 of Example 1] FIG. 7 is a plan view of a semiconductor device according to a first modification of the first embodiment. As shown in FIG. 7, in a semiconductor device 51, a plurality of FET sets 38 are arranged in the X direction. Gate pads 25a and 25b are provided on the -Y side of the FET groups 36a and 36b. The gate pads 25a and 25b are connected to the gate bus bars 24a and 24b, respectively, and have the same potential as the gate bus bars 24a and 24b, respectively. Drain pads 27a and 27b are provided on the +Y side of the FET groups 36a and 36b. The drain pads 27a and 27b are connected to the drain bus bars 26a and 26b, respectively, and have the same potential as the drain bus bars 26a and 26b, respectively. The gate pad 25a and the drain pad 27a are pads for electrically connecting the unit FET 35a to the outside, and the gate pad 25b and the drain pad 27b are pads for electrically connecting the unit FET 35b to the outside.

[0045] As shown in FIG. 7 , multiple FET sets 38 may be arranged in the X direction. In this case, for example, the leftmost FET group 36a and the rightmost FET group 36b have FET groups on only one side, making them less likely to heat up during operation. For this reason, the leftmost FET group 36a and the rightmost FET group 36b may be designed differently from the other FET groups 36a and 36b. In such a design, if there is significant thermal interference between the leftmost FET group 36a and the adjacent FET group 36b, the leftmost FET group 36a may be affected by the heat of the adjacent FET group 36b and may not operate as designed. Therefore, via holes 32 are provided in the source bus bar 22 located between the leftmost FET group 36a and the adjacent FET group 36b. This allows thermal isolation between the leftmost FET group 36a and the adjacent FET group 36b. The same applies to the rightmost FET group 36b and the adjacent FET group 36a.

[0046] In FIG. 7 , one gate bus bar 24a and one drain bus bar 26a and one drain bus bar 26b are electrically connected to one gate pad 25a and one drain pad 27a and one drain bus bar 26b. The gate pads 25a and 25b in the same FET set 38 may form one gate pad. The drain pads 27a and 27b in the same FET set 38 may form one drain pad. Multiple gate bus bars 24a and 24b may be electrically connected to one gate pad, and multiple drain bus bars 26a and 26b may be electrically connected to one drain pad. All multiple gate bus bars 24a and 24b on the substrate 10 may be electrically connected to one gate pad, and all multiple drain bus bars 26a and 26b on the substrate 10 may be electrically connected to one drain pad.

[0047] [Example 2] Example 2 is an example of a semiconductor device in which a semiconductor device 51, which is a semiconductor chip according to Modification 1 of Example 1, is mounted in a package. Fig. 8 is a plan view of the semiconductor device according to Example 2. In Fig. 8, gate pads 25a and 25b, drain pads 27a and 27b, conductor patterns 42, 45, and 48, input terminal 62, and output terminal 63 are indicated by cross-hatching.

[0048] As shown in FIG. 8, in semiconductor device 52, an insulating frame 61 made of ceramic or the like is mounted on a base 60 made of metal such as copper. An input terminal 62 and an output terminal 63 are provided on frame 61. Chips 40, 43, 46, and semiconductor device 52 are mounted on base 60. Chip 40 includes a dielectric layer 41, a conductor pattern 42 provided on dielectric layer 41, and a conductor pattern (not shown) provided below dielectric layer 41. Chip 43 includes a dielectric layer 44 and a conductor pattern 45 provided on dielectric layer 44. Chip 46 includes a dielectric layer 47 and a conductor pattern 48 provided on dielectric layer 47. The conductor patterns 42, 45, 48, the input terminal 62, and the output terminal 63 are metal layers such as gold layers. Gate pads 25a and 25b and drain pads 27a and 27b are provided on semiconductor device 52. In FIG. 8, elements other than the gate pads 25a and 25b and the drain pads 27a and 27b of the semiconductor device 52 are omitted from the illustration.

[0049] A bonding wire 64 electrically connects the input terminal 62 and the conductor pattern 42. A bonding wire 65 electrically connects the conductor patterns 42 and 45. A bonding wire 66 electrically connects the conductor pattern 45 and the gate pads 25a and 25b. A bonding wire 67 electrically connects the drain pads 27a and 27b and the conductor pattern 48. A bonding wire 68 electrically connects the conductor pattern 48 and the output terminal 63.

[0050] Conductor pattern 42 is a pattern for aligning the electrical length between bonding wires 64 and 65. Conductor pattern 45 sandwiching dielectric layer 44 and the conductive pattern below dielectric layer 44 function as a shunt-connected capacitor. Bonding wires 65 and 66 and chip 43 form an input matching circuit. Conductor pattern 48 is a pattern for aligning the electrical length between bonding wires 67 and 66. A high-frequency signal input from input terminal 62 is input to semiconductor device 52 via chips 40 and 43. A high-frequency signal amplified in semiconductor device 52 is output from output terminal 63 via chip 46. As shown in FIG. 7 of Modification 2 of Example 1, gate pads 25a and 25b and drain pads 27a and 27b are provided on the long sides of substrate 10. This allows bonding wires 65 and 67 to be easily bonded to gate pads 25a and 25b and drain pads 27a and 27b. As in the second embodiment, the semiconductor device of the first embodiment and its modified example may have a configuration in which a semiconductor chip is mounted in a package.

[0051] [Example 3] Fig. 9 is a plan view of a semiconductor device according to a third embodiment. As shown in Fig. 9, in a semiconductor device 53, a via hole 32a is provided in a source finger 12a, and a via hole 32b is provided in a source finger 12b. The via holes 32a and 32b have the same cross-sectional shape as the via hole 32 in Fig. 3, 5, or 6, and therefore a description thereof will be omitted. The other configurations are the same as those of the first embodiment, and therefore a description thereof will be omitted.

[0052] According to the third embodiment, the source finger 12a overlaps with the via hole 32a (second via hole) that penetrates the substrate 10 when viewed in the thickness direction of the substrate 10. The source finger 12b overlaps with the via hole 32b (third via hole) that penetrates the substrate 10 when viewed in the thickness direction of the substrate 10. This allows the unit FETs 35a in the FET group 36a to be thermally isolated from each other, and the unit FETs 35b in the FET group 36b to be thermally isolated from each other.

[0053] The source finger 12a is electrically connected to and shorted with the metal layer 34 through a via hole 32a. The source finger 12b is electrically connected to and shorted with the metal layer 34 through a via hole 32b. This reduces the source inductance of the unit FETs 35a and 35b.

[0054] [Modification 1 of Example 3] 10 is a plan view of a semiconductor device according to a first modification of the third embodiment. As shown in FIG. 10, in a semiconductor device 54, a plurality of FET sets 38, the same as in the third embodiment, are arranged in the X direction. A via hole 32a is provided in the source finger 12a, and a via hole 32b is provided in the source finger 12b. The other configurations are the same as in the third embodiment, and a description thereof will be omitted. As in the first modification of the third embodiment, a plurality of FET sets 38 may be arranged in the X direction.

[0055] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0056] 10, 10a board 10b Semiconductor layer 11a, 11b active area 12a, 12b Source Fingers 13 Inactive area 14a, 14b Gate fingers 16a, 16b Drain fingers 18a Ohmic metal layer 18b Low resistance layer 22 Source busbar 23a, 23b Source wiring 24a, 24b Gate bus bar 25a, 25b Gate pads 26a, 26b Drain busbar 27a, 27b drain pad 28 Insulating layer 30 surface 31 Back side 32, 32a, 32b via holes 33 Cavity 34, 34a, 39 metal layer 35a, 35b unit FET 36a, 36b FET group 37 Solder 37a mounting board 38 FET set 40, 43, 46 chips 41, 44, 47 Dielectric layers 42, 45, 48 Conductor patterns 50-54, 58 Semiconductor devices 60 base 61 Frame 62 input terminals 63 Output terminal 64~68 Bonding wire

Claims

1. A substrate having a rectangular planar shape; a source bus bar provided on a first surface of the substrate, penetrating the substrate when viewed in a thickness direction of the substrate, and overlapping with a first via hole having an elliptical shape or a track shape; a plurality of first transistors extending in a first direction and including first source fingers, first drain fingers, and first gate fingers provided on the first surface, the first source fingers being electrically connected to the source bus bar, the first transistors being arranged in a second direction intersecting the first direction; a plurality of second transistors arranged in the second direction, the second transistors including second source fingers, second drain fingers, and second gate fingers extending in the first direction and provided on the first surface, the second source fingers being electrically connected to the source bus bar, the second transistors sandwiching the source bus bar with the plurality of first transistors; Equipped with The semiconductor device is such that the major axis of the first via hole is arranged along the direction of the short side of the substrate.

2. 2. The semiconductor device according to claim 1, wherein at least a portion of the first via hole is a cavity.

3. 2. The semiconductor device according to claim 1, further comprising a first metal layer filled in the first via hole and having a thermal conductivity lower than that of the substrate.

4. The semiconductor device according to claim 1 , wherein a plurality of the first via holes are arranged in the second direction.

5. 5. The semiconductor device according to claim 1, wherein the width of the first via hole in the second direction is larger than the width of the first via hole in the first direction.

6. a first gate bus bar provided on the first surface between the plurality of first transistors and the source bus bar, the first gate finger being electrically connected to the first gate bus bar; a second gate bus bar provided on the first surface between the plurality of second transistors and the source bus bar, the second gate fingers being electrically connected to the second gate bus bar; The semiconductor device according to claim 1 , comprising:

7. a first source wiring that electrically connects the first source finger and the source bus bar and crosses the first gate bus bar without contacting the first source wiring; a second source wiring that electrically connects the second source finger and the source bus bar and crosses the second gate bus bar without contacting the second source wiring; The semiconductor device according to claim 6 , comprising:

8. a first drain bus bar provided on the first surface, sandwiching the plurality of first transistors between the first drain bus bar and the source bus bar, and connected to the first drain fingers; a second drain bus bar provided on the first surface, sandwiching the plurality of second transistors between the second drain bus bar and the source bus bar, and connected to the second drain fingers; The semiconductor device according to claim 6 or 7, comprising:

9. A source bus bar provided on a first surface of the substrate and overlapping with a first via hole penetrating the substrate when viewed in the thickness direction of the substrate; a plurality of first transistors extending in a first direction and including first source fingers, first drain fingers, and first gate fingers provided on the first surface, the first source fingers being electrically connected to the source bus bar, the first transistors being arranged in a second direction intersecting the first direction; a plurality of second transistors arranged in the second direction, the second transistors including second source fingers, second drain fingers, and second gate fingers extending in the first direction and provided on the first surface, the second source fingers being electrically connected to the source bus bar, the second transistors sandwiching the source bus bar with the plurality of first transistors; Equipped with the first source finger overlaps a second via hole penetrating the substrate when viewed in a thickness direction of the substrate; The semiconductor device, wherein the second source finger overlaps a third via hole that penetrates the substrate when viewed in a thickness direction of the substrate.

10. 10. The semiconductor device according to claim 1, further comprising: a second metal layer provided on a second surface of the substrate opposite the first surface, the second metal layer being electrically connected to the source bus bar through the first via hole.

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