Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device and a manufacturing method for semiconductor device, each enabling suppression of leakage current.SOLUTION: A semiconductor device includes: a semiconductor layer; a first insulating film provided on the semiconductor layer and having a first opening formed therein; an ohmic electrode in ohmic contact with the semiconductor layer through the first opening; a gate electrode provided on the first insulating film; and a second insulating film that covers at least a part of the side surface of the ohmic electrode on the gate electrode side and is continuous with the first insulating film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] A method for manufacturing a semiconductor device is disclosed in which a silicon nitride film is formed on a semiconductor layer, an opening is formed in the silicon nitride film, and an ohmic electrode is formed in the opening. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-216188 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, semiconductor devices have become increasingly miniaturized, and as the miniaturization progresses, there is a risk that leakage current will increase.

[0005] An object of the present disclosure is to provide a semiconductor device capable of suppressing leakage current and a method for manufacturing the semiconductor device. [Means for solving the problem]

[0006] The semiconductor device of the present disclosure includes a semiconductor layer, a first insulating film provided on the semiconductor layer and having a first opening formed therein, an ohmic electrode in ohmic contact with the semiconductor layer through the first opening, a gate electrode provided on the first insulating film, and a gate electrode of the ohmic electrode. All of the sides on both sides and the first insulating film covers the End of a second insulating film continuous with the wherein the first insulating film is a nitride film and the second insulating film is an aluminum oxide film. . [Effects of the Invention]

[0007] According to the present disclosure, leakage current can be suppressed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a ninth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a semiconductor device according to a modification of the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 14] FIG. 14 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 15] FIG. 15 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 16]FIG. 16 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 17] FIG. 17 is a cross-sectional view showing a semiconductor device according to a first modification of the second embodiment. [Figure 18] FIG. 18 is a cross-sectional view showing a semiconductor device according to a second modification of the second embodiment. [Figure 19] FIG. 19 is a cross-sectional view showing a semiconductor device according to a third modification of the second embodiment. [Figure 20] FIG. 20 is a cross-sectional view showing a semiconductor device according to a fourth modification of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer, a first insulating film provided on the semiconductor layer and having a first opening formed therein, an ohmic electrode making ohmic contact with the semiconductor layer through the first opening, a gate electrode provided on the first insulating film, and a second insulating film covering at least a portion of a side surface of the ohmic electrode facing the gate electrode and continuous with the first insulating film.

[0011] The second insulating film, which covers at least a portion of the side surface of the ohmic electrode facing the gate electrode, is continuous with the first insulating film, so that the ohmic electrode is electrically insulated from the upper surface of the first insulating film by the second insulating film, thereby suppressing leakage current that flows between the ohmic electrode and the gate electrode along the upper surface of the first insulating film.

[0012] [2] In [1], the first insulating film may be a nitride film, and the second insulating film may be an oxide film. In this case, the first insulating film can easily protect the surface of the semiconductor layer, and the second insulating film can be formed by oxidizing the ohmic electrode.

[0013] [3] In the configuration [1] or [2], the second insulating film may have a thickness of 3 nm or more. The thicker the second insulating film, the easier it is to suppress leakage current.

[0014] [4] In any one of [1] to [3], the second insulating film may be in contact with an upper surface of the first insulating film. In this case, electrical resistance to a leakage current that passes through the upper surface of the first insulating film between the ohmic electrode and the gate electrode can be easily increased, and the leakage current can be easily suppressed.

[0015] [5] In [4], the second insulating film may be in contact with the upper surface of the first insulating film over a range of 3 nm or more in cross section. The wider the area over which the second insulating film is in contact with the upper surface of the first insulating film, the easier it is to suppress leakage current.

[0016] [6] A semiconductor device according to another aspect of the present disclosure includes a semiconductor layer, a first insulating film provided on the semiconductor layer and having a first opening and a second opening, an ohmic electrode in ohmic contact with the semiconductor layer through the first opening, a gate electrode in Schottky contact with the semiconductor layer through the second opening, and a second insulating film covering a side surface of the ohmic electrode facing the gate electrode and in contact with an upper surface of the first insulating film over a range of 3 nm or more in cross section, wherein the first insulating film is a nitride film and the second insulating film is an oxide film.

[0017] The second insulating film covering the side surface of the ohmic electrode facing the gate electrode is in contact with the top surface of the first insulating film over a range of 3 nm or more in cross section, so the ohmic electrode is electrically insulated from the top surface of the first insulating film by the second insulating film, thereby suppressing leakage current that flows between the ohmic electrode and the gate electrode along the top surface of the first insulating film.

[0018] [7] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes the steps of forming a first insulating film on a semiconductor layer, forming a first opening in the first insulating film, forming an ohmic electrode in ohmic contact with the semiconductor layer through the first opening, forming a gate electrode on the first insulating film, and forming a second insulating film that covers at least a portion of a side surface of the ohmic electrode facing the gate electrode and is continuous with the first insulating film.

[0019] Since the second insulating film is formed to cover at least a part of the side surface of the ohmic electrode facing the gate electrode and to be continuous with the first insulating film, the ohmic electrode is electrically insulated from the upper surface of the first insulating film by the second insulating film, thereby suppressing leakage current that flows between the ohmic electrode and the gate electrode along the upper surface of the first insulating film.

[0020] [8] In the method [7], the step of forming the second insulating film may include a step of oxidizing the side surface of the ohmic electrode, which makes it easier to form the second insulating film.

[0021] [Details of the embodiments of the present disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description.

[0022] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Fig. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0023] As shown in FIG. 1, the semiconductor device 1 according to the first embodiment includes a substrate 10 and a stacked structure 20. The substrate 10 is, for example, a SiC substrate having a (0001) plane, and the stacking direction of the stacked structure 20 is, for example, the

[0001] direction. The stacked structure 20 is provided on the substrate 10. The stacked structure 20 includes a nucleation layer 12, a channel layer 14, a barrier layer 16, and a cap layer 18. The stacked structure 20 is an example of a semiconductor layer.

[0024] The nucleation layer 12 is formed on the substrate 10. For example, the nucleation layer 12 is an AlN layer, and the thickness of the nucleation layer 12 is 5 nm to 20 nm. The nucleation layer 12 functions as a seed layer for the channel layer 14.

[0025] The channel layer 14 is formed by epitaxial growth on the nucleation layer 12. For example, the channel layer 14 is an undoped GaN layer, and the thickness of the channel layer 14 is 500 nm. The channel layer 14 functions as an electron transit layer.

[0026] The barrier layer 16 is formed on the channel layer 14 by epitaxial growth. For example, the barrier layer 16 is an AlGaN layer, an InAlN layer, or an InAlGaN layer, and has a thickness of 5 nm to 30 nm. The band gap of the barrier layer 16 is larger than that of the channel layer 14. When the barrier layer 16 is an AlGaN layer, the Al composition of the barrier layer 16 is, for example, 0.15 to 0.35. The conductivity type of the barrier layer 16 is n-type or undoped. The barrier layer 16 and the channel layer 14 may be in contact with each other, or a spacer layer (not shown) may be interposed between the barrier layer 16 and the channel layer 14. Strain occurs between the barrier layer 16 and the channel layer 14 due to the difference in lattice constants between them. As a result, a two-dimensional electron gas (2DEG) resulting from piezoelectric charges is generated in a region on the channel layer 14 side near the interface between the barrier layer 16 and the channel layer 14, forming a channel region. The barrier layer 16 functions as an electron supply layer.

[0027] The cap layer 18 is formed by epitaxial growth on the barrier layer 16. For example, the cap layer 18 is a GaN layer, and the thickness of the cap layer 18 is 5 nm. For example, the conductivity type of the cap layer 18 is n-type.

[0028] The semiconductor device 1 has a passivation film 26. For example, the passivation film 26 is a nitride film such as a silicon nitride film, and the thickness of the passivation film 26 is 10 nm to 100 nm. A source opening 26S, a drain opening 26D, and a gate opening 26G are formed in the passivation film 26. The stacked structure 20 is exposed from the passivation film 26 in the source opening 26S, the drain opening 26D, and the gate opening 26G. Specifically, in the source opening 26S and the drain opening 26D, the cap layer 18 is removed to expose the barrier layer 16. The cap layer 18 is exposed in the gate opening 26G. The passivation film 26 is an example of a first insulating film. The source opening 26S and the drain opening 26D are examples of a first opening, and the gate opening 26G is an example of a second opening.

[0029] The semiconductor device 1 has a source electrode 22, a drain electrode 24, and a gate electrode 28. The source electrode 22 and the drain electrode 24 are arranged in order along the surface of the substrate 10.

[0030] The source electrode 22 covers a source opening 26S of the passivation film 26 and is in ohmic contact with the barrier layer 16 via the source opening 26S. The drain electrode 24 covers a drain opening 26D of the passivation film 26 and is in ohmic contact with the barrier layer 16 via the drain opening 26D. The source electrode 22 and the drain electrode 24 are formed by heat treating a titanium (Ti) layer and an aluminum (Al) layer that are provided in this order from the stacked structure 20 side. The source electrode 22 and the drain electrode 24 are examples of ohmic electrodes.

[0031] The source electrode 22 has a lower portion 221 in the source opening 26S and an upper portion 222 on the lower portion 221. The lower portion 221 is in contact with the sidewall surface of the source opening 26S. The upper portion 222 is formed on a pair of side surfaces 22 2 a and 22 2 b, and in plan view, the side surface 22 2 a and 22 2 b is located inside the side wall surface of the source opening 26S. 2 a and 22 2 The angle b is approximately perpendicular to the upper surface 26x of the passivation film 26. Therefore, the cross-sectional shape of the upper portion 222 is approximately rectangular.

[0032] The drain electrode 24 has a lower portion 241 in the drain opening 26D and an upper portion 242 on the lower portion 241. The lower portion 241 is in contact with the sidewall surface of the drain opening 26D. The upper portion 242 is in contact with the pair of side surfaces 24 2 a and 24 2 b, and the side surface is 24 2 a and 24 2 b is located inside the side wall surface of the drain opening 26D. 2 a and 24 2 The angle b is approximately perpendicular to the upper surface 26x of the passivation film 26. Therefore, the cross-sectional shape of the upper portion 242 is approximately rectangular.

[0033] The gate electrode 28 is provided on the stacked structure 20 between the source electrode 22 and the drain electrode 24. The gate electrode 28 covers the gate opening 26G of the passivation film 26 and is in Schottky contact with the cap layer 18 via the gate opening 26G. The gate electrode 28 has, for example, a nickel (Ni) layer, a gold (Au) layer, and a tantalum (Ta) layer provided in this order from the stacked structure 20 side.

[0034] Side 22 of source electrode 22 2 a is side 22 2 b, and the side surface 24 of the drain electrode 24 2 a is side 24 2 It is located closer to the gate electrode 28 and source electrode 22 than b.

[0035] The semiconductor device 1 has insulating films 32 and 34. The insulating film 32 is formed on the side surface 22 of the source electrode 22. 2 a and 22 2 The insulating film 34 covers the side surface 24 b of the drain electrode 24. 2 a and 24 2 b. The insulating films 32 and 34 are in contact with and continuous with the passivation film 26. The insulating film 32 also covers the upper surface of the source electrode 22, and the insulating film 34 also covers the upper surface of the drain electrode 24. In plan view, the side surface of the insulating film 32 is flush with the side wall surface of the source opening 26S or is located inside the side wall surface of the source opening 26S, and the side surface of the insulating film 34 is flush with the side wall surface of the drain opening 26D or is located inside the drain opening 26D. For example, the insulating films 32 and 34 are oxide films such as aluminum oxide films, and the thickness of the insulating films 32 and 34 is 3 nm or more and 20 nm or less. The insulating films 32 and 34 are an example of a second insulating film.

[0036] The semiconductor device 1 has an insulating film 30. The insulating film 30 is a protective film that covers the gate electrode 28 and is made of an insulating material containing Si, such as a SiN film, a SiO2 film, or a SiON film. For example, the thickness of the insulating film 30 is 200 nm to 400 nm.

[0037] Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described. Figures 2 to 10 are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.

[0038] First, as shown in FIG. 2, a stacked structure 20 including multiple nitride semiconductor layers is grown on a substrate 10 by metal organic chemical vapor deposition (MOCVD). Specifically, a nucleation layer 12 is first grown on the substrate 10. When the nucleation layer 12 is an AlN layer, the source gases are, for example, TMA (trimethylaluminum) and NH3 (ammonia), and the growth temperature is, for example, 1100°C. Next, a channel layer 14 is grown on the nucleation layer 12. When the channel layer 14 is a GaN layer, the source gases are, for example, TMG (trimethylgallium) and NH3, and the growth temperature is, for example, 1050°C. Next, a barrier layer 16 is grown on the channel layer 14. When the barrier layer 16 is an AlGaN layer, the source gases are, for example, TMA, TMG, and NH3, and the growth temperature is, for example, 1050°C. Next, a cap layer 18 is grown on the barrier layer 16. When the cap layer 18 is a GaN layer, the source gas is, for example, TMG and NH3, and the growth temperature is, for example, 1050°C.

[0039] Next, as shown in FIG. 3, a passivation film 26 in contact with the upper surface of the stacked structure 20 is formed using low-pressure CVD or plasma CVD. For example, when low-pressure CVD is used, the film formation temperature is 600°C to 850°C, and the growth pressure is, for example, 10 Pa to 50 Pa. The passivation film 26 formed by low-pressure CVD is denser and harder than when formed by plasma CVD. After forming a portion (lower layer) of the passivation film 26 by low-pressure CVD, the remaining portion (upper layer) of the passivation film 26 may be formed by plasma CVD. When forming the passivation film 26 by low-pressure CVD, ammonia gas and dichlorosilane (SiH2Cl2) are used as raw material gases.

[0040] 4, photoresist 52 and photoresist 54 are applied in this order on passivation film 26. For example, the material of photoresist 54 is polymethylglutarimide (PMGI), and photoresist 54 is an i-line resist. Next, by photolithography, an opening 54S for a source and an opening 54D for a drain are formed in photoresist 54, and an opening 52S for a source and an opening 52D for a drain are formed in photoresist 52. A portion of passivation film 26 is exposed through openings 54S and 52S, and another portion of passivation film 26 is exposed through openings 54D and 52D.

[0041] 5, using the photoresists 52 and 54 as masks, reactive ion etching (RIE) is performed to form a source opening 26S and a drain opening 26D in the passivation film 26 and the stacked structure 20. For example, a reactive gas containing fluorine (F) is used to etch the passivation film 26, and a reactive gas containing chlorine (Cl) is used to etch the stacked structure 20.

[0042] Next, as shown in FIG. 6, a metal layer 62 is formed by vapor deposition inside the source opening 26S and the drain opening 26D. The metal layer 62 is formed so as to protrude upward from the source opening 26S and the drain opening 26D. The metal layer 62 also adheres to the upper surface of the photoresist 54 and the sidewall surfaces of the opening 54S and the opening 54D. The metal layer 62 includes, for example, a Ti layer and an Al layer formed in this order from the substrate 10 side. For example, the Ti layer has a thickness of 30 nm, and the Al layer has a thickness of 300 nm.

[0043] Next, as shown in FIG. 7, the photoresists 52 and 54 are removed. As the photoresist 54 is removed, the portion of the metal layer 62 that is attached to the photoresist 54 is also removed. Meanwhile, the metal layer 62 remains inside the source opening 26S and the drain opening 26D. In other words, lift-off is performed. As a result, the source electrode 22 is formed in the source opening 26S, and the drain electrode 24 is formed in the drain opening 26D. The source electrode 22 has a lower portion 221 in the source opening 26S and an upper portion 222 on the lower portion 221. The drain electrode 24 has a lower portion 241 in the drain opening 26D and an upper portion 242 on the lower portion 241. The upper portion 222 Aspects of may be substantially flush with the sidewall surface of the source opening 26S, and the upper portion 242 Aspects of The source opening 26S and the drain opening 26D may be substantially flush with the sidewall surface of the drain opening 26D. To achieve such a shape, the shapes of the photoresists 52 and 54 may be adjusted, or the source opening 26S and the drain opening 26D may be widened by etching.

[0044] 8, the surfaces of the source electrode 22 and the drain electrode 24 are oxidized to form insulating films 32 and 34. The source electrode 22 and the drain electrode 24 are oxidized by, for example, plasma oxidation. 2 a and 22 2 b of the drain electrode 24. 2 a and 24 2 The insulating films 32 and 34 are in contact with the passivation film 26 and are continuous with the passivation film 26.

[0045] Next, the source electrode 22 and the drain electrode 24 are alloyed by heat treatment. The alloying temperature is, for example, 600° C. electrode 22 The drain electrode 24 comes into ohmic contact with the stacked structure 20 .

[0046] Next, as shown in FIG. 9, a gate opening 26G is formed in the passivation film 26. To form the gate opening 26G, a resist mask having an opening corresponding to the gate opening 26G is formed on the passivation film 26, and the passivation film 26 is etched through the resist mask. For example, a reactive gas containing fluorine is used to etch the passivation film 26. Thereafter, the resist mask is removed. Next, a gate electrode 28 is formed in Schottky contact with the stacked structure 20 through the gate opening 26G. The gate electrode 28 includes, for example, a Ni layer, an Au layer, and a Ta layer, which are formed in this order from the substrate 10 side.

[0047] 10, an insulating film 30 that covers the gate electrode 28 is formed on the passivation film 26. The insulating film 30 is formed by, for example, a plasma CVD method.

[0048] Thereafter, wiring and the like are formed as necessary. In this manner, the semiconductor device 1 according to the first embodiment can be manufactured.

[0049] In the first embodiment, the side surface 22 of the source electrode 22 2 An insulating film 32 is formed on the side surface 24 of the drain electrode 24. 2 a, and the insulating films 32 and 34 are continuous with the passivation film 26. Therefore, the source electrode 22 and the drain electrode 24 are electrically insulated from the upper surface 26x of the passivation film 26 by the insulating film 32. Furthermore, compared to the state before the insulating films 32 and 34 are formed, the distance between the source electrode 22 and the gate electrode 28 is increased by the thickness of the insulating film 32, and the distance between the drain electrode 24 and the gate electrode 28 is increased by the thickness of the insulating film 32. Therefore, leakage current passing through the upper surface 26x of the passivation film 26 between the source electrode 22 and the gate electrode 28 can be suppressed. Similarly, leakage current passing through the upper surface 26x of the passivation film 26 between the drain electrode 24 and the gate electrode 28 can be suppressed.

[0050] Furthermore, since the passivation film 26 is a nitride film, it is easy for the passivation film 26 to protect the surface of the semiconductor stacked structure 20. Furthermore, since the insulating films 32 and 34 are oxide films, the insulating films 32 and 34 can be formed by oxidizing the ohmic electrodes.

[0051] As described above, the thickness of the insulating films 32 and 34 is, for example, 3 nm or more. Although a natural oxide film is formed on the surface of aluminum, the thickness of the natural oxide film is at most about 2 nm, and the natural oxide film does not function as an insulating film. The thickness of the insulating films 32 and 34 is preferably 5 nm or more, and more preferably 10 nm or more. The thicker the insulating films 32 and 34 are, the easier it is to suppress leakage current. The thickness of the insulating film 32 is determined by the thickness of the side surface 22. 2 On the side of a 22 2 The thickness in the direction perpendicular to a and the side 22 2 On b, side 22 2 The thickness of the insulating film 34 is the thickness in the direction perpendicular to the side surface 24 b. 2 On the side of a 24 2 The thickness in the direction perpendicular to a is 2 On b, side 24 2 is the thickness in the direction perpendicular to b.

[0052] The interface between the source electrode 22 and the insulating film 32 and the interface between the drain electrode 24 and the insulating film 34 can be identified by energy dispersive X-ray spectroscopy (EDX) using a scanning transmission electron microscope (STEM) or a transmission electron microscope (TEM). In the present disclosure, the interface is considered to be located at a position where the detected waveforms of the main elements in each constituent layer intersect in a line scan waveform obtained by EDX.

[0053] (Modification of the first embodiment) Next, a description will be given of a modified example of the first embodiment. Fig. 11 is a cross-sectional view showing a semiconductor device according to a modified example of the first embodiment.

[0054] In the semiconductor device 1A according to the modification of the first embodiment, as shown in FIG. 11, the insulating film 32 is formed on the side surface 22 of the source electrode 22. 2 a and 22 2 b of the source electrode 22, but the top surface of the source electrode 22 is not covered by the insulating film 32. 2 a and 24 2 b, but the upper surface of the drain electrode 24 is not covered by the insulating film 34. The upper surfaces of the source electrode 22 and the drain electrode 24 are covered by the insulating film 30.

[0055] The other configurations are the same as those in the first embodiment.

[0056] This modification also provides the same effects as the first embodiment.

[0057] (Second embodiment) Next, a modified example of the second embodiment will be described below. Fig. 12 is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0058] As shown in FIG. 12, in the semiconductor device 2 according to the second embodiment, the side surface 22 of the upper portion 222 of the source electrode 22 2 a and 22 2 The side surface 22 b is inclined from a plane perpendicular to the upper surface 26 x of the passivation film 26. 2 a and 22 2 The distance b approaches each other as it is farther from the laminated structure 20. Therefore, the cross-sectional shape of the upper portion 222 is approximately trapezoidal.

[0059] Furthermore, the side surfaces 24a and 24b of the upper portion 242 of the drain electrode 24 are inclined from a plane perpendicular to the upper surface 26x of the passivation film 26. The side surfaces 24a and 24b approach each other as they move away from the stacked structure 20. Therefore, the cross-sectional shape of the upper portion 242 is approximately trapezoidal.

[0060] The insulating film 32 is formed on the side surface 22 of the source electrode 22. 2 a and 22 2The insulating film 34 covers the side surface 24 b of the drain electrode 24 and is in contact with the upper surface 26 x of the passivation film 26. 2 a and 24 2 b and contacts the upper surface 26x of the passivation film 26. The insulating films 32 and 34 are continuous with the passivation film 26. For example, the insulating films 32 and 34 contact the upper surface 26x of the passivation film 26 over a width of 3 nm or more in cross section.

[0061] The other configurations are the same as those in the first embodiment.

[0062] Next, a method for manufacturing the semiconductor device 2 according to the second embodiment will be described. Figures 13 to 16 are cross-sectional views showing the method for manufacturing the semiconductor device according to the second embodiment.

[0063] First, similarly to the first embodiment, processing up to the formation of the source opening 26S and the drain opening 26D is performed (see FIG. 5). Next, as shown in FIG. 13, a metal layer 62 is formed inside the source opening 26S and the drain opening 26D by evaporation. At this time, the metal layer 62 is formed not only inside the source opening 26S and the drain opening 26D, but also so as to run onto the passivation film 26 on the sides of the source opening 26S and the drain opening 26D. As in the first embodiment, the metal layer 62 also adheres to the upper surface of the photoresist 54 and the sidewall surfaces of the opening 54S and the opening 54D.

[0064] 14, the photoresists 52 and 54 are removed. As a result, the source electrode 22 including a portion that extends over the passivation film 26 and the drain electrode 24 including a portion that extends over the passivation film 26 are formed.

[0065] 15, the surfaces of the source electrode 22 and the drain electrode 24 are oxidized to form insulating films 32 and 34. Next, the source electrode 22 and the drain electrode 24 are alloyed by heat treatment. As a result, the source opening 26S and the drain electrode 24 come into ohmic contact with the stacked structure 20.

[0066] Next, as shown in FIG. 16, a gate opening 26G is formed in the passivation film 26, a gate electrode 28 is formed, and an insulating film 30 is formed in the same manner as in the first embodiment.

[0067] Thereafter, wiring and the like are formed as necessary. In this manner, the semiconductor device 2 according to the second embodiment can be manufactured.

[0068] The second embodiment also provides the same effects as the first embodiment. Furthermore, in the second embodiment, the insulating films 32 and 34 are in contact with the upper surface 26x of the passivation film 26. This further reduces leakage current that passes through the upper surface 26x of the passivation film 26. Furthermore, the metal layer 62 can be formed not only inside the source opening 26S and inside the drain opening 26D, but also on the passivation film 26 on the sides of the source opening 26S and the drain opening 26D. This makes it easier to fill the source opening 26S and the drain opening 26D with the metal layer 62.

[0069] As described above, the insulating films 32 and 34 are in contact with the upper surface 26x of the passivation film 26 over a cross-sectional area of ​​3 nm or more. Even if a natural oxide film is formed on the surface of aluminum, it will not be thick enough to be in contact with the upper surface 26x of the passivation film 26 over a cross-sectional area of ​​3 nm or more. The insulating films 32 and 34 are preferably in contact with the upper surface 26x of the passivation film 26 over a cross-sectional area of ​​5 nm or more, and preferably in contact with the upper surface 26x of the passivation film 26 over a cross-sectional area of ​​10 nm or more. The wider the area over which the insulating films 32 and 34 are in contact with the upper surface 26x of the passivation film 26, the easier it is to suppress leakage current.

[0070] In the second embodiment, the insulating films 32 and 34 are formed by oxidizing the entire portions of the source electrode 22 and the drain electrode 24 that extend over the passivation film 26, but only a portion of the portions of the source electrode 22 and the drain electrode 24 that extend over the passivation film 26 may be oxidized. That is, in the manufactured semiconductor device 2, a portion of the upper portion 222 of the source electrode 22 may be on the passivation film 26, and a portion of the upper portion 242 of the drain electrode 24 may be on the passivation film 26.

[0071] (First modified example of the second embodiment) Next, a first modification of the second embodiment will be described below. Fig. 17 is a cross-sectional view showing a semiconductor device according to the first modification of the second embodiment.

[0072] In the semiconductor device 2A according to the first modification of the second embodiment, as shown in FIG. 17, the insulating film 32 is formed on the side surface 22 of the source electrode 22. 2 a and 22 2 b of the source electrode 22, but the top surface of the source electrode 22 is not covered by the insulating film 32. 2 a and 24 2 b, but the upper surface of the drain electrode 24 is not covered by the insulating film 34. The upper surfaces of the source electrode 22 and the drain electrode 24 are covered by the insulating film 30.

[0073] The other configurations are the same as those in the second embodiment.

[0074] The first modified example also provides the same effects as the second embodiment.

[0075] (Second Modification of the Second Embodiment) Next, a second modification of the second embodiment will be described below. Fig. 18 is a cross-sectional view showing a semiconductor device according to the second modification of the second embodiment.

[0076] In the semiconductor device 2B according to the second modification of the second embodiment, as shown in FIG. 18, the insulating film 32 is formed on the side surface 22 of the source electrode 22. 2 a and 222 Covering a part of the lower part of b, side 22 2 a and 22 2 The remaining portion of the insulating film 32 is not covered with the insulating film 32. The insulating film 32 is in contact with the upper surface 26x of the passivation film 26 and is continuous with the passivation film 26. In addition, the insulating film 34 is formed on the side surface 24x of the drain electrode 24. 2 a and 24 2 Covering a part of the lower part of b, side 24 2 a and 24 2 The remaining portion of the side surface 22 b is not covered by the insulating film 32. The insulating film 34 is in contact with the upper surface 26 x of the passivation film 26 and is continuous with the passivation film 26. 2 a and 22 2 the remainder of b and the side surface 22 2 a and 22 2 The remaining portion of b is covered with an insulating film 30 .

[0077] The other configuration is the same as that of the first modified example of the second embodiment.

[0078] The second modified example also provides the same effects as the second embodiment.

[0079] (Third modified example of the second embodiment) Next, a description will be given of a third modified example of the second embodiment. Fig. 19 is a cross-sectional view showing a semiconductor device according to the third modified example of the second embodiment.

[0080] In the semiconductor device 2C according to the third modification of the second embodiment, as shown in FIG. 19, the side surface 22 2 a and 22 2 The line b is approximately perpendicular to the upper surface 26x of the passivation film 26, and the cross section of the upper portion 222 is approximately rectangular. 2 a and 24 2 The line b is approximately perpendicular to the upper surface 26x of the passivation film 26, and the cross-sectional shape of the upper portion 242 is approximately rectangular.

[0081] The insulating film 32 is in contact with the upper surface 26x of the passivation film 26 and is continuous with the passivation film 26. The insulating film 34 is in contact with the upper surface 26x of the passivation film 26 and is continuous with the passivation film 26.

[0082] The other configurations are the same as those in the second embodiment.

[0083] The third modified example also provides the same effects as the second embodiment.

[0084] (Fourth Modification of the Second Embodiment) Next, a fourth modification of the second embodiment will be described below. Fig. 20 is a cross-sectional view showing a semiconductor device according to the fourth modification of the second embodiment.

[0085] In the semiconductor device 2D according to the fourth modification of the second embodiment, as shown in FIG. 20, the insulating film 32 is formed on the side surface 22 of the source electrode 22. 2 a and 22 2 b of the source electrode 22, but the top surface of the source electrode 22 is not covered by the insulating film 32. 2 a and 24 2 b, but the upper surface of the drain electrode 24 is not covered by the insulating film 34. The upper surfaces of the source electrode 22 and the drain electrode 24 are covered by the insulating film 30.

[0086] The other configuration is the same as that of the third modified example of the second embodiment.

[0087] The fourth modified example also provides the same effects as the second embodiment.

[0088] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0089] 1, 1A, 2, 2A, 2B, 2C, 2D: Semiconductor device 10: Circuit board 12: Nucleation layer 14: Channel layer 16: Barrier layer 18: Cap layer 20:Laminated structure 22: Source electrode 24: Drain electrode twenty two 2 a, 24 2 a: Side twenty two 2 b, 24 2 b: Side 26: Passivation film 26D: Drain opening 26G: Gate opening 26S: Source opening 26x:Top surface 28: Gate electrode 30, 32, 34: insulating film 52, 54: Photoresist 52D, 52S, 54D, 54S: Opening 62: Metal layer 221, 241: Lower part 222, 242: Upper part

Claims

1. a semiconductor layer; a first insulating film provided on the semiconductor layer and having a first opening; an ohmic electrode making ohmic contact with the semiconductor layer through the first opening; a gate electrode provided on the first insulating film; a second insulating film covering the entire side surfaces of both sides of the ohmic electrode and continuing to an end of the first insulating film; Equipped with the first insulating film is a nitride film, The semiconductor device, wherein the second insulating film is an aluminum oxide film.

2. A semiconductor device as described in claim 1, wherein the second insulating film is spaced apart from the gate electrode.

3. 3. The semiconductor device according to claim 1, wherein the second insulating film has a thickness of 3 nm or more.

4. 3. The semiconductor device according to claim 1, wherein the second insulating film is in contact with an upper surface of the first insulating film.

5. 5. The semiconductor device according to claim 4, wherein the second insulating film is in contact with the upper surface of the first insulating film over a range of 3 nm or more in cross section.

6. a semiconductor layer; a first insulating film provided on the semiconductor layer and having a first opening and a second opening; an ohmic electrode making ohmic contact with the semiconductor layer through the first opening; a gate electrode making Schottky contact with the semiconductor layer through the second opening; a second insulating film covering the entire side surfaces of both sides of the ohmic electrode and contacting an upper surface of an end portion of the first insulating film over a range of 3 nm or more in cross section; and the first insulating film is a nitride film, The second insulating film is an aluminum oxide film.

7. forming a first insulating film on the semiconductor layer; forming a first opening in the first insulating film; forming an ohmic electrode that makes ohmic contact with the semiconductor layer through the first opening; forming a gate electrode on the first insulating film; forming an aluminum oxide film that covers the entire side surfaces of both sides of the ohmic electrode and is continuous with an end portion of the first insulating film; A method for manufacturing a semiconductor device having the above structure.

8. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the step of forming the aluminum oxide film includes a step of oxidizing the side surface of the ohmic electrode.

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