Image inspection method for semiconductor devices and manufacturing method for semiconductor devices

Abstract

To provide an image inspection method of a semiconductor element which accurately detects defects even when no feature point exists in an inspection range.SOLUTION: The image inspection method of a semiconductor element includes steps of: forming alignment marks in inspection ranges on a lower surface of the semiconductor element; photographing an upper surface inspection image and a lower surface inspection image for each inspection range; and performing image inspection with an image inspection device. The image inspection device stores an upper surface normal image and a lower surface normal image. In the image inspection, the image inspection device compares, for each inspection range, the upper surface inspection image to the upper surface normal image on the basis of the alignment mark position included in the lower surface inspection image and the alignment mark position included in the lower surface normal image, and determines thereby whether the upper surface inspection image includes defects.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to an image inspection method for semiconductor devices and a manufacturing method for semiconductor devices.

[0002] Patent Document 1 discloses a technique for detecting the relative positions of a mark on the front surface and a mark on the back surface of a semiconductor substrate with high accuracy. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-084437 Summary of the Invention [Problem to be solved by the invention]

[0004] There is a technology for detecting defects on the surface of a semiconductor element by dividing the surface of the semiconductor element into multiple inspection areas, capturing images of each inspection area, and comparing the captured images with a normal image. With this type of technology, if an inspection area does not contain a feature point, it is difficult to determine the relative positional relationship between the image of the inspection area and the normal image, making it difficult to accurately detect defects. For example, if a corner of an element pattern is present in the inspection area, defects can be accurately detected by comparing the images after aligning the image of the inspection area and the normal image so that the corners of the element pattern coincide. In contrast, if a feature point (e.g., a corner of the element pattern) is not present in the inspection area, alignment between the image of the inspection area and the normal image cannot be performed, making it difficult to accurately detect defects. This specification proposes an image inspection method that can accurately detect defects even if a feature point is not present in the inspection area. [Means for solving the problem]

[0005] In an image inspection method for a semiconductor element (14) disclosed herein, the semiconductor element has a plurality of inspection areas (50). The image inspection method includes the steps of forming alignment marks (20) within each inspection area on the underside (10b) of the semiconductor element, capturing an upper surface inspection image that is an image of the upper surface of the semiconductor element and a lower surface inspection image that is an image of the lower surface of the semiconductor element for each inspection area of ​​the semiconductor element, and performing image inspection using an image inspection device. The image inspection device stores a normal upper surface image that is a normal image of the upper surface of the semiconductor element and a normal lower surface image that is a normal image of the lower surface of the semiconductor element for each inspection area of ​​the semiconductor element. Each of the normal lower surface images is an image that includes the alignment mark. In the image inspection, the image inspection device compares the upper surface inspection image with the normal upper surface image for each inspection area based on the position of the alignment mark included in the lower surface inspection image and the position of the alignment mark included in the normal lower surface image, thereby determining whether or not the upper surface inspection image contains a defect.

[0006] In this image inspection method, a top surface inspection image and a bottom surface inspection image are captured for each inspection range of a semiconductor element. The bottom surface inspection image includes an alignment mark. In the image inspection, the top surface inspection image and the normal top surface image are compared based on the positions of the alignment marks included in the bottom surface inspection image and the normal bottom surface image. That is, the relative positions of the top surface inspection image and the normal top surface image are determined using the alignment marks included in the bottom surface inspection image and the normal bottom surface image, and the top surface inspection image and the normal top surface image are compared based on the relative positions. Therefore, even if there are no feature points on the top surface of the semiconductor element, alignment can be performed between the top surface inspection image and the normal top surface image. Therefore, this inspection method allows for accurate detection of defects even if there are no feature points within the inspection range. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. [Figure 2]FIG. 10 is a plan view of the semiconductor wafer after the top surface reference marks are formed. [Figure 3] FIG. 10 is a cross-sectional view of the semiconductor wafer after the top surface reference marks are formed. [Figure 4] FIG. 2 is a plan view of a semiconductor wafer after semiconductor elements are formed. [Figure 5] FIG. [Figure 6] FIG. 2 is an enlarged plan view showing an inspection range of a semiconductor element. [Figure 7] FIG. 10 is an enlarged plan view of a semiconductor element after alignment marks are formed. [Figure 8] FIG. 10 is a cross-sectional view of the inspection area after the alignment mark is formed. [Figure 9] FIG. 10 is a diagram showing positioning using an upper surface reference mark. [Figure 10] FIG. 2 is an explanatory diagram of an image inspection device 60. [Figure 11] FIG. 4 is an explanatory diagram of the position of an alignment mark. [Figure 12] FIG. 10 is an explanatory diagram of the difference in the positions of alignment marks. [Figure 13] 10 is an explanatory diagram of how to superimpose an upper surface inspection image and an upper surface normal image. [Figure 14] FIG. 10 is a plan view of the semiconductor wafer after the bottom surface reference marks are formed. [Figure 15] FIG. 10 is a cross-sectional view of the semiconductor wafer after the bottom surface reference marks are formed. [Figure 16] FIG. 7 is an explanatory diagram of an image inspection device 70. [Figure 17] 10 is an explanatory diagram of how to superimpose an upper surface inspection image and an upper surface normal image. [Figure 18] FIG. 10 is an explanatory diagram of another form of alignment mark. [Figure 19] FIG. 10 is an explanatory diagram of another form of alignment mark. [Figure 20] FIG. 10 is an explanatory diagram of another form of alignment mark. [Figure 21] FIG. 10 is an explanatory diagram of another form of alignment mark. DETAILED DESCRIPTION OF THE INVENTION

[0008] In the image inspection method disclosed in the present specification, the semiconductor element may be provided on a semiconductor wafer 10. The semiconductor wafer may be optically transparent.

[0009] In the case where the semiconductor wafer is optically transparent, the process of capturing the top surface inspection image and the bottom surface inspection image may include a process of capturing the top surface inspection image from the top surface side of the semiconductor element, and a process of capturing an image of the bottom surface seen through the semiconductor wafer from the top surface side of the semiconductor element as the bottom surface inspection image.

[0010] According to this configuration, it is possible to capture an upper surface inspection image and a lower surface inspection image from the upper surface side of the semiconductor element.

[0011] When the semiconductor wafer is optically transparent, the semiconductor wafer may have an upper surface reference mark (12) provided on its upper surface. In the step of forming the alignment marks within the inspection ranges on the lower surface of the semiconductor element, the alignment marks may be formed by positioning the upper surface reference marks by photographing them from the lower surface side of the semiconductor wafer.

[0012] According to this configuration, alignment marks can be formed on the lower surface by positioning them based on the upper surface reference marks.

[0013] In one example of an image inspection method disclosed in this specification, the semiconductor element may be provided on a semiconductor wafer. The semiconductor wafer may have an upper surface reference mark provided on its upper surface. The step of forming the alignment marks within the respective inspection areas on the lower surface of the semiconductor element may include the steps of forming lower surface reference marks (13) on the lower surface of the semiconductor wafer by positioning them based on the upper surface reference mark, and forming the alignment marks within the respective inspection areas on the lower surface of the semiconductor element by positioning them based on the lower surface reference mark.

[0014] According to this configuration, alignment marks can be formed on the lower surface by positioning them based on the upper surface reference marks.

[0015] In the above-mentioned image inspection method, the image inspection may detect the relative positions of the upper surface reference mark and the lower surface reference mark, and compare the upper surface inspection image and the upper surface normal image based on the relative positions, the position of the alignment mark included in the lower surface inspection image, and the position of the alignment mark included in the lower surface normal image.

[0016] This configuration allows the upper surface inspection image and the upper surface normal image to be compared after correcting the influence of the deviation in the relative positions of the upper surface reference mark and the lower surface reference mark, thereby enabling more accurate detection of defects.

[0017] The image inspection method disclosed in this specification as an example may further include a step of removing the alignment mark after the image inspection is performed.

[0018] In one example of an image inspection method disclosed in this specification, the photographing device that photographs the top surface inspection image and the bottom surface inspection image may have an upper camera (74) that photographs the top surface of the semiconductor element, and a lower camera (75) that is arranged simultaneously with the upper camera and photographs the bottom surface of the semiconductor element.

[0019] This configuration can suppress misalignment between the upper surface inspection image and the lower surface inspection image. [Example]

[0020] A manufacturing method of a semiconductor device according to Example 1 will be described. The manufacturing method according to Example 1 includes an image inspection method for the semiconductor device. FIG. 1 shows a semiconductor wafer 10 used in manufacturing the semiconductor device. The semiconductor wafer 10 has a disk shape. An orientation flat 10c is provided on the outer peripheral surface of the semiconductor wafer 10. In Example 1, the semiconductor wafer 10 is made of an optically transparent material such as GaN or SiC.

[0021] (Upper surface reference mark forming process) First, a top surface reference mark forming step is performed. In the top surface reference mark forming step, as shown in FIGS. 2 and 3, top surface reference marks 12 are formed on the top surface 10a of the semiconductor wafer 10. The top surface reference marks 12 are optically detectable marks. For example, the top surface reference marks 12 may be recesses provided on the top surface 10a. The top surface reference marks 12 are formed by positioning them based on the outer peripheral surface of the semiconductor wafer 10 (for example, an orientation flat 10c, etc.). The top surface reference marks 12 are formed in the outer peripheral portion of the top surface 10a where no semiconductor elements are formed.

[0022] (Semiconductor element structure formation process) Next, a semiconductor element forming process is performed. In the semiconductor element forming process, as shown in FIG. 4, the upper surface 10a of the semiconductor wafer 10 is processed to form multiple semiconductor elements 14 on the semiconductor wafer 10. For example, in the semiconductor element forming process, multiple semiconductor elements 14 are formed on the upper surface 10a of the semiconductor wafer 10 by performing ion implantation, epitaxial growth, etching, etc. on the upper surface 10a of the semiconductor wafer 10. The semiconductor elements 14 are formed by positioning them based on the upper surface reference mark 12. FIG. 5 illustrates an enlarged plan view of the upper surface 10a of one semiconductor element 14 (i.e., the upper surface 10a of the semiconductor wafer 10 within the area of ​​one semiconductor element 14). The semiconductor element 14 has two element regions 14a on the upper surface 10a. A trench-type FET is formed in each element region 14a. Therefore, a striped pattern formed by the trenches appears in each element region 14a. Note that, in figures other than FIG. 5, the striped pattern in each element region 14a is omitted for clarity. As will be described in detail later, image inspection is performed on the top surface 10a of the semiconductor element 14. In the image inspection, as shown in FIG. 6, the top surface 10a of the semiconductor element 14 is divided into a plurality of inspection areas 50, and inspection is performed on each inspection area 50. The inspection area 50x shown in FIG. 6 does not include feature points such as the outer periphery of the element region 14a. The image inspection method of the first embodiment can also properly inspect the inspection area 50x that does not include feature points.

[0023] (Alignment mark formation process) Next, an alignment mark forming process is performed. In the alignment mark forming process, as shown in FIGS. 7 and 8, multiple alignment marks 20 are formed on the underside 10b of the semiconductor elements 14. Here, the alignment marks 20 are formed within each inspection range 50 of each semiconductor element 14. Here, each alignment mark 20 is formed by positioning based on the top surface reference mark 12. In Example 1, alignment marks 20 made of a film having a predetermined shape are formed on the underside 10b of the semiconductor wafer 10. More specifically, first, a film is formed to cover the underside 10b of the semiconductor wafer 10. Next, as shown in FIG. 9, the semiconductor wafer 10 is placed on a stage 40 of an exposure tool so that the underside 10b of the semiconductor wafer 10 (i.e., the underside 10b covered with the film) faces upward. The exposure tool has a camera 42 that photographs the semiconductor wafer 10 from above. Next, the top surface reference mark 12 is photographed by the camera 42. As described above, the semiconductor wafer 10 is optically transparent, so the top surface reference mark 12 can be photographed from the bottom surface 10b side by the camera 42. Next, using the top surface reference mark 12 photographed by the camera 42 as a reference, a mask covering the bottom surface 10b of the semiconductor wafer 10 (i.e., the surface of the film) is formed by photolithography. Next, the film is etched using the mask to form alignment marks 20 within each inspection range 50 of each semiconductor element 14, as shown in FIGS. 7 and 8 . The film constituting the alignment marks 20 preferably has a lower light transmittance than the semiconductor wafer 10. For example, the film constituting the alignment marks 20 may be composed of polysilicon or a metal film (e.g., Al, Ti, Ni, etc.). As described above, the structure on the top surface of the semiconductor element 14 is formed by positioning the top surface reference mark 12 as a reference. Therefore, by forming the alignment marks 20 by positioning them using the top surface reference mark 12 as a reference, the alignment marks 20 can be formed with high positional accuracy relative to the structure on the top surface of the semiconductor element 14.

[0024] (Image inspection process) Next, an image inspection process is performed. In the image inspection process, the upper surface 10a of each semiconductor element 14 is photographed for each inspection range 50, and the upper surface 10a is inspected for defects. An image inspection device 60 shown in FIG. 10 is used in the image inspection process. The image inspection device 60 includes a stage 62, a camera 64, a storage device 66, and an arithmetic circuit 68. First, as shown in FIG. 10, the semiconductor wafer 10 is placed on the stage 62. Here, the semiconductor wafer 10 is placed on the stage 62 with the upper surface 10a facing upward. The stage 62 is a hollow stage with a hole 62a in its center. Therefore, the uneven shape of the lower surface 10b of the semiconductor wafer 10, which is formed by each alignment mark 20, does not come into contact with the stage 62. The stage 62 supports the outer periphery of the lower surface 10b of the semiconductor wafer 10. Note that if there is no problem even if the entire lower surface 10b of the semiconductor wafer 10 comes into contact with the stage 62, the stage 62 does not have to be a hollow stage.

[0025] The image inspection device 60 can move the camera 64 and the stage 62 (i.e., the semiconductor wafer 10) relatively along the x and y directions in FIGS. 7 and 10. Therefore, the imaging range of the camera 64 can be moved along the x and y directions relative to the semiconductor wafer 10. The x direction is a direction parallel to the top surface 10a of the semiconductor wafer 10. The y direction is a direction parallel to the top surface 10a of the semiconductor wafer 10 and perpendicular to the x direction. After the semiconductor wafer 10 is placed on the stage 62, the arithmetic circuit 68 executes an inspection program. The arithmetic circuit 68 then captures an image of the top surface reference mark 12 using the camera 64. This allows the arithmetic circuit 68 to position the camera 64 relative to the semiconductor wafer 10. By performing this positioning, it is possible to accurately control the imaging range of the camera 64 relative to the semiconductor wafer 10. In other embodiments, a camera that captures the image of the top surface reference mark 12 may be provided separately from the camera 64.

[0026] Next, the arithmetic circuit 68 performs image inspection on each semiconductor element 14. As shown in FIG. 7, multiple inspection areas 50 are set for one semiconductor element 14. The arithmetic circuit 68 performs image inspection on each inspection area 50. First, the arithmetic circuit 68 selects one inspection area 50 from the multiple inspection areas 50 and moves the imaging area of ​​the camera 64 to the coordinates corresponding to the selected inspection area 50. Next, the arithmetic circuit 68 performs imaging with the focus of the camera 64 adjusted to the top surface 10a. As a result, an image of the top surface 10a of the selected inspection area 50 (hereinafter referred to as a top surface inspection image) is captured. Next, the arithmetic circuit 68 performs imaging with the focus of the camera 64 adjusted to the bottom surface 10b without moving the imaging area of ​​the camera 64. Because the semiconductor wafer 10 is optically transparent, the camera 64 can capture an image of the bottom surface 10b from the top surface 10a side. As a result, an image of the bottom surface 10b of the selected inspection area 50 (hereinafter referred to as a bottom surface inspection image) is captured. Since the alignment mark 20 is formed on the bottom surface 10b of the inspection area 50, the alignment mark 20 is included in the bottom surface inspection image. In this manner, the arithmetic circuit 68 captures the top surface inspection image and the bottom surface inspection image of the selected inspection area 50. By capturing the top surface inspection image and the bottom surface inspection image by changing the focus in this manner, the top surface inspection image and the bottom surface inspection image can be captured on the same axis. Therefore, it is possible to suppress deviation in the capturing range between the top surface inspection image and the bottom surface inspection image.

[0027] Next, the arithmetic circuit 68 accesses the storage device 66 and reads out the normal top surface image and the normal bottom surface image. First, the normal top surface image and the normal bottom surface image will be described. The normal top surface image and the normal bottom surface image are images of the top surface 10a and the bottom surface 10b of the inspection area 50 of the semiconductor element 14 that has no defects. The normal top surface image and the normal bottom surface image are taken for all of the inspection areas 50. The normal top surface image and the normal bottom surface image are taken in advance by the image inspection device 60. The normal top surface image and the normal bottom surface image of all of the inspection areas 50 are stored in the storage device 66. After the arithmetic circuit 68 has taken the inspection image of the top surface and the inspection image of the selected inspection area 50, it reads out the normal top surface image and the normal bottom surface image of the inspection area 50 from the storage device 66.

[0028] Next, the arithmetic circuit 68 calculates the difference (Δx, Δy) in the position of the alignment mark 20 between the lower surface inspection image and the lower surface normal image. For example, as shown in FIG. 11, the arithmetic circuit 68 identifies the coordinates (x1, y1) of the center position of the alignment mark 20 within the shooting range of the lower surface inspection image. Similarly, the arithmetic circuit 68 identifies the coordinates (x2, y2) of the center position of the alignment mark 20 within the shooting range of the lower surface normal image. Then, the arithmetic circuit 68 calculates the difference (Δx, Δy) in the position of the alignment mark 20 between the lower surface inspection image and the lower surface normal image using the formulas Δx = x1 - x2 and Δy = y1 - y2. In another example, as shown in FIG. 12, the arithmetic circuit 68 may overlay the lower surface inspection image and the lower surface normal image so that the alignment mark 20 coincides between them, and calculate the positional differences (Δx, Δy) in the x and y directions between the lower surface inspection image and the lower surface normal image. The difference (Δx, Δy) can be calculated by either method shown in FIGS.

[0029] Next, the arithmetic circuit 68 overlays the normal top surface image on the top surface inspection image, as shown in FIG. 13. At this time, the arithmetic circuit 68 overlays the normal top surface image on the top surface inspection image while shifting the position by an amount equal to the difference in position (Δx, Δy) between the bottom surface inspection image and the normal bottom surface image. By overlaying the normal top surface image on the top surface inspection image in this manner, an image of a normal semiconductor element 14 that is substantially the same portion as the top surface inspection image can be accurately overlaid on the top surface inspection image. By overlaying the normal top surface image on the top surface inspection image in this manner, the arithmetic circuit 68 detects differences between the top surface inspection image and the normal top surface image as defects.

[0030] The arithmetic circuit 68 performs image inspection on all inspection areas 50 of all semiconductor elements 14. In this way, the arithmetic circuit 68 detects the presence or absence of defects in each inspection area 50 of each semiconductor element 14. Marking is applied to semiconductor elements 14 in which defects are detected during image inspection.

[0031] (Bottom surface polishing process) Next, a bottom surface polishing step is performed. In the bottom surface polishing step, all of the alignment marks 20 are removed by polishing the bottom surface 10b of the semiconductor wafer 10.

[0032] Next, electrodes (e.g., source electrodes of FETs, signal electrode pads, etc.) are formed on the upper surface 10a of each semiconductor element 14. Next, electrodes (e.g., drain electrodes of FETs) are formed over the entire lower surface 10b of the semiconductor wafer 10. Next, the semiconductor wafer 10 is divided into chips of multiple semiconductor elements 14. Thereafter, semiconductor elements 14 in which defects are detected are removed, and normal semiconductor elements 14 are shipped. In this way, according to this manufacturing method, semiconductor elements 14 without defects on their upper surfaces can be manufactured.

[0033] As described above, in the image inspection method of the first embodiment, the difference (Δx, Δy) in the position of the alignment mark 20 between the bottom surface inspection image and the bottom surface normal image is identified. Then, the top surface inspection image and the top surface normal image are overlaid and compared at positions shifted in the same manner as the difference in the position of the alignment mark 20. Because the alignment mark 20 and the structure on the top surface of the semiconductor element 14 are both positioned based on the top surface reference mark 12, the alignment mark 20 is formed with high positional accuracy relative to the structure on the top surface of the semiconductor element 14. Furthermore, because the top surface inspection image and the bottom surface inspection image are captured coaxially by the camera 64, the deviation in the x and y directions between the capture ranges of the top surface inspection image and the bottom surface inspection image is small. Similarly, the deviation in the x and y directions between the capture ranges of the top surface normal image and the bottom surface normal image is small. Therefore, the difference in the position of the alignment mark 20 between the bottom surface inspection image and the bottom surface normal image approximately matches the deviation in the capture range between the top surface inspection image and the top surface normal image. Therefore, by overlaying the top surface inspection image and the normal top surface image at positions shifted by the same amount as the difference in the positions of the alignment marks 20, it is possible to accurately overlay an image of substantially the same portion of a normal semiconductor element 14 on an image of the inspection area 50 of the semiconductor element 14 being inspected. This allows for accurate detection of defects in the semiconductor element 14. Therefore, this image inspection method allows for accurate detection of defects even when there are no feature points on the top surface 10a within the inspection area 50. In particular, it is possible to suppress false defect detection. For example, in image inspection of an element region 14a having a striped pattern extending in the x direction as shown in FIG. 5, if the top surface inspection image and the normal top surface image cannot be accurately aligned, the entire area where the trenches are misaligned will be erroneously detected as a defect. In contrast, the image inspection method of Example 1 allows for accurate alignment of the top surface inspection image and the normal top surface image, thereby suppressing false defect detection. [Example]

[0034] A method for manufacturing a semiconductor device according to Example 2 will now be described. The semiconductor wafer 10 used in Example 2 may or may not be optically transparent. In the manufacturing method according to Example 2, the semiconductor wafer 10 is processed to the state shown in FIGS. 4 and 5 in the same manner as in Example 1.

[0035] (Bottom reference mark formation process) Next, a bottom surface reference mark forming step is carried out. In the bottom surface reference mark forming step, as shown in Figures 14 and 15, bottom surface reference marks 13 are formed on the bottom surface 10b of the semiconductor wafer 10. The bottom surface reference marks 13 are marks that can be optically detected. For example, the bottom surface reference marks 13 may be recesses provided on the bottom surface 10b. The bottom surface reference marks 13 are formed by positioning them based on the top surface reference marks 12. The bottom surface reference marks 13 are formed on the outer periphery of the bottom surface 10b where no semiconductor elements 14 are formed.

[0036] (Alignment mark formation process) Next, an alignment mark forming process is performed. In the alignment mark forming process, multiple alignment marks 20 are formed on the bottom surface 10b of the semiconductor wafer 10, as in FIGS. 7 and 8. Here, the alignment marks 20 are formed within each inspection range 50 of each semiconductor element 14. Here, each alignment mark 20 is formed by positioning based on the bottom surface reference mark 13. The structure on the top surface of the semiconductor element 14 is formed by positioning based on the top surface reference mark 12. The bottom surface reference mark 13 is formed by positioning based on the top surface reference mark 12. Therefore, by forming the alignment marks 20 by positioning based on the bottom surface reference mark 13, the alignment marks 20 can be formed with high positional accuracy relative to the structure on the top surface of the semiconductor element 14.

[0037] (Image inspection process) Next, an image inspection process is performed. In the image inspection process of Example 2, an image inspection device 70 shown in FIG. 16 is used. The image inspection device 70 has a stage 72, cameras 74 and 75, a storage device 76, and an arithmetic circuit 78. The stage 72 is a hollow stage with a hole 72a in the center. The camera 74 is disposed above the stage 72 and takes images in the vertically downward direction. The camera 75 is disposed below the stage 72 and takes images in the vertically upward direction. The relative positions of the cameras 74 and 75 are fixed. The cameras 74 and 75 are disposed coaxially. First, as shown in FIG. 16, the semiconductor wafer 10 is placed on the stage 72. Here, the semiconductor wafer 10 is placed on the stage 72 with the top surface 10a facing upward. Therefore, the camera 74 takes an image of the top surface 10a of the semiconductor wafer 10, and the camera 75 takes an image of the bottom surface 10b of the semiconductor wafer 10.

[0038] The image inspection device 70 can move the cameras 74, 75 and the stage 72 (i.e., the semiconductor wafer 10) relatively along the x and y directions in FIGS. 7 and 16. Therefore, the imaging ranges of the cameras 74, 75 can be moved along the x and y directions relative to the semiconductor wafer 10. After the semiconductor wafer 10 is placed on the stage 72, the arithmetic circuit 78 executes an inspection program. The arithmetic circuit 78 then causes the camera 75 to capture an image of the bottom surface reference mark 13. This allows the arithmetic circuit 78 to position the camera 75 relative to the semiconductor wafer 10. By performing this positioning, it becomes possible to accurately control the imaging ranges of the cameras 74, 75 relative to the semiconductor wafer 10. Next, the arithmetic circuit 78 causes the camera 74 to capture an image of the top surface reference mark 12. This allows the arithmetic circuit 78 to calculate the relative position (xa, ya) of the top surface reference mark 12 with respect to the bottom surface reference mark 13. Furthermore, the arithmetic circuit 78 calculates the deviation (Δxa, Δya) of the relative position (xa, ya) from the design value.

[0039] Next, the arithmetic circuit 78 performs image inspection on each semiconductor element 14. The arithmetic circuit 78 performs image inspection on each inspection area 50. The arithmetic circuit 78 selects one inspection area 50 from the multiple inspection areas 50 and moves the imaging areas of the cameras 74 and 75 to the coordinates corresponding to the selected inspection area 50. Next, the arithmetic circuit 78 captures an image of the upper surface 10a of the inspection area 50 with the camera 74 (hereinafter referred to as the upper surface inspection image) and an image of the lower surface 10b of the inspection area 50 with the camera 75 (hereinafter referred to as the lower surface inspection image). Because an alignment mark 20 is formed on the lower surface 10b of the inspection area 50, the alignment mark 20 is included in the lower surface inspection image. Because the cameras 74 and 75 are arranged coaxially, the upper surface inspection image and the lower surface inspection image can be captured coaxially. Therefore, it is possible to suppress misalignment of the imaging areas between the upper surface inspection image and the lower surface inspection image.

[0040] After capturing the upper surface inspection image and the lower surface inspection image of the selected inspection range 50, the arithmetic circuit 78 reads out the upper surface normal image and the lower surface normal image of the inspection range 50 from the storage device 76. Next, the arithmetic circuit 78 calculates the difference (Δx, Δy) in the position of the alignment mark 20 between the lower surface inspection image and the lower surface normal image, in the same manner as in the first embodiment.

[0041] Next, the arithmetic circuit 78 calculates a slide amount (Δxs, Δys) based on the deviation (Δxa, Δya) of the relative positions of the top surface reference mark 12 and the bottom surface reference mark 13 from their design values ​​and the difference (Δx, Δy) in the position of the alignment mark 20 between the bottom surface inspection image and the bottom surface normal image. For example, the slide amount (Δxs, Δys) can be calculated using the formulas Δxs = Δxa + Δx and Δys = Δya + Δy. Next, the arithmetic circuit 78 overlays the top surface normal image on the top surface inspection image at a position shifted by the slide amount (Δxs, Δys), as shown in FIG. 17 . Overlaying the top surface normal image on the top surface inspection image in this manner allows an image of a normal semiconductor element 14 at a substantially identical portion to the top surface inspection image to be accurately overlaid on the top surface inspection image. By overlaying the top surface normal image on the top surface inspection image in this manner, the arithmetic circuit 68 detects differences between the top surface inspection image and the top surface normal image as defects.

[0042] The arithmetic circuit 68 performs image inspection on all inspection areas 50 of all semiconductor elements 14. In this way, the arithmetic circuit 68 detects the presence or absence of defects in each inspection area 50 of each semiconductor element 14. Marking is applied to semiconductor elements 14 in which defects are detected during image inspection.

[0043] (Bottom surface polishing process) Next, the same bottom surface polishing step as in Example 1 is carried out to remove the alignment marks 20.

[0044] Next, electrodes and the like are formed on the semiconductor wafer 10 in the same manner as in Example 1, and then the semiconductor wafer 10 is divided into chips of semiconductor elements 14. Thereafter, semiconductor elements 14 in which defects are detected are removed, and normal semiconductor elements 14 are shipped. In this way, according to this manufacturing method, semiconductor elements 14 without defects on their upper surfaces can be manufactured.

[0045] As described above, in the image inspection method of Example 2, the position of the alignment mark 20 between the bottom surface inspection image and the bottom surface normal image is adjusted based on the difference (Δx, Δy) in the position of the alignment mark 20 and the deviation (Δxa, Δya) of the relative position of the top surface reference mark 12 and the bottom surface reference mark 13 from the design value, and the top surface normal image is then superimposed on the top surface inspection image. If the relative positions of the top surface reference mark 12 and the bottom surface reference mark 13 are deviated from the design value (i.e., error), the alignment mark 20 on the bottom surface 10b side and the semiconductor element structure on the top surface 10a side are misaligned by the amount of the error. Therefore, by superimposing the top surface inspection image and the top surface normal image based on the deviation (Δxa, Δya), the influence of the error can be suppressed. This allows the top surface inspection image and the top surface normal image to be superimposed more accurately. This allows defects in the semiconductor element 14 to be accurately detected. Note that if sufficient accuracy can be obtained without considering the deviation (Δxa, Δya), the deviation (Δxa, Δya) may not be considered. That is, similarly to the first embodiment, the upper surface inspection image and the upper surface normal image may be superimposed at positions shifted by the difference in position of the alignment mark 20 (Δx, Δy).

[0046] In Example 1, as shown in Fig. 10, a top surface inspection image was taken by camera 64, and a bottom surface inspection image observed through the semiconductor wafer 10 was also taken by the same camera 64. However, in Example 1, the top surface inspection image and the bottom surface inspection image may be taken by separate cameras, as with cameras 74 and 75 in Fig. 16. Also, in Example 1, as shown in Fig. 9, the top surface reference mark 12 observed through the semiconductor wafer 10 from the bottom surface 10b side was photographed by camera 42, but the top surface reference mark 12 may also be photographed from the top surface 10a side.

[0047] In the first and second embodiments described above, the alignment mark 20 is a patterned film. However, various optically detectable structures can be employed as the alignment mark 20. For example, as shown in FIG. 18, the alignment mark 20 may be a film (e.g., a film made of polysilicon or metal) embedded in a recess provided in the lower surface 10b. As shown in FIG. 19, the alignment mark 20 may be a mark formed by irradiating the lower surface 10b with a laser L. As shown in FIG. 20, the alignment mark 20 may be formed by a region formed by implanting ions I into the lower surface 10b. As shown in FIG. 21, the alignment mark 20 may be a region roughened by etching the lower surface 10b.

[0048] In addition, in the above-described first and second embodiments, the top surface inspection image and the bottom surface inspection image are captured on the same axis. However, the capturing range of the top surface inspection image and the capturing range of the bottom surface inspection image may be misaligned due to an error or the like. Even in this case, as long as the relative positional relationship between the capturing range of the top surface inspection image and the capturing range of the bottom surface inspection image is fixed, the image inspection can be performed appropriately.

[0049] Furthermore, in the above-described first and second embodiments, the upper surface inspection image and the upper surface normal image are superimposed and compared, but defects may be detected by comparing them in other ways.

[0050] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0051] 10: semiconductor wafer, 12: upper surface reference mark, 13: lower surface reference mark, 14: semiconductor element, 20: alignment mark

Claims

1. A method for image inspection of a semiconductor element (14), comprising: The semiconductor device has a plurality of test areas (50); The image inspection method comprises: a step of forming alignment marks (20) within the respective inspection areas on the lower surface (10b) of the semiconductor element by positioning the alignment marks (20) relative to the upper surface structure of the semiconductor element; capturing an upper surface inspection image, which is an image of the upper surface of the semiconductor element, and a lower surface inspection image, which is an image of the lower surface of the semiconductor element, for each of the inspection ranges of the semiconductor element; A step of performing an image inspection using an image inspection device; and the image inspection device stores, for each of the inspection ranges of the semiconductor element, a normal upper surface image that is a normal image of the upper surface of the semiconductor element and a normal lower surface image that is a normal image of the lower surface of the semiconductor element; each of the lower surface normal images is an image including the alignment mark, In the image inspection, the image inspection device compares the upper surface inspection image with the upper surface normal image for each inspection range based on the positions of the alignment marks included in the lower surface inspection image and the positions of the alignment marks included in the lower surface normal image, thereby determining whether or not the upper surface inspection image contains a defect; The semiconductor element is provided on a semiconductor wafer (10), the semiconductor wafer is optically transparent; The semiconductor wafer has an upper surface reference mark (12) provided on its upper surface, The method further includes a step of forming the upper surface side structure of the semiconductor element on the upper surface of the semiconductor wafer by aligning the upper surface reference mark as a reference, In the step of forming the alignment marks within the respective inspection ranges on the lower surface of the semiconductor element, the alignment marks are formed by positioning the alignment marks based on the upper surface reference marks by photographing the upper surface reference marks from the lower surface side of the semiconductor wafer. Imaging methods.

2. A method for image inspection of a semiconductor element (14), comprising: The semiconductor device has a plurality of test areas (50); The image inspection method comprises: a step of forming alignment marks (20) within the respective inspection areas on the lower surface (10b) of the semiconductor element by positioning the alignment marks (20) relative to the upper surface structure of the semiconductor element; capturing an upper surface inspection image, which is an image of the upper surface of the semiconductor element, and a lower surface inspection image, which is an image of the lower surface of the semiconductor element, for each of the inspection ranges of the semiconductor element; A step of performing an image inspection using an image inspection device; and the image inspection device stores, for each of the inspection ranges of the semiconductor element, a normal upper surface image that is a normal image of the upper surface of the semiconductor element and a normal lower surface image that is a normal image of the lower surface of the semiconductor element; each of the lower surface normal images is an image including the alignment mark, In the image inspection, the image inspection device compares the upper surface inspection image with the upper surface normal image for each inspection range based on the positions of the alignment marks included in the lower surface inspection image and the positions of the alignment marks included in the lower surface normal image, thereby determining whether or not the upper surface inspection image contains a defect; The method further includes forming the top surface structure of the semiconductor element on a semiconductor wafer, the semiconductor wafer has an upper surface reference mark provided on its upper surface; In the step of forming the upper surface side structure, the upper surface side structure of the semiconductor element is formed on the upper surface of the semiconductor wafer while being positioned based on the upper surface reference mark; the step of forming the alignment marks within the respective inspection areas on the lower surface of the semiconductor element, a step of forming a lower surface reference mark (13) on the lower surface of the semiconductor wafer by aligning the upper surface reference mark based on the reference mark; forming the alignment marks within the respective inspection areas on the bottom surface of the semiconductor element by positioning the bottom surface reference marks as a reference; having Imaging methods.

3. 3. The image inspection method according to claim 2, wherein the image inspection detects the relative positions of the upper surface reference mark and the lower surface reference mark, and compares the upper surface inspection image with the upper surface normal image based on the relative positions, the position of the alignment mark included in the lower surface inspection image, and the position of the alignment mark included in the lower surface normal image.

4. 4. The image inspection method according to claim 1, further comprising the step of removing the alignment mark after the image inspection is performed.

5. The image inspection method according to claim 1 , wherein in the step of capturing the top surface inspection image and the bottom surface inspection image, the top surface inspection image and the bottom surface inspection image are captured coaxially.

6. 4. The image inspection method according to claim 2 or 3, wherein the photographing device for photographing the top surface inspection image and the bottom surface inspection image has an upper camera (74) for photographing the top surface of the semiconductor element, and a lower camera (75) arranged coaxially with the upper camera for photographing the bottom surface of the semiconductor element.

7. An image inspection method according to any one of claims 1 to 6, wherein in the image inspection, the image inspection device calculates the difference between the position of the alignment mark included in the bottom surface inspection image and the position of the alignment mark included in the bottom surface normal image for each inspection range, and determines whether or not the top surface inspection image contains a defect by comparing the top surface inspection image with the top surface normal image based on the difference.

8. In the image inspection, the image inspection device calculates the difference between the position of the alignment mark included in the bottom surface inspection image and the position of the alignment mark included in the bottom surface normal image for each inspection range, and determines whether or not the top surface inspection image contains a defect by overlaying the top surface inspection image and the top surface normal image with their positions shifted by the same amount as the difference.

9. In the image inspection, the image inspection device Detecting the relative positions of the upper surface reference mark and the lower surface reference mark; calculating a difference between the position of the alignment mark included in the lower surface inspection image and the position of the alignment mark included in the lower surface normal image for each of the inspection ranges; calculating a slide amount for each of the inspection ranges based on the relative position and the difference; and determining whether or not a defect is included in the upper surface inspection image by superimposing the upper surface inspection image and the upper surface normal image while the positions are shifted by the slide amount. The image inspection method according to claim 2 .

10. A method for manufacturing a semiconductor device, comprising the image inspection method according to any one of claims 1 to 9.

Images