Semiconductor device and electronic device

Abstract

Provided is a semiconductor device that has reduced power consumption and is capable of non-destructive readout. This semiconductor device has first to fourth transistors, and first and second ferroelectric tunnel junction (FTJ) elements. The first FTJ element and the second FTJ element each have an input terminal, a tunnel insulating film, a dielectric, and an output terminal. One of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the third transistor, the gate of the fourth transistor, and the output terminal of the first FTJ element. One of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the fourth transistor, the gate of the third transistor, and the output terminal of the second FTJ element.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] In recent years, the development of semiconductor devices has progressed, and CPUs (Central Processing Units), memories, etc. are mainly used in semiconductor devices as LSIs (Large Scale Integration). A CPU is an aggregate of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0004] Furthermore, development is underway for semiconductor devices that incorporate the above-mentioned semiconductor integrated circuits with ferroelectric capacitors, FTJ (Ferroelectric Tunnel Junction or Ferroelectric Transportation Junction) elements, FeFETs (Ferroelectric FETs), and the like, which use ferroelectric dielectrics. For example, Patent Document 1 discloses a semiconductor memory cell having a transistor with a ferroelectric film provided on the gate insulating film on the back gate side. Furthermore, for example, Patent Document 2 discloses a memory configured such that a ferroelectric capacitor is electrically connected to the gate of a transistor. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-164473 [Patent Document 2] Japanese Patent Application Laid-Open No. 2003-178577 Summary of the Invention [Problem to be solved by the invention]

[0006] In recent years, the amount of data handled by electronic devices and the like has tended to increase, and attempts have been made to miniaturize memory devices, particularly memory cells, in order to increase storage capacity. When memory cells are miniaturized to reduce their capacity, their electrostatic capacitance value decreases, making it difficult to retain data for a long period of time. Furthermore, the number of refresh operations required to retain data increases, which can result in higher power consumption. Therefore, it is preferable for memory devices to use memory cells that can retain data for a long period of time.

[0007] In particular, when a storage device is configured as a DRAM (Dynamic Random Access Memory), the data stored in the memory cell is destroyed when it is read (destructive read occurs), so the data must be rewritten. Therefore, DRAM may require a circuit to write back the data after it has been read. Furthermore, rewriting data may result in high power consumption.

[0008] An object of one embodiment of the present invention is to provide a semiconductor device that does not require rewriting of data (a semiconductor device that performs non-destructive readout).Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption.Another object of one embodiment of the present invention is to provide a semiconductor device with a reduced circuit area.Another object of one embodiment of the present invention is to provide a novel semiconductor device.Another object of one embodiment of the present invention is to provide an electronic device including any of the above-described semiconductor devices.

[0009] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0010] (1) One aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a first FTJ element, and a second FTJ element. Preferably, each of the first FTJ element and the second FTJ element has an input terminal, a tunnel insulating film, a dielectric, and an output terminal. Preferably, one of the source or drain of the first transistor is electrically connected to one of the source or drain of the third transistor, the gate of the fourth transistor, and the output terminal of the first FTJ element, and one of the source or drain of the second transistor is electrically connected to one of the source or drain of the fourth transistor, the gate of the third transistor, and the output terminal of the second FTJ element.

[0011] (2) Alternatively, in one embodiment of the present invention, in the above-described (1), a gate of the first transistor may be electrically connected to a gate of the second transistor.

[0012] (3) Alternatively, in one aspect of the present invention, in the above (1) or (2), the input terminal of the first FTJ element may be connected to the input terminal of the second FTJ element.

[0013] (4) Alternatively, in one aspect of the present invention, in any one of the above (1) to (3), the tunnel insulating film may have silicon oxide or silicon nitride, and the dielectric may have an oxide containing one or both of hafnium and zirconium.

[0014] (5) Alternatively, one aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a first ferroelectric capacitor, and a second ferroelectric capacitor. Preferably, one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the third transistor, a gate of the fourth transistor, and a first terminal of the first ferroelectric capacitor, and one of a source or a drain of the second transistor is electrically connected to one of a source or a drain of the fourth transistor, a gate of the third transistor, and a first terminal of the second ferroelectric capacitor.

[0015] (6) Alternatively, in one embodiment of the present invention, in the above-mentioned (5), a gate of the first transistor may be electrically connected to a gate of the second transistor.

[0016] (7) Alternatively, in one aspect of the present invention, in the above (5) or (6), the second terminal of the first ferroelectric capacitor may be connected to the second terminal of the second ferroelectric capacitor.

[0017] (8) Alternatively, in one aspect of the present invention, in any one of the above (5) to (7), the first ferroelectric capacitor and the second ferroelectric capacitor may each have a dielectric, and the dielectric may have an oxide containing one or both of hafnium and zirconium.

[0018] (9) Another embodiment of the present invention is an electronic device including any one of the semiconductor devices described above in (1) to (8) and a housing.

[0019] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device or may include a semiconductor device.

[0020] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0021] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0022] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0023] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0024] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0025] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0026] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification and the like, a "resistance element" is intended to include a wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can sometimes be replaced with terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," and "region having a resistance value" can sometimes be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be replaced with a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0027] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, a transistor gate capacitance, etc. Therefore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with terms such as "capacitance." Conversely, the term "capacitance" can sometimes be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," "pair of regions," etc. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0028] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0029] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current, improve the breakdown voltage of the transistor, and improve reliability. Alternatively, when operating in the saturation region, the multi-gate structure can provide a voltage-current characteristic with a flat slope, whereby the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing a voltage-current characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0030] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors electrically connected in series. For example, when a circuit diagram shows one capacitor, this includes two or more capacitors electrically connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors electrically connected in series, with the gates of the transistors electrically connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors electrically connected in series or parallel, with the gates of the transistors electrically connected to each other.

[0031] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and device structure. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0032] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0033] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0034] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current flow and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive or negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0035] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0036] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0037] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0038] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0039] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" and "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0040] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0041] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0042] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals for passing a current in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it can control a current.

[0043] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0044] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0045] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0046] According to one embodiment of the present invention, a semiconductor device that does not require rewriting of data (a semiconductor device that performs non-destructive readout) can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with a reduced circuit area can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, an electronic device including any of the above-described semiconductor devices can be provided.

[0047] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0048] 1A and 1B are circuit diagrams showing examples of the configuration of a memory cell in a semiconductor device. FIG. 2 is a timing chart illustrating an example of the operation of a memory cell in the semiconductor device. FIG. 3 is a timing chart illustrating an example of the operation of a memory cell in the semiconductor device. 4A to 4C are circuit diagrams showing examples of the configuration of a memory cell in a semiconductor device. 5A and 5B are circuit diagrams showing examples of the configuration of a memory cell in a semiconductor device. FIG. 6 is a circuit diagram showing an example of the configuration of a memory cell in a semiconductor device. FIG. 7 is a timing chart illustrating an example of the operation of a memory cell in the semiconductor device. FIG. 8 is a block diagram showing an example of the configuration of a storage device. FIG. 9 is a timing chart illustrating an example of the operation of the storage device. FIG. 10 is a timing chart illustrating an example of the operation of the storage device. FIG. 11 is a timing chart illustrating an example of the operation of the storage device. FIG. 12 is a timing chart illustrating an example of the operation of the storage device. FIG. 13 is a timing chart illustrating an example of the operation of the storage device. FIG. 14 is a block diagram showing an example of the configuration of an arithmetic circuit. FIG. 15 is a block diagram showing an example of the configuration of an arithmetic circuit. FIG. 16 is a circuit diagram showing an example of the configuration of a circuit included in the arithmetic circuit. FIG. 17 is a block diagram showing an example of the configuration of a storage device. FIG. 18 is a timing chart illustrating an example of the operation of the storage device. FIG. 19 is a schematic cross-sectional view showing a configuration example of a semiconductor device. 20A to 20C are cross-sectional views showing examples of the structure of a transistor. FIG. 21 is a schematic cross-sectional view showing a configuration example of a semiconductor device. 22A and 22B are cross-sectional views showing examples of the structure of a transistor. FIG. 23 is a schematic cross-sectional view showing a configuration example of a transistor. FIG. 24 is a schematic cross-sectional view showing a configuration example of a semiconductor device. FIG. 25 is a schematic cross-sectional view showing a configuration example of a transistor. FIG. 26 is a schematic cross-sectional view showing a configuration example of a semiconductor device. FIG. 27A is a diagram illustrating the classification of IGZO crystal structures, FIG. 27B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 27C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. FIG. 28A is a perspective view showing an example of a semiconductor wafer, FIG. 28B is a perspective view showing an example of a chip, and FIGS. 28C and 28D are perspective views showing an example of an electronic component. FIG. 29 is a block diagram illustrating the CPU. 30A to 30I are perspective views or schematic diagrams for explaining an example of a product. FIG. 31 is a graph showing the current density-voltage characteristics of the FTJ element. DETAILED DESCRIPTION OF THE INVENTION

[0049] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0050] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0051] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0052] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0053] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0054] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0055] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0056] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m,n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m,n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0057] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0058] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described.

[0059] <Configuration example 1> FIG. 1A illustrates an example of a circuit configuration of a memory cell MC included in a memory device, which is a semiconductor device of one embodiment of the present invention.

[0060] The memory cell MC includes a transistor M1, a transistor M1b, a transistor M6, a transistor M6b, an FTJ element FJA, and an FTJ element FJAb.

[0061] The FTJ element FJA and the FTJ element FJAb are tunnel junction elements that include a pair of electrodes, a material that may have ferroelectricity, and an insulator that functions as a tunnel insulating film. The FTJ element has a function in which its resistance changes depending on the direction and strength of polarization of the material that may have ferroelectricity.

[0062] The insulator is provided so as to overlap the material that may have ferroelectricity, and the insulator and the material that may have ferroelectricity are provided between the pair of electrodes. The FTJ element has rectifying properties because the insulator that functions as a tunnel insulating film is provided so as to overlap the material that may have ferroelectricity. For example, when the FTJ element has a configuration in which one of the pair of electrodes, the insulator that functions as a tunnel insulating film, the material that may have ferroelectricity, and the other of the pair of electrodes are stacked in this order, the forward direction of current flow in the FTJ element is from one of the pair of electrodes to the other of the pair of electrodes. In this specification, one of the pair of electrodes is referred to as an input terminal, and the other of the pair of electrodes is referred to as an output terminal.

[0063] For example, the FTJ element described in this specification can be formed by stacking a first conductor, a tunnel insulating film, a material that may have ferroelectricity, and a second conductor in this order on a flat insulating or conductive film. The first conductor can be referred to as a lower electrode, and the second conductor can be referred to as an upper electrode. In this case, the first conductor and the second conductor are the pair of electrodes described above, and the first conductor (lower electrode) functions as an input terminal, for example, and the second conductor (upper electrode) functions as an output terminal, for example. In addition, the FTJ element described in this specification may be formed by stacking a first conductor (lower electrode), a material that may have ferroelectricity, a tunnel insulating film, and a second conductor (upper electrode) in this order on a flat insulating or conductive film. In this case, the first conductor (lower electrode) functions as an output terminal, for example, and the second conductor (upper electrode) functions as an input terminal, for example.

[0064] The tunnel insulating film may be made of, for example, silicon oxide, silicon nitride, or a laminate of silicon oxide and silicon nitride.

[0065] As mentioned above, the resistance of an FTJ element changes depending on the direction and strength of polarization of the ferroelectric material. For example, when the polarization direction of the ferroelectric material between the input and output terminals of the FTJ element is from the output terminal to the input terminal (the polarization vector direction is negative in this case), the amount of current flowing from the input terminal to the output terminal in the FTJ element increases. On the other hand, when the polarization direction of the ferroelectric material between the input and output terminals of the FTJ element is from the input terminal to the output terminal (the polarization vector direction is positive in this case), the amount of current flowing from the input terminal to the output terminal in the FTJ element decreases. In other words, when the polarization direction of the FTJ element is from the input terminal to the output terminal, the resistance value of the current flowing from the input terminal to the output terminal of the FTJ element increases. Conversely, when the polarization direction of the FTJ element is from the output terminal to the input terminal, the resistance value of the current flowing from the input terminal to the output terminal of the FTJ element decreases.

[0066] One way to polarize (change the direction of polarization) a material that can exhibit ferroelectricity in an FTJ element is to apply a high voltage between the input and output terminals of the FTJ element. For example, applying a high-level potential to the input terminal of the FTJ element and a low-level potential to the output terminal causes the polarization to orient from the input terminal to the output terminal (positive direction) in the material that can exhibit ferroelectricity in the FTJ element. On the other hand, applying a low-level potential to the input terminal of the FTJ element and a high-level potential to the output terminal causes the polarization to orient from the output terminal to the input terminal (negative direction). Note that FTJ elements have hysteresis in the intensity of polarization, so to polarize (change the direction of polarization), a voltage appropriate for the structure of the FTJ element must be applied. At voltages lower than this voltage, polarization does not occur in the FTJ element (the direction of polarization does not change).

[0067] In the drawings of this specification, an FTJ element is represented by adding an arrow to the circuit symbol for a diode. In addition, in the drawings of this specification, the side of the triangle corresponding to the anode of the circuit symbol for the diode connected to the wiring is defined as the input terminal of the FTJ element, and the apex and line of the triangle corresponding to the cathode of the circuit symbol for the diode connected to the wiring are defined as the output terminal of the FTJ element.

[0068] Furthermore, it is preferable to use, for example, hafnium oxide as a material that can have ferroelectricity. When hafnium oxide is used as the material that can have ferroelectricity contained in the FTJ element, the film thickness of the hafnium oxide (or the distance between a pair of electrodes of the FTJ element) is preferably 10 nm or less, more preferably 5 nm or less, and even more preferably 2 nm or less.

[0069] Alternatively, materials that can have ferroelectricity include, other than hafnium oxide, zirconium oxide and hafnium zirconium oxide (HfZrO XExamples of suitable ferroelectric materials include metal oxides such as hafnium oxide (where X is a real number greater than 0), or HZO (sometimes referred to as HZO). Alternatively, examples of materials that may have ferroelectricity include materials in which element J1 is added to hafnium oxide (here, element J1 is one or more elements selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.). The atomic ratio of hafnium atoms to element J1 can be set appropriately; for example, the ratio may be 1:1 or a composition close to that ratio. Note that a composition close to that ratio includes a range of ±30% of the desired atomic ratio. Alternatively, examples of materials that can have ferroelectricity include materials in which element J2 (here, element J2 is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to zirconium oxide. The ratio of the number of zirconium atoms to the number of element J2 can be set appropriately, and for example, the ratio may be set to 1:1 or close to 1:1. Examples of materials that can have ferroelectricity include lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0070] Furthermore, materials that can have ferroelectricity include aluminum scandium nitride (Al 1-a Sc a N b(where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1.) Examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum (Al), gallium (Ga), indium (In), etc., and element M2 is one or more elements selected from boron (B), scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), neodymium (Nd), europium (Eu), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Ferroelectric materials include the above-mentioned metal nitrides to which element M3 is added. The element M3 is one or more elements selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), and cadmium (Cd). The ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be appropriately set. Because the above-mentioned metal nitrides contain at least a Group 13 element and nitrogen, a Group 15 element, these metal nitrides are sometimes referred to as Group III-V ferroelectrics or Group III nitride ferroelectrics.

[0071] Furthermore, materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure.

[0072] Furthermore, the material capable of exhibiting ferroelectricity can be, for example, a mixture or compound made of multiple materials selected from the materials listed above. Alternatively, the material capable of exhibiting ferroelectricity can be a layered structure made of multiple materials selected from the materials listed above. However, since the crystal structure and electrical properties of the materials listed above may change depending not only on the film formation conditions but also on various processes, the above-mentioned materials are referred to herein not only as ferroelectrics but also as materials capable of exhibiting ferroelectricity. Furthermore, the term "ferroelectric" is intended to include not only materials that exhibit ferroelectricity but also materials capable of exhibiting ferroelectricity.

[0073] Among these, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferred as a material capable of exhibiting ferroelectricity, since it can retain ferroelectricity even when processed into a thin film of a few nanometers. Here, the film thickness of the ferroelectric material can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). For example, a film thickness of 8 nm to 12 nm is preferred. By forming a thin ferroelectric layer, the ferroelectric layer can be sandwiched between a pair of electrodes of a capacitive element, and the capacitive element can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device. In this specification, a layer of a material capable of exhibiting ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification.

[0074] In addition, HfZrO is a material that can have ferroelectric properties. XWhen using a ferroelectric material, it is preferable to form the film using atomic layer deposition (ALD), particularly thermal ALD. Furthermore, when using thermal ALD to form a film of a material that can have ferroelectricity, it is preferable to use a material that does not contain hydrocarbons (also called hydrocarbon, HC) as a precursor. If the material that can have ferroelectricity contains either or both of hydrogen and carbon, this may inhibit the crystallization of the material that can have ferroelectricity. Therefore, as described above, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the material that can have ferroelectricity. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Furthermore, as a material that can have ferroelectricity, a material containing hafnium oxide and zirconium oxide (HfZrO x ) is used, HfCl4 and / or ZrCl4 may be used as the precursor.

[0075] When a film is formed using a material that can have ferroelectricity, impurities in the film, in this case at least one of hydrogen, hydrocarbon, and carbon, are thoroughly removed, thereby forming a film having high-purity intrinsic ferroelectricity. The film having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor shown in the embodiment described later have very high compatibility in manufacturing processes. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0076] In addition, HfZrO is a material that can have ferroelectric properties. X When used, it is preferable to use a thermal ALD method to alternately form films of hafnium oxide and zirconium oxide in a 1:1 ratio.

[0077] Furthermore, when a film of a material that may have ferroelectricity is formed using a thermal ALD method, the oxidizing agent may be H2O or O3. However, the oxidizing agent for the thermal ALD method is not limited to these. For example, the oxidizing agent for the thermal ALD method may include one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0078] Furthermore, the crystal structure of the material capable of exhibiting ferroelectricity is not particularly limited. For example, the crystal structure of the material capable of exhibiting ferroelectricity may be any one of crystal structures selected from cubic, tetragonal, orthorhombic, and monoclinic systems, or a composite structure having a plurality of such structures. In particular, the material capable of exhibiting ferroelectricity preferably has an orthorhombic crystal structure, since ferroelectricity is exhibited thereby. Alternatively, the material capable of exhibiting ferroelectricity may be a composite structure having an amorphous structure and a crystalline structure.

[0079] The transistor M1, the transistor M1b, the transistor M6, and the transistor M6b can each be, for example, an OS transistor. The metal oxide contained in the channel formation region of the OS transistor preferably includes an oxide containing at least one of indium, gallium, and zinc. Alternatively, the metal oxide may include an oxide containing at least one of indium, an element M (e.g., aluminum, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like), and zinc. The transistor M1, the transistor M1b, the transistor M6, and the transistor M6b preferably have the structure described in Embodiment 5.

[0080] The transistors M1, M1b, M6, and M6b may be transistors containing silicon in their channel formation regions (hereinafter referred to as Si transistors) other than OS transistors. The silicon may be, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or single-crystal silicon.

[0081] In addition, as each of the transistors M1, M1b, M6, and M6b, in addition to OS transistors and Si transistors, transistors having Ge or the like in a channel formation region, transistors having a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe in a channel formation region, transistors having carbon nanotubes in a channel formation region, transistors having an organic semiconductor in a channel formation region, etc. may be used.

[0082] The channel formation regions of the transistors M1, M1b, M6, and M6b may contain the same material or different materials. For example, some of the transistors M1, M1b, M6, and M6b may be OS transistors and the rest may be Si transistors.

[0083] Furthermore, the transistors M1, M1b, M6, and M6b shown in FIG. 1A are, for example, transistors having gates above and below the channel, and each of the transistors M1, M1b, M6, and M6b has a first gate and a second gate. For convenience, the first gate is described as a gate (sometimes referred to as a front gate) and the second gate as a back gate, but the first gate and the second gate can be interchanged. Therefore, in this specification, the term "gate" can be interchanged with the term "back gate." Similarly, the term "back gate" can be interchanged with the term "gate." As a specific example, a connection configuration in which "the gate is electrically connected to a first wiring, and the back gate is electrically connected to a second wiring" can be replaced with a connection configuration in which "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring."

[0084] Furthermore, the memory cell MC of the semiconductor device according to one embodiment of the present invention does not depend on the connection configuration of the back gate of the transistor. Although the back gates of the transistors M1, M1b, M6, and M6b shown in FIG. 1A are illustrated, the connection configuration of the back gates is not illustrated. However, the electrical connection destination of the back gate can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-state current of the transistor. That is, for example, the gate and the back gate of the transistor M1 may be electrically connected. Furthermore, in a transistor having a back gate, for example, a wiring electrically connected to an external circuit or the like may be provided to apply a fixed or variable potential to the back gate of the transistor by the external circuit or the like to change the threshold voltage of the transistor or reduce the off-state current of the transistor. Note that this also applies to transistors described elsewhere in the specification or illustrated in other drawings, not just FIG. 1A.

[0085] Furthermore, the memory cell MC of the semiconductor device of one embodiment of the present invention does not depend on the structure of the transistor included in the memory cell MC. For example, the transistor M1, the transistor M1b, the transistor M6, and the transistor M6b shown in FIG. 1A may each be configured without a back gate, that is, a single-gate transistor, as shown in FIG. 1B. Furthermore, some of the transistors may have a back gate, and other transistors may not have a back gate. This also applies to transistors described elsewhere in the specification or illustrated in other drawings, not just FIG. 1A.

[0086] Furthermore, while the transistors M1, M1b, M6, and M6b shown in FIG. 1A are illustrated as n-channel transistors as an example, some or all of them may be replaced with p-channel transistors depending on the situation or case. Furthermore, if the n-channel transistors are replaced with p-channel transistors, the potentials input to the memory cells MC and the like must be appropriately changed so that the memory cells MC operate normally. Furthermore, the results output from the memory cells MC may also change. This applies not only to FIG. 1A but also to transistors described elsewhere in the specification or illustrated in other drawings. Furthermore, in this embodiment, the configuration and operation of the memory cell MC will be described assuming that the transistors M1, M1b, M6, and M6b are n-channel transistors.

[0087] In the memory cell MC of FIG. 1A, the first terminal of the transistor M1 is electrically connected to the wiring WRDL, and the gate of the transistor M1 is electrically connected to the wiring WRWL. The input terminal of the FTJ element FJA is electrically connected to the wiring FCA. The output terminal of the FTJ element FJA is electrically connected to the second terminal of the transistor M1, the first terminal of the transistor M6, and the gate of the transistor M6b. The second terminal of the transistor M6 is electrically connected to the wiring FCB. The first terminal of the transistor M1b is electrically connected to the wiring WRDLb, and the gate of the transistor M1b is electrically connected to the wiring WRWL. The input terminal of the FTJ element FJAb is electrically connected to the wiring FCA. The output terminal of the FTJ element FJAb is electrically connected to the second terminal of the transistor M1b, the first terminal of the transistor M6b, and the gate of the transistor M6. The second terminal of the transistor M6b is electrically connected to the wiring FCB.

[0088] As an example, the wiring WRDL functions as a wiring that transmits data to be written to the memory cell MC. Also, the wiring WRDL functions as a wiring that transmits data read from the memory cell MC. That is, the wiring WRDL may function as both a write data line and a read data line. Similarly, as an example, the wiring WRDLb functions as a wiring that transmits data to be written to the memory cell MC. Also, the wiring WRDLb functions as a wiring that transmits data read from the memory cell MC. That is, the wiring WRDLb may also function as both a write data line and a read data line.

[0089] For example, the wiring WRWL functions as a wiring for selecting a memory cell MC to which data is to be written. Also, for example, the wiring WRWL functions as a wiring for selecting a memory cell MC from which data is to be read. In other words, the wiring WRWL may function as both a write word line and a read word line.

[0090] For example, the wiring FCA functions as a wiring that applies a variable potential to the extent that polarization occurs in the material (dielectric) that may have ferroelectricity included in each of the FTJ elements FJA and FJAb when writing data to the memory cell MC. Also, for example, the wiring FCA also functions as a wiring that applies a potential to the extent that polarization of the material (dielectric) does not change when reading data from the memory cell MC.

[0091] Incidentally, a detailed operation example will be described later, but the operation of the memory cell MC is as follows: a voltage is applied to the wiring FCA, and the voltage is applied to the input terminals of the FTJ element FJA and the FTJ element FJAb. At this time, a tunnel current may flow through each of the FTJ element FJA and the FTJ element FJAb. At this time, if it is desired to prevent leakage of the tunnel current via the transistor M1, it is preferable to use an OS transistor as the transistor M1 and / or the transistor M1b. Because the off-current of an OS transistor is very low, it may be possible to prevent leakage of the tunnel current flowing through the FTJ element FJA and / or the FTJ element FJAb to the wiring WRDL side.

[0092] <Example of operation> Next, an example of a data write operation and an example of a data read operation in the memory cell MC of FIG. 1A will be described.

[0093] <<Example of data write operation>> Fig. 2 is a timing chart showing an example of a data write operation in the memory cell MC of Fig. 1A. The timing chart of Fig. 2 shows changes in the potentials of the wires WRWL, WRDL, WRDLb, FCA, and FCB between time T11 and time T17 and around those times.

[0094] [From time T11 to time T12] Between time T11 and time T12, the potentials of the wirings WRWL and WRDL are low (denoted as "Low" in FIG. 2). Therefore, the low potential is input to the gates of the transistors M1 and M1b. Therefore, the transistors M1 and M1b are turned off.

[0095] Furthermore, data to be written to the memory cell MC has not yet been input to the wiring WRDL and the wiring WRDLb. Therefore, in this operation example, from time T11 to time T12, the potentials of the wiring WRDL and the wiring WRDLb are set to the ground potential (shown as GND in FIG. 2), for example. In this operation example, the ground potential is preferably set to 0 V.

[0096] The potentials given by the wirings FCA and FCB are V 0A , V 0B V 0A , and V 0B can be set to, for example, the reference potential or a value close to the reference potential. C It is preferable to set the reference potential to, for example, 0 [V] or the ground potential. C When V C -0.1[V] or more, V C -0.05[V] or more, or V C It is preferable that the potential is -0.01 [V] or more, and V C +0.01[V] or less, V C +0.05[V] or less, or V C It is preferable that the voltage is +0.1 [V] or less. The above-mentioned lower limit and upper limit values ​​can be combined. 0A , and V 0B It is more preferable that the potentials are equal to each other.

[0097] [From time T12 to time T13] Between time T12 and time T13, the potential provided by the wiring WRWL changes from a low-level potential to a high-level potential (denoted as High in FIG. 2). Therefore, a high-level potential is input to the gates of the transistors M1 and M1b, and the transistors M1 and M1b are turned on. That is, the wiring WRDL is electrically connected to the gate of the transistor M6b and the first terminal of the transistor M6 (the output terminal of the FTJ element FJA), and the wiring WRDLb is electrically connected to the gate of the transistor M6 and the first terminal of the transistor M6b (the output terminal of the FTJ element FJAb). Therefore, the ground potential provided by the wiring WRDL is applied to the gate of the transistor M6b (the output terminal of the FTJ element FJA). Therefore, the potential of the gate of the transistor M6 (the output terminal of the FTJ element FJA) is set to the ground potential. Furthermore, the ground potential provided by the wiring WRDLb is applied to the gate of the transistor M6 (the output terminal of the FTJ element FJAb). Therefore, the potential of the gate of the transistor M6 (the output terminal of the FTJ element FJAb) is also set to the ground potential.

[0098] [From time T13 to time T14] Between time T13 and time T14, data to be written to the memory cell MC is transmitted from the wiring WRDL and the wiring WRDLb to the memory cell MC. Specifically, for example, one of V0 or V1 is applied to the wiring WRDL as a potential corresponding to the data, and the other of V0 or V1 is applied to the wiring WRDLb as a potential corresponding to the data. Because the transistors M1 and M1b have been in the on state since before time T13, one of V0 or V1 is applied to the gate of the transistor M6b (the output terminal of the FTJ element FJA) as a potential from the wiring WRDL, and the other of V0 or V1 is applied to the gate of the transistor M6 (the output terminal of the FTJ element FJAb) as a potential from the wiring WRDLb.

[0099] Here, V0 and V1 are each potentials representing binary data (digital values). For example, when the potential of the output terminal of the FTJ element FJA of the memory cell MC is V0, the memory cell MC stores either "0" or "1" as data, or when the potential of the output terminal of the FTJ element FJA of the memory cell MC is V1, the memory cell MC stores the other of "0" or "1" as data. In this operation example, as an example, when the potential of the output terminal of the FTJ element FJA of the memory cell MC is V0, the memory cell MC stores "0" as data, or when the potential of the output terminal of the FTJ element FJA of the memory cell MC is V1, the memory cell MC stores "1" as data. Furthermore, the magnitudes of V0 and V1 can be set so that V1-V0 is a voltage that causes polarization of the FTJ element FJA and the FTJ element FJAb, respectively, or that rewrites the direction of polarization. For example, if the voltage required to generate polarization (to change the direction of polarization) in each of the FTJ elements FJA and FJAb is 3 V, then V1 and V0 should be set so that V1 - V0 is 3 V or more. 0A , and / or V 0B It is preferable that V0 is equal to the potential of V1. Specifically, V0 may be set to 0 V, for example, and V1 may be set to 3 V, for example. Note that although this operation example describes the writing of binary data, the memory cell MC may also be capable of writing, for example, multi-level data or an analog potential.

[0100] After data to be written to the memory cell MC is transmitted from the wiring WRDL and the wiring WRDLb to the memory cell MC, the wiring FCA is supplied with a potential V 1A The wiring FCB is given a potential V 0B is given. V 1A For example, V 0A The potential is higher than V 1Ais a potential at which polarization occurs in the FTJ element FJA (the direction of polarization changes) when the output terminal of the FTJ element FJA is V0. Note that the direction of polarization is from the input terminal to the output terminal of the FTJ element FJA (positive direction). Similarly, V 1A is also a potential at which polarization occurs in the FTJ element FJAb (the direction of polarization changes) when the output terminal of the FTJ element FJAb is at V0. Note that the direction of polarization is from the input terminal to the output terminal of the FTJ element FJAb (positive direction).

[0101] In this example, V 1A is preferably equal to the potential of V1, for example.

[0102] First, let us focus on the FTJ element FJA. When the potential of the output terminal of the FTJ element FJA (the gate of transistor M6b) is V0, the ferroelectric dielectric contained in the FTJ element FJA is polarized in the direction from the input terminal to the output terminal (positive direction). On the other hand, when the potential of the output terminal of the FTJ element FJA (the gate of transistor M6b) is V1, the polarization does not change in the ferroelectric dielectric contained in the FTJ element FJA.

[0103] Next, we focus on the FTJ element FJAb. When the potential of the input terminal (gate of transistor M6) of the FTJ element FJAb is V0, the polarization of the ferroelectric dielectric contained in the FTJ element FJAb does not change. On the other hand, when the potential of the input terminal (gate of transistor M6) of the FTJ element FJAb is V1, the ferroelectric dielectric contained in the FTJ element FJAb is polarized in the direction from the input terminal to the output terminal (positive direction).

[0104] [From time T14 to time T15] Between time T14 and time T15, the wiring FCA is supplied with a potential V 0A The wiring FCB continues to be supplied with a potential V 0B is given.

[0105] First, let us focus on the FTJ element FJA. When the potential of the output terminal of the FTJ element FJA (the gate of transistor M6b) is V0, the direction of polarization does not change in the ferroelectric dielectric contained in the FTJ element FJA. On the other hand, when the potential of the output terminal of the FTJ element FJA (the gate of transistor M6b) is V1, the ferroelectric dielectric contained in the FTJ element FJA is polarized in the direction from the output terminal to the input terminal (negative direction).

[0106] Next, we focus on the FTJ element FJAb. When the potential of the input terminal (gate of transistor M6) of the FTJ element FJAb is V0, the ferroelectric dielectric contained in the FTJ element FJAb is polarized in the direction from the output terminal to the input terminal (negative direction). On the other hand, when the potential of the input terminal (gate of transistor M6) of the FTJ element FJAb is V1, the direction of polarization does not change in the ferroelectric dielectric contained in the FTJ element FJAb.

[0107] Between time T13 and time T15, the potentials of the wirings FCA and FCB change according to the timing chart of Figure 2, and the polarization directions of the FTJ elements FJA and FJAb are determined as shown in the following table depending on the potentials applied to the memory cells MC from the wirings WRDL and WRDLb.

[0108] [Table 1]

[0109] After time T15, the potentials applied by the wirings FCA and FCB are V 0A , V 0B That is, after time T15, the potentials applied by the wirings FCA and FCB are set to be the same as the potentials applied by the wirings FCA and FCB before time T13.

[0110] [From time T15 to time T16] Between time T15 and time T16, data transmission from the lines WRDL and WRDLb to the memory cell MC is completed. Specifically, for example, it is assumed that the lines WRDL and WRDLb are supplied with a ground potential. Since the transistor M1 has been in an on state since before time T15, the ground potential from the line WRDL is supplied to the gate of the transistor M6b (the output terminal of the FTJ element FJAb). Meanwhile, since the transistor M1b has also been in an on state since before time T15, the ground potential from the line WRDLb is supplied to the gate of the transistor M6b (the output terminal of the FTJ element FJAb).

[0111] Even if the potentials of the gate of the transistor M6b (output terminal of the FTJ element FJA) and the gate of the transistor M6 (output terminal of the FTJ element FJAb) become the ground potential, the potential of the wiring FCA remains at V 0A Therefore, the directions of polarization of the FTJ elements FJA and FJAb written between time T14 and time T16 do not change.

[0112] [From time T16 to time T17] Between time T16 and time T17, the potential of the wiring WRWL changes from high to low, so that the low potential is input to the gates of the transistors M1 and M1b, turning off the transistors M1 and M1b.

[0113] By the operation between time T11 and time T17 described above, data can be written to the memory cell MC in FIG. 1A.

[0114] <<Example of data read operation>> Fig. 3 is a timing chart showing an example of a data read operation in the memory cell MC of Fig. 1A. The timing chart of Fig. 3 shows changes in the potentials of the wires WRWL, WRDL, WRDLb, FCA, and FCB between time T21 and time T27 and around those times.

[0115] [From time T21 to time T22] Between time T21 and time T22, the potential of the wiring WRWL is a low-level potential (denoted as Low in FIG. 3). Therefore, a low-level potential is input to the gates of the transistors M1 and M1b. Therefore, the transistors M1 and M1b are both in an off state.

[0116] Between time T21 and time T22, the potentials of the wiring WRDL and the wiring WRDLb are set to the ground potential (denoted as GND in FIG. 3).

[0117] In addition, the potentials applied by the wirings FCA and FCB from time T21 to time T22 are V 0A , V 0B Let's say.

[0118] [From time T22 to time T23] Between time T22 and time T23, the wiring WRDL and the wiring WRDLb are each supplied with a potential V MD is precharged. MD is V 0B is higher than V M The potential is set to be lower than

[0119] [From time T23 to time T24] Between time T23 and time T24, the wiring FCA is supplied with a potential V M The wiring FCB is given a potential V 0B is given. V M is V 0A and V 0B Higher than V 1A The potential of the wiring FCB is set to be lower than V 0B When V Mis set to a potential at which no change in polarization occurs (no change in the direction of polarization) in the FTJ element FJA and the FTJ element FJAb.

[0120] First, consider the case where the ferroelectric dielectric contained in the FTJ element FJA is polarized in the direction from the input terminal to the output terminal (positive direction), and the ferroelectric dielectric contained in the FTJ element FJAb is polarized in the direction from the output terminal to the input terminal (negative direction). In this case, the resistance value of the FTJ element FJA to the current flowing from the input terminal to the output terminal becomes high, while the resistance value of the FTJ element FJAb to the current flowing from the input terminal to the output terminal becomes low. Therefore, the potential of the output terminal of the FTJ element FJAb becomes the potential V given by the wiring FCA. M The gate of the transistor M6 is connected to a potential V M potential (V 0B Since the potential at the output terminal of the FTJ element FJA is higher than the potential V 0B The gate of the transistor M6b is connected to a potential V 0B As a result, the potential of the output terminal of the FTJ element FJAb is set to the potential V M It becomes closer to.

[0121] Next, consider the case where the ferroelectric dielectric contained in the FTJ element FJA is polarized in the direction from the output terminal to the input terminal (negative direction), and the ferroelectric dielectric contained in the FTJ element FJAb is polarized in the direction from the input terminal to the output terminal (positive direction). In this case, the resistance value to the current flowing from the input terminal to the output terminal of the FTJ element FJAb becomes high, while the resistance value to the current flowing from the input terminal to the output terminal of the FTJ element FJA becomes low. Therefore, the potential of the output terminal of the FTJ element FJA becomes equal to the potential V given by the wiring FCA. M The gate of the transistor M6b is connected to a potential V M potential (V 0BSince the potential at the output terminal of the FTJ element FJAb is higher than the potential V 0B The gate of the transistor M6 is connected to a potential V 0B As a result, the potential of the output terminal of the FTJ element FJA is set to the potential V given by the wiring FCA. M It becomes closer to.

[0122] In the explanation of this operation example, if the ferroelectric dielectric included in the FTJ element FJA is polarized in the direction from the input terminal to the output terminal (positive direction) and the ferroelectric dielectric included in the FTJ element FJAb is polarized in the direction from the output terminal to the input terminal (negative direction) between time T23 and time T24, the potential of the output terminal of the FTJ element FJA will be V 0B The potential at the output terminal of the FTJ element FJAb is V M Alternatively, if the ferroelectric dielectric included in the FTJ element FJA is polarized in the direction from the output terminal to the input terminal (negative direction), and the ferroelectric dielectric included in the FTJ element FJAb is polarized in the direction from the input terminal to the output terminal (positive direction), then for convenience, the potential of the output terminal of the FTJ element FJA will be V M The potential at the output terminal of the FTJ element FJAb is V 0B It shall be as follows.

[0123] [From time T24 to time T25] Between time T24 and time T25, the potential applied by the wiring WRWL changes from a low-level potential to a high-level potential (denoted as High in FIG. 3). As a result, the high-level potential is input to the gates of the transistors M1 and M1b, and the transistors M1 and M1b are turned on.

[0124] First, consider the case where the ferroelectric dielectric contained in the FTJ element FJA is polarized in the direction from the input terminal to the output terminal (positive direction), and the ferroelectric dielectric contained in the FTJ element FJAb is polarized in the direction from the output terminal to the input terminal (negative direction). In this case, the potential of the output terminal of the FTJ element FJA is V 0B The potential at the output terminal of the FTJ element FJAb is V M As a result, the charge precharged in the wiring WRDL flows to the wiring FCB via the transistors M1 and M6, and the potential of the wiring WRDL becomes V MD In addition, charges flow from the wiring FCA to the wiring WRDLb via the FTJ element FJAb and the transistor M1b, so the potential of the wiring WRDLb drops to V MD At this time, the potential of the wiring WRDL is V 0R The potential of the wiring WRDLb is V MR It shall be as follows.

[0125] In addition, V 0R For example, V 0B It is preferable that V MR For example, V M It is preferable that:

[0126] Next, consider the case where the ferroelectric dielectric contained in the FTJ element FJA is polarized from the output terminal to the input terminal (negative direction), and the ferroelectric dielectric contained in the FTJ element FJAb is polarized from the input terminal to the output terminal (positive direction). In this case, the potential of the output terminal of the FTJ element FJA is V M The potential at the output terminal of the FTJ element FJAb is V 0B As a result, the charge precharged in the wiring WRDLb flows to the wiring FCB via the transistors M1b and M6b, and the potential of the wiring WRDLb becomes V MD In addition, charges flow from the wiring FCA to the wiring WRDL via the FTJ element FJA and the transistor M1, so the potential of the wiring WRDL drops to V MDAt this time, the potential of the wiring WRDL is V M The potential of the wiring WRDLb is V 0R It shall be as follows.

[0127] Here, by reading out the potentials of the wiring WRDL and the wiring WRDLb, the data held in the memory cell MC can be read out. For example, if the ferroelectric dielectric included in the FTJ element FJA is polarized in the direction from the input terminal to the output terminal (positive direction) and the ferroelectric dielectric included in the FTJ element FJAb is polarized in the direction from the output terminal to the input terminal (negative direction), the data "0" written in the memory cell MC can be read out by reading out the potentials of the wiring WRDL and the wiring WRDLb. Also, if the ferroelectric dielectric included in the FTJ element FJA is polarized in the direction from the output terminal to the input terminal (negative direction) and the ferroelectric dielectric included in the FTJ element FJAb is polarized in the direction from the input terminal to the output terminal (positive direction), the data "0" written in the memory cell MC can be read out by reading out the potentials of the wiring WRDL and the wiring WRDLb.

[0128] Note that when reading out the potentials of the wiring WRDL and the wiring WRDLb, for example, a sense amplifier or the like can be used.

[0129] After time T25, the potentials applied by the wirings FCA and FCB are V 0A , V 0B That is, after time T25, the potentials applied by the wirings FCA and FCB are set to be the same as the potentials applied by the wirings FCA and FCB before time T23.

[0130] [From time T25 to time T26] Between time T25 and time T26, the ground potential is input to each of the wires WRDL and WRDLb. Since the transistor M1 has been in the on state since before time T25, the ground potential from the wire WRDL is applied to the gate of the transistor M6b (the output terminal of the FTJ element FJAb). Meanwhile, since the transistor M1b has also been in the on state since before time T125, the ground potential from the wire WRDLb is applied to the gate of the transistor M6 (the output terminal of the FTJ element FJAb).

[0131] Even if the potentials of the gate of the transistor M6b (output terminal of the FTJ element FJA) and the gate of the transistor M6 (output terminal of the FTJ element FJAb) become the ground potential, the potential of the wiring FCA remains at V 0A Therefore, the polarization directions of the FTJ elements FJA and FJAb do not change.

[0132] [From time T26 to time T27] Between time T26 and time T27, the potential of the wiring WRWL changes from high to low, so that the low potential is input to the gates of the transistors M1 and M1b, turning off the transistors M1 and M1b.

[0133] The above-described example of the operation between time T21 and time T27 allows the data written to the memory cell MC of FIG. 1A to be read. Furthermore, when data is read from the memory cell MC of FIG. 1A, the polarization directions of the FTJ elements FJA and FJAb do not change, so the above-described example of the data read operation is not destructive. In other words, the data written to the memory cell MC can be read from the memory cell MC while retaining the data.

[0134] 3, a method of reading data from the memory cell MC that is not destructive read has been described, but the data read from the memory cell MC in FIG. 1 may be destructive read. In this case, the potential input to the wiring FCA between time T23 and time T24 may be, for example, V 1A Furthermore, it is preferable that an integrating circuit (QV circuit) be used as a readout circuit electrically connected to the wiring WRDL and the wiring WRDLb.

[0135] 2 and 3 described in this embodiment are merely examples, and the operations can be changed depending on the situation or the occasion. For example, a high-level potential is applied to the wiring WRWL from time T12 to time T16 in the timing chart of FIG. 2, and one of V0 and V1 is applied to the wiring WRDL and the other of V0 and V1 is applied to the wiring WRDLb from time T13 to time T15. However, a high-level potential may be applied to the wiring WRWL during the period when one of V0 and V1 is applied to the wiring WRDL and the other of V0 and V1 is applied to the wiring WRDLb. Also, a potential V 1A is applied, and the wiring FCB is at potential V 0B is applied to the wiring FCA, and 0A is applied, and the wiring FCB is at potential V 0B The period during which the potential V is applied to the wiring WRWL may be any period during which a high-level potential is applied to the wiring WRWL, one of V0 and V1 is applied to the wiring WRDL, and the other of V0 and V1 is applied to the wiring WRDLb. 0A is applied, and the wiring FCB is at potential V 0B The period during which the potential V is applied to the wiring FCA is from time T13 to time T14. 1A is applied, and the wiring FCB is at potential V 0B may be performed prior to the given period.

[0136] <Configuration example 2> The memory cell MC included in a memory device, which is a semiconductor device of one embodiment of the present invention, is not limited to the circuit configuration shown in Figure 1A. The circuit configuration of the memory cell MC included in the memory device may be changed depending on the case or situation. In this configuration example, a memory cell MC in which one of the FTJ element FJA and the FTJ element FJAb included in the memory cell MC of Figure 1A is replaced with another circuit element will be described.

[0137] For example, the memory cell MC may have a configuration in which the FTJ element FJA is replaced with a ferroelectric capacitor FEA, and the FTJ element FJAb is replaced with a ferroelectric capacitor FEAb, as shown in FIG. 4A.

[0138] In the drawings of this specification, the circuit symbol for a ferroelectric capacitor (e.g., ferroelectric capacitor FEA, ferroelectric capacitor FEAb, etc.) is a circuit symbol for a capacitance with diagonal lines added, as shown in Fig. 4A. Alternatively, as shown in Fig. 4B, a circuit symbol for a capacitance may be one in which multiple diagonal lines are added between two parallel lines.

[0139] 4A and 4B, a first terminal of the ferroelectric capacitor FEA is electrically connected to the wiring FCA, a second terminal of the ferroelectric capacitor FEA is electrically connected to the second terminal of the transistor M1, the first terminal of the transistor M6, and the gate of the transistor M6b, and a first terminal of the ferroelectric capacitor FEAb is electrically connected to the wiring FCA, and a second terminal of the ferroelectric capacitor FEAb is electrically connected to the second terminal of the transistor M1b, the first terminal of the transistor M6b, and the gate of the transistor M6.

[0140] 4A and 4B, even if the FTJ element FJA and the FTJ element FJAb of the memory cell of FIG. 1A are replaced with ferroelectric capacitors FEA and FEAb, respectively, the memory cell MC of FIG. 4A and 4B can hold write data transmitted from the wiring WRDL and the wiring WRDLb and output the written data. In this case, the read circuit electrically connected to the wiring WRDL and the wiring WRDLb may be, for example, an integration circuit that converts the amount of charge flowing through the wiring into a voltage.

[0141] The method of writing data to the memory cells MC in FIGS. 4A and 4B may be the same as the method of writing data shown in FIG. 2, for example.

[0142] Furthermore, in the memory cell MC of FIGS. 4A and 4B, data is read, for example, by turning on each of the transistors M1 and M1b and setting the potentials of the wirings WRDL and WRDLb to ground potential. Then, a predetermined potential is input to the wiring FCA. This potential is set to a level that changes the direction of polarization of the ferroelectric material contained in each of the ferroelectric capacitors FEA and FEAb when the second terminals of the ferroelectric capacitors FEA and FEAb are at ground potential. Therefore, this potential may be either a negative potential or a positive potential, as long as it is a potential that changes the direction of polarization of the ferroelectric material.

[0143] By applying a ground potential to the second terminals of the ferroelectric capacitors FEA and FEAb and applying the same potential to the wiring FCA, the polarization direction of the ferroelectric material of the ferroelectric capacitors FEA and FEAb is changed. Specifically, the polarization direction of the dielectric of each of the ferroelectric capacitors FEA and FEAb changes from the first terminal to the second terminal. Before data is read, one of the dielectrics of the ferroelectric capacitors FEA and FEAb is polarized from the first terminal to the second terminal, and the other of the dielectrics of the ferroelectric capacitors FEA and FEAb is polarized from the second terminal to the first terminal. Therefore, when data is read, the polarization direction of the other of the dielectrics of the ferroelectric capacitors FEA and FEAb changes.

[0144] At this time, the direction of polarization of the other dielectric of the ferroelectric capacitor FEA and the ferroelectric capacitor FEAb changes, and the charge of the other of the ferroelectric capacitors FEA and FEAb changes. Therefore, the amount of change in the charge can be read using an integrating circuit electrically connected to the wiring WRDL or the wiring WRDLb, thereby reading out the data stored in the memory cell MC.

[0145] Note that the read operation described above is a destructive read because the direction of polarization of the other dielectric of the ferroelectric capacitor FEA and the ferroelectric capacitor FEAb changes, so after reading the data stored in the memory cell MC, it is necessary to write the data to the memory cell MC again.

[0146] 4A and 4B show an example in which the FTJ element FJA and the FTJ element FJAb of the memory cell MC of FIG. 1A are replaced with ferroelectric capacitors FEA and FEAb. However, the FTJ element FJA and the FTJ element FJAb of the memory cell MC of FIG. 1A may be replaced with circuit elements other than ferroelectric capacitors. For example, the FTJ element FJA and the FTJ element FJAb of the memory cell MC of FIG. 1A may be replaced with circuit elements ANA and ANAb, whose resistance values ​​can be changed, as shown in FIG. 4C. Specifically, the input terminal of the circuit element ANA is electrically connected to the wiring FCA, and the output terminal of the circuit element ANA is electrically connected to the second terminal of the transistor M1, the first terminal of the transistor M6, and the gate of the transistor M6b. The input terminal of the circuit element ANAb is electrically connected to the wiring FCA, and the output terminal of the circuit element ANAb is electrically connected to the second terminal of the transistor M1b, the first terminal of the transistor M6b, and the gate of the transistor M6. Examples of the circuit element ANA and the circuit element ANAb include resistance change elements used in ReRAM (Resistive Random Access Memory), MTJ (Magnetic Tunnel Junction or Magnetic Transportation Junction) elements used in MRAM (Magnetoresistive Random Access Memory), and phase change memory (PCM) elements.

[0147] As in the memory cell MC of Figure 4C, even if the FTJ elements FJA and FJAb of the memory cell of Figure 1A are replaced with the circuit elements ANA and ANAb, respectively, the circuit elements ANA and ANAb can change their resistance values, similar to the FTJ elements FJA and FJAb of the memory cell MC of Figure 1 A. Therefore, similar to the memory cell MC of Figure 1A, the memory cell MC of Figure 4C may be able to write data to the memory cell MC and read the data without destroying the stored data.

[0148] <Configuration example 3> In this configuration example, a memory cell that can be included in a memory device that is a semiconductor device of one embodiment of the present invention, which is different from the memory cell MC in FIG. 1A, will be described.

[0149] The memory cell MC shown in FIG. 5A is a modified example of the memory cell MC in FIG. 1A, and has a configuration in which a transistor M7 and a transistor M8 are further provided in the memory cell MC in FIG. 1A.

[0150] A first terminal of the transistor M7 is electrically connected to the wiring VCE, a second terminal of the transistor M7 is electrically connected to a first terminal of the transistor M8, a gate of the transistor M7 is electrically connected to an output terminal of the FTJ element FJA, a second terminal of the transistor M1, a first terminal of the transistor M6, and a gate of the transistor M6b, a second terminal of the transistor M8 is electrically connected to the wiring RDL, and a gate of the transistor M8 is electrically connected to the wiring RWLA.

[0151] The wiring VCE functions as a wiring that applies a constant voltage, for example, a low-level potential, a ground potential, or the like.

[0152] The wiring RDL functions as, for example, a wiring for transmitting data read from the memory cell MC.

[0153] The wiring RWLA functions as, for example, a wiring for selecting a memory cell MC from which data is to be read.

[0154] For an example of the operation of writing data to the memory cell MC in Fig. 5A, refer to the timing chart in Fig. 2. During the operation of writing data to the memory cell MC in Fig. 5A, the potentials applied to the wirings RWLA and RDL are preferably low-level potentials, ground potentials, or the like.

[0155] For an example of a data read operation from the memory cell MC of FIG. 5A, refer to the timing chart of FIG. 3. Note that, as an example, the line VCE is applied with a ground potential. In the memory cell MC of FIG. 5A, for example, between time T24 and time T25 in the timing chart of FIG. 3, a high-level potential is applied to the line RWLA, turning on the transistor M8, and a high-level potential is preferably applied to the line RDL. As a result, the first terminal of the transistor M7 is applied with a ground potential and the second terminal of the transistor M7 is applied with a high-level potential. The amount of current flowing between the first and second terminals of the transistor M7 is determined by the potential of the gate of the transistor M7 (the output terminal of the FTJ element FJAb). Since the current flows through the line RDL, the amount of the current can be converted into a voltage using a current-voltage converter or the like electrically connected to the line RDL, thereby reading data from the memory cell MC of FIG. 5A.

[0156] Next, a memory cell that can be included in a memory device that is a semiconductor device of one embodiment of the present invention, which is different from the memory cell MC in FIGS. 1A, 1B, and 5A, will be described.

[0157] The memory cell MC shown in Figure 5B is a modified example of the memory cell MC of Figure 5A, and differs from the memory cell MC of Figure 5A in that it has a transistor M9 and a capacitance CS, and that the gate of the transistor M7 is electrically connected to the output terminal of the FTJ element FJA via the capacitance CS.

[0158] 5B has the function of correcting the threshold voltage of transistor M7 in addition to the functions of the memory cell MC of FIG. 5A. By correcting the threshold voltage of transistor M7, the amount of current flowing between the first terminal and the second terminal of transistor M7 may become independent of the threshold voltage of transistor M7. As a result, for example, in a memory cell array in which multiple memory cells MC of FIG. 5B are arranged, the variation in the threshold voltage of transistor M7 included in each of the multiple memory cells MC can be reduced, thereby preventing erroneous data reading from the multiple memory cells MC.

[0159] The gate of the transistor M7 is electrically connected to the first terminal of the capacitor CS and the first terminal of the transistor M9, and the second terminal of the capacitor CS is electrically connected to the output terminal of the FTJ element FJA, the second terminal of the transistor M1, the first terminal of the transistor M6, and the gate of the transistor M6b. The second terminal of the transistor M9 is electrically connected to the second terminal of the transistor M7 and the first terminal of the transistor M8, and the gate of the transistor M9 is electrically connected to the wiring WCL. In FIG. 5B, the electrical connection point between the gate of the transistor M7, the first terminal of the capacitor CS, and the first terminal of the transistor M9 is referred to as a node ND.

[0160] For example, the wiring WCL functions as a control wiring that switches the transistor M9 between an on state and an off state. Specifically, for example, the wiring WCL has a function of inputting a high-level potential or a low-level potential to turn the transistor M9 on or off when correcting the threshold voltage of the transistor M7.

[0161] <<Example of threshold voltage correction operation>> Next, an operation for correcting the threshold voltage of the transistor M7 will be described. This operation example can be performed, for example, before or after writing data to the memory cell MC of FIG.

[0162] Fig. 7 is a timing chart showing an example of an operation for correcting the threshold voltage of transistor M7 in memory cell MC of Fig. 5B. The timing chart shown in Fig. 7 shows changes in the potentials of wirings WRWL, RWL, WCL, WRDL, RDL, and node ND from time T31 to time T36 and at times around those times.

[0163] [From time T31 to time T32] Between time T31 and time T32, the potentials of the wirings WRWL, RWL, and WCL are, for example, low-level potentials (denoted as "Low" in FIG. 7). Therefore, the low-level potentials are input to the gates of the transistors M1 and M1b. Therefore, the transistors M1, M1b, M8, and M9 are turned off.

[0164] Between time T31 and time T32, the potentials of the wiring WRDL and the wiring RDL are, for example, at the ground potential (denoted as GND in FIG. 7).

[0165] In addition, from time T31 to time T32, the potential of the node ND is set to the ground potential, for example.

[0166] [From time T32 to time T33] Between time T32 and time T33, the potentials applied by the wirings WRWL, RWL, and WCL change from low-level potential to high-level potential (denoted as "High" in FIG. 7). Therefore, a high-level potential is input to the gates of the transistors M1, M1b, M8, and M9, and the transistors M1, M1b, M8, and M9 are turned on. That is, the wiring WRDLb and the second terminal of the capacitor CS are electrically connected, and the wiring RDL and the first terminal of the capacitor CS are electrically connected. Therefore, the potentials of the output terminal of the FTJ element FJAb and the node ND are grounded, and the voltage between the first terminal and the second terminal of the capacitor CS is approximately 0 V.

[0167] [From time T33 to time T34] Between time T33 and time T34, the wiring RDL is supplied with a potential V D is given. The potential V D is set to a potential higher than the threshold voltage of the transistor M7, for example. At this time, the first terminal (node ​​ND) of the capacitor CS is supplied with the potential V D is given.

[0168] [From time T34 to time T35] Between time T34 and time T35, the potential applied to the wiring RWL changes from high to low, so that the low potential is input to the gate of the transistor M8, turning off the transistor M8.

[0169] Since the transistor M9 is in the ON state, the second terminal and gate of the transistor M7 are in a conductive state. Also, since the transistor M8 is in the OFF state, the potential of the first terminal (node ​​ND) of the capacitor CS drops due to a current flowing between the first terminal and the second terminal of the transistor M7. The drop in the potential of the first terminal (node ​​ND) of the capacitor CS occurs when the gate-source voltage of the transistor M7 drops below the threshold voltage (Vth This continues until the potential at the gate of the transistor M7 (the first terminal of the capacitor CS, the node ND) becomes equal to V D From V th It drops to.

[0170] [From time T35 to time T36] Between time T35 and time T36, the potential applied to the wiring WCL changes from a high-level potential to a low-level potential. As a result, a low-level potential is input to the gate of the transistor M9, and the transistor M9 is turned off. This maintains the voltage between the first terminal and the second terminal of the capacitor CS. At this time, the potential of the gate of the transistor M7 (the first terminal of the capacitor CS, the node ND) is V th and the gate-source voltage of the transistor M7 is equal to the threshold voltage.

[0171] Here, for example, if the potential of the second terminal of the capacitance CS is changed from the ground potential to the potential V MR When the voltage at the gate of transistor M7 changes to V MR +V th In addition, the difference between the gate-source voltage and the threshold voltage of the transistor M7 at this time is (V MR +V th )-V th =V MR By applying a potential higher than the ground potential to the second terminal of the transistor M7, a current flows between the source and drain of the transistor M7 according to the difference between the gate-source voltage and the threshold voltage of the transistor M7 and the source-drain voltage. MR Therefore, the current flowing between the source and drain of transistor M7 does not depend on the threshold voltage of transistor M7. In this way, by correcting the threshold voltage of transistor M7, a current that does not depend on the threshold voltage of transistor M7 can flow between the source and drain of transistor M7.

[0172] As described above, the threshold voltage of the transistor M7 can be corrected by the example of the operation from time T31 to time T36 shown in FIG.

[0173] <Configuration Example 4> The memory cell MC illustrated in Fig. 6 is an example of a circuit configuration of a memory cell that can be applied to a memory device of one embodiment of the present invention. The memory cell MC in Fig. 6 is a modified example of the memory cell MC in Fig. 5A, and has a configuration in which a transistor M7b and a transistor M8b are further provided in addition to the memory cell MC in Fig. 5A.

[0174] A first terminal of the transistor M7b is electrically connected to the wiring VCE, a second terminal of the transistor M7b is electrically connected to a first terminal of the transistor M8b, a gate of the transistor M7b is electrically connected to an output terminal of the FTJ element FJA, a second terminal of the transistor M1, a first terminal of the transistor M6, and a gate of the transistor M6b, a second terminal of the transistor M8b is electrically connected to the wiring RDLb, and gates of the transistors M8 and M8b are electrically connected to the wiring RWLA.

[0175] For example, the line RDLb functions as a line for transmitting data read from the memory cell MC, similar to the line RDL. The line RDL and the line RDLb function as a line pair for transmitting complementary data.

[0176] 2 is referred to for an example of the operation of writing data to the memory cell MC in Fig. 6. In addition, during the operation of writing data to the memory cell MC in Fig. 6, the potentials applied to the wiring RWLA, the wiring RDL, and the wiring RDLb are preferably, for example, a low-level potential or a ground potential.

[0177] For an example of a data read operation from the memory cell MC of FIG. 6, refer to the timing chart of FIG. 3. Note that, as an example, the wiring VCE is applied with a ground potential. In the memory cell MC of FIG. 6, for example, between time T24 and time T25 in the timing chart of FIG. 3, a high-level potential is applied to the wiring RWLA, turning on the transistors M8 and M8b, and a high-level potential is applied to the wirings RDL and RDLb. Thus, the first terminal of the transistor M7 is applied with a ground potential and the second terminal of the transistor M7 is applied with a high-level potential. Therefore, the amount of current flowing between the first and second terminals of the transistor M7 is determined by the potential of the gate of the transistor M7 (the output terminal of the FTJ element FJAb). At the same time, the first terminal of the transistor M7b is applied with a ground potential and the second terminal of the transistor M7b is applied with a high-level potential. Therefore, the amount of current flowing between the first and second terminals of the transistor M7b is determined by the potential of the gate of the transistor M7b (the output terminal of the FTJ element FJAb). In other words, currents flow through the wiring RDL and the wiring RDLb according to the source-drain voltages of the transistors M7 and M7b, respectively. Therefore, for example, by converting the amount of current flowing through the wiring RDL and the wiring RDLb into a voltage value using a current-voltage conversion circuit or the like, data can be read from the memory cell MC in Figure 7.

[0178] By applying the memory cell MC to the semiconductor device described in this embodiment, a semiconductor device that does not require rewriting of data (a semiconductor device that performs non-destructive readout) can be configured. Furthermore, by applying the memory cell MC to the semiconductor device, data rewriting is no longer necessary, and therefore power consumption required for rewriting can be reduced. Furthermore, by applying the memory cell MC to the semiconductor device, there is no need to provide a circuit that rewrites data, and therefore the circuit area of ​​the semiconductor device can be reduced.

[0179] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0180] (Embodiment 2) In this embodiment, a memory device that can include the memory cells MC described in the above embodiment will be described.

[0181] <Storage device configuration example> 8 shows an example of the circuit configuration of the memory device. The memory device 100 has a memory cell array MCA, a circuit WDD, a circuit WRWD, a circuit RDD, and a circuit FECD. Note that the memory cell MC applicable to the memory device 100 of FIG. 8 is the memory cell MC of FIG. 1A (FIG. 1B) as an example.

[0182] The memory cell array MCA has a plurality of memory cells MC. In the memory cell array MCA, the plurality of memory cells MC are arranged in a matrix of m rows and n columns (m and n are integers of 1 or more). In Fig. 8, for example, a memory cell MC located in the i-th row and j-th column (i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less) is illustrated as memory cell MC[i,j].

[0183] In addition, in the memory cell array MCA of the memory device 100, wirings WRDL[1] to WRDL[n] and wirings WRDLb[1] to WRDLb[n] are arranged extending in the column direction. Note that the [j] attached to the wirings WRDL and WRDLb indicates that they are wirings in the jth column. Also, wirings WRWL[1] to WRWL[m], wirings FCA[1] to FCA[m], and wirings FCB[1] to FCB[m] are arranged extending in the row direction. Note that the [i] attached to the wirings WRWL, FCA, and FCB indicates that they are wirings in the i-th row.

[0184] The wirings WRDL[1] to WRDL[n] correspond to the wiring WRDL in the memory cell MC in Figure 1A (Figure 1B). The wirings WRWL[1] to WRWL[m] correspond to the wiring WRDL in the memory cell MC in Figure 1A (Figure 1B), the wirings FCA[1] to FCA[m] correspond to the wiring FCA in the memory cell MC in Figure 1A (Figure 1B), and the wirings FCB[1] to FCB[m] correspond to the wiring FCB in the memory cell MC in Figure 1A (Figure 1B).

[0185] The circuit WDD is electrically connected to the wirings WRDL[1] to WRDL[n] and WRDLb[1] to WRDLb[n]. The circuit RDD is electrically connected to the wirings WRDL[1] to WRDL[n] and WRDLb[1] to WRDLb[n]. The circuit FECD is electrically connected to the wirings FCA[1] to FCA[m] and FCB[1] to FCB[m].

[0186] The circuit WRWD functions as a write word line driver circuit, for example. For example, the circuit WRWD can select multiple memory cells MC in the memory cell array MCA to perform a write operation by transmitting a select signal to one of the wirings WRWL[1] to WRWL[m] and a non-select signal to the remaining wirings. Specifically, for example, in the case of the memory cell MC of FIG. 1A, the select signal may be a high-level potential and the non-select signal may be a low-level potential. In the memory cell MC of FIG. 1A, when a high-level potential is applied to the wiring WRWL, the transistor M1 is turned on, and data to be written can be transmitted to the memory cell MC from the wirings WRDL and WRDLb. On the other hand, in the memory cell MC of FIG. 1A (FIG. 1B), when a low-level potential is applied to the wiring WRWL, the transistor M1 is turned off. Therefore, even if data to be written to another memory cell MC is transmitted from the wirings WRDL and WRDLb, the data is not written to the memory cell MC to which the low-level potential is applied from the wiring WRWL.

[0187] The circuit WRWD also functions as a read word line driver circuit, for example. For example, the circuit WRWD can select multiple memory cells MC for a read operation in the memory cell array MCA by transmitting a select signal to one of the wirings RWL[1] to RWL[m] and a non-select signal to the remaining wirings. Specifically, for example, in the case of the memory cell MC of FIG. 1A, the select signal may be a high-level potential and the non-select signal may be a low-level potential. In the memory cell MC of FIG. 1A, applying a high-level potential to the wiring WRWL turns on the transistor M1, allowing data stored in the memory cell MC to be transmitted from the memory cell MC to the wirings WRDL and WRDLb. On the other hand, in the memory cell MC of FIG. 1A, applying a low-level potential to the wiring WRWL turns off the transistors M1 and M1b, preventing data stored in the memory cell MC from being transmitted from the memory cell MC to the wirings WRDL and WRDLb.

[0188] As an example, the circuit FECD has a function of applying a potential to each of the wirings FCA and FCB. Specifically, for example, when writing data to a memory cell MC, the circuit FECD applies a potential to each of the wirings FCA and FCB, thereby generating polarization (changing the direction of polarization) in the FTJ elements FJA and FJAb provided in each of the multiple memory cells MC. Alternatively, when reading data from the memory cell MC, the circuit FECD applies a potential to each of the wirings FCA and FCB, thereby determining the potentials of the output terminals of the FTJ elements FJA and FJAb according to the direction of polarization of the FTJ elements FJA and FJAb.

[0189] The circuit WDD functions as a write data line driver circuit, for example. For example, the circuit WDD can write the write data (for example, a voltage) to the wirings WRDL[1] to WRDL[n] and the wirings WRDL[1] to WRDL[n], respectively, to a plurality of memory cells MC arranged in a specific row selected by the circuit WRWD.

[0190] The circuit RDD functions as a read circuit, for example. For example, the circuit RDD can acquire data (e.g., voltage, current, etc.) output from a plurality of memory cells MC arranged in a specific row selected by the circuit WRWD from each of the wirings WRDL[1] to WRDL[n] and WRDLb[1] to WRDLb[n], and read the data. For example, the circuit WDD includes one or more selected from a precharge circuit, a sense amplifier circuit, a current-voltage conversion circuit, etc.

[0191] <Example of storage device operation> Next, an example of the operation of the storage device 100 will be described.

[0192] <<Write operation example 1>> Fig. 9 is a timing chart showing an example of an operation of writing data to a memory cell MC of the memory device 100. Note that the timing chart of Fig. 2 described in the above embodiment shows an example of an operation in one memory cell MC, whereas the timing chart of Fig. 9 shows an example of an operation of writing data to a plurality of memory cells MC included in a memory cell array MCA.

[0193] The timing chart of Figure 9 shows the changes in potential of wiring WRWL[1], wiring WRWL[2], wiring WRWL[m], wiring WRDL[1], wiring WRDLb[1], wiring WRDL[2], wiring WRDLb[2], wiring WRDL[n], wiring WRDLb[n], wiring FCA[1], wiring FCB[1], wiring FCA[2], wiring FCB[2], wiring FCA[m], and wiring FCB[m] between time U1 and time U10 and at times around those times.

[0194] Between time U1 and time U2, for example, the circuit WRWD applies a low-level potential (denoted as Low in FIG. 9) to the wirings WRWL[1] to WRWL[m] as an initial potential. Therefore, the low-level potential is applied to the gates of the transistors M1 of all the memory cells MC included in the memory cell array MCA, and the transistors M1 are turned off.

[0195] Furthermore, between time U1 and time U2, the circuit WDD does not transmit write data to the wirings WRDL[1] to WRDL[n] and WRDLb[1] to WRDLb[n]. Therefore, between time U1 and time U2, the circuit WDD applies, for example, a ground potential to the wirings WRDL[1] to WRDL[n] and WRDLb[1] to WRDLb[n].

[0196] Furthermore, between time U1 and time U2, a switch or the like included in the circuit RDD or the like may be used to bring the circuit RDD into a non-conductive state with respect to the wirings WRDL[1] to WRDL[n] and the wirings WRDLb[1] to WRDLb[n]. By bringing the circuit RDD into a non-conductive state with respect to the wirings WRDL[1] to WRDL[n] and the wirings WRDLb[1] to WRDLb[n], write data sent from the circuit WDD to the wirings WRDL[1] to WRDL[n] and the wirings WRDLb[1] to WRDLb[n] is not input to the circuit RDD, which may reduce the power consumption required to transmit write data from the circuit WDD to the wirings WRDL[1] to WRDL[n] and the wirings WRDLb[1] to WRDLb[n].

[0197] Between time U1 and time U2, the circuit FECD supplies the potential V 0A , and potential V 0B The potential V 0A , and potential V 0B For details, please refer to the explanation of the timing chart in Figure 2.

[0198] Between time U2 and time U4, the circuit WRWD applies a high-level potential (denoted as "High" in FIG. 9) to the wiring WRWL[1] and a low-level potential to the wirings WRWL[2] to WRWL[m]. Therefore, in the memory cell array MCA, a high-level potential is applied to the gates of the transistors M1 and M1b included in each of the memory cells MC[1,1] to MC[1,n] arranged in the first row, so that the transistors M1 and M1b included in each of the memory cells MC[1,1] to MC[1,n] are turned on. In addition, in the memory cell array MCA, a low-level potential is applied to the gates of the transistors M1 and M1b included in each of the memory cells MC[2,1] to MC[m,n] arranged in the second to m rows, so that the transistors M1 and M1b included in each of the memory cells MC[2,1] to MC[m,n] are turned off. In other words, the circuit WRWD can select the memory cell MC located in the first row of the memory cell array MCA as the write destination by applying a high-level potential to the wiring WRWL[1] and a low-level potential to the wirings WRWL[2] to WRWL[m].

[0199] Furthermore, between time U2 and time U4, the circuit WDD provides, for example, Da[1,1] to Da[1,n], which are part of the rewrite data, to the wirings WRDL[1] to WRDL[n], respectively. The circuit WDD also provides, for example, Db[1,1] to Db[1,n], as write data, to the wirings WRDLb[1] to WRDLb[n], respectively. For example, when Da[1,j] and Db[1,j] (where j is an integer between 1 and n) are digital values, Da[1,j] and Db[1,j] are preferably logically inverted data. Specifically, when the potential corresponding to Da[1,j] is V0, the potential corresponding to Db[1,j] is preferably V1, or when the potential corresponding to Da[1,j] is V1, the potential corresponding to Db[1,j] is preferably V0. Note that for V0 and V1, refer to the description of V0 and V1 described in the operation example of the timing chart in Fig. 2. Furthermore, since the memory cell MC arranged in the first row of the memory cell array MCA is selected as the write destination by the circuit WRWD, potentials according to Da[1,1] to Da[1,n] are applied to the second terminals of the transistors M1 of the memory cells MC[1,1] to MC[1,n], respectively, and potentials according to Db[1,1] to Db[1,n] are applied to the second terminals of the transistors M1b of the memory cells MC[1,1] to MC[1,n], respectively.

[0200] Also, between time U2 and time U3, the circuit FECD applies a potential V 1A Applying a potential V 0B The circuit FECD applies a potential V 0A and a potential V 0B Give.

[0201] Furthermore, between time U3 and time U4, the circuit FECD applies a potential V 0A Applying a potential V 0BThe circuit FECD continues to apply a potential V 0A and a potential V 0B Give.

[0202] In addition, the potential V 1A , and potential V 1B For details, please refer to the explanation of the timing chart in Figure 2.

[0203] By the operation from time U2 to time U4, the direction of polarization generated in the FTJ element FJA and the FTJ element FJAb included in each of the memory cells MC[1,1] to MC[1,n] in the first row of the memory cell array MCA is determined according to Da[1,1] to Da[1,n] sent from the wiring WRDL[1] to wiring WRDL[n] and Db[1,1] to Db[1,n] sent from the wiring WRDLb[1] to wiring WRDLb[n]. In other words, focusing on the j-th column, Da[1,j] and Db[1,j] are written to the memory cell MC[1,j] in the operation from time U2 to time U4.

[0204] Between time U4 and time U6, the circuit WRWD applies a high-level potential to the wiring WRWL[2] and a low-level potential to the wiring WRWL[1] and the wirings WRWL[3] to WRWL[m]. Therefore, in the memory cell array MCA, a high-level potential is applied to the gates of the transistors M1 and M1b included in each of the memory cells MC[2,1] to MC[2,n] arranged in the second row, so that the transistors M1 and M1b included in each of the memory cells MC[2,1] to MC[2,n] are turned on. In the memory cell array MCA, a high-level potential is applied to the gates of the transistors M1 and M1b included in the memory cells MC[1,1] to MC[1,n] and the memory cells MC[3,1] to MC[m,n] arranged in the first row and the third to m rows, respectively. Therefore, the transistors M1 and M1b included in the memory cells MC[1,1] to MC[1,n] and the memory cells MC[3,1] to MC[m,n], respectively, are turned off. In other words, the circuit WRWD applies a high-level potential to the wiring WRWL[2] and a low-level potential to the wirings WRWL[1] and WRWL[3] to WRWL[m], thereby selecting the memory cell MC arranged in the second row of the memory cell array MCA as a write destination.

[0205] Furthermore, between time U4 and time U6, the circuit WDD provides, for example, Da[2,1] to Da[2,n], which are part of the write data, to the wirings WRDL[1] to WRDL[n], respectively. The circuit WDD also provides, for example, Db[2,1] to Db[2,n], as the write data, to the wirings WRDLb[1] to WRDLb[n], respectively. For example, when Da[2,j] and Db[2,j] are digital values, Da[2,j] and Db[2,j] are preferably logically inverted data. Specifically, when the potential corresponding to Da[2,j] is V0, the potential corresponding to Db[2,j] is preferably V1, or when the potential corresponding to Da[2,j] is V1, the potential corresponding to Db[2,j] is preferably V0. Note that for V0 and V1, refer to the description of V0 and V1 described in the operation example of the timing chart in Fig. 2. Furthermore, since the memory cell MC arranged in the second row of the memory cell array MCA is selected as the write destination by the circuit WRWD, potentials according to Da[2,1] to Da[2,n] are applied to the second terminals of the transistors M1 of the memory cells MC[2,1] to MC[2,n], respectively, and potentials according to Db[2,1] to Db[2,n] are applied to the second terminals of the transistors M1b of the memory cells MC[2,1] to MC[2,n], respectively.

[0206] Also, between time U4 and time U5, the circuit FECD applies a potential V 1A Applying a potential V 0B Note that the circuit FECD applies a potential V 0A and a potential V 0B Give.

[0207] Furthermore, between time U5 and time U6, the circuit FECD applies a potential V 0A Applying a potential V 0BThe circuit FECD continues to apply a potential V 0A and applies a potential V to each of the wirings FCB[1] and FCB[3] to FCB[m]. 0B Give.

[0208] By the operation from time U4 to time U6, the direction of polarization generated in the FTJ element FJA and the FTJ element FJAb included in each of the memory cells MC[2,1] to MC[2,n] in the second row of the memory cell array MCA is determined according to Da[2,1] to Da[2,n] sent from the wiring WRDL[1] to wiring WRDL[n] and Db[2,1] to Db[2,n] sent from the wiring WRDLb[1] to wiring WRDLb[n]. In other words, focusing on the j-th column, Da[2,j] and Db[2,j] are written to the memory cell MC[2,j] by the operation from time U4 to time U6.

[0209] Between time U6 and time U7, a data write operation is performed to memory cells MC arranged in the third to m-1th rows of the memory cell array MCA, similar to the data write operation to memory cells MC arranged in the first row of the memory cell array MCA that was performed between time U2 and time U4, and the data write operation to memory cells MC arranged in the second row of the memory cell array MCA that was performed between time U4 and time U6.

[0210] Between time U7 and time U9, the circuit WRWD applies a high-level potential to the wiring WRWL[m] and a low-level potential to the wirings WRWL[1] to WRWL[m-1]. Therefore, in the memory cell array MCA, a high-level potential is applied to the gates of the transistors M1 and M1b included in each of the memory cells MC[m,1] to MC[m,n] arranged in the m-th row, so that the transistors M1 and M1b included in each of the memory cells MC[m,1] to MC[m,n] are turned on. Furthermore, in the memory cell array MCA, a low-level potential is applied to the gates of the transistors M1 and M1b included in each of the memory cells MC[1,1] to MC[m-1,n] arranged in the 1st to m-1st rows, so that the transistors M1 and M1b included in each of the memory cells MC[1,1] to MC[m-1,n] are turned off. In other words, the circuit WRWD can select the memory cell MC located in the first row of the memory cell array MCA as the write destination by applying a high-level potential to the wiring WRWL[1] and a low-level potential to the wirings WRWL[2] to WRWL[m].

[0211] Furthermore, between time U7 and time U9, the circuit WDD provides, for example, Da[m,1] to Da[m,n], which are part of the rewrite data, to the wirings WRDL[1] to WRDL[n], respectively. The circuit WDD also provides, for example, Db[m,1] to Db[m,n], which are write data, to the wirings WRDLb[1] to WRDLb[n], respectively. For example, when Da[m,j] and Db[m,j] are digital values, Da[m,j] and Db[m,j] are preferably logically inverted data. Specifically, when the potential corresponding to Da[m,j] is V0, the potential corresponding to Db[m,j] is preferably V1, or when the potential corresponding to Da[m,j] is V1, the potential corresponding to Db[m,j] is preferably V0. 2. Furthermore, since the memory cell MC arranged in the first row of the memory cell array MCA is selected as the write destination by the circuit WRWD, potentials according to Da[m,1] to Da[m,n] are applied to the second terminals of the transistors M1 of the memory cells MC[m,1] to MC[m,n], respectively, and potentials according to Db[m,1] to Db[m,n] are applied to the second terminals of the transistors M1b of the memory cells MC[m,1] to MC[m,n], respectively.

[0212] In addition, between time U7 and time U8, the circuit FECD applies a potential V 1A Apply a potential V 0B Note that the circuit FECD applies a potential V 0A and applies a potential V to each of the wirings FCB[1] to FCB[m-1]. 0B Give.

[0213] Furthermore, between time U8 and time U9, the circuit FECD applies a potential V 0A Apply a potential V 0BThe circuit FECD continues to apply a potential V 0A and applies a potential V to each of the wirings FCB[1] to FCB[m-1]. 0B Give.

[0214] By the operation from time U7 to time U9, the direction of polarization generated in the FTJ element FJA and the FTJ element FJAb included in each of the memory cells MC[m,1] to MC[m,n] in the m-th row of the memory cell array MCA is determined according to Da[m,1] to Da[m,n] sent from the wiring WRDL[1] to wiring WRDL[n] and Db[m,1] to Db[m,n] sent from the wiring WRDLb[1] to wiring WRDLb[n]. In other words, focusing on the j-th column, Da[m,j] and Db[m,j] are written to the memory cell MC[m,j] in the operation from time U7 to time U8.

[0215] By performing the operations from time U1 to time U10, D[1,1] to D[m,n] can be written to the memory cells MC[1,1] to MC[m,n] included in the memory cell array MCA, respectively.

[0216] 9, in the operation after the end of the data write operation to the memory cells MC[1,1] to MC[m,n] (the operation between time U9 and time U10), the circuit WRWD applies a low-level potential to the wirings WRWL[1] to WRWL[m], for example. The circuit WDD applies a ground potential to the wirings WRDL[1] to WRDL[n], for example. The circuit FECD applies a potential V to each of the wirings FCA[1] to FCA[m] and the wirings FCB[1] to FCB[m], for example. 0A , and potential V 0B is given.

[0217] 9 is an example, and therefore, the operation may be changed depending on the situation or the case. For example, in the operation from time U2 to time U4 in the timing chart of FIG. 9, a high-level potential is applied to the wiring WRWL[1], Da[1,1] to Da[1,n] are applied to the wirings WRDL[1] to WRDL[n], and Db[1,1] to Db[1,n] are applied to the wirings WRDLb[1] to WRDLb[n]. However, during the period in which the high-level potential is applied to the wiring WRWL[1], Da[1,1] to Da[1,n] are applied to the wirings WRDL[1] to WRDL[n], and Db[1,1] to Db[1,n] are applied to the wirings WRDLb[1] to WRDLb[n]. Alternatively, a high-level potential may be applied to the wiring WRWL[1] during a period in which Da[1,1] to Da[1,n] are applied to the wirings WRDL[1] to WRDL[n] and Db[1,1] to Db[1,n] are applied to the wirings WRDLb[1] to WRDLb[n]. 1A is applied, and the potential V 0B is applied to the wiring FCA[1], and the potential V 0A is applied, and the potential V 0B The period during which a high-level potential is applied to the wiring WRWL[1], Da[1,1] to Da[1,n] are applied to the wirings WRDL[1] to WRDL[n], and Db[1,1] to Db[1,n] are applied to the wirings WRDLb[1] to WRDLb[n]. 0A is applied, and the potential V 0B During this period, the potential V 1A is applied, and the potential V 0B may be performed prior to the given period.

[0218] <<Write operation example 2>> Next, an example of a write operation of data to the memory cells MC of the memory device 100, which is different from the timing chart of FIG. 9, will be described.

[0219] The timing chart shown in Fig. 10 shows an example of a write operation that is different from the write operation example of the timing chart of Fig. 9. Like the timing chart of Fig. 9, the timing chart of Fig. 10 shows changes in the potential of the wiring WRWL[1], wiring WRWL[2], wiring WRWL[m], wiring WRDL[1], wiring WRDLb[1], wiring WRDL[2], wiring WRDLb[2], wiring WRDL[n], wiring WRDLb[n], wiring FCA[1], wiring FCB[1], wiring FCA[2], wiring FCB[2], wiring FCA[m], and wiring FCB[m] between time U1 and time U10 and around those times.

[0220] The write operation of the timing chart of Figure 10 differs from the write operation of the timing chart of Figure 9 in that a high-level potential is input to each of the wirings WRWL[1] to WRWL[m] between time U2 and time U9, and in that the potential of each of the wirings FCA[1] to FCA[m] fluctuates between time U1 and time U9.

[0221] 10, a high-level potential is input to each of the wirings WRWL[1] to WRWL[m], and therefore a high-level potential is input to the gates of the transistors M1 and M1b of the memory cells MC[1,1] to MC[m,n] included in the memory cell array MCA, and therefore the transistors M1 and M1b of the memory cells MC[1,1] to MC[m,n] are turned on. That is, focusing on the j-th column, the wiring WRDL[j] and the second terminals of the transistors M1 of the memory cells MC[1,j] to MC[m,j] are electrically connected, and the wiring WRDLb[j] and the second terminals of the transistors M1b of the memory cells MC[1,j] to MC[m,j] are electrically connected.

[0222] In addition, between time U1 and time U2 in the timing chart of FIG. 10, the wirings FCA[1] to FCA[m] are supplied with a potential V NA is given.

[0223] In addition, V NA is a potential at which no polarization occurs (no change) in the FTJ element FJA for all data (potentials) input from the wiring WRDL to the second terminal of the transistor M1, and is a potential at which no polarization occurs (no change) in the FTJ element FJAb for all data (potentials) input from the wiring WRDLb to the second terminal of the transistor M1b. For example, V NA is V 0A Higher than V 1A The potential can be lower than

[0224] In addition, between time U2 and time U3 in the timing chart of FIG. 10, the wiring FCA[1] is supplied with a potential V 1A is given, and the wiring FCB[1] has a potential V 0B The wirings FCA[2] to FCA[m] are each continuously supplied with a potential V NAis applied, and the potential V 0B is given.

[0225] In addition, between time U3 and time U4 in the timing chart of FIG. 10, the wiring FCA[1] is supplied with a potential V 0A is given, and the wiring FCB[1] has a potential V 0B The wirings FCA[2] to FCA[m] are each continuously supplied with a potential V NA is applied, and the potential V 0B is given.

[0226] 10, the direction of polarization generated in the FTJ element FJA included in each of the memory cells MC[1,1] to MC[1,n] in the first row of the memory cell array MCA is determined according to Da[1,1] to Da[1,n] sent from the wiring WRDL[1] to wiring WRDL[n], and the direction of polarization generated in the FTJ element FJAb included in each of the memory cells MC[1,1] to MC[1,n] in the first row of the memory cell array MCA is determined according to Db[1,1] to Db[1,n] sent from the wiring WRDL[1] to wiring WRDL[n]. Meanwhile, between time U2 and time U4, the wirings FCA[2] to FCA[m] are supplied with a potential V NA is applied to each of the wirings FCB[2] to FCB[m]. 0B Therefore, even if the transistors M1 of the memory cells MC[2,1] to MC[m,n] are turned on, the data Da[1,1] to Da[1,n] and the data Db[1,1] to Db[1,n] are not written to the memory cells MC of each column.

[0227] In other words, in the operation of the timing chart of Figure 10, each of the wirings FCA[1] to FCA[m] and wirings FCB[1] to FCB[m] can function not only as wirings for controlling the polarization of the FTJ element FJA and the FTJ element FJAb, but also as selection signal lines for writing data.

[0228] In the timing chart of Figure 10, even after time U4, by selecting memory cells MC from the second row to the mth row of the memory cell array MCA using wirings FCA[1] to FCA[m] and wirings FCB[1] to FCB[m] in accordance with the data transmitted from wirings WRDL[1] to WRDL[n] and wirings WRDLb[1] to WRDLb[n], respectively, D[1,1] to D[m,n] can be written to each of memory cells MC[1,1] to MC[m,n] included in the memory cell array MCA, as in the operation example of the timing chart of Figure 9.

[0229] <<Read operation example 1>> Fig. 11 is a timing chart showing an example of an operation of reading data from a memory cell MC of the memory device 100. Note that the timing chart of Fig. 3 described in the above embodiment shows an example of an operation in one memory cell MC, whereas the timing chart of Fig. 11 shows an example of an operation of writing data to multiple memory cells MC included in the memory cell array MCA.

[0230] The timing chart of Figure 11 shows the changes in potential of wiring WRWL[1], wiring WRWL[2], wiring WRWL[m], wiring FCA[1], wiring FCB[1], wiring FCA[2], wiring FCB[2], wiring FCA[m], wiring FCB[m], wiring WRDL[1], wiring WRDLb[1], wiring WRDL[2], wiring WRDLb[2], wiring WRDL[n], and wiring WRDLb[n] between time U21 and time U33 and at times around those times.

[0231] Between time U21 and time U22, for example, the circuit WRWD applies a low-level potential (denoted as Low in FIG. 11) to the wirings WRWL[1] to WRWL[m] as an initial potential. Therefore, the low-level potential is applied to the gates of the transistors M1 and M1b of all the memory cells MC included in the memory cell array MCA, and the transistors M1 and M1b are turned off.

[0232] Furthermore, between time U21 and time U22, the circuit FECD supplies the potential V 0A , and potential V 0B The potential V 0A , and potential V 0B For details, please refer to the timing charts in Figures 2 and 3.

[0233] In addition, between time U21 and time U22, the wirings WRDL[1] to WRDL[n] and the wirings WRDLb[1] to WRDLb[n] are supplied with a potential V MD is given. Note that V MD For details, please refer to the timing charts in Figure 3 and other figures.

[0234] Between time U22 and time U25, the circuit FECD applies a potential V M Applying a potential V 0B The circuit FECD also applies a potential V 0A and applies a potential V 0B At this time, between the wiring FCA[1] and the wiring FCB[1], V M -V 0BSince a voltage of 1 V is applied, a divided voltage of this voltage is applied to the FTJ elements FJA and transistor M6 of the memory cells MC[1,1] to MC[1,n] in the first row of the memory cell array MCA. Similarly, a divided voltage of this voltage is applied to the FTJ elements FJAb and transistor M6b of the memory cells MC[1,1] to MC[1,n] in the first row of the memory cell array MCA. The divided voltage applied to the FTJ element FJA is determined by the direction of polarization of the ferroelectric dielectric contained in the FTJ element FJA, and the divided voltage applied to the FTJ element FJAb is determined by the direction of polarization of the ferroelectric dielectric contained in the FTJ element FJAb. In other words, the divided voltages applied to the FTJ elements FJA and FJAb are determined by the data written in the memory cells MC.

[0235] Between time U23 and time U24, the circuit WRWD applies a high-level potential (denoted as "High" in FIG. 11) to the wiring WRWL[1]. The circuit WRWD also applies a low-level potential to the wirings WRWL[2] to WRWL[m]. Therefore, in the memory cell array MCA, a high-level potential is applied to the gates of the transistors M1 and M1b included in each of the memory cells MC[1,1] to MC[1,n] arranged in the first row, so that the transistors M1 and M1b included in each of the memory cells MC[1,1] to MC[1,n] are turned on. In the memory cell array MCA, a low-level potential is applied to the gates of the transistors M1 and M1b included in each of the memory cells MC[2,1] to MC[m,n] arranged in the second to m rows, so that the transistors M1 and M1b included in each of the memory cells MC[2,1] to MC[m,n] are turned off.

[0236] In other words, the circuit FECD applies a potential V M Applying a potential V 0Band applies a potential V 0A and applies a potential V 0B By applying a high-level potential to the wiring WRWL[1] and a low-level potential to the wirings WRWL[2] to WRWL[m], the memory cell MC arranged in the first row of the memory cell array MCA can be selected as the read source.

[0237] Furthermore, between time U23 and time U24, focusing on the first row, j-th column of the memory cell array MCA, a conduction state is established between the second terminal of the transistor M1 of the memory cell MC[1,j] and the wiring WRDL[j], so that a current corresponding to the divided voltage applied to the FTJ element FJA of the memory cell MC[1,j] flows through the wiring WRDL[j]. Alternatively, the potential of the wiring WRDL[j] changes depending on the divided voltage applied to the FTJ element FJA of the memory cell MC[1,j]. In other words, information (e.g., current or voltage) corresponding to Da[1,j] is transmitted to the wiring WRDL[j] as data held in the FTJ element FJA of the memory cell MC[1,j].

[0238] Furthermore, between time U23 and time U24, focusing on the first row, j-th column of the memory cell array MCA, a conduction state is established between the second terminal of the transistor M1b of the memory cell MC[1,j] and the wiring WRDLb[j], so that a current corresponding to the divided voltage applied to the FTJ element FJAb of the memory cell MC[1,j] flows through the wiring WRDLb[j]. Alternatively, the potential of the wiring WRDLb[j] changes depending on the divided voltage applied to the FTJ element FJAb of the memory cell MC[1,j]. In other words, information (e.g., current or voltage) corresponding to Db[1,j] is transmitted to the wiring WRDLb[j] as data held in the FTJ element FJAb of the memory cell MC[1,j].

[0239] Also, between time U23 and time U24, for memory cells MC other than those in column j, the data held in memory cells MC[1,1] to MC[1,n] arranged in the first row of the memory cell array MCA is transmitted in the same manner as described above.

[0240] Specifically, for example, data Da[1,1] and Db[1,1] are read from memory cell MC[1,1], and data Da[1,n] and Db[1,n] are read from memory cell MC[1,n]. At this time, Da[1,1] and Db[1,1] stored in memory cell MC[1,1] can be read by acquiring information (e.g., current or voltage) transmitted to wiring WRDL[1] and wiring WRDLb[1] using a circuit RDD or the like. On the other hand, Da[1,n] and Db[1,n] stored in memory cell MC[1,n] can be read by acquiring information (e.g., current or voltage) transmitted to wiring WRDL[n] and wiring WRDLb[n] using a circuit RDD or the like.

[0241] Between time U25 and time U27, the circuit FECD applies a potential V M Applying a potential V 0B The circuit FECD also applies a potential V 0A and applies a potential V 0B At this time, between the wiring FCA[2] and the wiring FCB[2], V M -V 0BSince a voltage of 1 V is applied, a divided voltage of this voltage is applied to the FTJ elements FJA and transistor M6 of the memory cells MC[2,1] to MC[2,n] in the second row of the memory cell array MCA. Similarly, a divided voltage of this voltage is applied to the FTJ elements FJAb and transistor M6b of the memory cells MC[2,1] to MC[2,n] in the second row of the memory cell array MCA. The divided voltage applied to the FTJ element FJA is determined by the direction of polarization of the ferroelectric dielectric contained in the FTJ element FJA, and the divided voltage applied to the FTJ element FJAb is determined by the direction of polarization of the ferroelectric dielectric contained in the FTJ element FJAb. In other words, the divided voltages applied to the FTJ elements FJA and FJAb are determined by the data written in the memory cells MC.

[0242] Between time U26 and time U27, the circuit WRWD applies a high-level potential to the wiring RWL[2]. The circuit WRWD also applies a low-level potential to the wiring WRWL[1] and the wirings WRWL[3] to WRWL[m]. Therefore, in the memory cell array MCA, a high-level potential is applied to the gates of the transistors M1 and M1b included in each of the memory cells MC[2,1] to MC[2,n] arranged in the second row, so that the transistors M1 and M1b included in each of the memory cells MC[2,1] to MC[2,n] are turned on. In the memory cell array MCA, a low-level potential is applied to the gates of the transistors M1 and M1b included in each of the memory cells MC arranged in the first row and the third to m-th rows, so that the transistors M1 and M1b included in each of the memory cells MC arranged in the first row and the third to m-th rows are turned off.

[0243] In other words, the circuit FECD applies a potential V M Applying a potential V 0Band applies a potential V 0A and applies a potential V 0B By applying a high-level potential to the wiring WRWL[2] and the circuit WRWD applying a low-level potential to the wiring WRWL[1] and the wirings WRWL[3] to WRWL[m], the memory cell MC arranged in the second row of the memory cell array MCA can be selected as the reading source.

[0244] Furthermore, between time U26 and time U27, focusing on the second row, j-th column of the memory cell array MCA, a conduction state is established between the second terminal of the transistor M1 of the memory cell MC[2,j] and the wiring WRDL[j], so that a current corresponding to the divided voltage applied to the FTJ element FJA of the memory cell MC[2,j] flows through the wiring WRDL[j]. Alternatively, the potential of the wiring WRDL[j] changes depending on the divided voltage applied to the FTJ element FJA of the memory cell MC[2,j]. In other words, information (e.g., current or voltage) corresponding to Da[2,j] is transmitted to the wiring WRDL[j] as data held in the FTJ element FJA of the memory cell MC[2,j].

[0245] Furthermore, between time U26 and time U27, focusing on the second row, j-th column of the memory cell array MCA, a conduction state is established between the second terminal of the transistor M1b of the memory cell MC[2,j] and the line WRDLb[j], so that a current corresponding to the divided voltage applied to the FTJ element FJAb of the memory cell MC[2,j] flows through the line WRDLb[j]. Alternatively, the potential of the line WRDLb[j] changes depending on the divided voltage applied to the FTJ element FJAb of the memory cell MC[2,j]. In other words, information (e.g., current or voltage) corresponding to Db[2,j] is transmitted to the line WRDLb[j] as data held in the FTJ element FJAb of the memory cell MC[2,j].

[0246] Also, between time U23 and time U24, for memory cells MC other than those in column j, the data held in memory cells MC[2,1] to MC[2,n] arranged in the second row of the memory cell array MCA is transmitted in the same manner as described above.

[0247] Specifically, for example, data Da[2,1] and Db[2,1] are read from memory cell MC[2,1], and data Da[2,n] and Db[2,n] are read from memory cell MC[2,n]. At this time, Da[2,1] and Db[2,1] stored in memory cell MC[2,1] can be read by acquiring information (e.g., current or voltage) transmitted to wiring WRDL[1] and wiring WRDLb[1] using a circuit RDD or the like. On the other hand, Da[2,n] and Db[2,n] stored in memory cell MC[2,n] can be read by acquiring information (e.g., current or voltage) transmitted to wiring WRDL[n] and wiring WRDLb[n] using a circuit RDD or the like.

[0248] Between time U28 and time U29, a data read operation is performed from memory cells MC arranged in the third to m-1th rows of the memory cell array MCA, similar to the data read operation from memory cells MC arranged in the first row of the memory cell array MCA performed between time U22 and time U25, and the data read operation from memory cells MC arranged in the second row of the memory cell array MCA performed between time U25 and time U28.

[0249] Between time U29 and time U32, the circuit FECD applies a potential V M Apply a potential V 0B The circuit FECD applies a potential V 0A and applies a potential V 0B At this time, between the wiring FCA[m] and the wiring FCB[m], V M-V 0B Since a voltage of 1 / 2 V is applied, a divided voltage of this voltage is applied to the FTJ elements FJA and transistor M6 of the memory cells MC[m,1] to MC[m,n] in the first row of the memory cell array MCA. Similarly, a divided voltage of this voltage is applied to the FTJ elements FJAb and transistor M6b of the memory cells MC[m,1] to MC[m,n] in the mth row of the memory cell array MCA. The divided voltage applied to the FTJ element FJA is determined by the direction of polarization of the ferroelectric dielectric contained in the FTJ element FJA, and the divided voltage applied to the FTJ element FJAb is determined by the direction of polarization of the ferroelectric dielectric contained in the FTJ element FJAb. In other words, the divided voltages applied to the FTJ elements FJA and FJAb are determined by the data written in the memory cells MC.

[0250] Between time U30 and time U31, the circuit WRWD applies a high-level potential to the wiring WRWL[m]. The circuit WRWD also applies a low-level potential to the wirings WRWL[1] to WRWL[m-1]. Therefore, in the memory cell array MCA, a high-level potential is applied to the gates of the transistors M1 and M1b included in each of the memory cells MC[m,1] to MC[m,n] arranged in the m-th row, so that the transistors M1 and M1b included in each of the memory cells MC[m,1] to MC[m,n] are turned on. In the memory cell array MCA, a low-level potential is applied to the gates of the transistors M1 and M1b included in each of the memory cells MC[1,1] to MC[m-1,n] arranged in the 1st to m-1st rows, so that the transistors M1 and M1b included in each of the memory cells MC[1,1] to MC[m-1,n] are turned off.

[0251] In other words, the circuit FECD applies a potential V M Apply a potential V 0Band applies a potential V 0A and applies a potential V 0B By applying a high-level potential to the wiring WRWL[m] and by the circuit WRWD applying a high-level potential to the wiring WRWL[m] and a low-level potential to the wirings WRWL[1] to WRWL[m-1], the memory cell MC arranged in the m-th row of the memory cell array MCA can be selected as the reading source.

[0252] Furthermore, between time U30 and time U31, focusing on the mth row and jth column of the memory cell array MCA, a conduction state is established between the second terminal of the transistor M1 of the memory cell MC[m,j] and the wiring WRDL[j], so that a current corresponding to the divided voltage applied to the FTJ element FJA of the memory cell MC[m,j] flows through the wiring WRDL[j]. Alternatively, the potential of the wiring WRDL[j] changes depending on the divided voltage applied to the FTJ element FJA of the memory cell MC[m,j]. In other words, information (e.g., current or voltage) corresponding to Da[m,j] is transmitted to the wiring WRDL[j] as data held in the FTJ element FJA of the memory cell MC[m,j].

[0253] Furthermore, between time U30 and time U31, focusing on the mth row and jth column of the memory cell array MCA, a conduction state is established between the second terminal of the transistor M1b of the memory cell MC[m,j] and the wiring WRDLb[j], so that a current corresponding to the divided voltage applied to the FTJ element FJAb of the memory cell MC[m,j] flows through the wiring WRDLb[j]. Alternatively, the potential of the wiring WRDLb[j] changes depending on the divided voltage applied to the FTJ element FJAb of the memory cell MC[m,j]. In other words, information (e.g., current or voltage) corresponding to Db[m,j] is transmitted to the wiring WRDLb[j] as data held in the FTJ element FJAb of the memory cell MC[m,j].

[0254] Also, between time U30 and time U31, for memory cells MC other than those in column j, the data held in memory cells MC[m,1] to MC[m,n] arranged in the mth row of the memory cell array MCA is transmitted in the same manner as described above.

[0255] Specifically, for example, data Da[m,1] and Db[m,1] are read from memory cell MC[m,1], and data Da[m,n] and Db[m,n] are read from memory cell MC[m,n]. At this time, Da[m,1] and Db[m,1] stored in memory cell MC[m,1] can be read by acquiring information (e.g., current or voltage) transmitted to wiring WRDL[1] and wiring WRDLb[1] using a circuit RDD or the like. On the other hand, Da[m,n] and Db[m,n] stored in memory cell MC[m,n] can be read by acquiring information (e.g., current or voltage) transmitted to wiring WRDL[n] and wiring WRDLb[n] using a circuit RDD or the like.

[0256] By performing the operations from time U21 to time U32, D[1,1] to D[m,n] can be read from the memory cells MC[1,1] to MC[m,n] included in the memory cell array MCA, respectively.

[0257] 11, after the data read operation from the memory cells MC[1,1] to MC[m,n] is completed (the operation from time U32 to time U33), the circuit WRWD applies a low-level potential to the wirings WRWL[1] to WRWL[m], for example. Also, the circuit FECD applies a potential V 0A , and potential V 0B In addition, as an example, a ground potential is applied to each of the wirings WRDL[1] to WRDL[n].

[0258] <<Read operation example 2>> Next, an example of an operation of reading data from the memory cells MC of the memory device 100, which is different from the timing chart of FIG. 11, will be described.

[0259] The timing chart shown in Fig. 12 shows an example of a read operation that is different from the read operation example of the timing chart of Fig. 11. Like the timing chart of Fig. 11, the timing chart of Fig. 12 shows changes in the potential of the wiring WRWL[1], wiring WRWL[2], wiring WRWL[m], wiring FCA[1], wiring FCB[1], wiring FCA[2], wiring FCB[2], wiring FCA[m], wiring FCB[m], wiring WRDL[1], wiring WRDLb[1], wiring WRDL[2], wiring WRDLb[2], wiring WRDL[n], and wiring WRDLb[n] between time U21 and time U33 and around those times.

[0260] The read operation of the timing chart of FIG. 12 is performed between time U22 and time U32 when each of the wirings FCA[1] to FCA[m] is at the potential V M This differs from the read operation in the timing chart of FIG.

[0261] Between time U22 and time U32 in the timing chart of FIG. 12, V M is input, and V is input to each of the wirings FCB[1] to FCB[m]. 0Bis input, between time U22 and time U32, the potential of the second terminal of the transistor M1 in each of the memory cells MC[1,1] to MC[m,n] is determined by the direction of polarization of the ferroelectric material contained in the FTJ element FJA of that memory cell MC. Similarly, the potential of the second terminal of the transistor M1b in each of the memory cells MC[1,1] to MC[m,n] is determined by the direction of polarization of the ferroelectric material contained in the FTJ element FJAb of that memory cell MC. In other words, the potential of the second terminal of each of the transistors M1 and M1b corresponds to the data stored in the respective memory cells MC.

[0262] In this operation example, when selecting a memory cell MC to be read from the memory cell array MCA, a high-level potential can be input from the circuit WRWD to any one of the wirings WRWL[1] to WRWL[m] and a low-level potential to the remaining wirings. For example, in the timing chart of Figure 12, by applying a high-level potential to the wiring WRWL[1] and a low-level potential to the wirings WRWL[2] to WRWL[m] between times U23 and U24, data stored in the memory cells MC arranged in the first row of the memory cell array MCA can be read. Similarly, as in the period from time U26 to time U27, by applying a high-level potential to wiring WRWL[2] and a low-level potential to wiring WRWL[1] and wiring WRWL[3] to wiring WRWL[m], data stored in memory cells MC arranged in the second row of the memory cell array MCA can be read out, and as in the period from time U30 to time U31, by applying a high-level potential to wiring WRWL[m] and a low-level potential to wiring WRWL[1] to wiring WRWL[m-1], data stored in memory cells MC arranged in the mth row of the memory cell array MCA can be read out.

[0263] That is, in the operation example of the timing chart in FIG. 12, the potentials of the wirings WRWL[1] to WRWL[m] can change in the same manner as in the operation example of the timing chart in FIG.

[0264] 12, when reading from a plurality of memory cells MC included in the memory cell array MCA, it is not necessary to change the potentials of the wirings FCA[1] to FCA[m] and the wirings FCB[1] to FCB[m] for each memory cell MC being read. In other words, by applying the operation example of the timing chart of FIG. 12, the circuit FECD can be configured without a circuit that selects a wiring that transmits a signal, such as a selector.

[0265] <<Read operation example 3>> Next, an example of an operation of reading data from the memory cells MC of the memory device 100, which is different from the timing charts of FIGS. 11 and 12, will be described.

[0266] The timing chart shown in Fig. 13 shows an example of a write operation that is different from the write operation examples of the timing charts of Fig. 11 and Fig. 12. Like the timing charts of Fig. 11 and Fig. 12, the timing chart of Fig. 13 shows changes in the potential of the wiring WRWL[1], wiring WRWL[2], wiring WRWL[m], wiring FCA[1], wiring FCB[1], wiring FCA[2], wiring FCB[2], wiring FCA[m], wiring FCB[m], wiring WRDL[1], wiring WRDLb[1], wiring WRDL[2], wiring WRDLb[2], wiring WRDL[n], and wiring WRDLb[n] between time U21 and time U33 and around that time.

[0267] The read operation of the timing chart of Figure 13 differs from the read operation of the timing chart of Figure 11 in that each of the wirings WRWL[1] to WRWL[m] is at a high level potential between time U22 and time U32, and in that each of the wirings FCA[1] to FCA[m] and wirings FCB[1] to FCB[m] fluctuates in potential between time U22 and time U32.

[0268] 13, a high-level potential is input to each of the wirings WRWL[1] to WRWL[m], and therefore a high-level potential is input to the gates of the transistors M1 and M1b in each of the memory cells MC[1,1] to MC[m,n] from time U22 to time U32. As a result, the transistors M1 and M1b in each of the memory cells MC[1,1] to MC[m,n] are turned on.

[0269] In addition, between time U23 and time U24 in the timing chart of FIG. 13, the wiring FCA[1] is supplied with a potential V M is given, and the wiring FCB[1] has a potential V 0B The wirings FCA[2] to FCA[m] are supplied with a potential V 0A is applied to the wirings FCB[2] to FCB[m], and a potential V 0B At this time, between the wiring FCA[1] and the wiring FCB[1], V M -V 0BSince a voltage of 1 V is applied, a divided voltage of this voltage is applied to the FTJ elements FJA and transistor M6 of the memory cells MC[1,1] to MC[1,n] in the first row of the memory cell array MCA. Similarly, a divided voltage of this voltage is applied to the FTJ elements FJAb and transistor M6b of the memory cells MC[1,1] to MC[1,n] in the first row of the memory cell array MCA. The divided voltage applied to the FTJ element FJA is determined by the direction of polarization of the ferroelectric dielectric contained in the FTJ element FJA, and the divided voltage applied to the FTJ element FJAb is determined by the direction of polarization of the ferroelectric dielectric contained in the FTJ element FJAb. In other words, the divided voltages applied to the FTJ elements FJA and FJAb are determined by the data written in the memory cells MC.

[0270] Furthermore, because the transistor M1 of each of the memory cells MC[1,1] to MC[1,n] is turned on, the potential of each of the wirings WRDL[1] to WRDL[n] is determined according to the divided voltage applied to the FTJ element FJA of each of the memory cells MC[1,1] to MC[1,n]. Similarly, because the transistor M1b of each of the memory cells MC[1,1] to MC[1,n] is turned on, the potential of each of the wirings WRDL[1] to WRDL[n] is determined according to the divided voltage applied to the FTJ element FJAb of each of the memory cells MC[1,1] to MC[1,n]. Therefore, information (e.g., current or voltage) corresponding to Da[1,1] to Da[1,n] is transmitted to each of the wirings WRDL[1] to WRDL[n] as data stored in the memory cells MC[1,1] to MC[1,n]. In addition, information (e.g., current or voltage) corresponding to Db[1,1] to Db[1,n] is transmitted to each of wirings WRDLb[1] to WRDLb[n] as data stored in memory cells MC[1,1] to MC[1,n].

[0271] On the other hand, the wiring FCA[2] to the wiring FCA[m] are connected to a potential V 0Ais applied to the wirings FCB[2] to FCB[m], and a potential V 0B is given, the FTJ elements FJA and transistors M6 of the memory cells MC from the second row to the m-th row of the memory cell array MCA are respectively supplied with V 0A -V 0B A partial pressure of V 0A -V 0B When V is set to a value of 0 V or close to 0 V, the potential of the second terminal of the transistor M1 in each of the memory cells MC[1,1] to MC[1,n] can also be set to a value of 0 V or close to 0 V. In other words, if the threshold voltage of the transistor M1 is an appropriate value, the transistor M1 is turned off, and therefore, in the memory cells MC from the second row to the m-th row of the memory cell array MCA, there is no conduction between the second terminal of the transistor M1 and the wirings WRDL[1] to WRDL[n], and information (for example, current, voltage, etc.) corresponding to the data stored in the memory cell MC does not flow to the wirings WRDL[1] to WRDL[n]. Similarly, V 0A -V 0B When the threshold voltage of the transistor M1b is set to 0 V or a value close to 0 V, the potential of the second terminal of the transistor M1b in each of the memory cells MC[1,1] to MC[1,n] can also be set to 0 V or a value close to 0 V. Therefore, if the threshold voltage of the transistor M1b is an appropriate value, the transistor M1 is turned off, and in the memory cells MC in the second to m-th rows of the memory cell array MCA, there is no conduction between the second terminal of the transistor M1b and the wirings WRDLb[1] to WRDLb[n]. Therefore, information (e.g., current, voltage, etc.) corresponding to the data stored in the memory cell MC does not flow to the wirings WRDLb[1] to WRDLb[n].

[0272] In addition, in this operation example, when data is read from the memory cell MC in the second row of the memory cell array MCA, the potential V M Applying a potential V 0BIn addition, when reading data from the memory cell MC in the m-th row of the memory cell array MCA, the potential V M Apply a potential V 0B Just give it the following.

[0273] 13, the wirings FCA[1] to FCA[m] function as selection signal lines for selecting memory cells MC to be read from the memory cell array MCA. Therefore, in the operation example of the timing chart of FIG. 13, it is not necessary to change the potential of each of the wirings WRWL[1] to WRWL[m] for each memory cell MC to be read. Therefore, by applying the operation example of the timing chart of FIG. 13, the circuit RDD can be configured without a circuit for selecting a wiring for transmitting a signal, such as a selector.

[0274] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0275] (Embodiment 3) In this embodiment mode, a case where the memory device described in the above embodiment mode is used as an arithmetic circuit will be described.

[0276] <Arithmetic circuit 1> As an example, consider the memory device 100A of FIG. 14, which uses the memory cell MC of FIG. 5A. In this case, the memory device 100A, which functions as an arithmetic circuit, can perform, for example, a multiply-and-accumulate operation on a plurality of first data and a plurality of second data. Each of the plurality of first data is set to "0" or "1," and each of the plurality of second data is set to "0" or "1."

[0277] The memory device 100A shown in FIG. 14 has a configuration in which a circuit RWDA is added to the memory device 100 of FIG. 8. The circuit RWDA functions as a read word line driver circuit, for example. The circuit RWDA also functions as a circuit that transmits second data to memory cells MC included in the memory cell array MCA. That is, in this case, the wirings RWLA[1] to RWLA[m] (corresponding to the wiring RWLA in FIG. 5A) function as wirings that transmit the second data. The operation of the memory cells MC that perform the multiplication of the first data and the second data will be described later.

[0278] The first data is assumed to be held in, for example, a plurality of memory cells MC included in the memory cell array MCA of the memory device 100A. That is, the plurality of memory cells MC included in the memory cell array MCA are assumed to hold data "0" or "1." Specifically, for example, as described in the data write operation of the first embodiment, the value of the first data may be determined depending on the direction of polarization generated in each of the FTJ element FJA and the FTJ element FJAb included in the memory cell MC.

[0279] Here, as an example, the relationship between the value of the first data written to the multiple memory cells MC included in the memory cell array MCA of the memory device 100 and the direction of polarization generated in each of the FTJ elements FJA and FJAb is defined as shown in the table below.

[0280] [Table 2]

[0281] That is, for example, when writing first data "1" to the memory cell MC, as shown in the example of the data write operation of the first embodiment, a potential V1 is input from the circuit WDD to the memory cell MC via the wiring WRDL, and a potential V0 is input to the memory cell MC via the wiring WRDLb, to generate polarizations in the FTJ elements FJA and FJAb included in the memory cell MC in predetermined directions (to rewrite). Also, for example, when writing first data "0" to the memory cell MC, as shown in the example of the data write operation of the first embodiment, a potential V0 is input from the circuit WDD to the memory cell MC via the wiring WRDL, and a potential V1 is input to the memory cell MC via the wiring WRDLb, to generate polarizations in the FTJ elements FJA and FJAb included in the memory cell MC in predetermined directions (to rewrite).

[0282] Furthermore, when the first data “1” is written to the memory cell MC, the operation from time T23 to time T25 in the timing chart of FIG. 3 of the data read operation example of the first embodiment is performed, and the potential of the output terminal of the FTJ element FJA becomes V 0B The potential at the output terminal of the FTJ element FJAb is V M Therefore, the potential of the gate of the transistor M7 included in the memory cell MC is V M At this time, for example, a low-level potential is applied to the first terminal of the transistor M7 from the wiring VCE, and for example, a high-level potential is applied to the second terminal of the transistor M7 from the wiring RDL via the transistor M8, so that a gate-source voltage (V M When the first data "0" is written to the memory cell MC, the operation from time T23 to time T25 in the timing chart of FIG. 3 of the data read operation example of the first embodiment is performed, and the potential of the output terminal of the FTJ element FJA becomes V M The potential at the output terminal of the FTJ element FJAb is V 0BTherefore, the potential of the gate of the transistor M7 included in the memory cell MC is V 0B At this time, for example, a low-level potential is applied to the first terminal of the transistor M7 from the wiring VCE, and for example, a high-level potential is applied to the second terminal of the transistor M7 from the wiring RDL via the transistor M8, so that a gate-source voltage (V 0B In this embodiment, when the first data "0" is written to the memory cell MC, that is, when the potential of the output terminal (gate of the transistor M7) of the FTJ element FJAb is V 0B When this occurs, it will be described as no current flows between the first terminal and the second terminal of transistor M7 (this can also be said as transistor M7 being in an off state and a current of 0 magnitude flowing between the first terminal and the second terminal of transistor M7).

[0283] The second data may have a value corresponding to the potential applied to the wiring RWLA. For example, when the second data is "0," a low-level potential is applied to the wiring RWLA by the circuit WRWD, and when the second data is "1," a high-level potential is applied to the wiring RWLA by the circuit WRWD.

[0284] Here, an example of the operation of the memory cell MC according to the first data held in the memory cell MC and the second data input to the memory cell MC will be described.

[0285] When the first data stored in the memory cell MC is “1”, as described above, the gate-source voltage (V M The amount of current that flows depends on the potential difference between the high-level potential and the low-level potential. ut Furthermore, when the first data held in the memory cell MC is "0", as described above, no current flows between the first terminal and the second terminal of the transistor M7 (a current of 0 flows).

[0286] When the second data is "0", that is, when a low-level potential is input to the memory cell MC from the wiring RWLA, the transistor M1 included in the memory cell MC is turned off. On the other hand, when the second data is "1", that is, when a high-level potential is input to the memory cell MC from the wiring RWLA, the transistor M1 included in the memory cell MC is turned on.

[0287] From the above, when the first data is “1” and the second data is “1”, the line VCE and the line RDL are in a conductive state, so that a current amount I ut Furthermore, when at least one of the first data and the second data is "0", the transistor M7 is in the off state and / or the transistor M8 is in the off state, so no current flows between the memory cell MC and the wiring RDL.

[0288] That is, the amount of current flowing through the wiring RDL and the circuit RDD is determined by the value of the first data and the value of the second data, as shown in the table below.

[0289] [Table 3]

[0290] That is, when the product of the first data and the second data is "1", the calculation result is a current I ut When the product of the first data and the second data is "0", a current of 0 flows between the memory cell MC and the circuit RDD as a result of the operation (no current flows between the memory cell MC and the circuit RDD). In this way, the memory cell MC can store the first data in the memory cell MC and then input the second data to the memory cell MC, thereby operating to calculate the product of the first data and the second data.

[0291] Next, consider a case where multiple pieces of second data are simultaneously supplied to each of the wirings RWLA[1] to RWLA[m] while multiple memory cells MC included in the memory cell array MCA are holding first data. Note that the first data held in the memory cell MC[i,j] (i is an integer between 1 and m, and j is an integer between 1 and n) is represented by W[i,j], and the second data supplied to the wiring RWLA[i] is represented by X[i].

[0292] For example, in the jth column, when X[1] to X[m] are input as second data from wirings RWLA[1] to RWLA[m] to each of memory cells MC[1,j] to MC[m,j], the calculations W[1,j]×X[1] to W[m,j]×X[m] are performed in each of memory cells MC[1,j] to MC[m,j].

[0293] For example, when the product of the first data and the second data is "1", the amount of current flowing from the memory cell MC to the wiring RDL[j] is I ut Furthermore, for example, when the product of the first data and the second data is "0", the amount of current flowing between the memory cell MC and the wiring WRDL[j] is 0 (no current flows between the memory cell MC and the wiring WRDL[j]).

[0294] Here, among the memory cells MC[1,j] to MC[m,j], the number of memory cells MC in which the product of the first data and the second data is “1” is set to p, and the number of memory cells MC in which the product of the first data and the second data is “0” is set to q. The sum of the currents flowing from the wiring RDL to the circuit RDD is p×I ut +q×0=p×I ut Here, p and q are positive integers that satisfy p+q=m.

[0295] Here, by providing the circuit RDD with a function such as a current-voltage conversion circuit, the sum of the currents flowing through the wiring RDL[j] can be converted into a voltage value. That is, the current amount p×I ut can be output as a voltage value.

[0296] The circuit RDD may also have the function of further computing a function using the result of the sum of products. For example, the circuit RDD can perform an artificial neural network operation by computing an activation function using the result of the sum of products. Examples of the activation function that can be used include a sigmoid function, a tanh function, a softmax function, a ReLU function, and a threshold function.

[0297] In addition, although the above description has been made on the results of the multiply-and-accumulate operation between the plurality of first data and the plurality of second data in the memory cells MC[1,j] to MC[m,j] located in the j-th column, the plurality of second data are transmitted via the wirings RWLA[1] to RWLA[m] extending in the row direction, so that the multiply-and-accumulate operation can also be performed in columns other than the j-th column. In other words, when the memory device 100A is used as a circuit that performs multiply-and-accumulate, it is possible to simultaneously perform multiply-and-accumulate operations for as many columns (n ​​in FIG. 14).

[0298] <Arithmetic circuit 2> In the above arithmetic circuit, an operation when the first data is binary ("0" or "1") and the second data is binary ("0" or "1") has been described as an example, but one aspect of the present invention is that by changing the configuration of the arithmetic circuit, it is possible to perform operations that handle multi-values, analog values, etc.

[0299] FIG. 15 shows an example of the configuration of an arithmetic circuit that can perform a product-sum operation between a plurality of first data that take on any of "-1", "0", or "1" and a plurality of second data that take on any of "-1", "0", and "1".

[0300] The arithmetic circuit 110 includes a memory cell array MCA, a circuit WDD, a circuit RDD, a circuit RWDA, a circuit WRWD, and a circuit FECD.

[0301] The memory cell array MCA has a plurality of memory cells MC. In the memory cell array MCA, the plurality of memory cells MC are arranged in a matrix of m rows and n columns (here, m and n are integers of 1 or more). In FIG. 15, the memory cell MC located in the i-th row and j-th column (here, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less) is illustrated as memory cell MC[i,j]. In FIG. 15, memory cell MC[1,j] and memory cell MC[m,j] are selectively shown.

[0302] The memory cell MC has a circuit MP and a circuit MPr, the circuit configurations of which will be described later.

[0303] In addition, in the memory cell array MCA of the arithmetic circuit 110, wirings WRDL[1] to WRDL[n], wirings WRDLb[1] to WRDLb[n], wirings WRDLr[1] to WRDLr[n], and wirings WRDLbr[1] to WRDLbr[n] are extended in the column direction. Note that the [j] attached to the wirings WRDL, WRDLb, WRDLr, and WRDLbr indicates that they are wirings in the j-th column. In addition, wirings WRWL[1] to WRWL[m], wirings RWLAa[1] to RWLAa[m], wirings RWLAb[1] to RWLAb[m], wirings FCA[1] to FCA[m], and wirings FCB[1] to FCB[m] are extended in the row direction. The [i] attached to the wiring WRWL, the wiring RWLAa, the wiring RWLAb, the wiring FCA, and the wiring FCB indicates that the wiring is in the i-th row.

[0304] In the memory cell MC[1,j], the circuit MP[1,j] is electrically connected to the wiring WRDL[j], the wiring WRDLb[j], the wiring WRWL[1], the wiring FCA[1], the wiring FCB[1], the wiring RWLAa[1], and the wiring RWLAb[1]. The circuit MPr[1,j] is electrically connected to the wiring WRDLr[j], the wiring WRDLbr[j], the wiring WRWL[1], the wiring FCA[1], the wiring FCB[1], the wiring RWLAa[1], and the wiring RWLAb[1].

[0305] In the memory cell MC[m,j], the circuit MP[m,j] is electrically connected to the wiring WRDL[j], the wiring WRDLb[j], the wiring WRWL[m], the wiring FCA[m], the wiring FCB[m], the wiring RWLAa[m], and the wiring RWLAb[m]. In addition, the circuit MPr[m,j] is electrically connected to the wiring WRDLr[j], the wiring WRDLbr[j], the wiring WRWL[m], the wiring FCA[m], the wiring FCB[m], the wiring RWLAa[m], and the wiring RWLAb[m].

[0306] Next, a configuration example of the circuit MP and the circuit MPr included in the memory cell MC will be described.

[0307] FIG. 16 shows an example of a circuit configuration that can be applied to the memory cells MC included in the memory cell array MCA of the arithmetic circuit 110 of FIG.

[0308] The circuit MP shown in FIG. 16 is a modification of the configuration of the memory cell MC in FIG. 5A described in the first embodiment, and is configured by further providing a transistor M8m in addition to the memory cell MC in FIG. 5A.

[0309] A first terminal of the transistor M8m is electrically connected to the second terminal of the transistor M7 and the first terminal of the transistor M8, a second terminal of the transistor M8m is electrically connected to the wiring RDLr[j], a gate of the transistor M8 is electrically connected to the wiring RWLAa, and a gate of the transistor M8m is electrically connected to the wiring RWLAb.

[0310] 16 has the same configuration as the circuit MP. Therefore, the circuit elements of the circuit MPr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MP.

[0311] In the circuit MPr, a first terminal of the transistor M1r is electrically connected to a wiring WRDLr, and a gate of the transistor M1r is electrically connected to a wiring WRWL. An input terminal of the FTJ element FJAr is electrically connected to a wiring FCA. An output terminal of the FTJ element FJAr is electrically connected to a second terminal of the transistor M1r, a first terminal of the transistor M6r, and a gate of the transistor M6br. A second terminal of the transistor M6r is electrically connected to a wiring FCB. A first terminal of the transistor M1br is electrically connected to a wiring WRDLbr, and a gate of the transistor M1br is electrically connected to a wiring WRWL. An input terminal of the FTJ element FJAbr is electrically connected to a wiring FCA. An output terminal of the FTJ element FJAbr is electrically connected to a second terminal of the transistor M1br, a first terminal of the transistor M6br, a gate of the transistor M6r, and a gate of the transistor M7r. A second terminal of the transistor M6br is electrically connected to a wiring FCB. The first terminal of the transistor M7r is electrically connected to the wiring VCEr. The first terminal of the transistor M8r is electrically connected to the second terminal of the transistor M7 and the first terminal of the transistor M8mr. The second terminal of the transistor M8r is electrically connected to the wiring RDLr, and the second terminal of the transistor M8mr is electrically connected to the wiring RDL[j]. The gate of the transistor M8m is electrically connected to the wiring RWLAa, and the gate of the transistor M8mr is electrically connected to the wiring RWLAb.

[0312] For example, the wiring WRDL and the wiring WRDLr function as wirings that transmit first data to be written to the circuit MP and the circuit MPr of the memory cell MC, respectively. Note that the first data is represented by a pair of signals transmitted to the wiring WRDL and the wiring WRDLr.

[0313] Moreover, the wiring RWLAa and the wiring RWLAb function as wirings for transmitting second data, for example. Note that the second data is represented by a pair of signals transmitted to the wiring RWLAa and the wiring RWLAb.

[0314] Moreover, the wiring RDL and the wiring RDLr function as wirings for transmitting the results of calculations by the circuits MP and MPr of the memory cells MC as data, for example.

[0315] Moreover, the wiring WRWL functions as, for example, a wiring for selecting a memory cell MC to which the first data is to be written. That is, the wiring WRWL may function as a write word line.

[0316] 1 described in the first embodiment, when writing first data to the circuit MP and the circuit MPr, the wiring FCA and the wiring FCB function as wirings that apply a potential that causes polarization to the material that may have ferroelectricity contained in the FTJ element FJA, the FTJ element FJAb, the FTJ element FJAr, and the FTJ element FJAbr, respectively. Furthermore, the wiring FCA and the wiring FCB also function as wirings that apply a potential that does not change the polarization of the dielectric material when calculating the product of the first data and the second data in the memory cell MC. Furthermore, the potential may be a pulse voltage.

[0317] As an example, the wiring VCE and the wiring VCEr each function as a wiring that applies a constant voltage, similar to the memory cell MC of FIG. 5A described in the first embodiment. The constant voltage may be, for example, a low-level potential, a ground potential, or the like. The voltage applied by the wiring VCE and the wiring VCEr may also be a pulse voltage.

[0318] The circuit WDD is electrically connected to wirings WRDL[1] to WRDL[n], WRDLb[1] to WRDLb[n], WRDLr[1] to WRDLr[n], and WRDLbr[1] to WRDLbr[n]. The circuit WRWD is electrically connected to wirings WRWL[1] to WRWL[m]. The circuit RWDA is electrically connected to wirings RWLAa[1] to RWLAa[m] and RWLAb[1] to RWLAb[m]. The circuit FECD is electrically connected to wirings FCA[1] to FCA[m] and wirings FCB[1] to FCB[m]. The circuit RDD is electrically connected to wirings RDL[1] to RDL[n] and wirings RDLr[1] to RDLr[1].

[0319] The circuit FECD is the same as that of the memory device 100 in FIG. 8 described in the second embodiment.

[0320] For example, the circuit WDD functions as a circuit that supplies first data to the wirings WRDL[j], WRDLb[j], WRDLr[j], and WRDLbr[j] in the j-th column. The circuit WDD may be configured to supply the first data to the wirings WRDL[1] to WRDL[n], WRDLb[1] to WRDLb[n], WRDLr[1] to WRDLr[n], and WRDLbr[1] to WRDLbr[n] all at once.

[0321] For example, the circuit WRWD functions as a wiring for selecting a memory cell MC to which the first data is to be written. That is, in the configuration of Fig. 15, the circuit WRWD functions as a circuit for selecting a word line during writing.

[0322] For example, the circuit RWDA functions as a circuit that supplies second data to the wirings RWLAa[i] and RWLAb[i] in the i-th row. The circuit RWDA may be configured to supply the second data to the wirings RWLAa[1] to RWLAa[m] and the wirings RWLAb[1] to RWLAb[m] all at once.

[0323] Here, as the first data, the potentials supplied to the circuit MP of the memory cell MC and the circuit MPr are defined as follows.

[0324] When "1" is stored as the first data in the memory cell MC, a potential is supplied from the circuit WDD to the circuit MP via the wiring WRDL and the wiring WRDLb so that the polarization direction of the FTJ element FJA included in the circuit MP is positive and the polarization direction of the FTJ element FJAb is negative, and a potential is supplied from the circuit WDD to the circuit MPr via the wiring WRDLr and the wiring WRDLbr so that the polarization direction of the FTJ element FJAr included in the circuit MPr is negative and the polarization direction of the FTJ element FJAbr is positive. Furthermore, when "-1" is stored as the first data in the memory cell MC, a potential is supplied from the circuit WDD to the circuit MP via the wiring WRDL and the wiring WRDLb so that the polarization direction of the FTJ element FJA included in the circuit MP is negative and the polarization direction of the FTJ element FJAb is positive, and a potential is supplied from the circuit WDD to the circuit MPr via the wiring WRDLr and the wiring WRDLbr so that the polarization direction of the FTJ element FJAr included in the circuit MPr is positive and the polarization direction of the FTJ element FJAbr is negative. Furthermore, when storing "0" as the first data in the memory cell MC, a potential is supplied from the circuit WDD to the circuit MP via the wiring WRDL and the wiring WRDLb so that the polarization direction of the FTJ element FJA included in the circuit MP is negative and the polarization direction of the FTJ element FJAb is positive, and a potential is supplied from the circuit WDD to the circuit MPr via the wiring WRDLr and the wiring WRDLbr so that the polarization direction of the FTJ element FJAr included in the circuit MPr is negative and the polarization direction of the FTJ element FJAbr is positive.

[0325] As second data, the potentials supplied to the wirings RWLAa and RWLAb are defined as follows:

[0326] When "1" is input as second data to the memory cell MC, a high-level potential is supplied from the wiring RWLAa to the circuits MP and MPr, and a low-level potential is supplied from the wiring RWLAb to the circuits MP and MPr. When "-1" is input as second data to the memory cell MC, a low-level potential is supplied from the wiring RWLAa to the circuits MP and MPr, and a high-level potential is supplied from the wiring RWLAb to the circuits MP and MPr. When "0" is input as second data to the memory cell MC, a low-level potential is supplied from the wiring RWLAa to the circuits MP and MPr, and a low-level potential is supplied from the wiring RWLAb to the circuits MP and MPr.

[0327] In other words, when "1" is input as the second data to the memory cell MC, in the circuit MP, the transistor M8 is in the on state and the transistor M8m is in the off state, and in the circuit MPr, the transistor M8r is in the on state and the transistor M8mr is in the off state, so that the circuit MP and the wiring RDL[j] are in a conductive state, the circuit MPr and the wiring RDLr[j] are in a conductive state, the circuit MP and the wiring RDLr[j] are in a non-conductive state, and the circuit MPr and the wiring RDL[j] are in a non-conductive state. Furthermore, when "-1" is input as the second data to the memory cell MC, in the circuit MP, the transistor M8 is in the off state and the transistor M8m is in the on state, and in the circuit MPr, the transistor M8r is in the off state and the transistor M8mr is in the on state, so that the circuit MP and the wiring RDL[j] are in a non-conductive state, the circuit MPr and the wiring RDLr[j] are in a non-conductive state, the circuit MP and the wiring RDLr[j] are in a conductive state, and the circuit MPr and the wiring RDL[j] are in a conductive state. Furthermore, when "0" is input as the second data to the memory cell MC, in the circuit MP, the transistor M8 is in the off state and the transistor M8m is in the off state, and in the circuit MPr, the transistor M8r is in the off state and the transistor M8mr is in the off state, so that the circuit MP and the wiring RDL[j] are in a non-conductive state, the circuit MPr and the wiring RDLr[j] are in a non-conductive state, the circuit MP and the wiring RDLr[j] are in a non-conductive state, and the circuit MPr and the wiring RDL[j] are in a non-conductive state.

[0328] As described above, by defining the first data stored in the memory cell MC and the second data input to the memory cell MC, the current flowing between the memory cell MC and the wiring RDL or the wiring RDLr is as shown in the table below.

[0329] [Table 4]

[0330] That is, when the product of the first data and the second data is "1", the calculation result is a current amount I ut When the product of the first data and the second data is "-1", the current amount I flows between the circuit MP or the circuit MPr and the wiring RDLr as a result of the calculation. ut When a current of "0" flows and the product of the first data and the second data is "0", as a result of the operation, a current of 0 flows between the circuit MP or the circuit MPr and the wiring RDL, and between the circuit MP or the circuit MPr and the wiring RDLr (no current flows between the circuit MP or the circuit MPr and the wiring RDL, and between the circuit MP or the circuit MPr and the wiring RDLr). In this way, the memory cell MC holds the first data in the memory cell MC, and then inputs the second data to the memory cell MC, thereby making it possible to operate the product of the first data and the second data.

[0331] Next, consider a case where multiple pieces of second data are supplied simultaneously to the wirings RWLAa[1] to RWLAa[m] and the wirings RWLAb[1] to RWLAb[m], respectively, while first data is held in each of multiple memory cells MC included in the memory cell array MCA. Note that the first data held in the memory cell MC[i,j] (i is an integer between 1 and m, and j is an integer between 1 and n) is represented by W[i,j], and the second data supplied to the wirings RWLAa[i] and RWLAb[i] is represented by X[i].

[0332] For example, in the jth column, when X[1] to X[m] are input as second data from wirings RWLAa[1] to RWLAa[m] and wirings RWLAb[1] to RWLAb[m] to each of memory cells MC[1,j] to MC[m,j], the calculations W[1,j]×X[1] to W[m,j]×X[m] are performed in each of memory cells MC[1,j] to MC[m,j].

[0333] Furthermore, since the product of the first data and the second data has three possibilities, "1", "-1", and "0", the number of memory cells MC in the memory cells MC[1,j] to MC[m,j] where the product of the first data and the second data is "1" is P, the number of memory cells MC where the product of the first data and the second data is "-1" is Q, and the number of memory cells MC where the product of the first data and the second data is "0" is R (each of P, Q, and R is an integer greater than or equal to 0 and satisfies P+Q+R=m). In this case, the total amount of current flowing through the wiring RDL[j] is P×I ut The total amount of current flowing through the wiring RDLr[j] is Q×I ut This becomes:

[0334] Here, the circuit RDD is, for example, the amount of current P×I flowing through the wiring RDL[j]. ut and the current flowing through the wiring RDLr[j] is Q×I ut By having the function of obtaining the difference between the first data and the second data and converting the difference into a voltage value, the result of a product-sum operation between multiple first data and multiple second data in memory cells MC[1,j] to MC[m,j] can be output as the voltage value.

[0335] The circuit RDD may also have the function of further computing a function using the result of the sum of products. For example, the circuit RDD can perform an artificial neural network operation by computing an activation function using the result of the sum of products. Examples of the activation function that can be used include a sigmoid function, a tanh function, a softmax function, a ReLU function, and a threshold function.

[0336] In addition, although the above description has been made on the results of the multiply-and-accumulate operation of the plurality of first data and the plurality of second data in the memory cells MC[1,j] to MC[m,j] located in the j-th column, the plurality of second data are transmitted via the wirings RWLAa[1] to RWLAa[m] and the wirings RWLAb[1] to RWLAb[m] extending in the row direction, so that the multiply-and-accumulate operation can also be performed in columns other than the j-th column. In other words, when the arithmetic circuit 110 performs the multiply-and-accumulate operation, it is possible to simultaneously perform the same number of multiply-and-accumulate operations as the number of columns of the memory cell array MCA.

[0337] Furthermore, although the above describes the case where the first data has three values, "1", "0", and "-1", by changing the operation method, changing the circuit configuration, etc., the first data may be treated as two values, four or more values, or an analog value.

[0338] Furthermore, although the above describes the case where the second data has three values, "1", "0", and "-1", by changing the operation method, changing the circuit configuration, etc., the second data can be treated as two values, four or more values, or an analog value.

[0339] For example, in the operation of the arithmetic circuit described above, the potentials corresponding to the second data and supplied to the wirings RWLAa and RWLAb are pulse voltages. When the pulse voltage input to either the wiring RWLAa or the wiring RWLAb is a high-level potential, one of the transistors M8 and M8r or the transistors M8m and M8mr is turned on for the duration of the input of the pulse voltage.

[0340] Here, when the polarization direction of the FTJ element FJA included in the circuit MP is positive and the polarization direction of the FTJ element FJAb is negative, and when the polarization direction of the FTJ element FJAr included in the circuit MPr is negative and the polarization direction of the FTJ element FJAbr is positive (i.e., when the first data stored in the memory cell MC is "1"), a current flows from the circuit MP to either the wiring RDL or the wiring RDLr for the input time.

[0341] For example, consider a case where the memory cell MC stores "1" as the first data. When the second data is "1", the input time T ut A high level potential is applied to the wiring RWLAa and a low level potential is applied to the wiring RWLAb. At this time, the amount of charge flowing between the circuit MP of the memory cell MC and the wiring RDL is T ut ×I MP and the amount of charge flowing between the circuit MPr of the memory cell MC and the wiring RDL is 0, the amount of charge flowing between the circuit MPr of the memory cell MC and the wiring RDLr is 0, and the amount of charge flowing between the circuit MPr of the memory cell MC and the wiring RDLr is 0.

[0342] Also, when the second data is "2", the input time is 2×T ut A high level potential is applied to the wiring RWLAa and a low level potential is applied to the wiring RWLAb. At this time, the amount of charge flowing between the circuit MP of the memory cell MC and the wiring RDL is 2×T ut ×I MP and the amount of charge flowing between the circuit MPr of the memory cell MC and the wiring RDL is 0, the amount of charge flowing between the circuit MPr of the memory cell MC and the wiring RDLr is 0, and the amount of charge flowing between the circuit MPr of the memory cell MC and the wiring RDLr is 0.

[0343] Also, when the second data is "-2", the input time is 2×T ut A low level potential is applied to the wiring RWLAa and a high level potential is applied to the wiring RWLAb. At this time, the amount of charge flowing between the circuit MP of the memory cell MC and the wiring RDL is 0, the amount of charge flowing between the circuit MPr of the memory cell MC and the wiring RDL is 0, and the amount of charge flowing between the circuit MP of the memory cell MC and the wiring RDLr is 2×T ut ×I MP As a result, the amount of charge flowing between the circuit MPr of the memory cell MC and the wiring RDLr becomes zero.

[0344] As described above, by increasing or decreasing the input time of the pulse voltage applied to the wiring RWLAa and the wiring RWLAb, it is possible to change the amount of charge flowing between the circuit MP or the circuit MPr of the memory cell MC and the wiring RDL, and the amount of charge flowing between the circuit MP or the circuit MPr of the memory cell MC and the wiring RDLr. Specifically, since the amount of charge flowing in each of the wiring RDL and the wiring RDLr is proportional to the input time of the pulse voltage, by determining the input time in accordance with the value of the second data, the memory cell MC can flow an amount of charge in accordance with the result of multiplying the first data and the second data into the wiring RDL or the wiring RDLr, with the second data being binary, four or more levels, or an analog value.

[0345] Furthermore, here, by configuring the circuit RDD to have a circuit (e.g., a QV conversion circuit, an integration circuit, etc.) that converts each of the amount of charge flowing into the wiring RDL and the amount of charge flowing into the wiring RDLr into a voltage value, the circuit RDD can obtain each of the amount of charge flowing into the wiring RDL and the amount of charge flowing into the wiring RDLr as a voltage value.

[0346] Furthermore, by configuring the circuit RDD to have a circuit that, for example, compares a voltage value corresponding to the amount of charge flowing through the wiring RDL with a voltage value corresponding to the amount of charge flowing through the wiring RDLr and outputs the comparison result as a voltage value, the circuit RDD can output the result of a product-sum operation between multiple first data and multiple second data in the memory cells MC[1,j] to MC[m,j] as the voltage value.

[0347] Furthermore, in the above example, an operation in which a pulse voltage is supplied to the wiring RWLAa and the wiring RWLAb has been described, but the product-sum operation may also be an operation in which a pulse voltage is supplied to at least one of, for example, the wiring FCA, the wiring FCB, etc. For example, a predetermined voltage may be input as a pulse voltage to each of the wiring FCA and the wiring FCB at the timing when charge is flowed between the memory cell MC and the wiring RDL and the wiring RDLr. Furthermore, for example, the product-sum operation may also be an operation in which a pulse voltage is supplied to at least one of, for example, the wiring VCE, the wiring VCEr, etc. For example, a predetermined voltage may be input as a pulse voltage to each of the wiring VCE and the wiring VCEr at the timing when charge is flowed between the memory cell MC and the wiring RDL and the wiring RDLr.

[0348] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0349] (Fourth embodiment) In this embodiment, a memory cell different from the memory cell MC described in the above embodiment will be described. The memory cell can be applied to a memory device that is a semiconductor device of one embodiment of the present invention.

[0350] <Configuration example> 17 shows an example of the configuration of the memory device 200. The memory device 200 includes, as an example, a memory cell array MCA, a circuit WDD, a circuit RDD, a circuit WRWD, and a circuit FECD.

[0351] The memory cell array MCA shown in Fig. 17 has a plurality of memory cells MC. Specifically, the memory cell array MCA has a plurality of memory cells MC arranged in a matrix. Note that, as an example, the memory cell array MCA shown in Fig. 17 has m rows of memory cells MC arranged therein. Also, Fig. 17 illustrates one column of a plurality of columns of the memory cell array MCA.

[0352] Therefore, the symbols of the circuit elements, wiring, etc. included in the memory cell array MCA in Fig. 17 are enclosed in brackets [ ] to indicate addresses. For example, in Fig. 17, the memory cell MC arranged in the first row is written as memory cell MC[1], and the memory cell MC arranged in the mth row is written as memory cell MC[m].

[0353] Each of the plurality of memory cells MC includes, for example, a transistor M1d and an FTJ element FJC.

[0354] As the transistor M1d, for example, a transistor applicable to the transistor M1 described in the first embodiment can be used.

[0355] As the FTJ element FJC, for example, an FTJ element that can be applied to the FTJ elements FJA and FJAb described in the first embodiment can be used.

[0356] 17, a first terminal of the transistor M1d is electrically connected to the wiring WRDL, a second terminal of the transistor M1d is electrically connected to the input terminal of the FTJ element FJC, a gate of the transistor M1d is electrically connected to the wiring WRWL[1], and an output terminal of the FTJ element FJC is electrically connected to the wiring FCL[1].

[0357] 17, a first terminal of the transistor M1d is electrically connected to the wiring WRDL, a second terminal of the transistor M1d is electrically connected to the input terminal of the FTJ element FJC, a gate of the transistor M1d is electrically connected to the wiring WRWL[m], and an output terminal of the FTJ element FJC is electrically connected to the wiring FCL[m].

[0358] The circuit WDD is electrically connected to the wiring WRDL. For example, the circuit WDD has a function of applying a potential corresponding to write data to one of the memory cells MC[1] to MC[m] through the wiring WRDL. The circuit WDD also has a function of supplying a potential corresponding to data read from one of the memory cells MC[1] to MC[m] to a read circuit or the like.

[0359] The circuit WRWD is electrically connected to each of the wirings WRWL[1] to WRWL[m]. For example, when performing a write operation or a read operation, the circuit WRWD has a function of transmitting a selection signal to one of the wirings WRWL[1] to WRWL[m] and a non-selection signal to the remaining wirings in order to select the memory cell MC[1] to MC[m] that is the target of the write operation or the read operation.

[0360] The circuit FECD is electrically connected to each of the wirings FCL[1] to FCL[m]. For example, when writing data to or reading data from a memory cell MC selected by the circuit WRWD, the circuit FECD applies a predetermined potential to the wiring FCL in the same row as the selected memory cell MC.

[0361] The circuit RDD shown in FIG. 17 includes a switch SW, a transistor M10, and a buffer circuit BUF.

[0362] As an example, the circuit RDD has the function of acquiring the current flowing from one of the plurality of memory cells MC included in the memory cell array MCA and converting the current into a voltage, thereby reading out the data stored in one of the plurality of memory cells MC.

[0363] 17, the wiring WRDL is electrically connected to a first terminal of the switch SW, and the second terminal of the switch SW is electrically connected to a first terminal of the transistor M10 and an input terminal of the buffer circuit BUF. The second terminal of the transistor M10 is electrically connected to the wiring VDL, and the gate of the transistor M10 is electrically connected to the wiring BSL. The output terminal of the buffer circuit BUF is electrically connected to the wiring OL.

[0364] For example, the switch SW functions to be in an off state when a write operation is being performed in any one of the memory cells MC[1] to MC[m] electrically connected to the wiring WRDL, and to be in an on state when a write operation is being performed in any one of the memory cells MC[1] to MC[m] electrically connected to the wiring WRDL.

[0365] The switch SW may be, for example, an electrical switch such as an analog switch or a transistor. When a transistor is used as the switch SW, the transistor may have a structure similar to that of the transistor M1. In addition, a mechanical switch may be used instead of an electrical switch.

[0366] For example, the transistor M10 functions as a load for converting a current flowing through the wiring WRDL into a voltage. For example, by applying a bias voltage from the wiring BSL to the gate of the transistor M10 and applying a high-level potential from the wiring VDL to the second terminal of the transistor M10, the potential of the first terminal of the transistor M10 is determined according to the current flowing from the wiring WRDL to the first terminal of the transistor M10 via the switch SW.

[0367] The buffer circuit BUF included in the circuit RDD functions as a circuit for stably outputting a potential equal to the potential of the first terminal of the transistor M10 to the wiring OL.

[0368] That is, the circuit RDD converts the current flowing through the wiring WRDL according to the data read from the memory cell MC into a voltage using the transistor M10, and outputs the voltage to the wiring OL. By acquiring the voltage of the wiring OL, the data read from the memory cell MC can be read.

[0369] <Example of operation> First, a description will be given of a write operation of data to the memory cell MC shown in Fig. 17. Note that, here, as an example, a write operation of data to the memory cell MC[1] will be described.

[0370] When data is written to the memory cell MC[1], the circuit WRWD selects the memory cell MC[1] to which the data is to be written. Specifically, the circuit WRWD applies a high-level potential to the wiring WRWL[1] and a low-level potential to the wirings WRWL[2] to WRWL[m]. At this time, a high-level potential is input to the gate of the transistor M1d in the memory cell MC[1], so that the transistor M1d in the memory cell MC[1] is turned on. On the other hand, a low-level potential is input to the gate of the transistor M1d in each of the memory cells MC[2] to MC[m], so that the transistor M1d in each of the memory cells MC[2] to MC[m] is turned off.

[0371] When a write operation is performed in the memory device 200, the switch SW of the circuit RDD is in an OFF state to prevent the transmission of write data from the wiring WRDL to the circuit RDD.

[0372] For example, the wiring FCL[1] is supplied with a reference potential from the circuit FECD. The reference potential may be, for example, a ground potential or a low-level potential.

[0373] Furthermore, a potential V0 or V1 is applied from the circuit WDD to the wiring WRDL as write data. Note that V0 is, for example, a potential lower than the reference potential applied to the wiring FCL[1]. Furthermore, V0 applied to the input terminal of the FTJ element FJC is a potential that generates polarization (changes the direction of polarization) in the material that may have ferroelectricity contained in the FTJ element FJC when a reference potential is applied to the output terminal of the FTJ element FJC. Note that because V0 is a potential lower than the reference potential, the direction of polarization written to the FTJ element FJC is from the output terminal to the input terminal (negative direction). Furthermore, V1 is, for example, a potential higher than the reference potential applied to the wiring FCL[1]. Furthermore, V1 applied to the input terminal of the FTJ element FJC is a potential that generates polarization (changes the direction of polarization) in the material that may have ferroelectricity contained in the FTJ element FJC when a reference potential is applied to the output terminal of the FTJ element FJC. Since V1 is a potential higher than the reference potential, the direction of polarization written to the FTJ element FJC is from the input terminal to the output terminal (positive direction).

[0374] After the write data is supplied from the circuit WDD to the wiring WRDL, the circuit WRWD supplies a low-level potential to the wiring WRWL[1]. At this time, the low-level potential is input to the gate of the transistor M1d of the memory cell MC[1], so that the transistor M1d of the memory cell MC[1] is turned off.

[0375] By the above-described operation, data can be written to the memory cell MC[1] of the memory device 200.

[0376] Next, a description will be given of an operation of reading data from the memory cell MC shown in Fig. 17. Note that, here, as an example, an operation of reading data from the memory cell MC[1] will be described.

[0377] When data is read from the memory cell MC[1], the circuit WRWD selects the memory cell MC[1] from which data is to be read. Specifically, the circuit WRWD applies a high-level potential to the wiring WRWL[1] and a low-level potential to the wirings WRWL[2] to WRWL[m]. At this time, a high-level potential is input to the gate of the transistor M1d in the memory cell MC[1], so that the transistor M1d in the memory cell MC[1] is turned on. On the other hand, a low-level potential is input to the gate of the transistor M1d in each of the memory cells MC[2] to MC[m], so that the transistor M1d in each of the memory cells MC[2] to MC[m] is turned off.

[0378] Furthermore, when a read operation is performed in the memory device 200, the switch SW of the circuit RDD is in an on state.

[0379] Moreover, as an example, a reference potential is applied to the wiring FCL[1] from the circuit FECD.

[0380] Moreover, as an example, a potential higher than the reference potential is applied to the wiring VDL.

[0381] At this time, conduction occurs between the input terminal of the FTJ element FJC of the memory cell MC[1] and the first terminal of the transistor M10 of the circuit RDD. A tunnel current flows between the input and output terminals of the FTJ element FJC of the memory cell MC[1]. The magnitude of the tunnel current depends on the polarization direction (positive or negative) of the ferroelectric material of the FTJ element FJC.

[0382] In the circuit RDD, the potential of the first terminal of the transistor M10 is determined by the amount of current flowing from the wiring WRDL to the input terminal of the FTJ element FJC of the memory cell MC[1]. As a result, a potential approximately equal to the potential of the first terminal of the transistor M10 is output to the output terminal of the buffer circuit BUF. Here, by obtaining this potential from the wiring OL, the data stored in the memory cell MC[1] can be read.

[0383] As described above, during a read operation of the memory device 200, a tunnel current flows between the input terminal and the output terminal of the FTJ element FJC included in each of the memory cells MC[1] to MC[m]. The amount of the tunnel current is determined by the direction of polarization of the ferroelectric material included in the FTJ element FJC, the material, the voltage between the input terminal and the output terminal, and the like, but is generally about 1×10 -8 A / cm 2 That's it, 1 x 10 -7 A / cm 2 The following may occur:

[0384] Here, when the transistor M1d included in each of the memory cells MC[1] to MC[m] is a Si transistor, even if the transistor M1d is in an off state, the current density is, for example, approximately 1×10 -10 A current of less than A may flow as an off-state current (leakage current). This also applies when the transistor M10 included in the circuit RDD is a Si transistor.

[0385] In particular, when the tunnel current flowing between the input terminal and output terminal of the FTJ element FJC is the same as the current flowing in the operating region where the off-current flows in the transistor M10, the potential of the first terminal of the transistor M10 is approximately the same as the potential of the second terminal of the transistor M10, that is, the potential provided by the wiring VDL. In other words, even if the amount of tunnel current flowing between the input terminal and output terminal of the FTJ element FJC changes, the potential of the first terminal of the transistor M10 hardly changes. Therefore, it is difficult to read the data held in the memory cell MC from the amount of tunnel current flowing between the input terminal and output terminal of the FTJ element FJC of the memory cell MC.

[0386] When transistors M1d, M10, etc. are Si transistors, it is preferable to increase the amount of tunnel current flowing between the input terminal and output terminal of the FTJ element FJC in order to read data held in the memory cell MC. Specifically, for example, the amount of tunnel current may be set to the amount of current flowing in the subthreshold region, saturation region, etc. of transistors M1d, M10, etc. To increase the amount of tunnel current flowing between the input terminal and output terminal of the FTJ element FJC, for example, the area of ​​a pair of electrodes of the FTJ element FJC may be increased.

[0387] When the transistor M1d included in each of the memory cells MC[1] to MC[m] is an OS transistor, the transistor M1d has a gate-source voltage of 1×10 -20 Less than A, 1 x 10 -22 Less than A or 1 x 10 -24 In some cases, the transistor M1d can pass a drain current of less than 1.0×10 A per 1 μm of channel width in a region where the gate-source voltage is close to the threshold voltage of the transistor M1d. -8 A or less, 1.0×10 -12 A or less, or 1.0 x 10 -15 In some cases, it is possible to pass a drain current of less than A per 1 μm of channel width.

[0388] FIG. 18 shows an overview of the source-drain current (Ids) and gate-source voltage (Vgs) characteristics of a Si transistor (Si FET) and an OS transistor (OS FET). In the characteristics of FIG. 18, the threshold voltages (V th ) are equal. For example, for each transistor, Vgs is the source-drain voltage Vds and V th When Vgs is greater than the sum of V, it operates in the linear region and V th The source-drain voltage Vds and V thWhen Vgs is less than the sum of V th If it is below this, it operates in the subthreshold region.

[0389] As shown in FIG. 18, the OS transistor can operate in a wider range of gate voltages in the subthreshold region than the Si transistor. Specifically, when the threshold voltage of the OS transistor is V th In the subthreshold region, V th -1.0V or more V th Below, or V th -0.5V or more V th The circuit can operate using gate voltages in the following voltage ranges:

[0390] Therefore, when transistors M1d, M10, etc. are OS transistors, if the amount of tunnel current flowing between the input terminal and output terminal of the FTJ element FJC is the same as the amount of current flowing in the subthreshold region of transistor M10, the potential of the first terminal of transistor M10 is determined according to the amount of tunnel current. Therefore, data held in memory cell MC can be read from the amount of tunnel current flowing between the input terminal and output terminal of the FTJ element FJC of memory cell MC.

[0391] Furthermore, by using an OS transistor for the transistor M10, the amount of current flowing in the subthreshold region of the transistor M10 can be read out as a potential, and therefore, as long as the transistor M10 operates in the subthreshold region, the tunneling current flowing between the input terminal and output terminal of the FTJ element FJC can be reduced.To reduce the amount of tunneling current flowing between the input terminal and output terminal of the FTJ element FJC, for example, the area of ​​a pair of electrodes of the FTJ element FJC can be reduced.

[0392] That is, by applying OS transistors to the transistors M1d, M10, and the like in the memory device 200, it is possible to reduce the circuit area required for the FTJ element FJC and to miniaturize the memory cells MC of the memory device 200. Furthermore, by reducing the amount of tunnel current flowing through the FTJ element FJC, it is possible to reduce the power consumption required for the read operation of the memory device 200.

[0393] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0394] (Embodiment 5) In this embodiment, structural examples of the semiconductor device described in the above embodiment and structural examples of a transistor that can be applied to the semiconductor device described in the above embodiment will be described.

[0395] <Configuration Example 1 of Semiconductor Device> 19 illustrates a semiconductor device having a memory cell including a capacitor, the semiconductor device including a transistor 300, a transistor 500, and a capacitor 600. Fig. 20A illustrates a cross-sectional view of the transistor 500 in the channel length direction, Fig. 20B illustrates a cross-sectional view of the transistor 500 in the channel width direction, and Fig. 20C illustrates a cross-sectional view of the transistor 300 in the channel width direction.

[0396] The transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. The transistor 500 has a small off-state current and a field-effect mobility that is not easily changed even at high temperatures. By applying the transistor 500 to a semiconductor device, such as the transistor M1 or M1b included in the memory cell MC described in the above embodiment, a semiconductor device whose operating capability is not easily degraded even at high temperatures can be realized. In particular, by utilizing the small off-state current, applying the transistor 500 to the transistor M1 or M1b, for example, the potential written to the capacitance of the memory cell MC can be held for a long time.

[0397] The transistor 500 is provided above the transistor 300, for example, and the capacitor 600 is provided above the transistors 300 and 500, for example. The capacitor 600 can be a capacitor that holds a potential according to data written to a memory cell. Depending on the circuit configuration, the capacitor 600 shown in FIG. 19 is not necessarily provided.

[0398] The transistor 300 is provided over a substrate 310 and includes an element isolation layer 312, a conductor 316, an insulator 315, a semiconductor region 313 formed of part of the substrate 310, and low-resistance regions 314a and 314b functioning as source and drain regions. Note that the transistor 300 can be applied to, for example, the transistor M6 and the transistor M6b described in the above embodiments. Note that Figure 19 shows a configuration in which the gate of the transistor 300 is electrically connected to one of the source and drain of the transistor 500 through one of the electrodes of the capacitor 600; however, depending on the configuration of the semiconductor device of one embodiment of the present invention, one of the source and drain of the transistor 300 can be electrically connected to one of the source and drain of the transistor 500 through one of the electrodes of the capacitor 600, or one of the source and drain of the transistor 300 can be electrically connected to the gate of the transistor 500 through one of the electrodes of the capacitor 600. Furthermore, each terminal of the transistor 300 can be not electrically connected to each terminal of the transistor 500 or each terminal of the capacitor 600.

[0399] The substrate 310 is preferably a semiconductor substrate (for example, a single crystal substrate or a silicon substrate).

[0400] 20C , the upper surface and the side surfaces in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this way, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 300. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300.

[0401] The transistor 300 may be either a p-channel type or an n-channel type.

[0402] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0403] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0404] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0405] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0406] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer can be formed by using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, a mesa isolation method, or the like.

[0407] 19 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like. For example, the transistor 300 may have a planar structure instead of the FIN structure shown in FIG. 20C. For example, when the semiconductor device is a unipolar circuit including only OS transistors, the structure of the transistor 300 may be the same as that of the transistor 500 including an oxide semiconductor, as shown in FIG. 21. The details of the transistor 500 will be described later. In this specification and the like, a unipolar circuit refers to a circuit including transistors of only one polarity, that is, an n-channel transistor or a p-channel transistor.

[0408] In FIG. 21, the transistor 300 is provided on a substrate 310A. However, in this case, the substrate 310A may be a semiconductor substrate similar to the substrate 310 of the semiconductor device in FIG. 19. The substrate 310A may be, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride, as well as polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper.

[0409] In the transistor 300 shown in FIG. 19, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side.

[0410] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0411] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0412] The insulator 322 may function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0413] The insulator 324 is preferably a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 310 or the transistor 300 to a region where the transistor 500 is provided.

[0414] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0415] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm2 The following is fine.

[0416] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0417] Conductors 328 and 330, which connect to the capacitor 600 or the transistor 500, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings. A plurality of conductors that function as plugs or wirings may be collectively denoted by the same reference numeral. In this specification and the like, a wiring and a plug connected to the wiring may be integral. That is, a part of a conductor may function as a wiring, and a part of a conductor may function as a plug.

[0418] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0419] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 19 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0420] Note that, for example, the insulator 350 is preferably an insulator having barrier properties against impurities such as hydrogen and water, similar to the insulator 324. Similarly to the insulator 326, the insulators 352 and 354 are preferably insulators having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The conductor 356 preferably includes a conductor having barrier properties against impurities such as hydrogen and water. In particular, a conductor having barrier properties against hydrogen is formed in the opening of the insulator 350 having barrier properties against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, thereby suppressing diffusion of hydrogen from the transistor 300 to the transistor 500.

[0421] Note that, for example, tantalum nitride or the like is preferably used as the conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0422] Furthermore, on the insulator 354 and the conductor 356, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order.

[0423] The insulator 360 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 360 can be made of, for example, a material that can be used for the insulator 324.

[0424] The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. As the insulators 362 and 364, it is preferable to use an insulator that has a barrier property against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 362 and / or the insulator 364 can be made of a material that can be used for the insulator 324.

[0425] Openings are formed in the insulators 360, 362, and 364 in regions that overlap with part of the conductor 356, and the conductor 366 is provided to fill the openings. The conductor 366 is also formed over the insulator 362. For example, the conductor 366 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0426] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 364 and the conductor 366. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made using a substance that has a barrier property against oxygen and hydrogen.

[0427] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate 310 or the region where the transistor 300 is provided to the region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0428] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0429] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0430] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0431] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulators 512 and 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0432] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503 shown in FIGS. 20A and 20B), and the like are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0433] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor that has a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated by a layer that has a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0434] Above the insulator 516 is the transistor 500 .

[0435] As shown in FIGS. 20A and 20B, the transistor 500 includes an insulator 516 on an insulator 514, a conductor 503 (conductor 503a and conductor 503b) disposed so as to be embedded in the insulator 514 or the insulator 516, an insulator 522 on the insulator 516 and on the conductor 503, an insulator 524 on the insulator 522, an oxide 530a on the insulator 524, an oxide 530b on the oxide 530a, a conductor 542a on the oxide 530b, an insulator 571a on the conductor 542a, and an oxide 572a on the oxide 572b. conductor 542b on oxide 530b, insulator 571b on conductor 542b, insulator 552 on oxide 530b, insulator 550 on insulator 552, insulator 554 on insulator 550, conductor 560 (conductor 560a and conductor 560b) located on insulator 554 and overlapping part of oxide 530b, and insulator 544 arranged on insulator 522, insulator 524, oxide 530a, oxide 530b, conductor 542a, conductor 542b, insulator 571a, and insulator 571b. 20A and 20B, insulator 552 contacts the upper surface of insulator 522, the side surface of insulator 524, the side surface of oxide 530a, the side surface and upper surface of oxide 530b, the side surface of conductor 542 (conductor 542a and conductor 542b), the side surface of insulator 571 (insulator 571a and insulator 571b), the side surface of insulator 544, the side surface of insulator 580, and the lower surface of insulator 550. The upper surface of conductor 560 is disposed so as to be at approximately the same height as the upper surfaces of insulator 554, insulator 550, insulator 552, and insulator 580. Insulator 574 contacts at least a portion of the upper surface of conductor 560, insulator 552, insulator 550, insulator 554, and insulator 580.

[0436] Openings reaching the oxide 530b are provided in the insulator 580 and the insulator 544. The insulator 552, the insulator 550, the insulator 554, and the conductor 560 are disposed in the openings. In addition, the conductor 560, the insulator 552, the insulator 550, and the insulator 554 are provided between the insulator 571a and the conductor 542a and between the insulator 571b and the conductor 542b in the channel length direction of the transistor 500. The insulator 554 has a region in contact with the side surface of the conductor 560 and a region in contact with the bottom surface of the conductor 560.

[0437] The oxide 530 preferably includes an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on the oxide 530a. By providing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b.

[0438] Note that although the transistor 500 has a structure in which the oxide 530 has two layers, the oxide 530a and the oxide 530b, the present invention is not limited to this. For example, the transistor 500 can have a single layer of the oxide 530b or a stacked structure of three or more layers. Alternatively, each of the oxide 530a and the oxide 530b can have a stacked structure.

[0439] The conductor 560 functions as a first gate (also referred to as a top gate) electrode, and the conductor 503 functions as a second gate (also referred to as a back gate) electrode. The insulators 552, 550, and 554 function as a first gate insulator, and the insulators 522 and 524 function as a second gate insulator. The gate insulators may also be referred to as a gate insulating layer or a gate insulating film. The conductor 542a functions as either a source or a drain, and the conductor 542b functions as the other. At least a part of a region of the oxide 530 that overlaps with the conductor 560 functions as a channel formation region.

[0440] FIG. 22A shows an enlarged view of the vicinity of the channel formation region in FIG. 20A. When oxygen is supplied to the oxide 530b, a channel formation region is formed in the region between the conductor 542a and the conductor 542b. Therefore, as shown in FIG. 22A, the oxide 530b includes a region 530bc that functions as the channel formation region of the transistor 500, and regions 530ba and 530bb that are provided on either side of the region 530bc and function as source and drain regions. At least a portion of the region 530bc overlaps with the conductor 560. In other words, the region 530bc is located in the region between the conductor 542a and the conductor 542b. The region 530ba overlaps with the conductor 542a, and the region 530bb overlaps with the conductor 542b.

[0441] The region 530bc, which functions as a channel formation region, has a smaller oxygen vacancy (in this specification, oxygen vacancy in a metal oxide is referred to as V) than the regions 530ba and 530bb. O The region 530bc is a high-resistance region with a low carrier concentration due to its low oxygen vacancy or low impurity concentration. Therefore, the region 530bc can be said to be i-type (intrinsic) or substantially i-type.

[0442] A transistor using a metal oxide has impurities or oxygen vacancies (V O ) may cause fluctuations in electrical characteristics and reduce reliability. O ) hydrogen near the oxygen vacancy (V O ) with hydrogen (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V OIt is preferable that H is reduced as much as possible.

[0443] The regions 530ba and 530bb that function as source and drain regions have oxygen vacancies (V O ) or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, resulting in an increased carrier concentration and low resistance. That is, the regions 530ba and 530bb are n-type regions with a higher carrier concentration and lower resistance than the region 530bc.

[0444] Here, the carrier concentration of the region 530bc that functions as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 530bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0445] A region having a carrier concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc may be formed between region 530bc and regions 530ba or 530bb. That is, this region functions as a junction region between region 530bc and regions 530ba or 530bb. The junction region may have a hydrogen concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc. The junction region may also have oxygen vacancies equal to or lower than those of regions 530ba and 530bb and equal to or higher than those of region 530bc.

[0446] 22A shows an example in which the regions 530ba, 530bb, and 530bc are formed in the oxide 530b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 530b but also in the oxide 530a.

[0447] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 530. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than gradually varying from region to region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in the region closer to the channel formation region.

[0448] In the transistor 500, the oxide 530 including the channel formation region (the oxide 530a and the oxide 530b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0449] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0450] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 530. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 530.

[0451] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 530b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0452] In this way, by disposing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 530a into the oxide 530b.

[0453] Furthermore, since the oxide 530a and the oxide 530b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Because the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0454] The oxide 530b preferably has crystallinity, and in particular, it is preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 530b.

[0455] CAAC-OS has a highly crystalline and dense structure and is free of impurities and defects (e.g., oxygen vacancies (V O In particular, the CAAC-OS can be made to have a dense structure with higher crystallinity by heat-treating the formed metal oxide at a temperature (for example, 400°C or higher and 600°C or lower) at which the metal oxide does not polycrystallize. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0456] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0457] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen near the oxygen vacancies may be introduced into the oxygen vacancies (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in an oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0458] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed to supply oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 500. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies across the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0459] Therefore, in the oxide semiconductor, the region 530bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 530ba and 530bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 530ba and 530bb.

[0460] Therefore, in this embodiment, in a state where the conductors 542a and 542b are provided on the oxide 530b, microwave treatment is performed in an atmosphere containing oxygen to remove oxygen vacancies in the region 530bc and V O The microwave treatment here refers to a treatment using a device with a power source that generates high-density plasma using microwaves, for example.

[0461] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can also be irradiated onto the region 530bc. The V of the region 530bc can be activated by the action of the plasma, microwaves, etc. O H is split off, hydrogen H is removed from the region 530bc, and oxygen vacancy V Ocan be compensated with oxygen. O H → H + V O This reaction occurs, and the hydrogen concentration in the region 530bc can be reduced. O H can be reduced to lower the carrier concentration.

[0462] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 542a and 542b and do not reach the regions 530ba and 530bb. Furthermore, the effects of oxygen plasma can be reduced by the insulators 571 and 580 that cover the oxide 530b and the conductor 542. As a result, during microwave processing, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0463] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes the insulator 552 or after forming the insulating film that becomes the insulator 550. By performing microwave treatment in an oxygen-containing atmosphere through the insulator 552 or the insulator 550 in this manner, oxygen can be efficiently injected into the region 530bc. Furthermore, by arranging the insulator 552 so as to be in contact with the side surface of the conductor 542 and the surface of the region 530bc, injection of more oxygen than necessary into the region 530bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 542. Furthermore, oxidation of the side surface of the conductor 542 can be suppressed during formation of the insulating film that becomes the insulator 550.

[0464] The oxygen implanted into the region 530bc can be in various forms, such as oxygen atoms, oxygen molecules, or oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen implanted into the region 530bc preferably takes one or more of the above forms, and oxygen radicals are particularly preferred. This can improve the film quality of the insulators 552 and 550, thereby improving the reliability of the transistor 500.

[0465] In this way, oxygen vacancies and V are selectively formed in the oxide semiconductor region 530bc. O By removing H, the region 530bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 530ba and 530bb, which function as source and drain regions, can be suppressed, thereby maintaining conductivity. This suppresses fluctuations in the electrical characteristics of the transistor 500 and reduces variations in the electrical characteristics of the transistor 500 within the substrate surface.

[0466] By adopting the above-described configuration, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device with good electrical characteristics.

[0467] 20B, in a cross-sectional view of the transistor 500 in the channel width direction, a curved surface may be formed between the side surface of the oxide 530b and the top surface of the oxide 530b. That is, the end portions of the side surface and the top surface may be curved (hereinafter also referred to as rounded).

[0468] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 530b with the insulators 552, 550, and 554, and the conductor 560.

[0469] The oxide 530 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to the metal element that is the main component is preferably greater than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0470] The oxide 530b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), and have a highly crystalline and dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 530b. This can reduce the extraction of oxygen from the oxide 530b even during heat treatment, making the transistor 500 stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0471] Here, the conduction band minimum changes gradually at the junction between the oxides 530a and 530b. In other words, the conduction band minimum at the junction between the oxides 530a and 530b changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the oxides 530a and 530b.

[0472] Specifically, when the oxide 530a and the oxide 530b contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-M-Zn oxide, the oxide 530a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0473] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. Oxide 530b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as element M.

[0474] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0475] 20A and other figures, providing an insulator 552 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 530 can cause indium in the oxide 530 to be unevenly distributed at and near the interface between the oxide 530 and the insulator 552. This results in an atomic ratio near the surface of the oxide 530 that is close to that of indium oxide or In-Zn oxide. The increased atomic ratio of indium near the surface of the oxide 530, particularly the oxide 530b, can improve the field-effect mobility of the transistor 500.

[0476] The oxide 530a and the oxide 530b have the above-described structure, which can reduce the defect state density at the interface between the oxide 530a and the oxide 530b. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can achieve a large on-state current and high frequency characteristics.

[0477] At least one of the insulators 512, 514, 544, 571, 574, 576, and 581 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, at least one of the insulators 512, 514, 544, 571, 574, 576, and 581 is preferably made of an insulating material that suppresses diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably made of an insulating material that suppresses diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., through which the above oxygen is less likely to permeate).

[0478] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0479] For the insulators 512, 514, 544, 571, 574, 576, and 581, it is preferable to use an insulator that has the function of suppressing diffusion of oxygen and impurities such as water and hydrogen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, silicon nitride, which has a high hydrogen barrier property, is preferably used for the insulators 512, 544, and 576. Furthermore, it is preferable to use aluminum oxide or magnesium oxide, which has a high ability to capture and fix hydrogen, for the insulators 514, 571, 574, and 581. This can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side through the insulators 512 and 514. Alternatively, impurities such as water and hydrogen can be prevented from diffusing toward the transistor 500 from an interlayer insulating film disposed outside the insulator 581. Alternatively, oxygen contained in the insulator 524 and the like can be prevented from diffusing toward the substrate through the insulators 512 and 514. Alternatively, oxygen contained in the insulator 580 and the like can be prevented from diffusing upward from the transistor 500 through the insulator 574. In this way, the transistor 500 is preferably surrounded by the insulators 512, 514, 571, 544, 574, 576, and 581, which have the function of preventing the diffusion of impurities such as water and hydrogen and oxygen.

[0480] Here, it is preferable to use an oxide having an amorphous structure as the insulators 512, 514, 544, 571, 574, 576, and 581. For example, AlO x (x is any number greater than 0), or MgO y It is preferable to use a metal oxide such as y (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, hydrogen contained in the transistor 500 or hydrogen present around the transistor 500 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, a highly reliable transistor 500 and semiconductor device can be manufactured with excellent characteristics.

[0481] Furthermore, the insulators 512, 514, 544, 571, 574, 576, and 581 preferably have an amorphous structure, but may have a polycrystalline structure in part. The insulators 512, 514, 544, 571, 574, 576, and 581 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0482] The insulators 512, 514, 544, 571, 574, 576, and 581 can be formed by, for example, a sputtering method. Sputtering does not require the use of molecules containing hydrogen in the film formation gas, and therefore can reduce the hydrogen concentrations of the insulators 512, 514, 544, 571, 574, 576, and 581. Note that the film formation method is not limited to sputtering, and chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like may also be used as appropriate.

[0483] It may also be desirable to reduce the resistivity of insulators 512, 544, and 576. For example, it may be desirable to reduce the resistivity of insulators 512, 544, and 576 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulators 512, 544, and 576 may be able to reduce charge-up of the conductors 503, 542, and 560 during treatment using plasma or the like in the manufacturing process of a semiconductor device. The resistivity of the insulators 512, 544, and 576 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0484] The insulators 516, 574, 580, and 581 preferably have a lower dielectric constant than the insulator 514. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 516, 580, and 581.

[0485] For example, the insulator 581 is preferably an insulator that functions as an interlayer film, a planarizing film, or the like.

[0486] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Here, the conductor 503 is preferably provided by being embedded in an opening formed in the insulator 516. In addition, a part of the conductor 503 may be embedded in the insulator 514.

[0487] The conductor 503 includes a conductor 503a and a conductor 503b. The conductor 503a is provided in contact with the bottom surface and sidewall of the opening. The conductor 503b is provided so as to be embedded in a recess formed in the conductor 503a. Here, the height of the top of the conductor 503b is approximately the same as the height of the top of the conductor 503a and the height of the top of the insulator 516.

[0488] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0489] By using a conductive material that can reduce hydrogen diffusion for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 via the insulator 524 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 503a, it is possible to prevent the conductor 503b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 503a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 503a may be made of titanium nitride.

[0490] The conductor 503b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0491] The conductor 503 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the Vth of the transistor 500 and reduce its off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0492] Note that if the oxide 530 is highly pure and intrinsic, and impurities are removed from the oxide 530 as much as possible, it may be possible to make the transistor 500 normally off (to make the threshold voltage of the transistor 500 higher than 0 V) ​​without applying a potential to the conductor 503 and / or the conductor 560. In this case, it is preferable to connect the conductor 560 and the conductor 503 so that the same potential is applied to them.

[0493] The electrical resistivity of the conductor 503 is designed taking into consideration the potential applied to the conductor 503, and the film thickness of the conductor 503 is set to match this electrical resistivity. The film thickness of the insulator 516 is approximately the same as that of the conductor 503. Here, it is preferable to make the film thicknesses of the conductor 503 and the insulator 516 as thin as possible within the range permitted by the design of the conductor 503. By making the film thickness of the insulator 516 thin, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, thereby reducing the diffusion of the impurities into the oxide 530.

[0494] Note that the conductor 503 is preferably larger than the area of ​​the oxide 530 that does not overlap with the conductors 542a and 542b when viewed from above. In particular, as shown in FIG. 20B , the conductor 503 preferably extends to an area outside the channel width direction ends of the oxides 530a and 530b. That is, outside the side surfaces of the oxide 530 in the channel width direction, the conductor 503 and the conductor 560 preferably overlap with each other via an insulator. With this structure, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560, which functions as the first gate electrode, and the electric field of the conductor 503, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0495] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0496] By configuring the transistor 500 as a normally-off transistor and adopting the above-described S-Channel structure, the channel formation region can be electrically surrounded. Therefore, the transistor 500 can also be considered to have a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By configuring the transistor 500 as an S-Channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the gate insulating film can be the entire bulk of the oxide 530. In other words, by configuring the transistor 500 as an S-Channel structure, a GAA structure, or an LGAA structure, the entire bulk can be used as a carrier path, making it a so-called bulk-flow type. The bulk-flow type transistor structure can increase the current density flowing through the transistor, which is expected to improve the on-state current or field-effect mobility of the transistor.

[0497] 20B, the conductor 503 is extended to function as a wiring. However, the present invention is not limited to this, and a conductor functioning as a wiring may be provided below the conductor 503. Furthermore, it is not necessary to provide one conductor 503 for each transistor. For example, the conductor 503 may be shared by multiple transistors.

[0498] Note that although the conductor 503 in the transistor 500 has a stacked structure of the conductor 503a and the conductor 503b, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0499] Insulator 522 and insulator 524 function as gate insulators.

[0500] The insulator 522 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 522 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 522 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 524.

[0501] The insulator 522 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 to the substrate and diffusion of impurities such as hydrogen from the periphery of the transistor 500 to the oxide 530. Therefore, the insulator 522 can suppress diffusion of impurities such as hydrogen into the transistor 500 and suppress generation of oxygen vacancies in the oxide 530. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0502] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 522 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0503] The insulator 522 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become smaller and more highly integrated, thinning of the gate insulator can lead to problems such as leakage current. Using a high-k material as the gate insulator can reduce the gate potential during transistor operation while maintaining the physical film thickness. Alternatively, the insulator 522 may be made of a material with a high dielectric constant, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST).

[0504] The insulator 524 in contact with the oxide 530 can be made of, for example, silicon oxide, silicon oxynitride, or the like as appropriate.

[0505] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 600° C., more preferably 350° C. to 550° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0506] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, OFurthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0507] The insulators 522 and 524 may each have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 524 may be formed in an island shape overlapping the oxide 530a. In this case, the insulator 544 is configured to contact the side surface of the insulator 524 and the top surface of the insulator 522.

[0508] The conductor 542a and the conductor 542b are provided in contact with the top surface of the oxide 530b. The conductor 542a and the conductor 542b function as a source electrode and a drain electrode of the transistor 500, respectively.

[0509] As the conductor 542 (conductor 542a and conductor 542b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0510] Note that hydrogen contained in the oxide 530b and the like may diffuse into the conductor 542a or the conductor 542b. In particular, by using a nitride containing tantalum for the conductors 542a and 542b, hydrogen contained in the oxide 530b and the like is likely to diffuse into the conductor 542a or the conductor 542b, and the diffused hydrogen may bond with nitrogen contained in the conductor 542a or the conductor 542b. In other words, hydrogen contained in the oxide 530b and the like may be absorbed by the conductor 542a or the conductor 542b.

[0511] Furthermore, it is preferable that no curved surface be formed between the side surface of the conductor 542 and the top surface of the conductor 542. The conductor 542 without such a curved surface can increase the cross-sectional area of ​​the conductor 542 in the cross section in the channel width direction. This can increase the conductivity of the conductor 542 and the on-state current of the transistor 500.

[0512] The insulator 571a is provided in contact with the top surface of the conductor 542a, and the insulator 571b is provided in contact with the top surface of the conductor 542b. The insulator 571 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 571 preferably has a function of suppressing oxygen diffusion. For example, the insulator 571 preferably has a function of suppressing oxygen diffusion more than the insulator 580. The insulator 571 may be, for example, a nitride containing silicon, such as silicon nitride. The insulator 571 preferably has a function of capturing impurities such as hydrogen. In this case, the insulator 571 may be an insulator of a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 571 is preferable because hydrogen can be more effectively captured or fixed. This enables the manufacture of a highly reliable transistor 500 and a semiconductor device with favorable characteristics.

[0513] The insulator 544 is provided to cover the insulator 524, the oxide 530a, the oxide 530b, the conductor 542, and the insulator 571. The insulator 544 preferably has a function of capturing and fixing hydrogen. In this case, the insulator 544 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, the insulator 544 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0514] By providing the insulator 571 and the insulator 544 as described above, the conductor 542 can be surrounded by an insulator having a barrier property against oxygen. That is, oxygen contained in the insulator 524 and the insulator 580 can be prevented from diffusing into the conductor 542. This can prevent the conductor 542 from being directly oxidized by the oxygen contained in the insulator 524 and the insulator 580, which increases the resistivity and reduces the on-state current.

[0515] The insulator 552 functions as part of the gate insulator. The insulator 552 is preferably a barrier insulating film against oxygen. Any of the insulators that can be used for the insulator 574 described above can be used as the insulator 552. The insulator 552 can be an insulator containing one or both of an oxide of aluminum and hafnium. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 552. In this case, the insulator 552 contains at least oxygen and aluminum.

[0516] As shown in FIG. 20B, the insulator 552 is provided in contact with the top surface and side surfaces of the oxide 530b, the side surfaces of the oxide 530a, the side surfaces of the insulator 524, and the top surface of the insulator 522. That is, the regions of the oxide 530a, the oxide 530b, and the insulator 524 that overlap with the conductor 560 are covered with the insulator 552 in the cross section in the channel width direction. This allows the insulator 552, which has oxygen barrier properties, to block oxygen from being released from the oxides 530a and 530b during heat treatment or the like. This reduces the formation of oxygen vacancies (Vo) in the oxides 530a and 530b. This reduces the oxygen vacancies (Vo) and V formed in the region 530bc. O H can be reduced. Therefore, the electrical characteristics of the transistor 500 can be improved, and the reliability can be improved.

[0517] Conversely, even if the insulator 580, the insulator 550, or the like contains excessive amounts of oxygen, the oxygen can be prevented from being excessively supplied to the oxide 530a and the oxide 530b. Therefore, the region 530bc can prevent the regions 530ba and 530bb from being excessively oxidized, which would cause a decrease in the on-state current or the field-effect mobility of the transistor 500.

[0518] 20A , the insulator 552 is provided in contact with the side surfaces of the conductor 542, the insulator 544, the insulator 571, and the insulator 580. This reduces the oxidation of the side surface of the conductor 542 and the formation of an oxide film on the side surface. This reduces the on-state current or field-effect mobility of the transistor 500.

[0519] The insulator 552, together with the insulator 554, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 552 preferably has a small thickness. The thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 552 only needs to have at least a region with the above-described thickness. The thickness of the insulator 552 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 552 only needs to have at least a region with a thickness thinner than the insulator 550.

[0520] To deposit the insulator 552 to a thin thickness as described above, it is preferable to use the ALD method. The ALD method alternately introduces a first source gas (also called a precursor, precursor, or metal precursor) and a second source gas (also called a reactant, reactant, oxidizer, or non-metal precursor) for the reaction into a chamber, and then repeats the introduction of these source gases to deposit the film. ALD methods include thermal ALD, in which the reaction between the precursor and the reactant is carried out using only thermal energy, and PEALD (Plasma Enhanced ALD), which uses plasma-excited reactants. The PEALD method may be preferable because it utilizes plasma, which allows film deposition at lower temperatures.

[0521] The ALD method utilizes the self-regulating property of atoms and can deposit atoms one layer at a time, which has the advantages of enabling ultrathin film formation, film formation on structures with high aspect ratios, film formation with few defects such as pinholes, film formation with excellent coverage, film formation at low temperatures, etc. Therefore, the insulator 552 can be formed with good coverage on the side surfaces of an opening formed in the insulator 580 or the like and with the thin film thickness described above.

[0522] Some precursors used in ALD contain carbon and other impurities. Therefore, films formed by ALD may contain more carbon and other impurities than films formed by other film formation methods. Quantitative determination of impurities can be performed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0523] The insulator 550 functions as part of the gate insulator. The insulator 550 is preferably disposed in contact with the upper surface of the insulator 552. The insulator 550 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 550 is an insulator containing at least oxygen and silicon.

[0524] Like the insulator 524, the insulator 550 preferably has a reduced concentration of impurities such as water and hydrogen. The thickness of the insulator 550 is preferably 1 nm or more, or 0.5 nm or more, and preferably 15 nm or less, or 20 nm or less. Note that the above-mentioned lower and upper limits can be combined. In this case, the insulator 550 only needs to have a region with the above-mentioned thickness in at least a portion thereof.

[0525] 20A and 20B show a configuration in which the insulator 550 is a single layer, but the present invention is not limited to this and the insulator 550 may have a laminated structure of two or more layers. For example, as shown in FIG. 22B, the insulator 550 may have a two-layer laminated structure of an insulator 550a and an insulator 550b on the insulator 550a.

[0526] As shown in FIG. 22B , when the insulator 550 has a two-layer stacked structure, the lower insulator 550a is preferably formed using an insulator that easily transmits oxygen, and the upper insulator 550b is preferably formed using an insulator that suppresses oxygen diffusion. This structure can suppress the diffusion of oxygen contained in the insulator 550a into the conductor 560. That is, it can suppress a decrease in the amount of oxygen supplied to the oxide 530. It can also suppress oxidation of the conductor 560 due to the oxygen contained in the insulator 550a. For example, the insulator 550a may be formed using a material that can be used for the insulator 550 described above, and the insulator 550b may be formed using an insulator containing one or both of aluminum and hafnium oxides. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b contains at least oxygen and hafnium. The thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, the insulator 550b only needs to have a region with the above-mentioned thickness in at least a portion.

[0527] When silicon oxide, silicon oxynitride, or the like is used for the insulator 550a, the insulator 550b may be an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator as a layered structure of the insulators 550a and 550b, a layered structure that is thermally stable and has a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. This allows the dielectric strength of the insulator 550 to be increased.

[0528] The insulator 554 functions as part of the gate insulator. A barrier insulating film against hydrogen is preferably used as the insulator 554. This can prevent impurities such as hydrogen contained in the conductor 560 from diffusing into the insulator 550 and the oxide 530b. The insulator 554 can be any of the insulators that can be used for the insulator 576. For example, silicon nitride formed by a PEALD method can be used as the insulator 554. In this case, the insulator 554 contains at least nitrogen and silicon.

[0529] The insulator 554 may further have a barrier property against oxygen, which can prevent oxygen contained in the insulator 550 from diffusing into the conductor 560.

[0530] The insulator 554, together with the insulator 552, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 554 preferably has a small thickness. The thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 554 only needs to have at least a region with the above-described thickness. The thickness of the insulator 554 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 554 only needs to have at least a region with a thickness thinner than the insulator 550.

[0531] The conductor 560 functions as a first gate electrode of the transistor 500. The conductor 560 preferably includes a conductor 560a and a conductor 560b disposed over the conductor 560a. For example, the conductor 560a is preferably disposed so as to surround the bottom and side surfaces of the conductor 560b. As shown in FIGS. 20A and 20B, the height of the top of the conductor 560 roughly coincides with the height of the top of the insulator 550. Note that although the conductor 560 is shown as having a two-layer structure of the conductor 560a and the conductor 560b in FIGS. 20A and 20B, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers, other than the two-layer structure.

[0532] The conductor 560a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0533] Furthermore, since conductor 560a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of conductor 560b caused by oxygen contained in insulator 550. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0534] Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 560b can be a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b can have a layered structure. Specifically, for example, the conductor 560b can have a layered structure of titanium or titanium nitride and the above conductive material.

[0535] Furthermore, in the transistor 500, the conductor 560 is formed in a self-aligned manner so as to fill an opening formed in the insulator 580 or the like. By forming the conductor 560 in this manner, the conductor 560 can be reliably placed in the region between the conductor 542a and the conductor 542b without alignment.

[0536] 20B , in the channel width direction of the transistor 500, the height of the bottom surface of the conductor 560 in a region where the conductor 560 does not overlap with the oxide 530b is preferably lower than the height of the bottom surface of the oxide 530b when the bottom surface of the insulator 522 is used as the reference. When the conductor 560, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 530b via the insulator 550 or the like, the electric field of the conductor 560 can be easily applied to the entire channel formation region of the oxide 530b. Therefore, the on-state current of the transistor 500 can be increased, and the frequency characteristics can be improved. The difference between the height of the bottom surface of conductor 560 and the height of the bottom surface of oxide 530b in the region where oxide 530a and oxide 530b do not overlap with conductor 560, relative to the bottom surface of insulator 522, is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and is preferably 20 nm or less, 50 nm or less, or 100 nm or less. Note that the above-mentioned lower limit and upper limit values ​​can be combined with each other.

[0537] The insulator 580 is provided on the insulator 544, and openings are formed in the regions where the insulator 550 and the conductor 560 are to be provided. The top surface of the insulator 580 may be planarized.

[0538] The insulator 580, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. The insulator 580 is preferably formed using, for example, the same material as the insulator 516. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form a region containing oxygen that is released by heating.

[0539] The insulator 580 preferably has a low concentration of impurities such as water and hydrogen. For example, the insulator 580 may be formed using an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0540] The insulator 574 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580 and preferably has a function of capturing impurities such as hydrogen. The insulator 574 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 574 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 574 contains at least oxygen and aluminum. By providing the insulator 574, which is in contact with the insulator 580 and has a function of capturing impurities such as hydrogen, in the region between the insulators 512 and 581, the insulator 574 can capture impurities such as hydrogen contained in the insulator 580 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure as the insulator 574 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 500 and semiconductor device with excellent characteristics.

[0541] The insulator 576 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580. The insulator 576 is disposed over the insulator 574. The insulator 576 is preferably a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 576 may be formed using silicon nitride deposited by a sputtering method. A high-density silicon nitride film can be formed by depositing the insulator 576 by a sputtering method. Alternatively, the insulator 576 may be formed by stacking a silicon nitride film deposited by a PEALD method or a CVD method on the silicon nitride film deposited by a sputtering method.

[0542] One of the first and second terminals of the transistor 500 is electrically connected to a conductor 540a functioning as a plug, and the other of the first and second terminals of the transistor 500 is electrically connected to a conductor 540b. Note that in this specification and the like, the conductors 540a and 540b are collectively referred to as conductors 540.

[0543] For example, the conductor 540a is provided in a region overlapping with the conductor 542a. Specifically, in the region overlapping with the conductor 542a, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in FIG. 20A and insulators 582 and 586 shown in FIG. 19, and the conductor 540a is provided inside the openings. For example, the conductor 540b is provided in a region overlapping with the conductor 542b. Specifically, in the region overlapping with the conductor 542b, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in Fig. 20A and insulators 582 and 586 shown in Fig. 19, and the conductor 540b is provided inside the openings. Note that the insulators 582 and 586 will be described later.

[0544] 20A, an insulator 541a may be provided as an insulator having a barrier property against impurities between the conductor 540a and a side surface of the opening in a region overlapping with the conductor 542a. Similarly, an insulator 541b may be provided as an insulator having a barrier property against impurities between the conductor 540b and a side surface of the opening in a region overlapping with the conductor 542b. Note that in this specification and the like, the insulators 541a and 541b are collectively referred to as the insulator 541.

[0545] The conductors 540a and 540b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 540a and 540b may have a layered structure.

[0546] Furthermore, when the conductor 540 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the insulators 574, 576, 581, 580, 544, and the first conductor disposed near the insulator 571. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 576 from being mixed into the oxide 530 through the conductors 540a and 540b.

[0547] The insulators 541a and 541b may be a barrier insulating film that can be used for the insulator 544, etc. For example, the insulators 541a and 541b may be made of an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 541a and 541b are provided in contact with the insulators 574, 576, and 571, and thus can prevent impurities such as water and hydrogen contained in the insulator 580 from entering the oxide 530 through the conductors 540a and 540b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b.

[0548] When the insulators 541a and 541b are formed into a layered structure as shown in FIG. 20A, it is preferable that the first insulator in contact with the inner wall of the opening, such as the insulator 580, and the second insulator inside it be formed by combining a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0549] For example, aluminum oxide formed by the ALD method can be used as the first insulator, and silicon nitride formed by the PEALD method can be used as the second insulator. With this structure, oxidation of the conductor 540 can be suppressed and hydrogen contamination of the conductor 540 can be reduced.

[0550] Although the transistor 500 has a stacked structure including a first insulator of the insulator 541 and a second conductor of the insulator 541, the present invention is not limited to this. For example, the insulator 541 may have a single layer or a stacked structure of three or more layers. Furthermore, the transistor 500 has a stacked structure including a first conductor of the conductor 540 and a second conductor of the conductor 540, but the present invention is not limited to this. For example, the conductor 540 may have a single layer or a stacked structure of three or more layers.

[0551] 19, conductors 610 and 612, which function as wiring and are in contact with the upper portions of conductors 540a and 540b, may be disposed. Conductor 610 and conductor 612 are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors may also have a layered structure. Specifically, for example, the conductors may be a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductors may be formed so as to be embedded in openings provided in an insulator.

[0552] Note that the structure of the transistor included in the semiconductor device of one embodiment of the present invention is not limited to the transistor 500 illustrated in Figures 19, 20A, 20B, and 21. The structure of the transistor included in the semiconductor device of one embodiment of the present invention may be changed depending on the situation.

[0553] For example, the transistor 500 illustrated in FIGS. 19, 20A, 20B, and 21 may have the structure illustrated in FIG. 23. The transistor in FIG. 23 differs from the transistor 500 illustrated in FIGS. 19, 20A, 20B, and 21 in that it includes an oxide 543a and an oxide 543b. Note that in this specification and the like, the oxide 543a and the oxide 543b are collectively referred to as the oxide 543. The cross-sectional structure of the transistor in FIG. 23 in the channel width direction can be similar to that of the cross-section of the transistor 500 illustrated in FIG. 20B.

[0554] The oxide 543a is provided between the oxide 530b and the conductor 542a, and the oxide 543b is provided between the oxide 530b and the conductor 542b. Here, the oxide 543a is preferably in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542a. The oxide 543b is preferably in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542b.

[0555] The oxide 543 preferably has a function of suppressing oxygen permeation. Placing the oxide 543, which has a function of suppressing oxygen permeation, between the conductor 542 functioning as a source or drain electrode and the oxide 530b is preferable because the electrical resistance between the conductor 542 and the oxide 530b can be reduced. Such a structure can improve the electrical characteristics, field-effect mobility, and reliability of the transistor 500 in some cases.

[0556] Alternatively, a metal oxide containing element M may be used as oxide 543. In particular, element M may be aluminum, gallium, yttrium, or tin. Preferably, oxide 543 has a higher concentr...

Claims

1. A semiconductor device comprising first to seventh transistors, a first FTJ element and a second FTJ element, and a capacitance element, one of the source and the drain of the first transistor is always electrically connected to a first wiring; the other of the source and the drain of the first transistor is always electrically connected to the gate of the fourth transistor; a gate of the first transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the second transistor is always electrically connected to a second wiring; the other of the source and the drain of the second transistor is always electrically connected to the gate of the third transistor and is always electrically connected to the first electrode of the capacitance element; one of the source and the drain of the third transistor is always electrically connected to the gate of the fourth transistor; the other of the source and the drain of the third transistor is always electrically connected to a third wiring; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the third transistor and is always electrically connected to the first electrode of the capacitance element; the other of the source and the drain of the fourth transistor is always electrically connected to the third wiring; one of the source and the drain of the fifth transistor is always electrically connected to one of the source and the drain of the sixth transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a fourth wiring; a gate of the fifth transistor is always electrically connected to a second electrode of the capacitance element; the other of the source and the drain of the sixth transistor is always electrically connected to a fifth wiring; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor and is always electrically connected to the second electrode of the capacitance element; an input terminal of the first FTJ element is always electrically connected to an input terminal of the second FTJ element; an output terminal of the first FTJ element is always electrically connected to the gate of the fourth transistor; an output terminal of the second FTJ element is always electrically connected to the gate of the third transistor and is always electrically connected to the first electrode of the capacitive element; Semiconductor device.

2. A semiconductor device comprising the semiconductor device according to claim 1 and a housing. electronic equipment.

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