Semiconductor Devices

Abstract

The present invention provides a semiconductor device which has a novel configuration. A semiconductor device which is provided with a plurality of memory cells each comprising a transistor and a capacitor element, wherein capacitor elements contained in memory cells that are adjacent to each other are arranged so as to overlap with each other. A first capacitor element contained in a first memory cell is arranged such that a part of the first capacitor element overlaps with a second memory cell that is adjacent to the first memory cell. A second capacitor element contained in the second memory cell is provided on a layer that is different from the first capacitor element. The second capacitor element is arranged such that a part of the second capacitor element overlaps with the first memory cell. The first capacitor element and the second capacitor element have regions that overlaps with each other. The first and second capacitor elements comprise a ferroelectric body. It is preferable that the ferroelectric body contains hafnium, zirconium or at least one element that is selected from among group III to V elements. It is also preferable that the transistor contains an oxide semiconductor in a semiconductor layer in which a channel is formed.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and testing methods thereof. [Background technology]

[0003] In recent years, the development of semiconductor devices such as LSIs, CPUs, and memories (storage devices) has progressed. These semiconductor devices are used in a variety of electronic devices, including computers and personal digital assistants. Furthermore, various types of memory have been developed to suit various applications, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory types include DRAM, SRAM, and flash memory.

[0004] Furthermore, as shown in Non-Patent Document 1, research and development of memories using ferroelectrics is being actively carried out. For the next generation of ferroelectric memories, research is being conducted on ferroelectric HfO2-based materials (Non-Patent Document 2), research on the ferroelectricity of hafnium oxide thin films (Non-Patent Document 3), research on the ferroelectricity of HfO2 thin films (Non-Patent Document 4), and research on the ferroelectric Hf 0.5 Zr 0.5 Research related to hafnium oxide is also being actively conducted, including the demonstration of the integration of FeRAM and CMOS using O2 (Non-Patent Document 5). [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] TSBoescke,et al,“Ferroelectricity in hafnium oxide thin films”,APL99,2011 [Non-patent document 2] Zhen Fan,et al,“Ferroelectric HfO▲2▼-based materials for next-generation ferroelectric memories”,JOURNAL OF ADVANCED DIELECTRICS,Vol.6,No.2,2016 [Non-patent document 3] Jun Okuno,et al,“SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf▲0.5▼Zr▲0.5▼O▲2▼”,VLSI 2020 [Non-patent document 4] Akira Toriumi, "Ferroelectricity of HfO2 Thin Films," The Japan Society of Applied Physics, Vol. 88, No. 9, 2019 [Non-patent document 5] T.Francois,et al,“Demonstration of BEOL-compatible ferroelectric Hf▲0.5▼Zr▲0.5▼O▲2▼ scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications”,IEDM 2019 Summary of the Invention [Problem to be solved by the invention]

[0006] In ferroelectric memory, data is written and read using the reversal of polarization in a ferroelectric material (a material that can have ferroelectric properties). To accurately retain the written data, it is necessary to increase the remanent polarization of the ferroelectric material.

[0007] Furthermore, in a ferroelectric memory equipped with a capacitive element using a ferroelectric substance (also called a "ferroelectric capacitor"), the reliability of data retention can be improved as the capacitance value of the capacitive element increases. Increasing the capacitance value can be achieved by thinning the dielectric and / or increasing the area of ​​the capacitive element. However, the former method is difficult to achieve because it reduces remanent polarization. Furthermore, the latter method is in a trade-off relationship with the reduction in the occupied area that accompanies increasing the density of memory elements ("memory cells").

[0008] An object of one embodiment of the present invention is to provide a novel memory device. Another object of one embodiment of the present invention is to provide a memory device with a small occupation area. Another object of one embodiment of the present invention is to provide a highly reliable memory device. Another object of one embodiment of the present invention is to provide a memory device with low power consumption. Another object of one embodiment of the present invention is to provide a memory device with a large storage capacity. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with a small occupation area. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device with a large storage capacity.

[0009] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0010] (1) One aspect of the present invention is a semiconductor device having first and second transistors and first and second capacitive elements, wherein the first transistor is electrically connected to the first capacitive element, the second transistor is electrically connected to the second capacitive element, the first and second capacitive elements are provided above the first and second transistors, the first and second capacitive elements each have a ferroelectric, and the first and second capacitive elements have an overlapping region.

[0011] (2) Another embodiment of the present invention is a semiconductor device including first and second transistors, first and second capacitance elements, and first to third wirings, wherein a gate of the first transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to the second wiring, one of a source or a drain of the first transistor is electrically connected to the first capacitance element, one of a source or a drain of the second transistor is electrically connected to the second capacitance element, and the other of the source or the drain of each of the first and second transistors is electrically connected to a third wiring, and the first and second capacitance elements each have a ferroelectric, and the first and second capacitance elements have an overlapping region.

[0012] In the above (1) or (2), the first and second transistors may be provided on the same layer.

[0013] (3) Another embodiment of the present invention is a semiconductor device including first to fourth transistors and first to fourth capacitors, in which the first transistor is electrically connected to the first capacitor, the second transistor is electrically connected to the second capacitor, the third transistor is electrically connected to the third capacitor, and the fourth transistor is electrically connected to the fourth capacitor, the first to fourth capacitors are provided above the first to fourth transistors, the first to fourth capacitors each have a ferroelectric, the third capacitor and the fourth capacitor are provided on the same layer, and the first to third capacitors have overlapping regions.

[0014] (4) Another embodiment of the present invention is a semiconductor device including first to fourth transistors, first to fourth capacitors, and first to fourth wirings, wherein a gate of each of the first and third transistors is electrically connected to a first wiring, a gate of each of the second and fourth transistors is electrically connected to a second wiring, one of a source or a drain of the first transistor is electrically connected to the first capacitor, one of a source or a drain of the second transistor is electrically connected to the second capacitor, one of a source or a drain of the third transistor is electrically connected to the third capacitor, one of a source or a drain of the fourth transistor is electrically connected to the fourth capacitor, the other of the source or the drain of each of the first and second transistors is electrically connected to a third wiring, and the other of the source or the drain of each of the third and fourth transistors is electrically connected to the second wiring, the third capacitor and the fourth capacitor are provided on the same layer, and the first to third capacitors have overlapping regions.

[0015] (5) Another embodiment of the present invention is a semiconductor device including first to fourth transistors and first to fourth capacitors, in which the first transistor is electrically connected to the first capacitor, the second transistor is electrically connected to the second capacitor, the third transistor is electrically connected to the third capacitor, and the fourth transistor is electrically connected to the fourth capacitor, the first to fourth capacitors are provided above the first to fourth transistors, the first to fourth capacitors each include a ferroelectric, and the first to fourth capacitors have regions that overlap with each other.

[0016] (6) Another embodiment of the present invention is a semiconductor device including first to fourth transistors, first to fourth capacitors, and first to fourth wirings, wherein a gate of each of the first and third transistors is electrically connected to a first wiring, a gate of each of the second and fourth transistors is electrically connected to a second wiring, one of a source or a drain of the first transistor is electrically connected to the first capacitor, one of a source or a drain of the second transistor is electrically connected to the second capacitor, one of a source or a drain of the third transistor is electrically connected to the third capacitor, one of a source or a drain of the fourth transistor is electrically connected to the fourth capacitor, the other of the source or the drain of each of the first and second transistors is electrically connected to a third wiring, and the other of the source or the drain of each of the third and fourth transistors is electrically connected to the second wiring, and the first to fourth capacitors each have a ferroelectric, and the first to fourth capacitors have overlapping regions.

[0017] In any one of the above (3) to (6), the first to fourth transistors may be provided on the same layer.

[0018] In any one of the above (3) to (6), the first to fourth transistors preferably include an oxide semiconductor in a semiconductor layer in which a channel is formed. The oxide semiconductor preferably includes at least one of indium and zinc. The ferroelectric may be a material including at least one of hafnium and zirconium, or may be a material including at least one element selected from the III-V group elements. [Effects of the Invention]

[0019] According to one embodiment of the present invention, a novel memory device can be provided. According to one embodiment of the present invention, a memory device with a small occupation area can be provided. According to one embodiment of the present invention, a highly reliable memory device can be provided. According to one embodiment of the present invention, a memory device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with a large storage capacity can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with a small occupation area can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with a large storage capacity can be provided.

[0020] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0021] 1A and 1B are diagrams illustrating an example of the configuration of a semiconductor device. Fig. 2A is a diagram showing an example of a circuit configuration of two adjacent memory cells. Fig. 2B is a perspective view showing an example of a configuration of two adjacent memory cells. Fig. 2C is a top view of two adjacent memory cells. Fig. 2D is a front view of two adjacent memory cells. 3A to 3C are top views illustrating one embodiment of the present invention. Fig. 4A is a perspective view showing an example of the configuration of two adjacent memory cells, Fig. 4B is a front view of the two adjacent memory cells, and Fig. 4C is a diagram showing an example of the circuit configuration of the two adjacent memory cells. 5A to 5E are top views illustrating one embodiment of the present invention. Fig. 6A is a perspective view showing an example of the configuration of two adjacent memory cells, Fig. 6B is a front view of the two adjacent memory cells, and Fig. 6C is a diagram showing an example of the circuit configuration of the two adjacent memory cells. 7A to 7F are top views illustrating one embodiment of the present invention. FIG. 8 is a diagram illustrating an example of a hysteresis characteristic. 9A is a top view illustrating an example of the structure of a transistor, and FIGS. 9B to 9D are cross-sectional views illustrating an example of the structure of a transistor. 10A and 10B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. Figure 11A is a diagram explaining the classification of crystal structures, Figure 11B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 11C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. FIG. 12 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 13 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 14 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 15A is a perspective view showing an example of a semiconductor wafer, FIG. 15B is a perspective view showing an example of a chip, and FIGS. 15C and 15D are perspective views showing an example of an electronic component. 16A to 16J are perspective views or schematic diagrams illustrating an example of an electronic device. 17A to 17E are perspective views or schematic diagrams illustrating an example of an electronic device. 18A to 18C are diagrams illustrating an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0022] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, or an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices.

[0023] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0024] As an example of the case where X and Y are electrically connected, one or more elements (e.g., switches, transistors, capacitance elements, inductors, resistance elements, diodes, display devices, light-emitting devices, loads, etc.) that enable the electrical connection between X and Y can be connected between X and Y.

[0025] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0026] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0027] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0028] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "electrically connected" also includes such cases where one conductive film has the functions of multiple components.

[0029] Furthermore, in this specification and the like, the term "resistance element" can refer to, for example, a circuit element, wiring, or the like having a resistance value higher than 0 Ω. Therefore, in this specification and the like, the term "resistance element" includes wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, the resistance value can be, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0030] When a wiring is used as a resistor, the resistance value may be determined by the length of the wiring, or a conductor having a different resistivity from that of the wiring may be used as the resistor, or the resistance value may be determined by doping impurities into a semiconductor.

[0031] Furthermore, in this specification, the term "capacitive element" can refer to, for example, a circuit element having a capacitance value greater than 0 F, a region of wiring having a capacitance value greater than 0 F, parasitic capacitance, or the gate capacitance of a transistor. Therefore, in this specification, the term "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric between the electrodes, but also parasitic capacitance occurring between wiring and one of the source or drain of a transistor and the gate, and the like. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0032] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are the input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the transistor's conductivity type (n-channel or p-channel) and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain are interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the transistor structure, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as the first gate, and the other of the gate or backgate of the transistor may be referred to as the second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0033] Furthermore, in this specification and the like, the term "node" can be rephrased as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration, device structure, etc. Furthermore, the term "node" can be rephrased as a terminal, wiring, etc.

[0034] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0035] Furthermore, in this specification and the like, the terms "high-level potential (also referred to as "high-level potential," "H potential," or "H")" and "low-level potential (also referred to as "low-level potential," "L potential," or "L")" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply high-level potentials," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply low-level potentials," the low-level potentials provided by both wirings do not have to be equal to each other.

[0036] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0037] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment, in the claims, etc. Furthermore, for example, a component referred to as "first" in one embodiment of this specification, etc. may be omitted in another embodiment, in the claims, etc.

[0038] Furthermore, in this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "an insulator located on the upper surface of a conductor" can be rephrased as "an insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0039] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0040] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0041] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0042] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0043] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

[0044] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Examples include electrical switches and mechanical switches. In other words, the switch is not limited to a specific type as long as it can control a current.

[0045] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0046] An example of a mechanical switch is a switch that uses MEMS (Micro Electro Mechanical Systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls conduction and non-conduction.

[0047] As used herein, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. This therefore includes cases in which the angle is -5° or more and 5° or less. "Substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This therefore includes cases in which the angle is 85° or more and 95° or less. "Substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0048] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, the term "OS transistor" can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0049] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0050] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0051] The embodiments described in this specification will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, top views, etc.

[0052] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size or aspect ratio is not necessarily limited. Note that the drawings are schematic illustrations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations may be included.

[0053] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, the symbol may be suffixed with an identifying character such as "A", "a", "_1", "[i]", "[m,n]", etc. For example, if there are two wirings A, one may be written as wiring A[1] and the other as wiring A[2].

[0054] (Embodiment 1) First, a configuration example of a semiconductor device 100 including a memory cell 10 (also called a "storage element") will be described.

[0055] 1A is a block diagram illustrating a configuration example of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 illustrated in FIG. 1A includes a driver circuit 21 and a memory array 20. The memory array 20 includes a plurality of memory cells 10. FIG. 1A illustrates an example in which the memory array 20 includes a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers equal to or greater than 2).

[0056] The rows and columns extend in directions perpendicular to each other. In this embodiment, the X direction (direction along the X axis) is referred to as a "row" and the Y direction (direction along the Y axis) is referred to as a "column," but the X direction may be referred to as a "column" and the Y direction as a "row."

[0057] In FIG. 1A, the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1], and the memory cell 10 in the mth row and nth column is indicated as memory cell 10[m,n]. In the present embodiment and the like, an arbitrary row may be indicated as row i. An arbitrary column may be indicated as column j. Therefore, i is an integer between 1 and m, and j is an integer between 1 and n. In the present embodiment and the like, the memory cell 10 in the ith row and jth column is indicated as memory cell 10[i,j]. In the present embodiment and the like, when "i+α" (α is a positive or negative integer) is indicated, "i+α" is not less than 1 or more than m. Similarly, when "j+α" is indicated, "j+α" is not less than 1 or more than n.

[0058] The memory array 20 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment and the like, the first wiring WL (first row) is referred to as wiring WL[1], and the mth wiring WL (mth row) is referred to as wiring WL[m]. Similarly, the first wiring PL (first row) is referred to as wiring PL[1], and the mth wiring PL (mth row) is referred to as wiring PL[m]. Similarly, the first wiring BL (first column) is referred to as wiring BL[1], and the nth wiring BL (nth column) is referred to as wiring BL[n].

[0059] The memory cells 10 arranged in the i-th row are electrically connected to the wiring WL (wiring WL[i]) in the i-th row and the wiring PL (wiring PL[i]) in the i-th row. The memory cells 10 arranged in the j-th column are electrically connected to the wiring BL (wiring BL[j]) in the j-th column.

[0060] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0061] In the semiconductor device 100, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0062] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by control circuit 32.

[0063] The control circuit 32 is a logic circuit having a function of controlling the overall operation of the semiconductor device 100. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 100. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0064] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0065] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0066] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 10, the function of reading data from the memory cell 10, the function of retaining the read data, etc.

[0067] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the semiconductor device 100. The data output from the output circuit 48 is a signal RDA.

[0068] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. In this example, the high power supply voltage of the semiconductor device 100 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of PSW22 is controlled by a signal PON1, and the on / off of PSW23 is controlled by a signal PON2. In FIG. 1A, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0069] The driving circuit 21 and the memory array 20 may be provided on the same plane. Alternatively, as shown in FIG. 1B, the driving circuit 21 and the memory array 20 may be provided overlapping each other. By providing the driving circuit 21 and the memory array 20 overlapping each other, the signal propagation distance can be shortened. Furthermore, the semiconductor device 100 can be made smaller.

[0070] <Memory cell configuration example 1> Next, a description will be given of an example of the configuration of the memory cell 10. Fig. 2 shows an example of the configuration of two adjacent memory cells 10 (memory cell 10a and memory cell 10b). Fig. 2A is a diagram showing an example of the circuit configuration of the two adjacent memory cells 10.

[0071] The memory cell 10a includes a transistor 120a and a capacitor 130a. The memory cell 10b includes a transistor 120b and a capacitor 130b. One of the source or drain of the transistor 120a is electrically connected to a wiring BL1, and the other is electrically connected to one electrode of the capacitor 130a. The gate of the transistor 120a is electrically connected to a wiring WL1, and the other electrode of the capacitor 130a is electrically connected to a wiring PL1. One of the source or drain of the transistor 120b is electrically connected to a wiring BL1, and the other is electrically connected to one electrode of the capacitor 130b. The gate of the transistor 120b is electrically connected to a wiring WL2, and the other electrode of the capacitor 130b is electrically connected to a wiring PL2.

[0072] For example, when memory cell 10a is memory cell 10[i,j], memory cell 10b can be expressed as memory cell 10[i+1,j]. When wiring WL1 is wiring WL[i], wiring WL2 can be expressed as wiring WL[i+1]. Furthermore, wiring BL1 can be expressed as wiring BL[j].

[0073] Furthermore, when the wiring PL1 is the wiring PL[i], the wiring PL2 can be expressed as the wiring PL[i+1]. It is preferable that a fixed potential is supplied to the wiring PL. Furthermore, in the present embodiment and the like, the wiring PL extends along the X-axis, but this is not limiting. For example, the wiring PL may extend along the Y-axis. The wiring PL1 and the wiring PL2 may be electrically connected.

[0074] A material that can have ferroelectricity is used for the dielectric that constitutes the capacitive element 130 (capacitive element 130a, capacitive element 130b, etc.), and the capacitive element 130 functions as a ferroelectric capacitor.

[0075] As a material that can have ferroelectricity, for example, hafnium oxide is preferable. Alternatively, as a material that can have ferroelectricity, zirconium oxide, HfZrO X(X is a real number greater than 0. Hereinafter, simply referred to as HfZrOx) can be used. Alternatively, as a material that can have ferroelectricity, a material in which element J1 (here, element J1 is one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to hafnium oxide can be used. Here, the atomic ratio of hafnium atoms to element J1 can be set appropriately, for example, to 1:1 or approximately 1:1. Alternatively, as a material that can have ferroelectricity, a material in which element J2 (here, element J2 is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to zirconium oxide can be used. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1:1 or close to 1:1. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as lead zirconate titanate (PZT), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0076] Furthermore, materials that can have ferroelectricity include aluminum scandium nitride (Al 1-a Sc a N b(where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1; hereinafter, simply referred to as AlScN), Al-Ga-Sc nitride, Ga-Sc nitride, etc. can be used. Furthermore, as a material that can have ferroelectricity, a metal nitride having an element M1, an element M2, and nitrogen can be used. Here, the element M1 is one or more selected from aluminum (Al), gallium (Ga), indium (In), etc. Furthermore, the element M2 is one or more selected from boron (B), scandium (Sc), yttrium (Y), lanthanides (lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu)), actinides (15 elements from actinium (Ac) to lawrencium (Lr)), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), and the like. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Ferroelectric materials can be obtained by adding element M3 to the above-mentioned metal nitrides. The element M3 is one or more elements selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), and the like. The ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately. Because the above-mentioned metal nitrides contain at least a Group 13 element and nitrogen, a Group 15 element, these metal nitrides are sometimes referred to as Group III-V ferroelectrics or Group III nitride ferroelectrics.

[0077] Moreover, as a material that can have ferroelectricity, perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure can be used.

[0078] Furthermore, the material capable of exhibiting ferroelectricity can be, for example, a mixture or compound of multiple materials selected from the materials listed above. Alternatively, the material capable of exhibiting ferroelectricity can be a layered structure of multiple materials selected from the materials listed above. However, since the crystal structure or properties of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is not only referred to as a ferroelectric, but also as a material capable of exhibiting ferroelectricity or a material that imparts ferroelectricity.

[0079] As a material that can have ferroelectricity, hafnium oxide or a material containing hafnium oxide and zirconium oxide (typically HfZrOx) is suitable because it can have ferroelectricity even when processed into a thin film of several nm.

[0080] Alternatively, aluminum scandium nitride (AlScN) is suitable as a material that can have ferroelectricity because it can be formed by sputtering, and the impurity concentration in the film can be reduced or a dense film can be formed. When aluminum scandium nitride (AlScN) is used as a material that can have ferroelectricity, it is expected to form a highly reliable film.

[0081] Furthermore, the film thickness of the ferroelectric material can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). For example, the film thickness is preferably 8 nm to 12 nm. By setting the film thickness of the ferroelectric material as described above, it is possible to achieve a thin film and ferroelectricity. By forming a ferroelectric layer that can be thinned, the ferroelectric layer can be sandwiched between a pair of electrodes of a capacitive element, and the capacitive element can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device. In other words, it is easy to realize a semiconductor device with a reduced footprint. In this specification, a layer of a ferroelectric material may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0082] In addition, HfZrO is a material that can have ferroelectric properties. X When using a ferroelectric material, it is preferable to form the film using atomic layer deposition (ALD), particularly thermal ALD. Furthermore, when using thermal ALD to form a film of a material that can have ferroelectricity, it is preferable to use a material that does not contain hydrocarbons (also called hydrocarbon, HC) as a precursor. If the material that can have ferroelectricity contains either or both of hydrogen and carbon, this may inhibit the crystallization of the material that can have ferroelectricity. Therefore, as described above, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the material that can have ferroelectricity. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Furthermore, as a material that can have ferroelectricity, a material containing hafnium oxide and zirconium oxide (HfZrO x), HfCl4 and / or ZrCl4 may be used as the precursor. On the other hand, a dopant (typically silicon, carbon, etc.) for controlling the polarization state may be added to a material that may have ferroelectricity. In this case, one method for adding carbon as a dopant may be to use a formation method using a material containing hydrocarbon as the precursor.

[0083] When a film is formed using a material that can have ferroelectricity, impurities in the film, in this case at least one of hydrogen, hydrocarbon, and carbon, are thoroughly removed, thereby forming a film having high-purity intrinsic ferroelectricity. The film having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor shown in the embodiment described later have very high compatibility in manufacturing processes. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0084] Furthermore, it is preferable that the impurity concentration of the material capable of having ferroelectricity is low. In particular, it is preferable that the concentrations of hydrogen (H) and carbon (C) are low. Specifically, the hydrogen concentration of the material capable of having ferroelectricity is 5×10 20 atoms / cm 3 Less than 1×10 is preferred 20 atoms / cm 3 The carbon concentration of the material that can have ferroelectricity is preferably 5×10 or less. 19 atoms / cm 3 Less than 1×10 is preferred 19 atoms / cm 3 The following is more preferred:

[0085] In addition, HfZrO is a material that can have ferroelectric properties. X When using hafnium oxide and zirconium oxide, it is preferable to use a thermal ALD method to alternately form films of hafnium oxide and zirconium oxide in a 1:1 ratio.

[0086] Furthermore, when a film of a material that may have ferroelectricity is formed using a thermal ALD method, the oxidizing agent may be H2O or O3. However, the oxidizing agent for the thermal ALD method is not limited to these. For example, the oxidizing agent for the thermal ALD method may include one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0087] The crystal structure of the ferroelectric material is not particularly limited. For example, the crystal structure of the ferroelectric material may be one or more selected from cubic, tetragonal, orthorhombic, and monoclinic systems. An orthorhombic crystal structure is particularly preferred for ferroelectric materials because it exhibits ferroelectricity. A layer for enhancing crystallinity may be formed before forming the ferroelectric material. For example, when HfZrOx is used as the ferroelectric material, the layer for enhancing crystallinity may be a metal oxide such as hafnium oxide or zirconium oxide, or hafnium or zirconium. When AlScN is used as the ferroelectric material, the layer for enhancing crystallinity may be a metal nitride such as aluminum nitride or scandium nitride, or aluminum or scandium. The layer for enhancing crystallinity may be formed after forming the ferroelectric material. Alternatively, the material that can have ferroelectricity may have a composite structure that has an amorphous structure and a crystalline structure.

[0088] Ferroelectrics may exhibit hysteresis characteristics. Figure 8 shows an example of hysteresis characteristics. Hysteresis characteristics can be measured using a capacitance element (ferroelectric capacitor) that uses a ferroelectric layer as the dielectric layer. In Figure 8, the horizontal axis represents the voltage (electric field) applied to the ferroelectric layer. This voltage is the potential difference between one electrode and the other electrode of a capacitance element that uses a ferroelectric layer as the dielectric layer. The electric field strength can be calculated by dividing this potential difference by the thickness of the ferroelectric layer.

[0089] In Figure 8, the vertical axis represents the polarization of the ferroelectric layer. When the polarization is positive, it indicates that the positive charges in the ferroelectric layer are biased toward one electrode of the capacitance element, and the negative charges are biased toward the other electrode of the capacitance element. On the other hand, when the polarization is negative, it indicates that the negative charges in the ferroelectric layer are biased toward one electrode of the capacitance element, and the positive charges are biased toward the other electrode of the capacitance element.

[0090] In addition, the polarization shown on the vertical axis of the graph in Figure 8 may be positive when negative charges are biased toward one electrode side of the capacitance element and positive charges are biased toward the other electrode side of the capacitance element, and negative when positive charges are biased toward one electrode side of the capacitance element and negative charges are biased toward the other electrode side of the capacitance element.

[0091] 8, the hysteresis characteristics of the ferroelectric layer can be represented by curve 51 and curve 52. The voltages at the intersections of curve 51 and curve 52 are called the saturated polarization voltage VSP and the saturated polarization voltage −VSP. It can be said that VSP and −VSP have opposite polarities.

[0092] When a voltage equal to or less than -VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 51. On the other hand, when a voltage equal to or greater than VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 52. Note that VSP is sometimes called the "positive saturation polarization voltage" or "first saturation polarization voltage," and -VSP is sometimes called the "negative saturation polarization voltage" or "second saturation polarization voltage." The absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage may be the same or different.

[0093] Here, when the polarization of the ferroelectric layer changes according to curve 51, the voltage at which the polarization becomes zero is called the coercive voltage Vc. Also, when the polarization of the ferroelectric layer changes according to curve 52, the voltage at which the polarization becomes zero is called the coercive voltage -Vc. The values ​​of Vc and -Vc are between -VSP and VSP. Note that Vc may also be called the "positive coercive voltage" or "first coercive voltage," and -Vc may also be called the "negative coercive voltage" or "second coercive voltage." The absolute values ​​of the first coercive voltage and the second coercive voltage may be the same or different.

[0094] Furthermore, when no voltage is applied to the ferroelectric layer (when the voltage is 0V), the maximum value of polarization is called the "residual polarization Pr" and the minimum value is called the "residual polarization -Pr." The absolute value of the difference between the remnant polarization Pr and the remnant polarization -Pr is called the "residual polarization 2Pr." The larger the remnant polarization 2Pr, the greater the fluctuation range of the capacitance value of the ferroelectric capacitor due to polarization reversal. The larger the remnant polarization 2Pr, the more preferable it is.

[0095] The memory cell 10 includes a capacitance element 130, which is a ferroelectric capacitor, and a transistor 120, and has the function of storing information using a change in capacitance value caused by polarization reversal of the capacitance element 130. The memory cell 10 functions as a ferroelectric memory. A memory cell consisting of one transistor and one ferroelectric capacitor is also called a 1T1F type memory cell.

[0096] A semiconductor layer in which a channel of the transistor 120 (such as the transistor 120a and the transistor 120b) is formed can be formed using a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like, either singly or in combination. Examples of semiconductor materials that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

[0097] Note that the transistor 120 is preferably a transistor (also referred to as an "OS transistor") that uses an oxide semiconductor, which is a type of metal oxide, for a semiconductor layer in which a channel is formed. Since an oxide semiconductor has a band gap of 2 eV or more, the off-state current is significantly small. Therefore, the power consumption of the memory cell 10 can be reduced. Therefore, the power consumption of the semiconductor device 100 including the memory cell 10 can be reduced.

[0098] A memory cell including an OS transistor can be called an “OS memory.” The semiconductor device 100 including the memory cell can also be called an “OS memory.”

[0099] Furthermore, OS transistors operate stably even in high-temperature environments, with little fluctuation in their characteristics. For example, the off-state current hardly increases even in high-temperature environments. Specifically, the off-state current hardly increases even in temperatures above room temperature and below 200°C. Furthermore, the on-state current is unlikely to decrease even in high-temperature environments. Therefore, OS memory operates stably even in high-temperature environments, achieving high reliability.

[0100] Furthermore, an OS transistor has a high breakdown voltage between the source and drain. By using an OS transistor as the transistor 120, the voltage required for polarization inversion can be supplied to the capacitor 130 even if the channel length of the transistor 120 is reduced. This reduces the area occupied by the memory cell 10. This increases the storage capacity and / or storage density of the semiconductor device.

[0101] FIG. 2B is a perspective view showing an example of the configuration of two adjacent memory cells 10. In the drawings, arrows indicating the X direction (direction along the X axis), the Y direction (direction along the Y axis), and the Z direction (direction along the Z axis) may be used. In this specification, the "X direction" refers to the direction along the X axis, and the forward and reverse directions may not be distinguished. The same applies to the "Y direction" and the "Z direction." The X direction, the Y direction, and the Z direction intersect with each other. More specifically, the X direction, the Y direction, and the Z direction are perpendicular to each other. In this specification, one of the X direction, the Y direction, and the Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction." In FIG. 2 and other figures, the direction in which the wiring WL extends is the X direction, and the direction in which the wiring BL extends is the Y direction.

[0102] 2C is a top view of the configuration example shown in FIG. 2B. FIG. 2D is a view (front view) of the configuration example shown in FIG. 2B as viewed in the X direction. In the configuration example shown in FIG. 2, two memory cells 10 are provided in a transistor layer 151, a first capacitance layer 152, and a second capacitance layer 153. The first capacitance layer 152 is provided on the transistor layer 151, and the second capacitance layer 153 is provided on the first capacitance layer 152.

[0103] The transistor 120a and the transistor 120b are provided in a transistor layer 151. The capacitor 130b is provided in a first capacitor layer 152. The capacitor 130a is provided in a second capacitor layer 153.

[0104] Fig. 3A is a top view of the transistor layer 151 when viewed in the Z direction. Fig. 3B is a top view of the first capacitance layer 152 when viewed in the Z direction. Fig. 3C is a top view of the second capacitance layer 153 when viewed in the Z direction.

[0105] The region where the semiconductor Sem1 and the wiring WL1 overlap functions as a channel formation region of the transistor 120a. The region where the semiconductor Sem1 and the wiring WL2 overlap functions as a channel formation region of the transistor 120b. The region of the semiconductor Sem1 that does not overlap with either the wiring WL1 or the wiring WL2 functions as a source or a drain. Therefore, the wiring WL1 functions as the gate of the transistor 120a. The wiring WL2 functions as the gate of the transistor 120b.

[0106] The source or the drain of each of the transistors 120a and 120b is electrically connected to the wiring BL1 through a conductor 141. The other of the source or the drain of the transistor 120a is electrically connected to the capacitor 130a through a conductor 142a. The other of the source or the drain of the transistor 120b is electrically connected to the capacitor 130b through a conductor 142b.

[0107] The capacitor 130a is electrically connected to the wiring PL1 through a conductor 143a, and the capacitor 130b is electrically connected to the wiring PL2 through a conductor 143b.

[0108] 2B to 2D, the capacitor 130a and the capacitor 130b are provided in different layers, overlapping each other. That is, when viewed in the Z direction, the capacitor 130a and the capacitor 130b have overlapping regions. By providing the capacitor 130a and the capacitor 130b above the transistor 120a and the transistor 120b, the area of ​​the capacitor 130 can be increased without increasing the area occupied by the memory cell 10.

[0109] 2, the memory cell 10a and the memory cell 10b are adjacent to each other in the Y direction, so the capacitive elements 130a and 130b can extend in the Y direction. This allows the reliability of the memory cell 10 to be improved without reducing the integration density of the memory cell 10. This allows the reliability of the storage device including the memory cell 10 to be improved.

[0110] Furthermore, it is preferable that the remanent polarization of the capacitor 130a is equal to that of the capacitor 130b. By making the remanent polarizations equal, variations in the write and read characteristics between memory cells are reduced, which leads to reduced power consumption and improved reliability.

[0111] It is also preferable that the capacitance value of the capacitor 130a and the capacitance value of the capacitor 130b are equal. By making the capacitance values ​​equal, the characteristic variations between memory cells are reduced, and it is possible to reduce power consumption and improve reliability.

[0112] <Memory cell configuration example 2> Although the memory cell configuration example 1 shows a configuration in which the capacitor 130 is stacked in two layers, one embodiment of the present invention is not limited to this. 4 and 5 show a configuration example in which the capacitors 130 of four adjacent memory cells 10 are stacked in three layers.

[0113] 4 shows an example of the configuration of four adjacent memory cells 10 (memory cell 10a, memory cell 10b, memory cell 10c, and memory cell 10d). FIG. 4A is a perspective view showing the example of the configuration of the four adjacent memory cells 10. FIG. 4B is a view (front view) of the example of the configuration shown in FIG. 4A as seen in the X direction. FIG. 4C is a diagram showing an example of the circuit configuration of the four adjacent memory cells 10.

[0114] In FIG. 4C, the circuit configurations of the memory cell 10a and the memory cell 10b are the same as those described in FIG. 2A. The memory cell 10c includes a transistor 120c and a capacitor 130c. The memory cell 10d includes a transistor 120d and a capacitor 130d. One of the source or drain of the transistor 120c is electrically connected to a wiring BL2, and the other is electrically connected to one electrode of the capacitor 130c. The gate of the transistor 120c is electrically connected to a wiring WL1, and the other electrode of the capacitor 130c is electrically connected to a wiring PL3. One of the source or drain of the transistor 120d is electrically connected to a wiring BL2, and the other is electrically connected to one electrode of the capacitor 130d. The gate of the transistor 120d is electrically connected to a wiring WL2, and the other electrode of the capacitor 130d is electrically connected to a wiring PL4.

[0115] For example, when memory cell 10a is memory cell 10[i,j], memory cell 10b can be expressed as memory cell 10[i+1,j]. Memory cell 10c can be expressed as memory cell 10[i,j+1]. Memory cell 10d can be expressed as memory cell 10[i+1,j+1]. When wiring WL1 is wiring WL[i], wiring WL2 can be expressed as wiring WL[i+1]. When wiring BL1 is wiring BL[j], wiring BL2 can be expressed as wiring BL[j+1]. Wiring PL1, wiring PL2, wiring PL3, and wiring PL4 may be electrically connected.

[0116] 4A and 4B, the transistors 120 included in the four memory cells 10 are provided in a transistor layer 151, and the capacitive elements 130 are provided in any of a first capacitive layer 152, a second capacitive layer 153, or a third capacitive layer 154. The first capacitive layer 152 is provided on the transistor layer 151, the second capacitive layer 153 is provided on the first capacitive layer 152, and the third capacitive layer 154 is provided on the second capacitive layer 153.

[0117] More specifically, the transistor 120a, the transistor 120b, the transistor 120c, and the transistor 120d are provided in a transistor layer 151. The capacitor 130b is provided in a first capacitor layer 152. The capacitor 130a is provided in a second capacitor layer 153. The capacitors 130c and 130d are provided in a third capacitor layer 154.

[0118] 4, the capacitors 130a to 130d are provided over an insulator (insulating layer). The capacitors 130c and 130d are provided over the same insulating layer, and the capacitors 130a and 130b are provided over different insulating layers.

[0119] Fig. 5A is a top view of the transistor layer 151 when viewed in the Z direction. Fig. 5B is a top view of the first capacitance layer 152 when viewed in the Z direction. Fig. 5C is a top view of the second capacitance layer 153 when viewed in the Z direction. Fig. 5D is a top view of the third capacitance layer 154 when viewed in the Z direction.

[0120] The region where the semiconductor Sem1 and the wiring WL1 overlap functions as a channel formation region of the transistor 120a. The region where the semiconductor Sem1 and the wiring WL2 overlap functions as a channel formation region of the transistor 120b. The region of the semiconductor Sem1 that does not overlap with either the wiring WL1 or the wiring WL2 functions as a source or a drain. Therefore, the wiring WL1 functions as the gate of the transistor 120a. The wiring WL2 functions as the gate of the transistor 120b.

[0121] The region where the semiconductor Sem2 and the wiring WL1 overlap functions as a channel formation region of the transistor 120c. The region where the semiconductor Sem2 and the wiring WL2 overlap functions as a channel formation region of the transistor 120d. The region of the semiconductor Sem2 that does not overlap with either the wiring WL1 or the wiring WL2 functions as a source or a drain. Therefore, the wiring WL1 functions as the gate of the transistor 120c. The wiring WL2 functions as the gate of the transistor 120d.

[0122] The source or the drain of each of the transistors 120a and 120b is electrically connected to the wiring BL1 through a conductor 141a. The other of the source or the drain of the transistor 120a is electrically connected to the capacitor 130a through a conductor 142a. The other of the source or the drain of the transistor 120b is electrically connected to the capacitor 130b through a conductor 142b.

[0123] The capacitor 130a is electrically connected to the wiring PL1 through a conductor 143a, and the capacitor 130b is electrically connected to the wiring PL2 through a conductor 143b.

[0124] The transistors 120c and 120d each have a source or a drain electrically connected to the wiring BL2 through a conductor 141b. The transistor 120a has a source or a drain electrically connected to the capacitor 130c through a conductor 142c. The transistor 120d has a source or a drain electrically connected to the capacitor 130d through a conductor 142d.

[0125] The capacitor 130c is electrically connected to the wiring PL3 through a conductor 143c, and the capacitor 130d is electrically connected to the wiring PL4 through a conductor 143d.

[0126] 4 and 5, the area of ​​the capacitive element can be increased by stacking the capacitive elements of memory cell 10a, memory cell 10b, memory cell 10c, and memory cell 10d. In memory cell configuration example 1, the capacitive element 130 can be expanded in the Y direction, but in the configuration disclosed in memory cell configuration example 2, the capacitive element 130 can be expanded not only in the Y direction but also in the X direction. Therefore, in the configuration disclosed in memory cell configuration example 2, the area of ​​the capacitive element 130 can be further increased compared to the configuration disclosed in memory cell configuration example 1.

[0127] In addition, in the memory cell configuration example 2, four capacitive elements 130 are provided in the first to third capacitive layers. Therefore, of the four capacitive elements 130, two capacitive elements 130 (capacitive element 130c and capacitive element 130d) are provided in the same capacitive layer.

[0128] Therefore, in memory cell configuration example 2, when viewed in the Z direction, three of the four capacitive elements 130 have regions where they overlap one another. FIG. 5E shows the four capacitive elements 130 viewed in the Z direction from the third capacitive layer 154 side. In region 901, capacitive elements 130a, 130b, and 130c partially overlap. In region 902, capacitive elements 130a, 130b, and 130d partially overlap.

[0129] The configuration disclosed in Configuration Example 2 of the memory cell can increase the area of ​​the capacitor 130 compared to the configuration disclosed in Configuration Example 1 of the memory cell, thereby further improving the reliability of the storage device.

[0130] <Memory cell configuration example 3> 6 and 7 show a configuration example in which four layers of capacitance elements 130 of four adjacent memory cells 10 are stacked. To avoid repetition of explanation, differences from the configuration example described above will be mainly described.

[0131] 6 shows an example of the configuration of four adjacent memory cells 10 (memory cell 10a, memory cell 10b, memory cell 10c, and memory cell 10d). FIG. 6A is a perspective view showing the example of the configuration of the four adjacent memory cells 10. FIG. 6B is a view (front view) of the example of the configuration shown in FIG. 6A as seen in the X direction. FIG. 6C is a diagram showing an example of the circuit configuration of the four adjacent memory cells 10.

[0132] The circuit configuration example shown in Figure 6C is generally the same as the circuit configuration example shown in Figure 4C, but differs in that the other electrode of the capacitance element 130c is electrically connected to the wiring PL1 and the other electrode of the capacitance element 130d is electrically connected to the wiring PL2.

[0133] 6A and 6B, the transistors 120 included in the four memory cells 10 are provided in a transistor layer 151, and the capacitive elements 130 are provided in any of a first capacitive layer 152, a second capacitive layer 153, a third capacitive layer 154, or a fourth capacitive layer 155. The first capacitive layer 152 is provided on the transistor layer 151, the second capacitive layer 153 is provided on the first capacitive layer 152, the third capacitive layer 154 is provided on the second capacitive layer 153, and the fourth capacitive layer 155 is provided on the third capacitive layer 154.

[0134] More specifically, the transistor 120a, the transistor 120b, the transistor 120c, and the transistor 120d are provided in a transistor layer 151. The capacitor 130b is provided in a first capacitor layer 152. The capacitor 130a is provided in a second capacitor layer 153. The capacitor 130d is provided in a third capacitor layer 154. The capacitor 130c is provided in a fourth capacitor layer 155.

[0135] Although not shown in FIG. 6, the capacitors 130a to 130d are provided over different insulators (insulating layers).

[0136] 7A is a top view of the transistor layer 151 when viewed in the Z direction. FIG. 7B is a top view of the first capacitance layer 152 when viewed in the Z direction. FIG. 7C is a top view of the second capacitance layer 153 when viewed in the Z direction. FIG. 7D is a top view of the third capacitance layer 154 when viewed in the Z direction. FIG. 7E is a top view of the fourth capacitance layer 155 when viewed in the Z direction.

[0137] The connection configuration of the transistor 120, the capacitor 130, the conductor 142, and the conductor 143 is generally the same as that shown in Configuration Example 2, but differs in that the wiring PL3 and the wiring PL4 are absent and the arrangement of the conductors 143a and 143b when viewed from the Z direction is different. Also, since the wiring PL3 and the wiring PL4 are absent, the capacitor 130c is electrically connected to the wiring PL1 via the conductor 143c. The capacitor 130d is electrically connected to the wiring PL2 via the conductor 143d. The wiring PL1 and the wiring PL2 are provided above the capacitor 130c.

[0138] 6 and 7, the area of ​​the capacitive element can be increased by stacking the capacitive elements of the memory cell 10a, the memory cell 10b, the memory cell 10c, and the memory cell 10d. In the memory cell configuration example 3, the number of wirings can be reduced compared to the configuration disclosed in the memory cell configuration example 2. Furthermore, in the memory cell configuration example 3, the capacitive element 130 can be further extended in the Y direction compared to the configuration disclosed in the memory cell configuration example 2. Therefore, in the configuration disclosed in the memory cell configuration example 3, the area of ​​the capacitive element 130 can be increased compared to the configuration disclosed in the memory cell configuration example 2.

[0139] In addition, in memory cell configuration example 3, the four capacitive elements 130 have regions where they overlap each other when viewed in the Z direction. Fig. 7F shows the four capacitive elements 130 as viewed in the Z direction from the fourth capacitive layer 155 side. In region 911, the capacitive elements 130a, 130b, 130c, and 130d partially overlap each other.

[0140] By increasing the number of adjacent memory cells 10 and providing the respective capacitor elements 130 so that they overlap, it is possible to increase the area of ​​the capacitor element 130. This makes it possible to further improve the reliability of the memory device.

[0141] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0142] (Embodiment 2) In this embodiment, a structural example of a transistor will be described as an example of a semiconductor device.

[0143] <Configuration example of semiconductor device> FIG. 9A is a top view of a transistor 200 that can be used for the transistors 120a and 120b. FIGS. 9B to 9D are cross-sectional views of the transistor. FIG. 9B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 9A and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 9C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 9A and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 9D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 9A. Note that some elements are omitted from the top view in FIG. 9A for clarity.

[0144] The transistor 200 includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, the transistor 200 on the insulator 214, an insulator 280 on an insulator 275 provided in the transistor 200, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282, an insulator 274 on the insulator 283, and an insulator 285 on the insulators 283 and 274. The insulators 212, 214, 216, 275, 280, 282, 283, 285, and 274 function as interlayer films. Furthermore, insulator 283 contacts the side surfaces of insulators 214 , 216 , 222 , 275 , 280 , and the side surfaces and top surface of insulator 282 .

[0145] The transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) disposed so as to be embedded in the insulator 214 and / or the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, a conductor 242a on the oxide 230b, an insulator 271a on the conductor 242a, and a conductor on the oxide 230b. The oxide 230b includes a conductor 242b, an insulator 271b on the conductor 242b, an insulator 252 on the oxide 230b, an insulator 250 on the insulator 252, an insulator 254 on the insulator 250, a conductor 260 (conductor 260a and conductor 260b) located on the insulator 254 and overlapping with part of the oxide 230b, and an insulator 275 arranged on the insulator 222, the insulator 224, the oxide 230a, the oxide 230b, the conductor 242a, the conductor 242b, the insulator 271a, and the insulator 271b. 9B and 9C , insulator 252 contacts the upper surface of insulator 222, the side surface of insulator 224, the side surface of oxide 230a, the side surface and upper surface of oxide 230b, the side surface of conductor 242, the side surface of insulator 271, the side surface of insulator 275, the side surface of insulator 280, and the lower surface of insulator 250. Furthermore, the upper surface of conductor 260 is disposed so as to be at approximately the same height as the top of insulator 254, the top of insulator 250, the top of insulator 252, and the upper surface of insulator 280. Furthermore, insulator 282 contacts at least a portion of the upper surfaces of conductor 260, insulator 252, insulator 250, insulator 254, and insulator 280.

[0146] In the following, the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230. The conductor 242a and the conductor 242b may be collectively referred to as the conductor 242. The insulator 271a and the insulator 271b may be collectively referred to as the insulator 271.

[0147] Openings are provided in the insulator 280 and the insulator 275, reaching the oxide 230b. The insulator 252, the insulator 250, the insulator 254, and the conductor 260 are disposed in the openings. In addition, the conductor 260, the insulator 252, the insulator 250, and the insulator 254 are disposed between the insulator 271a and the conductor 242a and the insulator 271b and the conductor 242b in the channel length direction of the transistor 200. The insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260.

[0148] The oxide 230 preferably includes an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on the oxide 230a. By providing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b.

[0149] Note that in the transistor 200, the oxide 230 has a two-layer structure of the oxide 230a and the oxide 230b, but the present invention is not limited to this. For example, the oxide 230b may have a single layer or a stacked structure of three or more layers, or each of the oxide 230a and the oxide 230b may have a stacked structure.

[0150] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulators 252, 250, and 254 function as first gate insulators, and the insulators 222 and 224 function as second gate insulators. The gate insulators may also be referred to as a gate insulating layer or a gate insulating film. The conductor 242a functions as either a source or a drain, and the conductor 242b functions as the other. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0151] FIG. 10A shows an enlarged view of the vicinity of the channel formation region in FIG. 9B. When oxygen is supplied to the oxide 230b, a channel formation region is formed in the region between the conductor 242a and the conductor 242b. Therefore, as shown in FIG. 10A, the oxide 230b includes a region 230bc that functions as the channel formation region of the transistor 200, and regions 230ba and 230bb that are provided on either side of the region 230bc and function as source and drain regions. At least a portion of the region 230bc overlaps with the conductor 260. In other words, the region 230bc is located in the region between the conductor 242a and the conductor 242b. The region 230ba overlaps with the conductor 242a, and the region 230bb overlaps with the conductor 242b.

[0152] The region 230bc, which functions as a channel formation region, has fewer oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb, making it a high-resistivity region with a low carrier concentration. Therefore, the region 230bc can be said to be i-type (intrinsic) or substantially i-type. The region 230bc can be easily formed, for example, by microwave treatment in an oxygen-containing atmosphere. Here, microwave treatment refers to treatment using, for example, an apparatus with a power source that generates high-density plasma using microwaves. Furthermore, in this specification and elsewhere, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0153] Furthermore, the regions 230ba and 230bb, which function as source and drain regions, have many oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, which increases the carrier concentration and reduces resistance. That is, the regions 230ba and 230bb are n-type regions with a higher carrier concentration and lower resistance than the region 230bc.

[0154] Here, the carrier concentration of the region 230bc that functions as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less.17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 230bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0155] Furthermore, a region may be formed between region 230bc and region 230ba or region 230bb, whose carrier concentration is equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. That is, this region functions as a junction region between region 230bc and region 230ba or region 230bb. The junction region may have a hydrogen concentration equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. The junction region may also have oxygen vacancies equal to or lower than those of region 230ba and region 230bb, and equal to or higher than those of region 230bc.

[0156] 10A shows an example in which the regions 230ba, 230bb, and 230bc are formed in the oxide 230b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 230b but also in the oxide 230a.

[0157] Furthermore, it may be difficult to clearly detect the boundaries between regions in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in regions closer to the channel formation region.

[0158] In the transistor 200, the oxide 230 including the channel formation region (the oxide 230a and the oxide 230b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0159] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0160] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 230. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0161] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0162] In this way, by disposing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a into the oxide 230b.

[0163] Furthermore, since the oxide 230a and the oxide 230b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced. Because the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0164] The oxide 230b preferably has crystallinity, and it is particularly preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0165] CAAC-OS has a highly crystalline and dense structure, and is free of impurities and defects (e.g., oxygen vacancies (V O In particular, the CAAC-OS can be made to have a dense structure with higher crystallinity by heat-treating the formed metal oxide at a temperature (for example, 400°C or higher and 600°C or lower) at which the metal oxide does not polycrystallize. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0166] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0167] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen near the oxygen vacancies may be introduced into the oxygen vacancies (hereinafter referred to as V OH.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in an oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0168] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed to supply oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies across the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0169] Therefore, in the oxide semiconductor, the region 230bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 230ba and 230bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 230ba and 230bb.

[0170] Therefore, in a state where the conductors 242a and 242b are provided on the oxide 230b, microwave treatment is performed in an atmosphere containing oxygen to remove oxygen vacancies in the region 230bc and V OIt is preferable to reduce H.

[0171] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can also be irradiated onto the region 230bc. The V of the region 230bc can be activated by the action of the plasma, microwaves, etc. O H is split off, hydrogen H is removed from the region 230bc, and oxygen vacancy V is formed. O can be compensated with oxygen. O H→H+V O " occurs, and the hydrogen concentration in the region 230bc can be reduced. Therefore, oxygen vacancies and V O H can be reduced to lower the carrier concentration.

[0172] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 242a and 242b and do not reach the regions 230ba and 230bb. Furthermore, the effects of oxygen plasma can be reduced by the insulators 271 and 280 that are provided to cover the oxide 230b and the conductor 242. As a result, during microwave processing, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0173] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes the insulator 252 or after forming the insulating film that becomes the insulator 250. By performing microwave treatment in an oxygen-containing atmosphere through the insulator 252 or the insulator 250 in this manner, oxygen can be efficiently injected into the region 230bc. Furthermore, by arranging the insulator 252 so that it is in contact with the side surface of the conductor 242 and the surface of the region 230bc, it is possible to prevent more oxygen than necessary from being injected into the region 230bc, and to prevent oxidation of the side surface of the conductor 242. Furthermore, it is possible to prevent oxidation of the side surface of the conductor 242 during the formation of the insulating film that becomes the insulator 250.

[0174] The oxygen implanted into the region 230bc can take various forms, such as oxygen atoms, oxygen molecules, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen implanted into the region 230bc may take one or more of the above forms, and oxygen radicals are particularly preferred. This also improves the film quality of the insulators 252 and 250, thereby improving the reliability of the transistor 200.

[0175] In this way, oxygen vacancies and V are selectively formed in the oxide semiconductor region 230bc. O By removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb, which function as source and drain regions, can be suppressed, maintaining the n-type conductivity. This suppresses fluctuations in the electrical characteristics of the transistor 200 and suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0176] 9C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0177] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 230b with the insulators 252, 250, 254, and conductor 260.

[0178] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.

[0179] The oxide 230b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), a highly crystalline, and a dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 230b. This reduces the extraction of oxygen from the oxide 230b even during heat treatment, making the transistor 200 stable against high temperatures (so-called thermal budget) during the manufacturing process.

[0180] Here, the conduction band minimum changes gradually at the junction between the oxide 230a and the oxide 230b. In other words, the conduction band minimum at the junction between the oxide 230a and the oxide 230b changes continuously or can be said to be a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b.

[0181] Specifically, when the oxide 230a and the oxide 230b contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 230b is an In-M-Zn oxide, the oxide 230a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0182] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. The oxide 230b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, an atomic ratio of In:M:Zn=1:1:2 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0183] Here, the oxide 230a and the oxide 230b are preferably formed by sputtering. Oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. The oxygen content in the formed film can be increased by increasing the proportion of oxygen contained in the sputtering gas. Note that the method for forming the oxide 230a and the oxide 230b is not limited to sputtering, and CVD, MBE, PLD, ALD, etc. may also be used as appropriate.

[0184] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0185] 9C and other figures, providing an insulator 252 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 230 may result in indium being unevenly distributed in the oxide 230 at and near the interface between the oxide 230 and the insulator 252. This results in the surface area of ​​the oxide 230 having an atomic ratio similar to that of indium oxide or In-Zn oxide. The increased atomic ratio of indium near the surface of the oxide 230, particularly the oxide 230b, can improve the field-effect mobility of the transistor 200.

[0186] By configuring the oxide 230a and the oxide 230b as described above, the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, which reduces the influence of interface scattering on carrier conduction, and the transistor 200 can achieve a large on-state current and high frequency characteristics.

[0187] At least one of the insulators 212, 214, 271, 275, 282, 283, and 285 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, at least one of the insulators 212, 214, 271, 275, 282, 283, and 285 is preferably an insulating material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably an insulating material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., through which the above oxygen is less likely to permeate).

[0188] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0189] For the insulators 212, 214, 271, 275, 282, 283, and 285, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has a high hydrogen barrier property, for the insulators 212, 275, and 283. Furthermore, it is preferable to use aluminum oxide or magnesium oxide, which has a high hydrogen capture and fixation function, for the insulators 214, 271, 282, and 285. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film disposed outside the insulator 285 toward the transistor 200. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like toward the substrate through the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 280 or the like toward an upper side of the transistor 200 through the insulator 282 or the like. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 275, 282, 283, and 285, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0190] In this specification and the like, the term "oxynitride" refers to a material that contains more oxygen than nitrogen as a main component. For example, "silicon oxynitride" refers to a material that contains more oxygen than nitrogen and that contains silicon, nitrogen, and oxygen. In this specification and the like, the term "nitride oxide" refers to a material that contains more nitrogen than oxygen as a main component. For example, "aluminum nitride oxide" refers to a material that contains more nitrogen than oxygen and that contains aluminum, nitrogen, and oxygen.

[0191] Here, it is preferable to use an oxide having an amorphous structure as the insulators 212, 214, 271, 275, 282, 283, and 285. For example, AlO x (x is any number greater than 0), or MgO y It is preferable to use a metal oxide such as y (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, a highly reliable transistor 200 and a semiconductor device can be manufactured that have excellent characteristics.

[0192] Furthermore, the insulators 212, 214, 271, 275, 282, 283, and 285 preferably have an amorphous structure, but may have a polycrystalline structure in some areas. The insulators 212, 214, 271, 275, 282, 283, and 285 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0193] The insulators 212, 214, 271, 275, 282, 283, and 285 may be deposited by, for example, sputtering. Sputtering does not require the use of hydrogen-containing molecules in the deposition gas, and therefore can reduce the hydrogen concentration in the insulators 212, 214, 271, 275, 282, 283, and 285. Note that the deposition method is not limited to sputtering, and chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like may also be used as appropriate.

[0194] It may also be preferable to reduce the resistivity of the insulators 212, 275, and 283. For example, it may be preferable to reduce the resistivity of the insulators 212, 275, and 283 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulators 212, 275, and 283 may be able to reduce charge-up of the conductor 205, the conductor 242, or the conductor 260 during treatment using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulators 212, 275, and 283 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0195] Furthermore, the insulators 216, 274, 280, and 285 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like can be used as the insulators 216, 274, 280, and 285 as appropriate.

[0196] The conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. Also, a part of the conductor 205 may be embedded in the insulator 214.

[0197] The conductor 205 includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the height of the upper surface of the conductor 205b is approximately the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216.

[0198] Here, the conductor 205a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0199] By using a conductive material for the conductor 205a that has the function of reducing hydrogen diffusion, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 224 or the like. Furthermore, by using a conductive material for the conductor 205a that has the function of suppressing oxygen diffusion, it is possible to suppress oxidation of the conductor 205b and a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be formed as a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be made of titanium nitride.

[0200] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0201] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V compared to not applying a negative potential to the conductor 205.

[0202] The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of the impurities into the oxide 230.

[0203] As shown in FIG. 9A, the conductor 205 is preferably larger than the area of ​​the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as shown in FIG. 9C, the conductor 205 preferably extends to areas outside the channel width direction ends of the oxide 230a and the oxide 230b. That is, outside the side surfaces of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator. This structure allows the channel formation region of the oxide 230 to be electrically surrounded by the electric field of the conductor 260, which functions as the first gate electrode, and the electric field of the conductor 205, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0204] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0205] 9C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0206] Note that although the conductor 205 in the transistor 200 has a stacked structure of the conductor 205a and the conductor 205b, the present invention is not limited to this. For example, the conductor 205 may have a single layer structure or a stacked structure of three or more layers.

[0207] Insulator 222 and insulator 224 function as gate insulators.

[0208] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0209] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. Alternatively, an oxide containing hafnium and zirconium, such as hafnium zirconium oxide, is preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with the insulator 224 and the oxygen contained in the oxide 230.

[0210] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0211] The insulator 222 may be a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide. As transistors become smaller and more highly integrated, thinning of the gate insulator can lead to problems such as leakage current. Using a high-k material as the gate insulator can reduce the gate potential during transistor operation while maintaining the physical film thickness. Alternatively, the insulator 222 may be made of a material with a high dielectric constant, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST).

[0212] The insulator 224 in contact with the oxide 230 may be made of, for example, silicon oxide, silicon oxynitride, or the like, as appropriate.

[0213] In addition, during the manufacturing process of the transistor 200, it is preferable to perform heat treatment while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100°C or higher and 600°C or lower, more preferably 350°C or higher and 550°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0214] By subjecting the oxide 230 to oxygen addition treatment, oxygen vacancies in the oxide 230 are repaired by the supplied oxygen. In other words, O Furthermore, the reaction of the hydrogen remaining in the oxide 230 with the supplied oxygen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0215] The insulators 222 and 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 224 may be formed in an island shape by overlapping with the oxide 230a. In this case, the insulator 275 is configured to contact the side surface of the insulator 224 and the top surface of the insulator 222.

[0216] The conductor 242a and the conductor 242b are provided in contact with the top surface of the oxide 230b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0217] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when they absorb oxygen.

[0218] Note that hydrogen contained in the oxide 230b and the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b and the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b and the like may be absorbed by the conductor 242a or the conductor 242b.

[0219] Preferably, no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. By forming the conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the cross section in the channel width direction can be increased, as shown in Fig. 9D. This increases the conductivity of the conductor 242 and the on-state current of the transistor 200.

[0220] The insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b. The insulator 271 preferably functions as a barrier insulating film at least against oxygen. Therefore, the insulator 271 preferably has a function of suppressing oxygen diffusion. For example, the insulator 271 preferably has a function of suppressing oxygen diffusion more than the insulator 280. The insulator 271 may be made of, for example, aluminum oxide or magnesium oxide.

[0221] The insulator 275 is provided to cover the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, and the insulator 271. The insulator 275 preferably has the function of capturing and fixing hydrogen. In this case, the insulator 275 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, the insulator 275 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0222] By providing the insulators 271 and 275 as described above, the conductor 242 can be wrapped in an insulator that has a barrier property against oxygen. That is, it is possible to prevent the oxygen contained in the insulators 224 and 280 from diffusing into the conductor 242. This makes it possible to suppress the conductor 242 from being directly oxidized by the oxygen contained in the insulators 224 and 280, which would increase the resistivity and reduce the on-current.

[0223] The insulator 252 functions as part of the gate insulator. A barrier insulating film against oxygen is preferably used as the insulator 252. Any of the insulators that can be used for the insulator 282 described above may be used as the insulator 252. An insulator containing an oxide of one or both of aluminum and hafnium may be used as the insulator 252. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 252. In this case, the insulator 252 is an insulator containing at least oxygen and aluminum.

[0224] As shown in FIG. 9C , the insulator 252 is provided in contact with the top surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 224, and the top surface of the insulator 222. That is, the regions of the oxide 230a, the oxide 230b, and the insulator 224 that overlap with the conductor 260 are covered with the insulator 252 in the cross section in the channel width direction. This allows the insulator 252, which has oxygen barrier properties, to block oxygen from being released from the oxide 230a and the oxide 230b when heat treatment or the like is performed. This reduces the formation of oxygen vacancies (Vo) in the oxide 230a and the oxide 230b. This reduces the oxygen vacancies (Vo) and V formed in the region 230bc. O H can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved, and the reliability can be improved.

[0225] Conversely, even if the insulators 280 and 250 contain excessive amounts of oxygen, the oxygen can be prevented from being excessively supplied to the oxides 230a and 230b. Therefore, the regions 230ba and 230bb can be prevented from being excessively oxidized via the region 230bc, which can cause a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0226] 9B, the insulator 252 is provided in contact with the side surfaces of the conductor 242, the insulator 271, the insulator 275, and the insulator 280. This reduces the oxidation of the side surface of the conductor 242 and the formation of an oxide film on the side surface. This reduces the decrease in the on-state current or the field-effect mobility of the transistor 200.

[0227] Furthermore, the insulator 252, together with the insulator 254, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. To miniaturize the transistor 200, it is preferable that the insulator 252 be thin. The thickness of the insulator 252 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, the insulator 252 only needs to have a region with the above-described thickness in at least a portion thereof. Furthermore, it is preferable that the thickness of the insulator 252 is thinner than the thickness of the insulator 250. In this case, it is preferable that the insulator 252 only needs to have a region with a thickness thinner than the insulator 250 in at least a portion thereof.

[0228] To form the insulator 252 into a thin film as described above, it is preferable to use the ALD method. ALD methods include the thermal ALD method, in which the reaction between a precursor and a reactant is carried out using only thermal energy, and the plasma enhanced ALD method, in which a plasma excited reactant is used. The PEALD method may be preferable because it uses plasma, allowing film formation at a lower temperature.

[0229] The ALD method utilizes the self-regulating property of atoms to deposit atoms layer by layer, and therefore has the advantages of enabling the formation of extremely thin films, the formation of films on structures with high aspect ratios, the formation of films with few defects such as pinholes, the formation of films with excellent coverage, the formation of films at low temperatures, etc. Therefore, the insulator 252 can be formed with good coverage on the side surfaces of openings formed in the insulator 280 or the like, and with the thin film thickness as described above.

[0230] Some precursors used in ALD contain carbon and other impurities. Therefore, films formed by ALD may contain more carbon and other impurities than films formed by other film formation methods. Quantitative determination of impurities can be performed using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0231] The insulator 250 functions as part of the gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the insulator 252. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 250 is an insulator containing at least oxygen and silicon.

[0232] As with insulator 224, insulator 250 preferably has a reduced concentration of impurities such as water and hydrogen. The thickness of insulator 250 is preferably 1 nm or more and 20 nm or less, and more preferably 0.5 nm or more and 15.0 nm or less. In this case, insulator 250 only needs to have a region with the above-mentioned thickness in at least a portion thereof.

[0233] 9A to 9D, the insulator 250 is shown as a single layer, but the present invention is not limited to this and may have a laminated structure of two or more layers. For example, as shown in Fig. 10B, the insulator 250 may have a two-layer laminated structure of an insulator 250a and an insulator 250b on the insulator 250a.

[0234] As shown in FIG. 10B , when the insulator 250 has a two-layer stacked structure, the lower insulator 250a is preferably formed using an insulator that is easily permeable to oxygen, and the upper insulator 250b is preferably formed using an insulator that suppresses oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the insulator 250a into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulator 250a may be formed using a material that can be used for the insulator 250 described above, and the insulator 250b may be formed using an insulator containing one or both of aluminum and hafnium oxides. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, hafnium oxide is used as the insulator 250b. In this case, the insulator 250b contains at least oxygen and hafnium. The thickness of the insulator 250b is 0.5 nm to 5.0 nm, preferably 1.0 nm to 5.0 nm, and more preferably 1.0 nm to 3.0 nm. In this case, the insulator 250b only needs to have a region with the above-described thickness in at least a portion.

[0235] When silicon oxide or silicon oxynitride is used for the insulator 250a, the insulator 250b may be an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator as a stacked structure of the insulators 250a and 250b, a thermally stable stacked structure with a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. This allows the dielectric strength of the insulator 250 to be increased.

[0236] The insulator 254 functions as part of the gate insulator. A barrier insulating film against hydrogen is preferably used as the insulator 254. This can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the insulator 250 and the oxide 230b. The insulator 254 may be any of the insulators that can be used for the insulator 283 described above. For example, silicon nitride formed by the PEALD method may be used as the insulator 254. In this case, the insulator 254 is an insulator containing at least nitrogen and silicon.

[0237] Furthermore, the insulator 254 may also have a barrier property against oxygen, which can prevent oxygen contained in the insulator 250 from diffusing into the conductor 260.

[0238] Furthermore, the insulator 254, together with the insulator 252, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. To miniaturize the transistor 200, it is preferable that the insulator 254 be thin. The thickness of the insulator 254 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, the insulator 254 only needs to have a region with the above-described thickness in at least a portion thereof. Furthermore, it is preferable that the thickness of the insulator 254 is thinner than the thickness of the insulator 250. In this case, it is preferable that the insulator 254 only needs to have a region with a thickness thinner than the insulator 250 in at least a portion thereof.

[0239] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIGS. 9B and 9C, the top surface of the conductor 260 is generally flush with the top surface of the insulator 250. Although the conductor 260 is shown in FIGS. 9B and 9C as having a two-layer structure of the conductor 260a and the conductor 260b, it may have a single-layer structure or a stacked structure of three or more layers.

[0240] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0241] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0242] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0243] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably placed in the region between the conductor 242a and the conductor 242b without alignment.

[0244] 9C , in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b, relative to the bottom surface of the insulator 222. When the conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, the electric field of the conductor 260 can be easily applied to the entire channel formation region of the oxide 230b. This increases the on-state current of the transistor 200 and improves its frequency characteristics. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260, relative to the bottom surface of the insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0245] The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulator 250 and the conductor 260 are to be provided. The top surface of the insulator 280 may be flattened.

[0246] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce the parasitic capacitance that occurs between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is released by heating.

[0247] The insulator 280 preferably has an excess oxygen region or excess oxygen. Furthermore, the concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. For example, the insulator 280 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200. The insulator 280 containing excess oxygen can be formed by depositing the insulator 280 by a sputtering method in an oxygen-containing atmosphere. Furthermore, the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require hydrogen as a deposition gas. Furthermore, the insulator 282 in contact with the top surface of the insulator 280 may be deposited by a sputtering method in an oxygen-containing atmosphere, and oxygen may be added to the insulator 280. When oxygen is added to the insulator 280 in forming the insulator 282, the method for forming the insulator 280 is not limited to sputtering, and CVD, MBE, PLD, ALD, or the like may be used as appropriate. For example, the insulator 280 may have a layered structure of silicon oxide formed by sputtering and silicon oxynitride formed by CVD on top of it. Silicon nitride may also be further layered on top of that.

[0248] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280 and preferably has a function of capturing impurities such as hydrogen. The insulator 282 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 282 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 282 contains at least oxygen and aluminum. By providing the insulator 282 in contact with the insulator 280 in the region between the insulators 212 and 283 and having a function of capturing impurities such as hydrogen, the insulator 282 can capture impurities such as hydrogen contained in the insulator 280 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure as the insulator 282 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with excellent characteristics.

[0249] The insulator 282 is preferably formed by a sputtering method. By forming the insulator 282 by a sputtering method, oxygen can be added to the insulator 280. However, the method for forming the insulator 282 is not limited to a sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0250] The insulator 283 functions as a barrier insulating film that prevents impurities such as water and hydrogen from diffusing from above into the insulator 280. The insulator 283 is disposed on the insulator 282. It is preferable to use a nitride containing silicon, such as silicon nitride or silicon nitride oxide, as the insulator 283. For example, silicon nitride formed by a sputtering method can be used as the insulator 283. By forming the insulator 283 by a sputtering method, a high-density silicon nitride film can be formed. Alternatively, as the insulator 283, silicon nitride formed by a PEALD method or a CVD method may be stacked on silicon nitride formed by a sputtering method.

[0251] 9 also shows conductor 240 (conductor 240a and conductor 240b) connected to transistor 200. Conductor 240 is provided so as to fill an opening formed in insulators 271, 275, 280, 282, 283, and 285. The lower surface of conductor 240a contacts the upper surface of conductor 242a. The lower surface of conductor 240b contacts the upper surface of conductor 242b. Conductor 240 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Conductor 240 may also have a layered structure including a thin first conductor provided along the side and bottom surfaces of the opening and a second conductor on the first conductor.

[0252] When the conductor 240 has a layered structure, the first conductor disposed near the insulator 285 and the insulator 280 is preferably made of a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from being mixed into the oxide 230 through the conductor 240. The second conductor may be made of the above-mentioned conductive material mainly composed of tungsten, copper, or aluminum.

[0253] 9B shows a configuration in which the first conductor and the second conductor are stacked, the present invention is not limited to this. For example, the conductor 240 may be configured as a single layer or a stacked structure of three or more layers.

[0254] Furthermore, an insulator 241a functioning as a barrier insulating film is preferably provided between the conductor 240a and the insulator 280. An insulator 241b functioning as a barrier insulating film is preferably provided between the conductor 240b and the insulator 280. The insulator 241 (insulator 241a and insulator 241b) is preferably disposed in contact with the side surfaces of openings formed in the insulators 271, 275, 280, 282, 283, and 285.

[0255] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0256] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, or the like.

[0257] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0258] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0259] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0260] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0261] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0262] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0263] <<Conductors>> The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0264] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0265] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0266] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0267] <<Metal oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as the oxide 230. Metal oxides that can be used as the oxide 230 according to the present invention will be described below.

[0268] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0269] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where a combination of the aforementioned elements can be used as element M.

[0270] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0271] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 11A. Fig. 11A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0272] As shown in FIG. 11A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). The "Crystalline" classification excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0273] The structure within the bold frame in Figure 11A is an intermediate state between "amorphous" and "crystal," and is a structure that belongs to a new boundary region (new crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "amorphous" and "crystal."

[0274] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 11B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 11B may be simply referred to as the XRD spectrum in this specification. The composition of the CAAC-IGZO film shown in Figure 11B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 11B is 500 nm.

[0275] In Figure 11B, the horizontal axis is 2θ [deg.] and the vertical axis is intensity [au]. As shown in Figure 11B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 11B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0276] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 11C. Figure 11C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 11C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0277] As shown in Figure 11C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0278] <<Oxide semiconductor structure>> Note that oxide semiconductors may be classified differently from those shown in FIG. 11A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0279] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0280] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0281] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0282] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0283] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0284] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0285] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0286] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0287] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the decrease in electron mobility due to grain boundaries is unlikely to occur in CAAC-OS. Furthermore, since the crystallinity of oxide semiconductors can be reduced by impurities or defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using CAAC-OS for OS transistors enables greater flexibility in the manufacturing process.

[0288] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0289] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0290] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0291] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0292] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0293] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0294] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0295] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0296] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0297] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0298] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0299] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0300] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0301] An oxide semiconductor with a low carrier concentration is preferably used for a channel formation region of a transistor. For example, the carrier concentration of the channel formation region of an oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0302] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0303] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0304] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0305] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0306] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the silicon or carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0307] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0308] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0309] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0310] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0311] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 230. For example, it is preferable to use a semiconductor of a simple element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also called an atomic layer material or a two-dimensional material). In particular, it is preferable to use a layered material that functions as a semiconductor.

[0312] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0313] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0314] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0315] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0316] (Embodiment 3) In this embodiment, an example of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

[0317] [Example of semiconductor device configuration] A cross-sectional structure example of a semiconductor device (memory device) according to one embodiment of the present invention is shown in Fig. 12. Fig. 12 is a cross-sectional view illustrating a part of a semiconductor device 100 in which a memory cell in the memory array 20 includes a first structural example of a memory cell.

[0318] In the semiconductor device illustrated in FIG. 12, transistors 120a and 120b are provided above a transistor 300 provided in the driver circuit 21. Capacitors 130a and 130b are provided above the transistors 120a and 120b. Note that the transistor 200 described in the above embodiment can be used as the transistor 120a. For example, the transistor 120a illustrated in FIG. 12 has a structure in which the insulator 241b and the insulator 241b are removed from the transistor 200 illustrated in FIG. 9. The transistor 200 described in the above embodiment can be used as the transistor 120b. For example, the transistor 120b illustrated in FIG. 12 has a structure in which the insulator 241a and the insulator 241a are removed from the transistor 200 illustrated in FIG. 9.

[0319] 12, the transistor 120a and the transistor 120b are provided in one oxide 230. The conductor 240b electrically connected to the transistor 120a is omitted from FIG. 12. The conductor 240a electrically connected to the transistor 120b is also omitted from FIG. 12.

[0320] The insulator 228, which functions as the dielectric of the capacitive element 130a, and the insulator 234, which functions as the dielectric of the capacitive element 130b, are made of a ferroelectric material, which has the property that polarization occurs internally when an external electric field is applied, and the polarization remains even when the electric field is removed from the capacitor. This allows the capacitive element to be used to form a nonvolatile memory element. In other words, a one-transistor-one-capacitor ferroelectric memory can be formed by using a capacitive element that functions as a ferroelectric capacitor and a transistor.

[0321] The transistors 120a and 120b are OS transistors. OS transistors have the characteristic of being able to withstand high voltages. Therefore, even if the transistors 120a and 120b are miniaturized, a high voltage can be applied to the transistors 120a and 120b. By miniaturizing the transistors 120a and 120b, the area occupied by the semiconductor device can be reduced.

[0322] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel type or an n-channel type.

[0323] Here, in the transistor 300 shown in FIG. 12, a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. An insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0324] Note that the transistor 300 illustrated in FIG. 12 is just an example, and the structure is not limited to this example. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0325] <Wiring layer> Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0326] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330 electrically connected to the transistors 120a and 120b are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as contact plugs or wirings.

[0327] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0328] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 12 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a contact plug or a wiring.

[0329] An insulator 357 is provided over the insulator 354 and the conductor 356, and a conductor 359 is provided over the insulator 357. The conductor 359 corresponds to the wiring BL described in the above embodiment. A conductor 358 is embedded in the insulator 357. The conductor 358 functions as a contact plug or a wiring. The conductor 359 and the conductor 356 are electrically connected to each other through the conductor 358.

[0330] An insulator 361 is provided over the conductor 359, and the transistors 120a and 120b are provided above the insulator 361. The conductor 260 corresponds to the wiring WL described in the above embodiment. The conductor 359 is electrically connected to the oxide 230 through the conductor 141. The conductor 141 functions as a contact plug or a wiring. Similar to the conductor 240 described in the above embodiment, an insulator 241 is provided in contact with the side surface of the conductor 141 functioning as a contact plug.

[0331] Furthermore, a conductor 233 is provided over the insulator 285 and the conductor 240b. The conductor 233 is electrically connected to the transistor 120b through the conductor 240b. An insulator 234 is provided over the conductor 233, and a conductor 235 is provided over the insulator 234. A region where the conductor 233 and the conductor 235 overlap with each other with the insulator 234 interposed therebetween functions as the capacitor 130b.

[0332] It is preferable that a material having ferroelectricity be used for the insulator 234. By using a material having ferroelectricity for the insulator 234, the capacitive element 130b can function as a ferroelectric capacitor. In addition, insulators 236, 237, 238, and 239 are provided to cover the conductor 235.

[0333] A conductor 225 is provided so as to be embedded in the insulators 234, 236, 237, 238, and 239. The conductor 225 functions as a contact plug or a wiring. The conductor 225 is electrically connected to the conductor 240a. Furthermore, a conductor 226 is provided so as to be embedded in the insulators 236, 237, 238, and 239. The conductor 226 functions as a contact plug or a wiring. The conductor 226 is electrically connected to the conductor 235.

[0334] Furthermore, a conductor 227 is provided over the insulator 239 and the conductor 225. The conductor 227 is electrically connected to the transistor 120a through the conductor 225 and the conductor 240a. An insulator 228 is provided over the conductor 227, and a conductor 229 is provided over the insulator 228. A region where the conductor 229 and the conductor 227 overlap with each other with the insulator 228 interposed therebetween functions as a capacitor 130a.

[0335] It is preferable that a material having ferroelectricity be used for the insulator 228. By using a material having ferroelectricity for the insulator 228, the capacitor 130b can function as a ferroelectric capacitor. In addition, insulators 243, 244, and 247 are provided to cover the conductor 229.

[0336] A conductor 249 is provided so as to be embedded in the insulators 247, 244, 243, and 228. The conductor 249 functions as a contact plug or a wiring. The conductor 249 is electrically connected to the conductor 235 via the conductor 226. In addition, a conductor 248 is provided so as to be embedded in the insulators 247, 244, and 243. The conductor 248 functions as a contact plug or a wiring. The conductor 248 is electrically connected to the conductor 229.

[0337] Furthermore, a conductor 256 is provided on the conductor 248 and the insulator 247. The conductor 256 is electrically connected to the conductor 229 via the conductor 248. Furthermore, a conductor 257 is provided on the conductor 249 and the insulator 247. The conductor 257 is electrically connected to the conductor 235 via the conductor 249 and the conductor 226. The conductor 256 and the conductor 257 function as wirings PL.

[0338] Furthermore, insulators 258a, 258b, and 261 may be provided to cover the conductor 256 and the conductor 257. At least one of the insulator 258a and the insulator 258b is preferably an insulating film having a barrier property against hydrogen. As the insulating film having a barrier property against hydrogen, a barrier insulating film that can be used for the above-described insulator 283, etc. may be used. By providing such a barrier insulating film, it is possible to reduce the diffusion of impurities such as hydrogen contained in the insulator 261, etc., into the transistor 200 through the conductor 256, the conductor 257, etc.

[0339] The insulator 258a can be formed by a sputtering method. For example, the insulator 258a can be formed using silicon nitride by a sputtering method. The sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, so the hydrogen concentration in the insulator 258a can be reduced.

[0340] The insulator 258b is preferably formed by an ALD method, particularly a PEALD method. For example, silicon nitride formed by the PEALD method can be used as the insulator 258b. This allows the insulator 258b to be formed with good coverage. Therefore, even if pinholes or discontinuities are formed in the insulator 258a due to unevenness of the base, the diffusion of hydrogen into the transistor 200 can be reduced by covering them with the insulator 258b.

[0341] However, the method for forming the insulators 258a and 258b is not limited to sputtering and ALD, and CVD, MBE, PLD, etc. may also be used as appropriate. In addition, although the two-layer structure of the insulators 258a and 258b is shown above, the present invention is not limited to this, and a single-layer structure or a stacked structure of three or more layers may also be used.

[0342] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0343] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0344] For example, insulators 361, 352, and 354 preferably have an insulator with a low dielectric constant. For example, the insulator preferably includes fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, or resin. Alternatively, the insulator preferably has a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.

[0345] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen. Therefore, the insulators 214, 212, and 350 can be formed using insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen.

[0346] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0347] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0348] For example, conductors 328, 330, 356, conductor 141, conductor 256, and conductor 257 can be formed using conductive materials such as metals, alloys, metal nitrides, or metal oxides, either in a single layer or in a stacked layer. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferred, and tungsten is preferred. Alternatively, low-resistance conductive materials such as aluminum and copper are preferred. The use of low-resistance conductive materials can reduce wiring resistance. Furthermore, the capacitor element 130, which functions as a ferroelectric capacitor, can increase remanent polarization without high-temperature baking after formation by depositing conductors 229 and 235 using a method involving substrate heating, such as thermal ALD. Therefore, semiconductor devices can be fabricated without high-temperature baking, allowing the use of low-resistance conductive materials, such as copper, which have a low melting point.

[0349] <Capacitor element> The conductor 229 functions as an upper electrode of the capacitor 130a, the conductor 227 functions as a lower electrode of the capacitor 130a, and the insulator 228 functions as a dielectric of the capacitor 130a. The conductor 235 functions as an upper electrode of the capacitor 130b, the conductor 233 functions as a lower electrode of the capacitor 130b, and the insulator 234 functions as a dielectric of the capacitor 130b.

[0350] The materials shown in the above embodiments that can have ferroelectricity are used as the insulators 228 and 234. The insulators 228 and 234 may be stacked layers of a plurality of materials that can have ferroelectricity.

[0351] As a material capable of exhibiting ferroelectricity, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferable because it can retain ferroelectricity even when processed into a thin film of a few nanometers. Here, the film thickness of the insulator 228 and the insulator 234 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less. By using a ferroelectric layer that can be thinned, a semiconductor device can be formed in which the capacitor element 130 is combined with a miniaturized transistor 120.

[0352] In some cases, the insulators 228 and 234 may have a laminated structure of the above-mentioned material that may have ferroelectricity and a material with high dielectric strength. Materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide or resin with vacancies, etc. By using a laminate of such insulators with high dielectric strength, the dielectric strength may be improved and the leakage current of the capacitor 130 may be suppressed.

[0353] The conductors 227 and 233 functioning as the lower electrodes, and the conductors 229 and 235 functioning as the upper electrodes may be formed by ALD, CVD, sputtering, etc. For example, a titanium nitride film may be formed as the lower electrode by thermal ALD.

[0354] The conductor functioning as the upper electrode and the conductor functioning as the lower electrode may be a laminate of multiple conductors. For example, the upper electrode may be formed by depositing a titanium nitride film using the ALD method, followed by depositing a tungsten film using the sputtering method.

[0355] After the upper electrode is formed, a heat treatment may be performed at about 400° C. to 500° C. For example, after the upper electrode is formed, a heat treatment may be performed at 500° C. for 60 seconds by the RTA method.

[0356] <Wiring or plug in layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 120, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having barrier properties is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0357] For example, an insulator 241 may be provided between the insulator 280 containing excess oxygen and the conductor 240 (see Embodiment 2). When the insulator 241 is provided in contact with the insulators 282 and 283, the transistor 120 can be sealed with an insulator having a barrier property.

[0358] That is, by providing the insulator 241, excess oxygen contained in the insulator 280 is less likely to be absorbed by the conductor 240. Furthermore, by providing the insulator 241, diffusion of hydrogen, which is an impurity, to the transistor 200 through the conductor 240 can be suppressed.

[0359] The insulator 241 may be an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide may be preferably used. Silicon nitride is particularly preferred because of its high blocking properties against hydrogen. Other examples that may be used include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide.

[0360] As described in the above embodiment, the transistor 120 is preferably sealed with the insulators 212, 214, 282, and 283. Such a structure can reduce the amount of hydrogen contained in the insulators 274, 285, and the like that gets mixed into the insulator 280 and the like. In this case, the insulators 212, 214, 282, and 283 function as sealing films.

[0361] Here, the conductor 240 penetrates the insulator 283 and the insulator 282, and the conductor 141 penetrates the insulator 214 and the insulator 212. However, as described above, the insulator 241 is provided in contact with the conductor 240 and the conductor 141, respectively. This reduces hydrogen that enters the inside of the insulators 212, 214, 282, and 283 through the conductor 240 and the conductor 141. In this manner, the transistor 120 is sealed, and impurities such as hydrogen contained in the insulator 274 and the like can be reduced from entering the transistor 120. Note that while FIG. 12 shows two transistors 120 in the region sealed with the insulator 212, the insulator 283, and the like, this is not limiting, and one, three, or more transistors 120 can be provided in the sealed region.

[0362] <Dicing line> The following describes dicing lines (sometimes called scribe lines, dividing lines, or cutting lines) that are provided when dividing a large-area substrate into individual semiconductor elements to extract multiple semiconductor devices in chip form. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (divide) the multiple semiconductor devices.

[0363] Here, for example, it is preferable to design the insulator 283 so that the region where the insulator 212 contacts overlaps with the dicing line. That is, openings are provided in the insulators 282, 280, 275, 224, 222, 216, and 214 near the region that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200.

[0364] That is, the insulators 283 and 212 are in contact with each other through openings formed in the insulators 282, 280, 275, 224, 222, 216, and 214. Note that the insulators 212 and 283 may be formed using the same material and the same method. Adhesion can be improved by forming the insulators 212 and 283 using the same material and the same method. For example, silicon nitride may be used.

[0365] Furthermore, for example, openings may be provided in the insulators 282, 280, 275, 224, 222, and 216. With this configuration, the insulators 283 and 214 come into contact with each other through the openings provided in the insulators 282, 280, 275, 224, 222, and 216.

[0366] With this structure, the transistor 120 can be surrounded by the insulators 212, 214, 282, and 283. At least one of the insulators 214, 282, and 283 has a function of suppressing diffusion of oxygen, hydrogen, and water. By dividing the substrate into each circuit region in which the semiconductor element according to this embodiment is formed, impurities such as hydrogen or water can be prevented from diffusing from the divided portion to the transistor 120.

[0367] Furthermore, this structure can prevent excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which the channel of the transistor 120 is formed. The oxygen can reduce oxygen vacancies in the oxide in which the channel of the transistor 120 is formed. As a result, the oxide in which the channel of the transistor 120 is formed can be an oxide semiconductor with a low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 120 can be suppressed and reliability can be improved.

[0368] <Modification 1 of storage device> Fig. 13 shows a modification of the memory device shown in Fig. 12. In Fig. 12, the conductor 141 is provided so as to be embedded in the insulators 224, 222, 216, 214, 212, and 361, but it may also be provided so as to be embedded in the insulators 285, 283, 282, 280, 271, and 275.

[0369] 13, a conductor 292 is provided on the conductor 141 and the insulator 285, and an insulator 293 and an insulator 294 are provided on the conductor 292 and the insulator 285. In addition, a conductor 295 and a conductor 296 are provided so as to be embedded in the insulators 293 and 294.

[0370] The conductor 233 and the insulator 234 are provided above the insulator 294. The conductor 225 and the conductor 240a are electrically connected to each other through the conductor 295. The conductor 233 is electrically connected to the conductor 240b through the conductor 296. The conductor 292 is electrically connected to the conductor 359. Although the conductor 359 is provided below the transistor 120 in FIG. 13, it may be provided above the transistor 120.

[0371] <Modification 2 of Storage Device> As described in the above embodiment, the number of overlapping capacitors 130 is not limited to two. Three or more capacitors 130 may be overlapped. Fig. 14 shows a configuration example in which not only the capacitors 130a and 130b but also the capacitors 130m and 130n are overlapped.

[0372] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0373] (Fourth embodiment) In this embodiment, an example of a semiconductor wafer on which a semiconductor device or the like according to one embodiment of the present invention is formed and an example of an electronic component in which the semiconductor device is incorporated will be described.

[0374] <Semiconductor wafer> First, an example of a semiconductor wafer on which a semiconductor device or the like is formed will be described with reference to FIG. 15A.

[0375] 15A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that on the upper surface of the wafer 4801, a portion where the circuit portions 4802 are not present is a spacing 4803, which is a region for dicing.

[0376] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0377] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0378] By performing a dicing process, chips 4800a as shown in FIG. 15B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. It is preferable to make spacing 4803a as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0379] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Figure 15A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the device for manufacturing the element.

[0380] <Electronic components> 15C is a perspective view of an electronic component 4700 and a substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 15C includes a chip 4800a in a mold 4711. A semiconductor device according to one embodiment of the present invention or the like can be used as the chip 4800a.

[0381] 15C omits some parts to show the interior of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a via wires 4714. Electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on printed circuit board 4702 to complete mounted board 4704.

[0382] 15D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 provided on interposer 4731.

[0383] The semiconductor device 4710 may be, for example, a chip 4800a, the semiconductor device described in the above embodiment, or a high bandwidth memory (HBM). The semiconductor device 4735 may be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0384] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0385] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 4731, and the integrated circuits and the package substrate 4732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0386] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0387] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0388] Furthermore, in SiP or MCM using silicon interposers, a decrease in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on the interposer.

[0389] A heat sink (heat sink) may be provided overlapping the electronic component 4730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the height of the semiconductor device 4710 and the height of the semiconductor device 4735.

[0390] Electrodes 4733 may be provided on the bottom of package substrate 4732 in order to mount electronic component 4730 on another substrate. Fig. 15D shows an example in which electrodes 4733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 4733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0391] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0392] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0393] (Embodiment 5) In this embodiment, application examples of a semiconductor device according to one embodiment of the present invention will be described.

[0394] The semiconductor device according to one embodiment of the present invention can be applied to, for example, various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, and the like). It can also be used in image sensors, IoT (Internet of Things) devices, healthcare-related devices, and the like. Note that the term "computer" as used herein includes tablet computers, notebook computers, desktop computers, and large-scale computers such as server systems.

[0395] By using the semiconductor device according to one embodiment of the present invention, an electronic device with a large storage capacity per unit area can be realized.By using the semiconductor device according to one embodiment of the present invention, the electronic device can be miniaturized.

[0396] 16A to 16J and 17A to 17E illustrate examples of electronic devices including a semiconductor device according to one embodiment of the present invention. Each electronic device includes an electronic component 4700 including the semiconductor device.

[0397] [mobile phone] 16A is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As input interfaces, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0398] By applying the semiconductor device according to one embodiment of the present invention, the information terminal 5500 can hold temporary files (for example, caches when using a web browser) generated when an application is executed.

[0399] [Wearable devices] 16B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0400] Like the above-described information terminal 5500, the wearable terminal can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.

[0401] [Information terminal] 16C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0402] Like the above-described information terminal 5500, the desktop information terminal 5300 can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.

[0403] 16A to 16C are taken as examples of electronic devices, and are illustrated in Fig. 16A to 16C, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0404] [electric appliances] 16D also illustrates an electric refrigerator-freezer 5800 as an example of an electrical appliance. Electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, etc. For example, electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0405] The semiconductor device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to an information terminal or the like via the Internet. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in the semiconductor device.

[0406] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0407] [Game consoles] 16E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0408] FIG. 16F further illustrates a stationary game console 7500, which is an example of a game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 16F, the controller 7522 can include a display unit that displays game images, and an input interface other than buttons, such as a touch panel, a stick, a rotary knob, or a sliding knob. The shape of the controller 7522 is not limited to the shape shown in FIG. 16F, and the shape of the controller 7522 may be varied depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In a music game, for example, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0409] Furthermore, the images of the above-mentioned game machines can be output by display devices such as television devices, personal computer displays, game displays, and head-mounted displays.

[0410] By applying the semiconductor device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500, it is possible to realize the portable game machine 5200 or the stationary game machine 7500 with a large storage capacity without increasing the occupation area. In addition, it is possible to realize the portable game machine 5200 or the stationary game machine 7500 with low power consumption. Furthermore, the low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0411] Furthermore, by applying the semiconductor device described in the above embodiments to the portable game console 5200 or the stationary game console 7500, temporary files and the like necessary for calculations occurring during game execution can be stored.

[0412] 16E shows a portable game machine as an example of a game machine. Also, FIG. 16F shows a home-use stationary game machine. Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include an arcade game machine installed in an entertainment facility (such as an arcade or amusement park) and a pitching machine for batting practice installed in a sports facility.

[0413] [Moving object] The semiconductor device described in the above embodiment can be applied to automobiles, which are moving objects, and to the vicinity of the driver's seat of an automobile.

[0414] FIG. 16G illustrates an automobile 5700 as an example of a moving object.

[0415] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows this information may also be provided around the driver's seat.

[0416] In particular, the display device can compensate for the view obstructed by pillars and the blind spot of the driver's seat by displaying an image from an imaging device (not shown) provided on the automobile 5700, thereby improving safety. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, it is possible to compensate for the blind spot and improve safety.

[0417] The semiconductor device described in the above embodiment can temporarily store data, and therefore, for example, the semiconductor device can be used to store necessary temporary data in a system that performs automatic driving, road guidance, hazard prediction, or the like of the automobile 5700. The display device may be configured to display temporary data such as road guidance and hazard prediction. The display device may also be configured to store video images from a driving recorder installed in the automobile 5700.

[0418] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies may include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0419] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0420] 16H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0421] A low-power digital camera 6240 can be realized by applying the semiconductor device described in the above embodiment modes to the digital camera 6240. Furthermore, low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0422] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0423] 16I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0424] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By using the semiconductor device described above, the video camera 6300 can store temporary files generated during encoding.

[0425] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0426] 16J is a cross-sectional schematic diagram showing an example of an ICD. ICD main body 5400 has at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0427] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0428] The ICD main body 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with an electric shock is administered.

[0429] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store in the electronic component 4700 heart rate data acquired by the sensor, the number of pacing treatments performed, the duration, and so on.

[0430] Furthermore, the antenna 5404 can receive power, which is then charged into the battery 5401. Furthermore, the ICD main body 5400 can improve safety by having multiple batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 can also function as an auxiliary power source.

[0431] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0432] [PC expansion device] The semiconductor device described in the above embodiment can be applied to an expansion device for a computer such as a PC (Personal Computer) or an information terminal.

[0433] Figure 17A shows an example of such an expansion device: a portable expansion device 6100 that is external to a PC and equipped with a chip capable of storing information. The expansion device 6100 can store information using the chip by connecting to a PC via, for example, a USB (Universal Serial Bus). Note that while Figure 17A shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this; for example, it may be a relatively large expansion device equipped with a cooling fan or the like.

[0434] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with circuits that drive the semiconductor devices described in the above embodiments. For example, the board 6104 is equipped with an electronic component 4700 and a controller chip 6106. The USB connector 6103 functions as an interface for connecting to an external device.

[0435] [SD card] The semiconductor device described in the above embodiment can be applied to an SD card which can be attached to electronic devices such as information terminals and digital cameras.

[0436] FIG. 17B is a schematic diagram of the external appearance of an SD card, and FIG. 17C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. A semiconductor device and a circuit for driving the semiconductor device are provided on the substrate 5113. For example, an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, the write circuit, row driver, read circuit, and the like provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 4700.

[0437] The capacity of the SD card 5110 can be increased by providing the electronic component 4700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 4700.

[0438] [SSD] The semiconductor device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

[0439] FIG. 17D is a schematic diagram of the external appearance of an SSD, and FIG. 17E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is provided with a storage device and a circuit for driving the storage device. For example, the circuit board 5153 is equipped with an electronic component 4700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 4700 on the back side of the circuit board 5153. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0440] [Calculator] 18A is an example of a large-scale computer. The computer 5600 has a rack 5610 storing a plurality of rack-mounted computers 5620.

[0441] Computer 5620 can have the configuration shown in the perspective view of Fig. 18B, for example. In Fig. 18B, computer 5620 has motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. PC card 5621 is inserted into slot 5631. In addition, PC card 5621 has connection terminal 5623, connection terminal 5624, and connection terminal 5625, which are each connected to motherboard 5630.

[0442] PC card 5621 shown in FIG. 18C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 includes board 5622. Board 5622 includes connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that FIG. 18C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 may be referred to.

[0443] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0444] Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Examples of standards for outputting video signals from connection terminals 5623, 5624, and 5625 include HDMI (registered trademark).

[0445] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0446] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 4730 can be used as the semiconductor device 5627.

[0447] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring on the board 5622. The semiconductor device 5628 can be, for example, a memory device. The electronic component 4700 can be used as the semiconductor device 5628.

[0448] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0449] By using the semiconductor device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be miniaturized and / or consume less power. Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which reduces heat generation from the circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.

[0450] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. [Explanation of symbols]

[0451] 100: semiconductor device, 120: transistor, 130: capacitance element, 141: conductor, 142: conductor, 143: conductor, 151: transistor layer, 152: capacitance layer, 153: capacitance layer, 154: capacitance layer, 155: capacitance layer

Claims

1. first to fourth transistors; The capacitor includes first to fourth capacitance elements and a first wiring, the first transistor is electrically connected to the first capacitance element; the second transistor is electrically connected to the second capacitance element, the third transistor is electrically connected to the third capacitive element, the fourth transistor is electrically connected to the fourth capacitive element, the first to fourth capacitance elements are provided above the first to fourth transistors, the first to fourth capacitance elements each have a ferroelectric substance; the third capacitance element and the fourth capacitance element are provided on the same layer, the third capacitive element has a first electrode; the first electrode is electrically connected to the first wiring; When viewed from above, the first electrode has a region that overlaps with the first wiring and a region that does not overlap with the first wiring. Semiconductor device.

2. In claim 1, The semiconductor device in which the first to fourth transistors are provided on the same layer.

3. In claim 1 or claim 2, Each of the first to fourth transistors is a semiconductor device including an oxide semiconductor in a semiconductor layer in which a channel is formed.

4. In claim 3, The oxide semiconductor device includes at least one of indium and zinc.

5. In any one of claims 1 to 4, The ferroelectric material includes at least one of hafnium and zirconium.

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