Semiconductor Devices

Abstract

This semiconductor device comprises: a semiconductor element; an island lead having the semiconductor element mounted thereto; a terminal lead conductively connected to the semiconductor element; a wire connected to the semiconductor element and the terminal lead; and a sealing resin that covers the semiconductor element, the island lead, the terminal lead, and the wire. The terminal lead includes: a base material having a main surface facing in the thickness direction of the terminal lead; and a metal layer interposed between the main surface and the wire. The bonding strength between the base material and the sealing resin is greater than that between the metal layer and the sealing resin. The main surface has an opposing side opposed to the island lead. The main surface has a first portion that includes at least a part of the opposing side and that is exposed from the metal layer.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device including terminal leads that are electrically connected to a semiconductor element and a sealing resin that covers the terminal leads. [Background technology]

[0002] An example of a conventional semiconductor device is disclosed in Patent Document 1. The semiconductor device includes inner leads that are electrically connected to a semiconductor chip, wires connected to the semiconductor chip and the inner leads, and a sealing body that covers the semiconductor chip, the inner leads, and the wires. The sealing body is made of a material that contains synthetic resin. The semiconductor device further includes outer leads that are connected to the inner leads and exposed from the sealing body.

[0003] In the semiconductor device disclosed in Patent Document 1, a metal layer may be formed on the surface of the inner lead. This can mitigate the thermal shock acting on the inner lead when connecting a wire to the inner lead. However, the bond strength between the metal layer and the encapsulant is weaker than the bond strength between the inner lead and the encapsulant. Therefore, when a tensile force acts on the outer lead in a direction to pull the inner lead out of the encapsulant, there is a concern that delamination may occur at the interface between the metal layer and the encapsulant. The likelihood of this delamination increases as the surface area of ​​the inner lead becomes relatively smaller. This delamination can cause problems such as increased leakage current in the semiconductor device. Therefore, measures to prevent this delamination are needed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-30049 Summary of the Invention [Problem to be solved by the invention]

[0005] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can suppress peeling that occurs at the interface between a terminal lead and a sealing resin. [Means for solving the problem]

[0006] The semiconductor device provided by the present disclosure includes a semiconductor element, an island lead on which the semiconductor element is mounted, a terminal lead electrically connected to the semiconductor element, a wire connected to the semiconductor element and the terminal lead, and a sealing resin covering at least a portion of each of the semiconductor element, the island lead, the terminal lead, and the wire. The terminal lead includes a substrate having a main surface facing the thickness direction of the terminal lead, and a metal layer interposed between the main surface and the wire. The substrate has a higher bonding strength with the sealing resin than the metal layer. The main surface includes an opposing side facing the island lead. The main surface includes at least a portion of the opposing side and a first portion exposed from the metal layer. [Effects of the Invention]

[0007] According to the above configuration, it is possible to suppress peeling that occurs at the interface between the terminal lead and the sealing resin.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view corresponding to FIG. 1, seen through the sealing resin. [Figure 3] FIG. 2 is a front view of the semiconductor device shown in FIG. [Figure 4] FIG. 2 is a left side view of the semiconductor device shown in FIG. [Figure 5] FIG. 3 is a cross-sectional view taken along line VV in FIG. 2. [Figure 6]FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 3 is a partially enlarged view of FIG. 2. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7. [Figure 9] FIG. 3 is a partially enlarged view of FIG. 2. [Figure 10] FIG. 3 is a partially enlarged view of FIG. 2. [Figure 11] FIG. 3 is a partially enlarged view of FIG. 2. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. [Figure 13] FIG. 3 is a partially enlarged view of FIG. 2. [Figure 14] FIG. 3 is a partially enlarged view of FIG. 2. [Figure 15] 1. FIG. 4 is a partially enlarged plan view of a first modified example of the semiconductor device shown in FIG. [Figure 16] 1. FIG. 4 is a partially enlarged plan view of a second modified example of the semiconductor device shown in FIG. [Figure 17] 1. FIG. 4 is a partially enlarged plan view of a third modified example of the semiconductor device shown in FIG. [Figure 18] 10 is a plan view of a semiconductor device according to a second embodiment of the present disclosure, seen through a sealing resin. FIG. [Figure 19] FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0011] A semiconductor device A1 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 12. The semiconductor device A1 includes two semiconductor elements 10, an insulating element 12, two island leads 2, a plurality of terminal leads 3, a plurality of first wires 41, a plurality of second wires 42, a plurality of third wires 43, a plurality of fourth wires 44, and a sealing resin 5. The semiconductor device A1 is surface-mounted on a wiring board of an inverter device of, for example, an electric vehicle or a hybrid vehicle. The package format of the semiconductor device A1 is an SOP (Small Outline Package). However, the package format of the semiconductor device A1 is not limited to an SOP. In FIG. 2, for ease of understanding, the sealing resin 5 is shown transparently and indicated by an imaginary line (two-dot chain line).

[0012] In the description of the semiconductor device A1, three mutually orthogonal directions, i.e., direction x, direction y, and direction z, will be referred to as appropriate. In the following description, the thickness direction of each of the multiple terminal leads 3 will be referred to as the "thickness direction z," direction x as the "first direction x," and direction y as the "second direction y," but the present disclosure is not limited to these.

[0013] The two semiconductor elements 10 and the insulating element 12 are elements that form the functional core of the semiconductor device A1. As shown in Fig. 2, the two semiconductor elements 10 include a first semiconductor element 11 and a second semiconductor element 13. In the semiconductor device A1, the first semiconductor element 11, the second semiconductor element 13, and the insulating element 12 are each composed of individual elements. When viewed in the thickness direction z, the first semiconductor element 11, the second semiconductor element 13, and the insulating element 12 each have a rectangular shape with the longer side extending in the second direction y.

[0014] The first semiconductor element 11 is a controller (control element) of a gate driver that drives switching elements such as IGBTs, MOSFETs, etc. The first semiconductor element 11 has a circuit that converts a control signal input from an ECU or the like into a PWM control signal, a transmission circuit that transmits the PWM control signal to the second semiconductor element 13, and a reception circuit that receives an electrical signal from the second semiconductor element 13.

[0015] The second semiconductor element 13 is a gate driver (drive element) for driving the switching element. The second semiconductor element 13 has a receiving circuit for receiving a PWM control signal, a circuit for driving the switching element based on the PWM control signal, and a transmitting circuit for transmitting an electrical signal to the first semiconductor element 11. The electrical signal may be, for example, an output signal from a temperature sensor arranged near the motor.

[0016] The isolation element 12 is an element for transmitting PWM control signals and other electrical signals in an isolated state. In the semiconductor device A1, the isolation element 12 is an inductive type. An example of an inductive isolation element 12 is an isolation transformer. An isolation transformer transmits electrical signals in an isolated state by inductively coupling two inductors (coils). The isolation element 12 has a silicon substrate. A copper inductor is formed on the substrate. The inductors include a transmitting inductor and a receiving inductor, and these inductors are stacked in the thickness direction z. A dielectric layer made of silicon dioxide (SiO2) or the like is interposed between the transmitting inductor and the receiving inductor. The dielectric layer electrically insulates the transmitting inductor from the receiving inductor. Alternatively, the isolation element 12 may be a capacitive type. An example of a capacitive isolation element 12 is a capacitor. The isolation element 12 may also be a photocoupler.

[0017] In semiconductor device A1, second semiconductor element 13 requires a power supply voltage higher than that required for first semiconductor element 11. This results in a significant potential difference between first semiconductor element 11 and second semiconductor element 13. Therefore, in semiconductor device A1, a first circuit including first semiconductor element 11 as a component and a second circuit including second semiconductor element 13 as a component are insulated from each other by isolation element 12. The first circuit and the second circuit have relatively different potentials. In semiconductor device A1, the second circuit has a higher potential than the first circuit. Furthermore, isolation element 12 relays signals between the first circuit and the second circuit. For example, in an inverter device for an electric vehicle or hybrid vehicle, the voltage applied to the ground of first semiconductor element 11 is approximately 0 V, while the voltage applied to the ground of second semiconductor element 13 may transiently reach 600 V or higher.

[0018] 2 and 5, a plurality of electrodes 111 are provided on the upper surface of the first semiconductor element 11 (a surface facing in the same direction as the mounting surfaces 211 of the island portions 21 of the two island leads 2 described below). The plurality of electrodes 111 are electrically connected to a circuit configured in the first semiconductor element 11. Similarly, a plurality of electrodes 131 are provided on the upper surface of the second semiconductor element 13 (a surface facing in the same direction as the mounting surfaces 211 described above). The plurality of electrodes 131 are electrically connected to a circuit configured in the second semiconductor element 13.

[0019] 2 and 5, the insulating element 12 is located between the first semiconductor element 11 and the second semiconductor element 13 in the first direction x. A plurality of first electrodes 121 and a plurality of second electrodes 122 are provided on the upper surface of the insulating element 12 (the surface facing the same direction as the mounting surface 211 described above). Each of the plurality of first electrodes 121 and the plurality of second electrodes 122 is electrically connected to either the transmitting inductor or the receiving inductor. The plurality of first electrodes 121 are arranged along the second direction y and are located closer to the first semiconductor element 11 than the second semiconductor element 13 in the first direction x. The plurality of second electrodes 122 are arranged along the second direction y and are located closer to the second semiconductor element 13 than the first semiconductor element 11 in the first direction x.

[0020] The two island leads 2 and the multiple terminal leads 3 are conductive members that form conductive paths between the two semiconductor elements 10, the insulating element 12, and the wiring board on which the semiconductor device A1 is mounted. These main components are obtained from the same lead frame. The lead frame contains copper (Cu) in its composition.

[0021] As shown in FIGS. 1 and 2, the two island leads 2 are spaced apart from each other in the first direction x. The two island leads 2 include a first island 2A and a second island 2B. The first island 2A is located on one side in the first direction x. The second island 2B is located on the other side in the first direction x. In the semiconductor device A1, a first semiconductor element 11 and an insulating element 12 are mounted on the first island 2A, and a second semiconductor element 13 is mounted on the second island 2B.

[0022] As shown in FIG. 2, each of the two island leads 2 has an island portion 21 and two lead portions 22. At least one of two semiconductor elements 10 and an insulating element 12 is mounted on the island portion 21. The island portion 21 is covered with a sealing resin 5. The island portion 21 has a mounting surface 211 facing the thickness direction z. The first semiconductor element 11 and the insulating element 12 are mounted on the mounting surface 211 of the island portion 21 of the first island 2A. The second semiconductor element 13 is mounted on the mounting surface 211 of the island portion 21 of the second island 2B. Each of the two semiconductor elements 10 and the insulating element 12 is bonded to either the mounting surface 211 of the first island 2A or the mounting surface 211 of the second island 2B via a conductive bonding material (such as solder or metal paste) not shown. The island portion 21 has a thickness of, for example, 100 μm or more and 300 μm or less.

[0023] 2 and 5, a plurality of through holes 23 are formed in the island portion 21 of the first island 2A. Each of the plurality of through holes 23 penetrates the island portion 21 in the thickness direction z and extends along the second direction y. As viewed in the thickness direction z, at least one of the plurality of through holes 23 is located between the first semiconductor element 11 and the insulating element 12. The plurality of through holes 23 are arranged along the second direction y.

[0024] As shown in Fig. 2, the two lead portions 22 are connected to both sides of the island portion 21 in the second direction y. The two lead portions 22 are positioned apart from each other in the second direction y. At least one of the two lead portions 22 of the first island 2A is electrically connected to the first semiconductor element 11 via a second wire 42. At least one of the two lead portions 22 of the second island 2B is electrically connected to the second semiconductor element 13 via a fourth wire 44.

[0025] As shown in FIG. 2, each of the two lead portions 22 has a covering portion 221 and an exposed portion 222. The covering portion 221 is connected to the island portion 21 and is covered with the sealing resin 5. A metal layer 24 is interposed between one side of the covering portion 221 in the thickness direction z (the side facing the mounting surface 211 of the island portion 21) and the sealing resin 5. The metal layer 24 contains silver (Ag). The exposed portion 222 is connected to the covering portion 221 and is exposed from the sealing resin 5. When viewed in the thickness direction z, the exposed portion 222 extends along the first direction x. When viewed in the second direction y, the exposed portion 222 is bent in a gull-wing shape as shown in FIG. 3. The surface of the exposed portion 222 may be plated with, for example, tin (Sn).

[0026] 1 and 2, the multiple terminal leads 3 are arranged on both sides in the first direction x and aligned along the second direction y. At least one of the multiple terminal leads 3 is electrically connected to one of the two semiconductor elements 10. The multiple terminal leads 3 include multiple first terminals 3A, two second terminals 3B, and two third terminals 3C arranged on one side in the first direction x, and multiple fourth terminals 3D, two fifth terminals 3E, and two sixth terminals 3F arranged on the other side in the first direction x.

[0027] 2, at least one of the plurality of first terminals 3A, two second terminals 3B, and two third terminals 3C is electrically connected to the first semiconductor element 11 via second wires 42. The two second terminals 3B are located on both sides of the plurality of first terminals 3A in the second direction y. Each of the two third terminals 3C is located between one of the two lead portions 22 of the first island 2A and the second terminal 3B located closest to that lead portion 22 in the second direction y.

[0028] 2, at least one of the plurality of fourth terminals 3D, two fifth terminals 3E, and two sixth terminals 3F is electrically connected to the second semiconductor element 13 via a fourth wire 44. The two fifth terminals 3E are located on both sides of the plurality of fourth terminals 3D in the second direction y. Each of the two sixth terminals 3F is located between one of the two lead portions 22 of the second island 2B and the fifth terminal 3E located closest to that lead portion 22 in the second direction y.

[0029] As shown in FIGS. 2 and 5 , each of the multiple terminal leads 3 has a covering portion 31 and an exposed portion 32. The covering portion 31 is covered with a sealing resin 5. Either one of multiple second wires 42 or multiple fourth wires 44 is connected to the covering portion 31 of at least one of the multiple terminal leads 3. The dimension in the first direction x of the covering portion 31 of each of the two second terminals 3B and the two fifth terminals 3E is larger than the dimension in the first direction x of the covering portion 31 of each of the multiple first terminals 3A and the multiple fourth terminals 3D. The exposed portion 32 is connected to the covering portion 31 and is exposed from the sealing resin 5. When viewed in the thickness direction z, the exposed portion 32 extends along the first direction x. When viewed in the second direction y, the exposed portion 32 is bent in a gull-wing shape. The shape of the exposed portion 32 is equal to the shape of each of the exposed portions 222 of the two lead portions 22 of the two island leads 2. The surface of the exposed portion 32 may be plated with tin, for example.

[0030] As shown in FIG. 2 , the covering portion 31 of each of the two third terminals 3C and the two sixth terminals 3F has a base portion 311 and an extending portion 312. The base portion 311 extends from the exposed portion 32 in the first direction x. The dimension of the base portion 311 in the first direction x is greater than the dimension of the covering portion 31 of each of the two second terminals 3B and the two fifth terminals 3E in the first direction x. The extending portion 312 extends from the base portion 311 in the second direction y toward the island portions 21 of the two island leads 2. A plurality of fourth wires 44 are connected to the extending portions 312 of the two sixth terminals 3F.

[0031] As shown in FIGS. 7 to 14 , each of the multiple terminal leads 3 includes a substrate 33 and a metal layer 34. The substrate 33 has a main surface 331 facing the thickness direction z. The orientation of the main surface 331 is the same as the orientation of the mounting surfaces 211 of the island portions 21 of the two island leads 2. The substrate 33 is part of a lead frame that forms a main portion of the multiple terminal leads 3. Therefore, the substrate 33 contains copper. The metal layer 34 is interposed between the main surface 331 and either the multiple second wires 42 or the multiple fourth wires 44. The metal layer 34 is included in the coating portion 31 of the multiple terminal leads 3. The metal layer 34 is in contact with the sealing resin 5. The metal layer 34 contains silver. Alternatively, the metal layer 34 may contain at least one of nickel (Ni), palladium (Pd), and gold (Au). The substrate 33 has a higher bonding strength with the sealing resin 5 than the metal layer 34. For example, if the composition of base material 33 includes copper and the composition of metal layer 34 includes silver, the bonding strength per unit area between base material 33 and sealing resin 5 is approximately 14 times the bonding strength between metal layer 34 and sealing resin 5.

[0032] As shown in FIGS. 7 to 14, the main surface 331 of the substrate 33 included in each of the multiple terminal leads 3 includes an opposing side 332. The opposing side 332 faces the island portion 21 of one of the two island leads 2. In the semiconductor device A1, the opposing side 332 is a straight line. Alternatively, the opposing side 332 may be a curved line. The opposing side 332 has two end portions 332A. The main surface 331 further includes a first portion 333. The first portion 333 includes at least a portion of the opposing side 332 and is exposed from the metal layer 34. The first portion 333 is in contact with the sealing resin 5. In the semiconductor device A1, the first portion 333 includes the entire opposing side 332.

[0033] Each of the multiple terminal leads 3 satisfies the following requirements. As viewed in the thickness direction z, the distance d between the metal layer 34 and the opposing side 332 (see FIGS. 7 to 14) is 0.03 to 1.0 times the thickness t of the base material 33 (see FIGS. 8 and 12). The distance d is, for example, 10 μm to 100 μm. The thickness t is, for example, 100 μm to 300 μm. As viewed in the thickness direction z, the distance d is 0.25 to 5.0 times the length L of the opposing side 332 (see FIGS. 7, 9 to 11, 13, and 14). The length L is, for example, 20 μm to 40 μm. As viewed in the thickness direction z, the distance d is 0.02 to 0.25 times the distance D between the opposing side 332 and one of the island portions 21 of the two island leads 2 (see FIGS. 7 to 14). The distance D is, for example, not less than 400 μm and not more than 500 μm.

[0034] As shown in FIGS. 7 to 14, the island portion 21 of each of the two island leads 2 has a plurality of first sides 212. The first sides 212 extend in a direction perpendicular to the thickness direction z. In the semiconductor device A1, the first sides 212 extend along either the first direction x or the second direction y. As shown in FIGS. 7 and 11, the first terminals 3A and the fourth terminals 3D face the first sides 212 extending along the second direction y. As shown in FIGS. 9 and 14, two second terminals 3B and two fifth terminals 3E face the ends of the first sides 212 extending along the second direction y. As shown in FIGS. 10 and 13, two third terminals 3C and two sixth terminals 3F face the first sides 212 extending along the first direction x.

[0035] The plurality of first wires 41, the plurality of second wires 42, the plurality of third wires 43, and the plurality of fourth wires 44, together with the two island leads 2 and the plurality of terminal leads 3, form a conductive path for the two semiconductor elements 10 and the insulating element 12 to perform predetermined functions. The composition of the plurality of first wires 41, the plurality of second wires 42, the plurality of third wires 43, and the plurality of fourth wires 44 includes gold. Alternatively, the composition of these wires may include copper or aluminum (Al).

[0036] 2 and 5, each of the multiple first wires 41 is connected to one of the multiple first electrodes 121 of the insulating element 12 and one of the multiple electrodes 111 of the first semiconductor element 11. This establishes mutual conduction between the first semiconductor element 11 and the insulating element 12. The multiple first wires 41 are arranged along the second direction y.

[0037] As shown in FIGS. 2 and 5 , each of the second wires 42 is connected to one of the electrodes 111 of the first semiconductor element 11 and to the coating 31 of one of the first terminals 3A and two second terminals 3B. This provides electrical continuity between the first semiconductor element 11 and at least one of the first terminals 3A and two second terminals 3B. Furthermore, at least one of the second wires 42 is connected to one of the electrodes 111 and to the coating 221 of one of the two lead portions 22 of the first island 2A. This provides electrical continuity between the first island 2A and the first semiconductor element 11. Each of the second wires 42 is in contact with the metal layer 34 of one of the first terminals 3A and two second terminals 3B. As shown in FIGS. 7 and 9 , at least one of the second wires 42 overlaps the opposing side 332 of one of the first terminals 3A and two second terminals 3B. Furthermore, any of the plurality of second wires 42 overlaps the first portions 333 of any of the plurality of first terminals 3A and two second terminals 3B.

[0038] 2 and 5, each of the multiple third wires 43 is connected to one of the multiple second electrodes 122 of the insulating element 12 and one of the multiple electrodes 131 of the second semiconductor element 13. This establishes mutual conduction between the second semiconductor element 13 and the insulating element 12. The multiple third wires 43 are arranged along the second direction y. In the semiconductor device A1, the multiple third wires 43 straddle the island portion 21 of the first island 2A and the island portion 21 of the second island 2B.

[0039] As shown in FIGS. 2 and 5 , each of the multiple fourth wires 44 is connected to one of the multiple electrodes 131 of the second semiconductor element 13 and to the coating 31 of one of the multiple fourth terminals 3D, two fifth terminals 3E, and two sixth terminals 3F. As a result, at least one of the multiple fourth terminals 3D, two fifth terminals 3E, and two sixth terminals 3F is electrically connected to the second semiconductor element 13. Furthermore, at least one of the multiple fourth wires 44 is connected to one of the multiple electrodes 131 and to the coating 221 of one of the two lead portions 22 of the second island 2B. As a result, the second island 2B is electrically connected to the second semiconductor element 13. Each of the multiple fourth wires 44 is in contact with the metal layer 34 of one of the multiple fourth terminals 3D, two fifth terminals 3E, and two sixth terminals 3F. 10 and 12, at least one of the multiple fourth wires 44 overlaps the opposing sides 332 of either the multiple fourth terminals 3D or the two fifth terminals 3E. Furthermore, one of the multiple fourth wires 44 overlaps the first portions 333 of either the multiple fourth terminals 3D or the two fifth terminals 3E.

[0040] As shown in FIG. 1, the sealing resin 5 covers the two semiconductor elements 10, the insulating element 12, the two island leads 2, and a portion of each of the multiple terminal leads 3. Furthermore, as shown in FIG. 5, the sealing resin 5 covers the multiple first wires 41, the multiple second wires 42, the multiple third wires 43, and the multiple fourth wires 44. The sealing resin 5 has electrical insulation properties. The sealing resin 5 insulates the two island leads 2 from each other. The sealing resin 5 is made of a material containing, for example, black epoxy resin. When viewed in the thickness direction z, the sealing resin 5 is rectangular.

[0041] As shown in FIGS. 3 and 4, the sealing resin 5 has a top surface 51, a bottom surface 52, a pair of first side surfaces 53, and a pair of second side surfaces .

[0042] 3 and 4, the top surface 51 and the bottom surface 52 are spaced apart from each other in the thickness direction z. The top surface 51 and the bottom surface 52 face opposite each other in the thickness direction z. Each of the top surface 51 and the bottom surface 52 is flat (or substantially flat).

[0043] 3 and 4, the pair of first side surfaces 53 are connected to the top surface 51 and the bottom surface 52 and are spaced apart in the first direction x. The exposed portions 222 of the two lead portions 22 of the first island 2A and the exposed portions 32 of the first terminals 3A, two second terminals 3B, and two third terminals 3C are exposed from the first side surface 53 located on one side in the first direction x. The exposed portions 222 of the two lead portions 22 of the second island 2B and the exposed portions 32 of the fourth terminals 3D, two fifth terminals 3E, and two sixth terminals 3F are exposed from the first side surface 53 located on the other side in the first direction x.

[0044] As shown in FIGS. 3 and 4 , each of the pair of first side surfaces 53 includes a first upper portion 531, a first lower portion 532, and a first intermediate portion 533. One side of the first upper portion 531 in the thickness direction z is connected to the top surface 51, and the other side in the thickness direction z is connected to the first intermediate portion 533. The first upper portion 531 is inclined with respect to the top surface 51. One side of the first lower portion 532 in the thickness direction z is connected to the bottom surface 52, and the other side in the thickness direction z is connected to the first intermediate portion 533. The first lower portion 532 is inclined with respect to the bottom surface 52. One side of the first intermediate portion 533 in the thickness direction z is connected to the first upper portion 531, and the other side in the thickness direction z is connected to the first lower portion 532. The in-plane directions of the first intermediate portion 533 are the thickness direction z and the second direction y. When viewed in the thickness direction z, the first intermediate portion 533 is located outward from the top surface 51 and the bottom surface 52. From the first intermediate portion 533 of the pair of first side surfaces 53, the exposed portions 222 of the two lead portions 22 of the two island leads 2 and the exposed portions 32 of the multiple terminal leads 3 are exposed.

[0045] 3 and 4, the pair of second side surfaces 54 are connected to the top surface 51 and the bottom surface 52 and are spaced apart from each other in the second direction y. As shown in FIG. 1, the two island leads 2 and the plurality of terminal leads 3 are spaced apart from the pair of second side surfaces 54.

[0046] As shown in FIGS. 3 and 4 , each of the pair of second side surfaces 54 includes a second upper portion 541, a second lower portion 542, and a second intermediate portion 543. The second upper portion 541 is connected to the top surface 51 on one side in the thickness direction z and to the second intermediate portion 543 on the other side in the thickness direction z. The second upper portion 541 is inclined with respect to the top surface 51. The second lower portion 542 is connected to the bottom surface 52 on one side in the thickness direction z and to the second intermediate portion 543 on the other side in the thickness direction z. The second lower portion 542 is inclined with respect to the bottom surface 52. The second intermediate portion 543 is connected to the second upper portion 541 on one side in the thickness direction z and to the second lower portion 542 on the other side in the thickness direction z. The in-plane directions of the second intermediate portion 543 are the thickness direction z and the second direction y. The second intermediate portion 543 is located outward from the top surface 51 and the bottom surface 52 when viewed in the thickness direction z.

[0047] A motor driver circuit in an inverter device typically includes a half-bridge circuit including a low-side (low potential side) switching element and a high-side (high potential side) switching element. The following description focuses on the case where these switching elements are MOSFETs. Here, for the low-side switching element, the reference potentials of the source of the switching element and the gate driver driving the switching element are both ground. For the high-side switching element, the reference potentials of the source of the switching element and the gate driver driving the switching element are both equivalent to the potential at the output node of the half-bridge circuit. The potential at the output node changes depending on the driving of the high-side and low-side switching elements, so the reference potential of the gate driver driving the high-side switching element also changes. When the high-side switching element is on, the reference potential is equivalent to the voltage applied to the drain of the high-side switching element (e.g., 600 V or higher). In the semiconductor device A1, the ground of the first semiconductor element 11 and the ground of the second semiconductor element 13 are separated. Therefore, when the semiconductor device A1 is used as a gate driver for driving a high-side switching element, a voltage equivalent to the voltage applied to the drain of the high-side switching element is transiently applied to the ground of the second semiconductor element 13.

[0048] Next, a semiconductor device A11, which is a first modification of the semiconductor device A1, will be described with reference to FIG.

[0049] 15, the semiconductor device A11 differs from the semiconductor device A1 in the configuration of the first portion 333 of the substrate 33 included in each of the multiple terminal leads 3. In the semiconductor device A11, the first portion 333 does not include the entire opposing side 332, but includes one of the two end portions 332A of the opposing side 332.

[0050] Next, a semiconductor device A12, which is a second modification of the semiconductor device A1, will be described with reference to FIG.

[0051] 16, the semiconductor device A12 differs from the semiconductor device A1 in the configuration of the first portion 333 of the substrate 33 included in each of the multiple terminal leads 3. In the semiconductor device A12, the first portion 333 does not include the entire opposing side 332, but includes two end portions 332A of the opposing side 332. As a result, the first portion 333 includes multiple regions located apart from each other in the direction in which the opposing side 332 extends.

[0052] Next, a semiconductor device A13, which is a third modification of the semiconductor device A1, will be described with reference to FIG.

[0053] 17, the semiconductor device A13 differs from the semiconductor device A1 in the configuration of the first portion 333 of the substrate 33 included in each of the multiple terminal leads 3. In the semiconductor device A13, the first portion 333 does not include the entire opposing side 332 or the two end portions 332A of the opposing side 332.

[0054] Next, the effects of the semiconductor device A1 will be described.

[0055] The semiconductor device A1 includes a terminal lead 3 electrically connected to the semiconductor element 10 and a sealing resin 5 covering a portion of the terminal lead 3. The terminal lead 3 includes a base material 33 having a main surface 331 and a metal layer 34 interposed between the main surface 331 and a wire (either one of the plurality of second wires 42 or the plurality of fourth wires 44). The base material 33 has a higher bonding strength with the sealing resin 5 than the metal layer 34. The main surface 331 includes an opposing side 332 facing the island lead 2 and a first portion 333 that includes at least a portion of the opposing side 332 and is exposed from the metal layer 34. This results in the terminal lead 3 being configured such that the metal layer 34 and the first portion 333 are in contact with the sealing resin 5. Furthermore, the bonding strength between the terminal lead 3 and the sealing resin 5 is increased at the first portion 333, i.e., the tip portion of the terminal lead 3 located closest to the island lead 2. Therefore, the semiconductor device A1 makes it possible to suppress peeling at the interface between the terminal lead 3 and the sealing resin 5.

[0056] When a tensile force is applied to the terminal lead 3 in a direction in which the terminal lead 3 is pulled out from the sealing resin 5 (first direction x in the semiconductor device A1), the tensile stress acting on the interface between the terminal lead 3 and the sealing resin 5 is concentrated on the two end portions 332A of the opposing side 332 of the base material 33. Therefore, if the first portion 333 of the base material 33 includes at least one of the two end portions 332A of the opposing side 332, peeling that occurs at the interface between the terminal lead 3 and the sealing resin 5 can be effectively suppressed.

[0057] The composition of the base material 33 preferably contains copper, which further improves the bonding strength between the first portion 333 and the sealing resin 5. The composition of the metal layer 34 preferably contains silver, which effectively reduces the thermal shock acting on the base material 33 when connecting the wire to the terminal lead 3. Furthermore, if the composition of the wire contains gold, the thermal shock can be reduced even more effectively.

[0058] As viewed in the thickness direction z, the distance d (see FIGS. 7 to 14) between the metal layer 34 and the opposing side 332 is preferably 0.03 to 1.0 times the thickness t (see FIGS. 8 and 12) of the base material 33. This increases the bonding strength between the terminal lead 3 and the sealing resin 5, while suppressing an increase in both the tensile stress generated in the base material 33 when attempting to pull out the terminal lead 3 from the sealing resin 5 and the volume of the terminal lead 3.

[0059] As viewed in the thickness direction z, the distance d between the metal layer 34 and the opposing side 332 is 0.25 to 5.0 times the length L (FIGS. 7, 9 to 11, 13, and 14) of the opposing side 332. This makes it possible to increase the bonding strength between the terminal lead 3 and the sealing resin 5 while maintaining the size of the terminal lead 3.

[0060] As viewed in the thickness direction z, the distance d between the metal layer 34 and the opposing side 332 is 0.02 to 0.25 times the distance D (see FIGS. 7 to 14) between the opposing side 332 and the island lead 2. This makes it possible to increase the bonding strength between the terminal lead 3 and the sealing resin 5 while preventing both a decrease in the dielectric strength between the island lead 2 and the terminal lead 3 due to the occurrence of voids in the sealing resin 5 and an increase in the size of the semiconductor device A1.

[0061] When viewed in the thickness direction z, the wire overlaps the first portion 333. This effectively prevents the wire from peeling off from the terminal lead 3 due to tensile stress generated at the interface between the terminal lead 3 and the sealing resin 5.

[0062] In the semiconductor device A1, a portion of each of the island lead 2 and the terminal lead 3 is exposed from one of the pair of first side surfaces 53 of the sealing resin 5. In this case, the island lead 2 and the terminal lead 3 are located away from the pair of second side surfaces 54 of the sealing resin 5. Therefore, in the semiconductor device A1, metal members such as the island support are not exposed from the pair of second side surfaces 54. This allows the dielectric strength of the semiconductor device A1 to be improved.

[0063] In the semiconductor device A1, of the two island leads 2, the island portion 21 of the first island 2A, which has a relatively large area, has a plurality of through holes 23 formed in the island portion 21. The larger the area of ​​the island portion 21, the more likely voids are to occur in the sealing resin 5. Therefore, by adopting this configuration, it is possible to prevent imperfect filling of the sealing resin 5 injected into the mold when forming the sealing resin 5, thereby effectively suppressing the occurrence of voids in the sealing resin 5.

[0064] A semiconductor device A2 according to a second embodiment of the present disclosure will be described with reference to Figures 18 and 19. In these figures, elements that are the same as or similar to those in the semiconductor device A1 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Figure 18 shows the sealing resin 5 as it is seen through, and is indicated by imaginary lines.

[0065] In the semiconductor device A2, the mounting configuration of the insulating element 12 is different from that of the semiconductor device A1 described above.

[0066] 18 and 19, the insulating element 12 is mounted on the mounting surface 211 of the island portion 21 of the second island 2B. Therefore, in the semiconductor device A2, a plurality of first wires 41 extend between the island portion 21 of the first island 2A and the island portion 21 of the second island 2B. In this way, the insulating element 12 can be mounted on the island portion 21 regardless of the relative magnitude of the potential applied to the island portion 21.

[0067] Next, the effects of the semiconductor device A2 will be described.

[0068] The semiconductor device A2 includes a terminal lead 3 electrically connected to the semiconductor element 10 and a sealing resin 5 covering a portion of the terminal lead 3. The terminal lead 3 includes a base material 33 having a main surface 331 and a metal layer 34 interposed between the main surface 331 and a wire (either a plurality of second wires 42 or a plurality of fourth wires 44). The base material 33 has a higher bonding strength with the sealing resin 5 than the metal layer 34. The main surface 331 includes an opposing side 332 opposing the island lead 2 and a first portion 333 including at least a portion of the opposing side 332 and exposed from the metal layer 34. Therefore, the semiconductor device A2 can also suppress peeling at the interface between the terminal lead 3 and the sealing resin 5. Furthermore, the semiconductor device A2 has a configuration in common with the semiconductor device A1, thereby achieving the same effects as the semiconductor device A1.

[0069] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0070] The present disclosure includes the embodiments described in the following appendices. Appendix 1. A semiconductor element; an island lead on which the semiconductor element is mounted; a terminal lead electrically connected to the semiconductor element; a wire connected to the semiconductor element and the terminal lead; a sealing resin that covers at least a portion of each of the semiconductor element, the island lead, the terminal lead, and the wire, the terminal lead includes a substrate having a main surface facing a thickness direction of the terminal lead, and a metal layer interposed between the main surface and the wire, the base material has a higher bonding strength with the sealing resin than the metal layer; the main surface includes an opposing side facing the island lead, The main surface includes at least a portion of the opposing side and a first portion exposed from the metal layer. Appendix 2. 2. The semiconductor device according to claim 1, wherein the first portion includes an end portion of the opposing side. Appendix 3. 2. The semiconductor device according to claim 1, wherein the first portion includes the entire opposing side. Appendix 4. 4. The semiconductor device according to claim 1, wherein the opposing side is linear. Appendix 5. 5. The semiconductor device according to any one of claims 1 to 4, wherein, when viewed in the thickness direction, the distance between the metal layer and the opposing edge is 0.03 to 1.0 times the thickness of the base material. Appendix 6. 6. The semiconductor device according to any one of claims 1 to 5, wherein, when viewed in the thickness direction, the distance between the metal layer and the opposing side is 0.25 to 5.0 times the length of the opposing side. Appendix 7. A semiconductor device described in any one of Appendix 1 to 6, wherein, when viewed in the thickness direction, the distance between the metal layer and the opposing side is 0.02 to 0.5 times the distance between the opposing side and the island lead. Appendix 8. 8. The semiconductor device according to claim 1, wherein the substrate contains copper. Appendix 9. 9. The semiconductor device according to claim 1, wherein the metal layer contains silver. Appendix 10. 10. The semiconductor device according to any one of claims 1 to 9, wherein the wire contains gold or copper. Appendix 11. the island lead has a first side perpendicular to the thickness direction, 11. The semiconductor device according to any one of claims 1 to 10, wherein the terminal lead faces an end of the first side. Appendix 12. 12. The semiconductor device of claim 11, further comprising an additional terminal lead facing the first side. Appendix 13. 13. The semiconductor device according to any one of claims 1 to 12, wherein the wire overlaps the opposing side when viewed in the thickness direction. Appendix 14. 14. The semiconductor device according to any one of claims 1 to 13, wherein the wire overlaps the first portion when viewed in the thickness direction. Appendix 15. 15. The semiconductor device according to any one of claims 1 to 14, wherein the semiconductor element is a gate driver. Appendix 16. 15. The semiconductor device according to any one of claims 1 to 14, wherein the semiconductor element is a controller. Appendix 17. 17. The semiconductor device according to claim 15, further comprising an inductive insulating element electrically connected to the semiconductor element. [Explanation of symbols]

[0071] A1, A2: Semiconductor device 10: Semiconductor element 11: First semiconductor element (controller) 111: Electrode 12: insulating element 121: first electrode 122: Second electrode 13: Second semiconductor element (gate driver) 131: Electrode 2: Island lead 2A: 1st Island 2B: 2nd Island 21: Island section 211: Mounting surface 212: First side 22: Lead part 221: Covered portion 222: Exposed portion 23: Through hole 24: Metal layer 3: Terminal lead 3A: First terminal 3B: 2nd terminal 3C: 3rd terminal 3D: 4th terminal 3E: 5th terminal 3F: 6th terminal 31: Covering part 311: Base 312: Extension 32: Exposed part 33: Base material 331: Main surface 332: Opposite side 332A: Opposite side 333: Part 1 34: Metal layer 41: First wire 42: Second wire 43: Third wire 44: 4th wire 5: Sealing resin 51:Top 52:Bottom 53: 1st side 531: 1st top 532: 1st lower part 533: 1st middle part 54:Second side 541:Second top 542: Second lower part 543: Second middle part d, D: Spacing L: Length t: thickness z: thickness direction x: 1st direction y: 2nd direction

Claims

1. A semiconductor element; an island lead on which the semiconductor element is mounted; a terminal lead electrically connected to the semiconductor element; a wire connected to the semiconductor element and the terminal lead; a sealing resin that covers at least a portion of each of the semiconductor element, the island lead, the terminal lead, and the wire, the semiconductor element is either a gate driver that drives a switching element or a controller of the gate driver, the terminal lead includes a substrate having a main surface facing a thickness direction of the terminal lead, and a metal layer interposed between the main surface and the wire, the base material has a higher bonding strength with the sealing resin than the metal layer; the main surface includes an opposing side facing the island lead, The opposing side has two opposing end portions located at both ends of the opposing side when viewed in the thickness direction, the main surface includes a first portion that includes a part of the opposing side and is exposed from the metal layer; The first part has any one of a first configuration, a second configuration, and a third configuration, The first configuration is a configuration in which the first portion includes either of the two opposing ends, the second configuration is a configuration in which the first portion includes the two opposing ends and is two regions spaced apart from each other; The third configuration is a configuration in which the first portion is spaced apart from each of the two opposing ends.

2. A semiconductor element; an island lead on which the semiconductor element is mounted; a terminal lead electrically connected to the semiconductor element; a wire connected to the semiconductor element and the terminal lead; a sealing resin that covers at least a portion of each of the semiconductor element, the island lead, the terminal lead, and the wire, the semiconductor element is either a gate driver that drives a switching element or a controller of the gate driver, the terminal lead includes a substrate having a main surface facing a thickness direction of the terminal lead, and a metal layer interposed between the main surface and the wire, the base material has a higher bonding strength with the sealing resin than the metal layer; the main surface includes an opposing side facing the island lead, the main surface includes a first portion that includes a part of the opposing side and is exposed from the metal layer; the opposing side includes a first section included in the first portion and a second section connected to the first section, When viewed in the thickness direction, the metal layer overlaps the entire second section.

3. A semiconductor device as described in claim 1 or 2, wherein the opposing sides are straight.

4. A semiconductor device described in any one of claims 1 to 3, wherein, when viewed in the thickness direction, the distance between the metal layer and the opposing edge is greater than or equal to 0.03 times and less than or equal to 1.0 times the thickness of the substrate.

5. A semiconductor device described in any one of claims 1 to 4, wherein, when viewed in the thickness direction, the distance between the metal layer and the opposing edge is 0.25 times or more and 5.0 times or less the length of the opposing edge.

6. A semiconductor device described in any one of claims 1 to 5, wherein, when viewed in the thickness direction, the distance between the metal layer and the opposing edge is 0.02 times or more and 0.25 times or less the distance between the opposing edge and the island lead.

7. A semiconductor device described in any one of claims 1 to 6, wherein the substrate contains copper.

8. A semiconductor device described in any one of claims 1 to 7, wherein the metal layer contains silver.

9. A semiconductor device described in any one of claims 1 to 8, wherein the wire contains gold or copper.

10. The island lead has a first side perpendicular to the thickness direction, 10. The semiconductor device according to claim 1, wherein said terminal lead faces an end of said first side.

11. The semiconductor device according to claim 10 , further comprising an additional terminal lead facing the first side.

12. A semiconductor device described in any one of claims 1 to 11, wherein, when viewed in the thickness direction, the wire overlaps the opposing edge.

13. A semiconductor device as described in any one of claims 1 to 12, wherein, when viewed in the thickness direction, the wire overlaps the first portion.

14. A semiconductor device described in any one of claims 1 to 13, further comprising an insulating element that is conductive to the semiconductor element and is of an inductive type.

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