Register addressing information for data transfer instructions

Abstract

A data transfer instruction is provided that specifies register addressing information for identifying a target portion of register storage. In response to the data transfer instruction, instruction decode circuitry 30 controls processing circuitry to perform a data transfer operation to transfer data to or from the target portion of register storage. The register addressing information includes at least a base register identifier that identifies a base register of register storage for storing a base value, and an immediate value specified in the encoding of the data transfer instruction, the immediate value representing a value to be added to the base value to provide an index value for selecting the target portion of register storage. This can be useful for providing an instruction set architecture that supports code that is scalable to variable data structure sizes and supports loop unrolling.

Description

[Technical Field]

[0001] The present technique relates to the field of data processing.

[0002] Data transfer instructions can be used in data processing to control the transfer of data to or from register storage.

[0003] At least some examples provide an apparatus including instruction decode circuitry for decoding instructions; register storage for storing data; and processing circuitry for performing data processing in response to instructions decoded by the instruction decode circuitry and generating a processing result to be written to at least one register of the register storage, wherein in response to a data transfer instruction specifying register addressing information for identifying a target portion of the register storage, the instruction decode circuitry is configured to control the processing circuitry to perform a data transfer operation to transfer data to or from the target portion of the register storage, the register addressing information including at least a base register identifier that identifies a base register of the register storage for storing a base value, and an immediate value specified in an encoding of the data transfer instruction, the immediate value representing a value to be added to the base value to provide an index value for selecting the target portion of the register storage.

[0004] At least some examples provide a method that includes decoding an instruction and controlling processing circuitry, in response to the decoded instruction, to perform data processing to generate a processing result to be written to at least one register of a register storage, wherein in response to a data transfer instruction that specifies register addressing information for identifying a target portion of the register storage, the processing circuitry is controlled to perform a data transfer operation to transfer data to or from the target portion of the register storage, the register addressing information including at least a base register identifier that identifies a base register of the register storage for storing a base value, and an immediate value specified in an encoding of the data transfer instruction, the immediate value representing a value to be added to the base value to provide an index value for selecting the target portion of the register storage.

[0005] 1. A computer program for controlling a host data processing apparatus to provide an instruction execution environment for executing instructions of a target code, the computer program comprising: instruction decode program logic for controlling the host data processing apparatus to decode instructions of the target code and perform processing operations corresponding to the decoded instructions; and register emulating program logic for maintaining a register emulating data structure in host storage of the host data processing apparatus to emulate register storage of a target instruction set architecture associated with the target code, wherein in response to a data transfer instruction specifying register addressing information for identifying a target portion of the register storage, the instruction decode program logic is configured to control the host data processing apparatus to perform a data transfer operation to transfer data to or from a location in the register emulating data structure corresponding to the target portion of the register storage, the register addressing information including at least a base register identifier identifying a base register in the register storage for storing a base value, and an immediate value specified in an encoding of the data transfer instruction, the immediate value representing a value to be added to the base value to provide an index value for selecting the target portion of the register storage.

[0006] At least some examples provide a storage medium that stores the aforementioned computer program. The storage medium may be a temporary storage medium or a non-transitory storage medium. [Brief explanation of the drawings]

[0007] Further aspects, features, and advantages of the present technique will become apparent from the following description of examples, read in conjunction with the accompanying drawings. [Figure 1] 1 illustrates schematically a first example of a data processing device that supports matrix processing; [Figure 2A] 2 shows a second example of a data processing device that supports matrix processing. [Figure 2B] 2 shows a second example of a data processing device that supports matrix processing. [Figure 2C] 2 shows a second example of a data processing device that supports matrix processing. [Figure 2D] 2 shows a second example of a data processing device that supports matrix processing. [Figure 3] We show how to split a matrix multiplication operation into cross product operations to produce equivalent results. [Figure 4] An example cross-product engine is shown that performs a cross-product operation on a pair of vector operands, resulting in a two-dimensional (2D) array of data. [Figure 5] 1 illustrates an example of architectural registers for a processing unit, including vector registers for storing vector operands and array registers for storing 2D arrays of data. [Figure 6] 1 illustrates an example of a physical implementation of an array register. [Figure 7] It shows how the physical storage capacity of an array register can be logically divided into a variable number of architectural array registers. [Figure 8] It shows how the physical storage capacity of an array register can be logically divided into a variable number of architectural array registers. [Figure 9] It shows how the physical storage capacity of an array register can be logically divided into a variable number of architectural array registers. [Figure 10] It shows how the physical storage capacity of an array register can be logically divided into a variable number of architectural array registers. [Figure 11] It shows how the physical storage capacity of an array register can be logically divided into a variable number of architectural array registers. [Figure 12] 1 illustrates an example of a load / store data transfer instruction encoding for transferring a portion of a 2D array of data between array register storage and memory. [Figure 13]An example of encoding an array identifier and an immediate value using a combined field in the instruction encoding of a data transfer instruction is shown below. [Figure 14] An example of program code using the data transfer instructions of FIG. 12 is shown below. [Figure 15] 10 shows an example of a register move data transfer instruction for transferring a portion of a 2D array of data between an array register and a vector register. [Figure 16] FIG. 10 is a flow diagram illustrating a method of instruction processing. [Figure 17] An example of a simulator that can be used is shown.

[0008] The data processing apparatus may have instruction decode circuitry for decoding instructions in response to the decoded instructions and processing circuitry for performing data processing. Register storage may be provided for storing data. The register storage may be used to provide operands for processing by the processing circuitry. When the processing circuitry generates a processing result in response to the instruction, the processing result may be written to at least one register of the register storage.

[0009] Data transfer instructions are provided for transferring data to or from register storage. In response to the data transfer instructions, instruction decode circuitry controls processing circuitry to perform a data transfer operation. The data transfer operation includes transferring data to or from a target portion of register storage. The data transfer instruction specifies register addressing information that identifies the target portion of register storage.

[0010] In a typical data transfer instruction, the register to use as the target portion of register storage may be identified by a register field in the instruction encoding, where the value in the register field is an identifier that directly specifies the architectural register to / from which the data is to be transferred.

[0011] However, in the examples described below, the register addressing information includes at least a base register identifier that identifies a base register of register storage for storing the base value, and an immediate value that is specified directly in the encoding of the data transfer instruction and represents a value that should be added to the base value to provide an index value for selecting a target portion of register storage where data is to be transferred to or from memory.

[0012] This approach of using a base register and an immediate to define register addressing information will be understood to be counterintuitive by those skilled in the art of instruction set architecture design. While addressing based on a base register and an immediate value is known for memory addressing, it appears unnecessary for register addressing because it is assumed that the specific register accessed in a data transfer can be directly selected by the compiler of the program code being executed, thus eliminating the need to use indirection to the base register. However, the inventors have recognized that register addressing information that uses a base register to provide a base value for generating an index to select a target portion of register storage can be useful in enabling a compiler to generate code that can dynamically adapt to scalable data storage sizes.

[0013] Additionally, using an immediate value to provide an offset that is added to a base value when generating an index value can be useful in enabling a compiler to use a technique called loop unrolling, which can help reduce the overhead of controlling the iterations of a program loop. Each iteration of a loop can incur a performance cost in executing loop control instructions, such as instructions to increment a loop counter or other variable, such as a base value in a base register of a data transfer instruction, and in testing whether a loop termination condition is satisfied. By performing loop unrolling, a compiler can map a group of two or more iterations of a loop contained in high-level code written by a programmer into a single loop iteration in the compiled code that performs the same operations as the two or more iterations in the high-level code loop. This reduces the number of times loop control instructions need to be executed for a given number of loop iterations in the high-level code and also allows for greater instruction-level parallelism because some instructions from subsequent iterations of the loop in the high-level code, if independent, may be executed in parallel with instructions from previous iterations; on the other hand, if the loop is compiled in the compiled code into code that executes a single high-level loop iteration per loop iteration, the instructions for subsequent iterations of the high-level loop may depend on instructions from previous iterations, reducing the amount of possible parallelism. The use of base registers and immediate values ​​to define register addressing information is useful in supporting loop unrolling because the immediate values ​​can be used to add different offsets to values ​​in base registers of different data transfer instructions that correspond to unrolled versions of separate iterations of the high-level code loop that are combined into a single loop iteration in the compiled code.

[0014] Thus, in summary, data transfer instructions having register addressing information defined using a base register identifier and an immediate value as described above can be particularly useful in supporting scalable code that can scale to different data storage sizes and can enable compilers to perform loop unrolling.

[0015] The immediate value represents a value to be added to a base value to provide an index value for selecting a target portion of register storage. In some implementations of the instruction, the value to be added to the base value may be the exact value specified as the immediate value. In other examples, the immediate value may have an encoding that does not directly specify the value to be added. For example, the immediate value may specify the value to be added as a multiple of a given constant Z, such that the product of Z and the immediate value is added to the base value.

[0016] Also, in some examples, the index value may be equal to the sum of the base value and the value represented by the immediate value. In other examples, the index value may depend on the addition of the base value and the value represented by the immediate value, but may not be exactly equal to the sum of the base value and the value represented by the immediate value. For example, to accommodate values ​​outside the range of the base value, in some cases the index value may correspond to the result of summing the base value and the value represented by the immediate value modulo a given value chosen to ensure that the resulting index is within the required range (i.e., the index value is the remainder after dividing the sum by the given value).

[0017] Encoding register addressing information using a base register identifier and an immediate value may be applied to all forms of data transfer instructions, including data transfer instructions in which an index value is used to select which integer register, floating-point register, vector register, or other type of register storage is to be accessed in a data transfer.

[0018] However, in one example, the register storage includes 2D array register storage for storing at least one two-dimensional (2D) array of data, and the target portion of the register storage includes a target portion of the 2D array register storage. Thus, in this example, the data transfer instruction may be an array data transfer instruction for transferring at least a portion of the 2D array of data to or from the array register storage. 2D arrays, such as matrices, are useful in a wide range of processing applications. One example is the field of machine learning, where matrix multiplication may be the backbone of inference and training algorithms for many types of machine learning models, although other applications, such as fields like augmented reality, virtual reality, computer vision, computational photography, scientific simulation, and digital signal processing, may also use matrix arithmetic. Thus, support for matrix arithmetic is likely to be an important feature of upcoming processing applications, and thus, providing 2D array register storage designed to store 2D arrays of data may be useful in supporting such applications. The term "tile" is used in some examples below to refer to 2D arrays of data.

[0019] Data transfer instructions that include register addressing information, including a base register identifier and an immediate value, may be particularly useful in systems that support 2D array register storage, as applications that involve processing 2D arrays of data may need to be scalable to handle variations in array size in two dimensions of the array structure. By specifying register addressing information to identify a target portion of register storage using a base register identifier and an immediate value, it is possible to define program loops that can change which register is accessed depending on the variable array dimension, which may be useful for processing 2D arrays of data.

[0020] In one example, a data transfer operation performed in response to a data transfer instruction may include transferring a subportion of a target 2D array to or from a target portion of 2D array register storage, and an index value generated from a base value and an immediate value may identify which particular subportion of the target 2D array is to be transferred. For example, the base value and immediate value may be used to define a program loop that iterates over each subportion of the target 2D array.

[0021] For example, an index value may identify as a sub-portion a single horizontal group of elements that share the same vertical position in the target 2D array, or a single vertical group of elements that share the same horizontal position in the target 2D array. Other implementations may allow a single data transfer instruction to transfer multiple horizontal groups of elements or multiple vertical groups of elements of the target 2D array. In either case, by using a base register and an immediate value to select which sub-portion of the target 2D array to transfer, this makes it easier for software to be scalable to different array dimensions (different numbers of rows or columns).

[0022] In this application, the terms "horizontal" and "vertical" are used to refer to the "row" and "column" orientation of a 2D array from the perspective of the 2D array register storage. Rather, "horizontal" and "vertical" orientation refer to the logical arrangement of elements within the 2D array, in the sense that computational instructions or instructions for transferring 2D arrays to / from memory take into account the logical location of each element within the 2D array. However, it will be understood that the physical layout of the register storage need not necessarily be arranged on a 2D grid of storage elements. Storage elements may be physically placed in any convenient location within the integrated circuit layout.

[0023] The "horizontal" and "vertical" directions associated with a 2D array stored in a 2D array register storage do not necessarily correspond to the same row / column layout of the matrix data structure stored in memory. Matrix data can be stored in memory in different layouts, such as row-major order or column-major order. In row-major order, adjacent elements in a row of the matrix are stored at consecutive addresses in memory, while adjacent elements in a column of the matrix are offset in memory by a stride value. Conversely, in column-major order, adjacent elements in a column of the matrix are stored at consecutive addresses in memory, while adjacent elements in a row of the matrix are offset in memory by a stride value.

[0024] Thus, when data is read from memory, it can be in either row-major order (so that consecutive memory elements read into the register storage represent a row or part of a row of the underlying matrix structure in the memory) or column-major order (so that consecutive memory elements read represent a column or part of a column), but either way it is possible to write elements to horizontal groups of elements or vertical groups of elements in the 2D array register storage.

[0025] It will thus be appreciated that a horizontal group of elements in the 2D array register storage can represent either a row or a column of elements from a matrix structure in memory (or a newly calculated set of elements that may later be written back to either a row or a column of elements in the matrix structure in memory). Similarly, a vertical group of elements in the 2D array register storage can represent either a row or a column of elements from the underlying matrix structure stored in memory (or can represent newly calculated values ​​to be written back to such a row or column). To avoid confusion, the terms "row" and "column" are used to refer to the arrangement of matrix elements in memory, and "horizontal group" and "vertical group" may be used to refer to the arrangement of elements in the 2D array stored in the 2D array register storage.

[0026] In some implementations, the data transfer instructions may only support transferring data to / from the 2D array register storage in one of the horizontal / vertical directions. For example, some implementations may only support accessing the 2D array register storage in the horizontal direction. This may simplify the circuit logic for accessing the 2D array register storage.

[0027] However, in other examples, an Instruction Set Architecture (ISA) may support reading / writing 2D array register storage in both horizontal and vertical directions. Thus, a data transfer instruction may specify an array direction identifier that identifies one of the horizontal and vertical directions. When the array direction identifier identifies a horizontal direction, a subportion of the target 2D array includes at least one horizontal group of elements of the target 2D array identified by an index value, where each horizontal group of elements includes elements that share the same vertical position within the target 2D array. When the array direction identifier identifies a vertical direction, a subportion of the target 2D array includes at least one vertical group of elements of the target 2D array identified by an index value, where each vertical group of elements includes elements that share the same horizontal position within the target 2D array. This can be useful to enable on-the-fly transposition of matrices at the time of transferring data from memory to 2D array register storage, or when transferring data from 2D array register storage back to memory, which can help improve performance of applications where the matrix memory layout is incompatible with the computational requirements, whereby on-the-fly transposition can be much faster than executing numerous load / store or vector permute instructions to shuffle elements when transferring matrix data between memory and register storage.

[0028] Data transfer instructions may be used in embodiments that handle 2D arrays defined with a certain fixed data element size, where element size refers to the number of bits in one single element of the 2D array.

[0029] However, it may be useful to support variable data element sizes so that the data transfer instructions can be used in applications that may process matrices defined using data values ​​of different levels of precision. Thus, the data transfer instructions may be associated with a current data element size E specified for the data transfer instruction from among two or more data element sizes supported by the processing circuitry.

[0030] The current data element size E may be specified for a data transfer instruction in a variety of ways. In some cases, a parameter of the data transfer instruction itself may specify the current data element size E. For example, part of the instruction encoding of the data transfer instruction may specify the current data element size E. Another option is that control information stored in a control register or other storage location may define the current data element size E. In this case, the encoding of the data transfer instruction itself need not include any bits identifying the current data element size E. An instruction executed prior to execution of the data transfer instruction may be used to set a value in a control storage location to set the current data element size E used for a subsequent data transfer instruction. Some approaches may also use a mode approach, where the current data element size used depends on the operating mode of the processing circuitry that is operating when executing the data transfer instruction. Thus, it will be appreciated that there are a variety of ways in which the current data element size E for a given data transfer instruction may be identified.

[0031] In implementations that support variable data element sizes, the immediate value of the register addressing information is a fixed number of bits N in the instruction encoding of the data transfer instruction. imm can be encoded using N imm is a variable depending on the current data element size E, and decreases as E decreases immincreases. This technique can be particularly useful when an immediate value is used to generate an index that identifies which subportion of a target 2D array should be transferred in a data transfer performed in response to a data transfer instruction. As the data element size decreases, this means that more data elements can fit within a register of a given size, supporting 2D arrays with a larger dimension in the first horizontal / vertical direction, corresponding to the width of the register. Increasing the size of the immediate value as the element size decreases allows a larger subportion of the target 2D array to be selected, allowing the second dimension of the 2D array in the opposite vertical / horizontal direction to scale comparable to the scaling in the first direction. By using an encoding of the immediate value with a variable length, such that the immediate value is encoded using fewer bits when the data element size is larger than when the data element size is smaller, at larger element sizes this may free up some extra bits that can be used to encode other parameters.

[0032] In one example, a 2D array register storage is a fixed number N R A vector register may include vector registers, each containing a fixed number of bits MVL (MVL indicates the "vector length" of a single vector register). By implementing 2D array register storage as a group of vector registers, this can simplify the implementation of the processor's microarchitecture, as techniques for providing vector registers used to store 1D arrays of data as vectors can be reused to implement 2D array register storage. For example, a single 2D array of data may be represented within a group of vector registers, with each vector register in the group storing a different horizontal (or vertical) group of elements of the 2D array, and the group of vector registers collectively storing multiple such groups of elements to form the 2D array.

[0033] In some implementations, the ISA supported by the processing circuitry and instruction decode circuitry may support variable vector length MVL for vector registers in 2D array register storage. This allows microarchitecture designers to vary the size of registers used on a given microarchitecture processor implementation depending on design preferences, such as prioritizing higher performance or higher energy efficiency. For example, an ISA may support a minimum vector length MVL. min to maximum vector length MVL max It can support a range of vector lengths ranging from

[0034] To simplify software development, it may be useful to design an ISA so that program code can run correctly on various processors that use different vector length MVLs without requiring any program code modifications to account for such differences in vector length. This property is sometimes referred to as vector-length-agnostic program code. For example, an ISA may support a register that indicates the vector length implemented on the current platform; this vector length may be static for a given implementation but may vary between processor implementations; program code may reference that register when controlling program code loops to vary how much data is processed per loop iteration depending on the implemented vector length MVL. Thus, a program with a given amount of data to process may process that data using fewer loop iterations on a microarchitecture that implements a longer vector length than on a microarchitecture that implements a shorter length, but in both cases, perform the same functional processing operations to produce the same computational results (albeit at different levels of performance).

[0035] The immediate value can represent which sub-portion of the 2D array should be transferred. Since the number of elements that can fit in a vector register increases as the vector length MVL increases, the immediate value must be limited to the maximum vector length MVL (to allow the other dimensions of the 2D array to scale similarly). max One might think that when implemented, a sufficient number of bits should be provided to be able to distinguish between the number of vector registers corresponding to the number of elements that can fit within one vector register.

[0036] However, we have found that in practice the number of distinct encodings of immediate values ​​is MVL min / E(Minimum vector length supported by ISA MVL min If the vector register size is greater than the number of elements in the MVL register, min / E is the minimum vector length MVL min We realized that this would mean that the program code would no longer be vector-length agnostic, since it would be unable to run correctly on microarchitectures that implement MVL. Therefore, in an ISA designed to be vector-length agnostic, there is no value in using the additional bits in the instruction encoding to provide larger immediate values. The number of distinct encodings is MVL. min By restricting the number of bits in the immediate value encoding to be less than or equal to / E, this frees up encoding bit space for other parameters and improves support for vector length agnosticism.

[0037] Of course, it is still possible for the aforementioned data transfer instructions to support larger values ​​of immediates if they are implemented in an ISA where vector length agnosticism is not preferred.

[0038] In some instances, an index value generated based on the base and immediate values ​​of the register addressing information may be the only item of register identification information used to select the target portion of the register storage where the data transfer should be performed. For example, the index value may specify the register identifier of an individual vector register within the aforementioned 2D array register storage. In this approach, the group of vector registers may be considered as a whole to form a 2D array of data, such as a matrix, but an instruction may reference an individual horizontal / vertical group of elements of the array by specifying the particular register identifier of the vector register used to store that group of elements.

[0039] However, certain programming techniques require processing multiple 2D arrays rather than individual horizontal / vertical groups of elements. Therefore, another approach may be for the 2D array register storage to be logically divided into at least two array storage areas, each storing a respective 2D array. In addition to an index value, the register addressing information may also include an array identifier that identifies a selected array storage area of ​​the 2D array register storage. In this case, the index value may identify which subportion of the selected array storage area is the target portion of the register storage. Thus, a data transfer instruction may specify the array ID of the array to be accessed for the data transfer, and an index value defined using a base register and an immediate may be used to select individual horizontal / vertical groups of elements from that array. This approach may make it easier for software to define program loops that loop over each horizontal / vertical group of elements in the array to transfer 2D arrays to and from register storage.

[0040] In some implementations, the division of the 2D array register storage into array storage regions may be fixed, such that a given array identifier always corresponds to a particular fixed portion of the 2D array register storage. For example, when the 2D array register storage is implemented using a set of vector registers as described above, each array storage region may correspond to a fixed block of vector registers.

[0041] However, in implementations that support variable data element sizes, such as those described above, it may be useful to use a variable mapping for dividing the 2D array register storage into array storage regions that depends on the current data element size. The processing circuitry may identify which portion of the 2D array register storage is the array storage region that corresponds to a given value of the array identifier based on the variable mapping that depends on the current data element size E specified for the data transfer operation. This may help improve performance by improving the utilization of available register capacity implemented in hardware.

[0042] As noted above, when the data element size E is variable, this means that a single register can store a variable number of data elements, but it may be desirable for the second dimension of the array to be scaled similarly. Thus, if a larger number of elements can fit within one vector register (representing either the horizontal or vertical dimension), the array will span a larger number of vector registers (representing the array's other horizontal / vertical dimension). If a larger number of vector registers are allocated to represent a single 2D array structure, this means that fewer 2D arrays in total can be accommodated within the available register storage capacity of the 2D array register storage as a whole. On the other hand, as the data element size increases, each vector register can store fewer data elements in the first dimension of the array, and therefore fewer vector registers are required to accommodate the other dimension of the array, allowing a larger number of separate 2D arrays to fit within the available hardware storage capacity. If a fixed mapping between array identifiers and array storage regions were used, each storage region would have to be large enough to store a 2D array at the minimum data element size, which would waste storage capacity if larger element sizes were used. As mentioned above, by using a variable mapping between array identifiers and array storage regions, the partitioning can be adjusted to fully utilize available register capacity, which can help improve performance because when more arrays can fit within register storage, the number of (slower) load / store instructions executed per computational instruction can be reduced.

[0043] In one example, a 2D array register storage is a fixed number N A may be logically divided into N array storage areas, A may vary depending on the current data element size E, and N Aincreases as E increases. This relationship may seem counterintuitive, since one would normally (in vector processing) assume that the number of partitions decreases as the data element size increases. However, in 2D array processing, while the number of elements that fit within a single register in the first dimension decreases as the element size E increases, in the second dimension where elements are striped across vector registers, each element requires a single vector register regardless of its element size, and therefore the number of vector registers used for a single 2D array in the second dimension actually decreases as the element size increases. Therefore, the total number of array storage regions (N) that can fit in a fixed amount of physical storage A ) can increase as the element size increases.

[0044] Because smaller element sizes require less array storage space to distinguish than larger element sizes, the array identifier encoded by the data transfer instruction may also have a variable number of bits that depends on the current data element size E. However, the number of bits required for the array identifier may have an inverse relationship to the current data element size E compared to the relationship for immediate values ​​discussed above. The array identifier may have more bits in larger data element sizes than in smaller data element sizes, while the immediate value may have more bits in smaller data element sizes than in larger data element sizes.

[0045] Thus, while some implementations of data transfer instructions may encode the array identifier and the immediate value using two separate, non-shared fields in the instruction encoding, one particularly efficient encoding may be to encode the array identifier and the immediate value using a shared portion of bits in the instruction encoding of the data transfer instruction. For a given bit in that shared portion, the instruction decode circuitry varies whether the given bit is interpreted as the designating portion of the array identifier or the designating portion of the immediate value depending on the current data element size E specified for the data transfer instruction. This helps reduce the total number of bits required to represent both the array identifier and the immediate value, freeing up other bits in the instruction encoding for other purposes. This can be very beneficial in ISA designs, where encoding space is typically at a premium.

[0046] In some examples, the total number of bits in the instruction encoding of a data transfer instruction used to encode the array identifier and the immediate value may be constant regardless of the current data element size E.

[0047] In some examples, the data transfer instruction may be a load / store instruction that specifies register addressing information and memory addressing information to identify a target portion of memory, where the data transfer operation includes transferring data between the target portion of register storage and the target portion of memory, where the memory addressing information may be defined according to any known memory addressing mode (e.g., using a base register and an offset register, or a base register and an immediate value, to define the memory address(es) to be accessed).

[0048] Alternatively, the data transfer instruction may be a register move instruction that specifies register addressing information and further register addressing information for identifying the further portion of register storage, and the data transfer operation may include transferring data between the target portion of register storage and the further portion of register storage. In this case, the target portion of register storage may be identified using a base register identifier as described above, but the further addressing information need not include the base register identifier. For example, the further addressing information may simply be a register identifier that directly specifies a register to be accessed as the further portion of register storage. For example, in an example where the target portion of register storage is part of the aforementioned 2D array register storage, the further portion of register storage may be a vector register.

[0049] Thus, data transfer instructions can be used to transfer data between register storage and memory, or between respective portions of register storage. Some ISAs may support only one of load / store and register move instructions that use a base register identifier and an immediate value as part of the register addressing information (other types of instructions do not use addressing based on a base register identifier and an immediate). Other ISAs may support both load / store and register move instructions that use register addressing information that includes a base register identifier and an immediate value.

[0050] It will be appreciated that data transfer instructions that include register addressing information, including a base register identifier and an immediate value, may not be the only type of data transfer instruction supported in an ISA implemented by the instruction decode and processing circuitry. There may be other types of data transfer instructions that do not use a base register identifier and an immediate value to define an index used to select the portion of register storage to access in a data transfer.

[0051] The base register identified in the register addressing information may be a scalar register, which is a register intended to store a single data value (as opposed to a vector register, which may be divided into multiple independent data elements, each data element representing a separate data value).

[0052] In some implementations, the scalar register may be selected from among a particular pool of scalar registers available for selection by an instruction. For example, a scalar computation instruction may have a K-bit scalar register field to specify a particular scalar register that stores the operands or result of the instruction as the source or destination register of the instruction. With a K-bit scalar register field, this allows the system to K This may allow for supporting different scalar registers.

[0053] In some implementations, the number of distinct scalar registers supported in the ISA is 2. K If , the number of bits used for the base register field of the register addressing information may be K bits so that any of the supported scalar registers can be selected as the base register.

[0054] However, in other examples, the data transfer instruction can specify a base register using an L-bit scalar register field, and at least one scalar register that can be specified as a source or destination register for at least one scalar computation instruction cannot be specified as the base register for the register address specification information for the data transfer instruction, such that L < K. That is, the base register field is a compressed field that is shorter than the number of bits required to enable selection of any scalar register supported in the architecture. This can serve to free up bits in the instruction encoding for other purposes. In practice, restricting the base register to be selected from a limited subset of scalar registers may be sufficient to handle the expected use cases of applications such as matrix processing.

[0055] The instruction decode circuitry can support a 2D array-generating computation instruction, and in response, the instruction decode circuitry controls the processing circuitry to perform a computation operation that generates a 2D array of result values ​​to be written to the 2D array register storage. The 2D array of result values ​​can be generated in response to a single instance of the 2D array-generating computation instruction. In a system that can support generating a 2D array of values ​​in response to a single instruction, processing throughput can be much greater than in implementations where vector processing is used to process a single 1D array of data at a time. This can be particularly useful for applications such as machine learning and signal processing, as described above. For example, the computation operation can be a matrix multiplication operation in which the input operands of the computation are 2D arrays of data and the result is a 2D array representing the result of multiplying the matrices represented by the 2D array operands. However, in other examples, the computation operation can include a cross product operation performed on first and second vector operands to generate a 2D array of result values. Performing a cross product operation in hardware can be simpler than performing a full matrix multiplication. Accumulating the results of a sequence of cross product operations can generate a result equivalent to a matrix multiplication. Thus, a computation instruction may be a cross-product and accumulate instruction that not only generates the cross product of two vectors, but also adds the resulting elements to an accumulator 2D array of elements (e.g., stored in one of the 2D array storage areas of the register storage described above). Data transfer instructions of the type described above are particularly useful in systems that support such 2D array-generating computation instructions, as they allow efficient access to individual horizontal / vertical groups of elements in the 2D array registers. The encoding of the data transfer instructions allows such accesses to be unrolled and scheduled by the compiler, while still being able to dynamically adapt to scalable array sizes.

[0056] The techniques described above may be implemented in a data processing apparatus having hardware circuitry provided for implementing the instruction decoder and processing circuitry described above.

[0057] However, the same technique may also be implemented in a computer program that runs on a host data processing device to provide an instruction execution environment for the execution of target code. Such a computer program may control a host data processing device to simulate the architectural environment that would be provided on a target data processing device that actually supports target code according to a particular ISA, even if the host data processing device itself does not support that architecture. Such a simulation program is useful, for example, when legacy code written for one ISA is being executed on a host process that supports a different ISA. Running software on a simulated execution environment may also enable testing of software in parallel with the ongoing development of hardware that supports the new architecture, so that simulation may allow software development of a new version of an ISA to begin before the processing hardware that supports the new architecture version is ready. The simulation program may be stored on a storage medium, which may be a non-transitory storage medium.

[0058] Thus, the computer program may include instruction decoding program logic that decodes program instructions of the target code and controls the host data processing apparatus to perform data processing in accordance with the program instructions (e.g., mapping each instruction of the target code to a sequence of one or more instructions in the host's native instruction set that perform equivalent functionality). The computer program may also have register emulating program logic that maintains data structures in host storage of the host data processing apparatus (e.g., in the host's registers or memory) that are expected to be provided in hardware in a processor that actually supports the target ISA, to emulate the register storage of the target ISA being simulated.

[0059] In such an implementation, the instruction decode program logic may support data transfer instructions having the same register addressing information as described above, but in this case, references to register storage based on the register addressing information are mapped by the register-emulating data structure to corresponding locations in the register-emulating data structure stored in host storage. Thus, the base register identifier and the immediate value may be used to identify which portion of the emulated register should be accessed in the data transfer of the data transfer instruction, whose execution on the target processing unit is being simulated on the host device.

[0060] 1 illustrates a schematic diagram of an example data processing device 20. The data processing device has a processing pipeline 24 that includes several pipeline stages. In this example, the pipeline stages include a fetch stage 26 for fetching instructions from an instruction cache 28, a decode stage 30 (instruction decode circuitry) for decoding the fetched program instructions to generate micro-ops that are processed by the remaining stages of the pipeline, an issue stage 32 for checking whether operands required for the micro-op are available in a register file 34 and for issuing the micro-op for execution once the operands required for a given micro-op are available, an execute stage 36 (processing circuitry) for performing a data processing operation corresponding to the micro-op by processing the operands read from the register file 34 to generate a result value, and a writeback stage 38 for writing the results of the processing back to the register file 34. It will be appreciated that this is merely one example of a possible pipeline architecture and that other systems may have additional stages or different configurations of stages. For example, an out-of-order processor may include a register renaming stage for mapping architectural registers specified by program instructions or micro-ops to physical register specifiers that identify physical registers in register file 34.

[0061] The execution stage 36 includes several processing units for performing different classes of processing operations. For example, the execution units may include a scalar arithmetic / logic unit (ALU) 40 for performing arithmetic or logical operations on scalar operands read from the registers 34, a floating-point unit 42 for performing operations on floating-point values, a branch unit 44 for evaluating the results of branch operations and adjusting a program counter representing the current execution point accordingly, a matrix processing unit 46 for matrix processing (described in more detail below), and a load / store unit 48 for performing load / store operations to access data in the memory systems 50, 52, 54.

[0062] In this example, the memory system includes a level 1 data cache 50, a shared level 2 cache 52, and a main system memory 54. It will be understood that this is only one example of a possible memory hierarchy and that other arrangements of caches can be provided. The particular types of processing units 40-48 shown in the execution stage 36 are merely an example; other implementations may have different sets of processing units or may include multiple instances of the same type of processing unit such that multiple micro-operations of the same type can be processed in parallel. It will be understood that FIG. 1 is only a simplified representation of some components of a possible processor pipeline architecture and that a processor may include many other elements that are not shown for the sake of brevity.

[0063] In some implementations, data processing device 20 may be a multiprocessor device including multiple CPUs (Central Processing Units, or processor cores) 60, each having a processing pipeline 24 similar to that shown for one of CPUs 60 in Figure 1. Device 20 may also include at least one Graphics Processing Unit (GPU) 62 and / or other master devices 64 that can communicate with each other and with the CPUs via an interconnect 66 used to access memory 54.

[0064] One approach to supporting matrix processing operations may be to decompose the individual multiplications of a given matrix processing operation into separate scalar integer or floating-point instructions that can be processed on the processing pipeline 24 of a given CPU 60. However, this may be relatively time consuming.

[0065] Another approach to accelerating matrix processing may be to provide a hardware accelerator with dedicated hardware designed to handle matrix operations as one of the devices 64 connected to the interconnect 66. To interact with such a hardware accelerator, the CPU 24 executes load / store instructions using the load / store unit 48 to define the matrix operands to be read from memory by the hardware accelerator and writes configuration data to memory 54 (memory-mapped registers within the hardware accelerator) defining the processing operations to be applied to the operands. Once the hardware accelerator has completed performing the matrix processing, the CPU 60 can then read back the results of the matrix processing from the hardware accelerator using a load instruction that specifies an address mapped to a register within the hardware accelerator. While this approach may be faster than using integer operations in a pipeline, there may nevertheless be overhead associated with using a load / store mechanism to transfer information between the general-purpose processor 60 and the hardware accelerator 64, and the hardware accelerator approach may pose challenges when different virtual machines running on the same processing system need to share access to the hardware accelerator. Therefore, this approach may not scale well in virtualization implementations with several virtual machines.

[0066] 1, within the normal processing pipeline 24 of a given CPU 60, it is possible to provide matrix processing circuitry 46 that is controllable to perform matrix operations in response to matrix operation program instructions decoded by the pipeline's decode stage 30 (similar to controlling normal integer or floating point arithmetic operations using the ALU 40 or floating point unit 42). This avoids the need to transfer data back and forth between the CPU 60 and a hardware accelerator, making it much easier to enable many different virtual machines to perform matrix operations.

[0067] Although FIG. 1 shows a multiprocessor device 20 having several CPUs 60, this is not required and the matrix processing circuitry 46 can also be implemented in a single-core system.

[0068] In the example of FIG. 1, the matrix processing functionality is provided within the CPU 60 itself.

[0069] 2A-2D show a second example of a data processing device in which each CPU 60 does not itself have matrix processing functionality, but matrix processing is supported in a coprocessor 70 connected to the CPU 60 via interconnect 66. This approach can be useful for reducing the hardware cost of implementing matrix processing functionality, since the hardware resources used to support matrix processing in the coprocessors 70 can be shared among the CPUs 60. To enable the coprocessors 70 to access memory using address translation data corresponding to that used by the CPU 60 itself, a memory management unit (MMU) 72 can be provided as a separate block shared between the CPU 60 and the coprocessor 70, as shown in FIG. 2A, or as each CPU 60 and coprocessor 70 has its own MMU 72 that can be loaded with address translation data from a common set of page tables in memory, as shown in FIG. 2B. Note that, although not shown in FIG. 1 for simplicity, in that example, the CPU 60 could also have an internal MMU 72. Also, in some examples, translation of addresses used in coprocessor load / store operations could be performed by an MMU in CPU 60, with the resulting physical addresses being passed along with the load / store instructions to coprocessor 70. MMU 72 translates a virtual address identified based on memory addressing information specified by a program instruction into a physical address that identifies the location to be accessed in memory 54. MMU 72 may also implement a permission check to check whether program code is permitted to access a given memory address.

[0070] Figure 2C shows CPU 60 in the example of Figures 2A / 2B. Elements that are the same as elements in Figure 1 are designated with the same reference numerals. In this example, scalar execution units 40, 42, 44 shown in Figure 1 are collectively referred to as scalar processing circuitry, which performs operations on scalar operands stored in scalar registers 80. Execution stage 36 also includes vector processing circuitry 76 for performing vector processing operations on vector operands stored in vector registers 82. Vector processing circuitry 76 and vector registers 82 are not shown in Figure 1, but they may also be provided in that example.

[0071] 2A-2D, the processing unit supports processing of programs in either a non-matrix or a matrix processing mode. Instructions processed in the non-matrix processing mode are issued by issue circuitry 85 of issue stage 32 of CPU 60 for execution by processing units in execution stage 36.

[0072] However, instructions to be processed in matrix processing mode are forwarded by a coprocessor interface 87 in issue stage 32 of CPU 60 to a queue manager 84 in coprocessor 70 (as shown in FIG. 2D ). Queue manager 84 passes the instructions to a pipeline in coprocessor 70 that includes instruction decode circuitry 30, issue circuitry 32, execution stage 36, and writeback circuitry 38 similar to those of CPU 60, although the pipeline in coprocessor 70 may support a different subset of instructions of the ISA compared to CPU 60. For example, coprocessor 70 may support a more restricted instruction set than CPU 60 in order to limit the complexity of the coprocessor while still supporting operations expected to be useful for matrix processing.

[0073] The CPU 60 in this example does not support any matrix processing calculation instructions; instead, matrix processing calculation instructions are supported by the matrix processing execution unit 86 in the coprocessor 70. The selection of whether a program is currently running in matrix processing mode or non-matrix processing mode can be made based on a specific mode control instruction that enables / disables the matrix processing mode.

[0074] To support matrix processing, coprocessor 70 has matrix registers (2D array registers) 88 designated to store 2D arrays (matrices) of data. Data transfer instructions that transfer portions of matrices between matrix registers 88 and memory 54 or between matrix registers 88 and other types of registers (such as vector registers 82) are restricted to executing in matrix processing mode. Although not shown in FIG. 1, in embodiments in which the CPU itself supports matrix processing, CPU 60 may similarly have matrix registers 88 within its registers 34.

[0075] The vector length of vector registers 82 in coprocessor 70 need not be the same as the vector length of vector registers 82 in CPU 60. Because matrix processing operations may be more efficient with larger vector lengths (enabling greater data throughput), in some cases a processor designer may wish to select a vector length VL2 for vector registers 82 (and the vector registers used to provide the coprocessor's matrix registers 88) that is longer than the vector length VL1 used for vector registers 82 in CPU 60. Nevertheless, the ISA may support variable vector lengths VL1, VL2 for non-matrix and matrix processing modes, both of which may be selected for a given hardware implementation from among the range of vector lengths supported by the ISA (in some cases, the range available for selection as VL1 may not be the same as the range available for selection as VL2, although the ranges may overlap. Thus, it may be possible for a particular implementation to select VL1=VL2). Vector control registers (ZCR, ZCR') 81, 81' may be provided within the CPU 60 to indicate the respective vector lengths VL1, VL2 to be used in the non-matrix and matrix processing modes, respectively.

[0076] Program code defined according to the ISA may function equally well on both hardware implementations (either the matrix processing implemented within the CPU 60 of FIG. 1 or the example coprocessor of FIGS. 2A-2D). When executed on an implementation such as that shown in FIG. 1, the mode select instruction may be treated as a non-operational instruction, and the vector length implemented for any vector register may be the same in both modes (since the same register is used in both modes). When executed on an implementation such as that shown in FIGS. 2A-2D, the mode select instruction may signal that the instruction should be forwarded to the coprocessor for execution, and it may be useful to support different vector lengths VL1, VL2 in the two modes. In either case, from a software developer's perspective, matrix processing is performed by the matrix processing logic 46, 86 in response to regular CPU instructions (computation / arithmetic instructions) that define register-to-register operations that act on operands stored in registers and produce results that are written back to the registers. This makes controlling matrix processing much simpler than implementations that perform matrix processing using a hardware processor controlled based on load / store instructions, which may require specialized software drivers to implement matrix processing. Of course, even in a system with a CPU 60 or coprocessor that has ISA support for register-to-register arithmetic instructions that perform matrix operations, it is still possible to provide a dedicated hardware accelerator as device 64 accessible via interconnect 66 using load / store instructions to provide additional support for forms of matrix operations not supported by the ISA's register-to-register arithmetic instructions, but such a hardware accelerator is not required.

[0077] Figure 3 shows an example of matrix multiplication between a first matrix A and a second matrix B to produce a result matrix C. In this example, the matrices are all square matrices of 4x4 dimensions in the particular example, although this is not required. For a matrix multiplication operation C=AB where A is an mxn matrix and B is an nxp matrix, C is an mxp matrix and a given element at position (i,j) of C is the i element of matrix A. th(i)th row and j of matrix B th corresponds to the result of adding the pairwise products of the elements of the (jth) column of ij teeth,

[0078]

number

[0079] It is possible to produce an equivalent result by performing a series of cross-product operations, as shown on the right side of Figure 3. In contrast, a cross-product operation operates on a first vector operand u = (u1, u2, ..., u m ) and the second vector operand v=(v1,v2,...,v n ) and combine them to form a two-dimensional result matrix W,

[0080]

number

[0081] Thus, in some examples, the matrix processing unit 46, 88 of the processing circuitry (in any of the examples of FIGS. 1 and 2A-2D) may include a cross product engine, such as that shown in FIG. 4, to perform a cross product operation. The cross product engine takes as input a first vector operand opa associated with a first predicate value Pa and a second vector operand opb associated with a second predicate value Pb. The result output by the cross product engine is a 2D array (matrix) C'. The result matrix may be stored in 2D array register storage provided for storing 2D arrays (e.g., matrix register 88 shown in FIG. 2D, which is also provided in register 34 in the example of FIG. 1). The previous value stored in each element of the result array storage C can also serve as input to the operation to perform a cross product and accumulate operation to generate a given element C'[i,j] according to the formula shown in Figure 4, where Pa[i].opa[i] indicates that element i of opa is predicated by element i of Pa, and Pb[j].opb[j] indicates that element j of opb is predicated by element j of Pa. For a cross product instruction that performs a merge predicate, when a predicate element Pa[i] or Pb[j] is indicated as inactive, the corresponding element C'[i,j] retains its previous value. It is also possible to implement a zero predicate, in which the element C'[i,j] of the result matrix corresponding to the inactive predicate element Pa[i] or Pb[j] is set to 0, overwriting the previous value C[i,j] at that element position. Predicates can be useful, for example, when matrix processing reaches the end of the matrix structure and the number of elements to be processed is not sufficient to fill the entire matrix supported by the hardware. 4 is useful because it simplifies the implementation of hardware support for matrix multiplication operations; the accumulation means that it is not necessary to store each cross-product result separately and then add them as a final step. However, the cross-product engine shown in FIG. 4 is only an example, and other implementations of the matrix processing engine 46, 88 may provide support for performing a full matrix processing operation in a single instruction. However, as noted above, in practice, the cross-product operation may be easier to implement.

[0082] 5 shows an example of the architectural registers 34 of a CPU 60 or coprocessor for supporting matrix operations. The architectural registers (as defined in the ISA) may include a set of scalar integer registers that serve as general purpose registers for ALU operations performed by ALU 40 or other instructions processed in the pipeline. For example, a certain number of general purpose registers may be provided, e.g., 31 registers X0-X30 in this example (32 of the scalar register field). nd (The 32nd encoding may not correspond to a register provided in hardware, for example, because it may be considered to indicate a value of 0 by default, or may be used to indicate a special-purpose register rather than a general-purpose register.) It may be possible to access scalar registers of different sizes that are mapped to the same physical storage. For example, register labels X0 through X30 may refer to 64-bit registers, but the same registers may also be accessed as 32-bit registers (e.g., accessed using the lower 32 bits of each 64-bit register provided in hardware), in which case register labels W0 through W30 may be used in assembler code to refer to the same registers.

[0083] Additionally, the architectural registers supported by decoder 30 and available for selection by program instructions within the ISA may include a fixed number of vector registers 82 (labeled Z0 through Z31 in this example). Of course, providing the number of scalar / vector registers shown in FIG. 5 is not required, and other examples may provide a different number of registers that can be specified by program instructions. Each vector register may store vector operands that include a variable number of data elements, each of which may represent an independent data value. In response to vector processing (SIMD) instructions, the processing circuitry may perform vector operations on the vector operands stored in the registers to generate a result. For example, vector processing may include lane-by-lane operations, in which a corresponding operation is performed on each lane of elements in one or more operand vectors to generate a corresponding result of the elements of the result vector. When performing vector or SIMD operations, each vector register may have a fixed vector length VL, where the vector length refers to the number of bits in a given vector register (e.g., the vector length VL of a vector instruction may be the first vector length VL1 described above with reference to FIGS. 2A-2D). The vector length VL used in vector processing mode may be fixed for a given hardware implementation or may be variable. The ISA supported by CPU 60 may support variable vector lengths, so that different processor implementations may choose to implement vector registers of different sizes, but the ISA may be vector-length agnostic, so that instructions are designed so that code can function correctly regardless of the specific vector length implemented on a given CPU that executes the program. For example, there may be a control register (e.g., ZCR81) that stores a value indicating the specific vector length VL used for vector processing instructions. This register can be read by software to control a loop that iterates through the processing of a fixed number of elements, so that an implementation with a longer vector length may process a given number of elements in fewer loop iterations than an implementation with a shorter vector length.

[0084] Vector registers Z0-Z31 may also function as operand registers for storing vector operands that provide input to the outer product operations performed by the outer product engines 48, 86, as described above with respect to FIG. 4 . When vector registers are used to provide input to an outer product operation or other matrix operation, the vector registers have a matrix vector length MVL, which may be the same as the vector length VL used for the vector operation or may be a different vector length (e.g., VL2, instead of VL1, as described above for mode functionality in embodiments using the coprocessor 70). By providing architectural support at the ISA level to support different vector lengths for SIMD and matrix operations, this may provide processor microarchitects more flexibility to select different physical implementations, including the option to perform matrix operations using the coprocessor 70, as described above. The ISA may support a mode select instruction that can select whether the processor is operating in a matrix processing mode or a non-matrix processing mode, which, when implemented, may be useful for configuring the CPU to offload processing to a coprocessor. In this case, the mode select instruction may, among other functions, trigger a switch in the current vector length implemented, selecting one of VL and MVL depending on the current mode. Vector control registers 81, 81' may be provided to indicate the particular vector lengths to be used as VL and MVL for each mode.

[0085] Thus, in general, the vector length MVL described in subsequent examples is the vector length used in the matrix processing mode, which may or may not be the same as the vector length VL used in other modes. A control register may store a value indicating the matrix vector length MVL of the current processor implementation, which may be made available to software to control program loops.

[0086] As shown in Figure 5, the architecture registers are also a fixed number NA Array register 88, ZA0 to ZA(N A -1). Each array register can be considered a set of register storage for storing a single 2D array of data, such as the result of the cross product operation described above. However, the cross product operation may not be the only operation for which an array register can be used. Array registers can also be used to store arrays when performing row / column transpositions of matrix structures in memory. When a program instruction references one of the array registers 88, it is referenced as a single entity using the array identifier ZAi, although some types of instructions (e.g., data transfer instructions) can also select a subportion of the array by defining an index value that selects a portion of the array (e.g., one horizontal / vertical group of elements).

[0087] Figure 5 shows an architectural diagram of the array register from a software perspective. However, as shown in Figure 6, in reality, the physical implementation of the register storage corresponding to the array register is limited to a fixed number N R Vector registers ZAR0 to ZAR(N R The vector registers ZAR forming the array register storage 88 may be a separate register set from the vector registers Z0 to Z31 used for vector input to SIMD and matrix operations. Each of the vector registers ZAR may have a matrix vector length MVL, and thus each vector register ZAR may store a 1D vector of length MVL that may be logically divided into a variable number of data elements. For example, if MVL is 512 bits, this may be, for example, a set of 64 8-bit elements, 32 16-bit elements, 16 32-bit elements, 8 64-bit elements, or 4 128-bit elements. It will be understood that not all of these options need to be supported in a given implementation. By supporting variable element sizes, this provides flexibility for computations involving data structures of different precision. To represent 2D arrays of data, the vector registers ZAR0 to ZAR(N R-1) group is made up of array register identifiers ZA0 to ZA(N A -1) can be logically thought of as a single entity that is allocated to a given one of the vector registers, and thus a 2D array is formed with elements spread out within a single vector register corresponding to one dimension of the array, and elements of the other dimension of the array striped across multiple vector registers.

[0088] It may be useful, though not required, to implement the matrix processing circuitry 46, 86 so that the array register ZA stores a square array of data in which the number of horizontal elements equals the number of vertical elements. This may help support on-the-fly transposition of matrices, in which the row / column dimensions of the matrix structure in memory may be switched when transferring matrices between the array register 88 and the memory 54, by providing support for reading / writing the array register 88 either horizontally or vertically. It is common for machine learning algorithms and other applications that process matrix data to represent data stored in memory in either row-major or column-major format, as described above, and some algorithms may need to process data in a mix of formats. With previous techniques, if some processing requires input data to be in a different format than its layout in memory, ensuring format consistency may require some rearrangement of the data stored in memory using several load / store or vector permute instructions before the data can be processed in matrix processing operations. These operations can be time-consuming. By providing support for writing / reading data from 2D array registers in either horizontal or vertical directions, this can allow data loaded from memory in one direction (e.g., row-by-row) to be written back to memory in the opposite direction (e.g., column-by-column) faster than is possible using some gather / scatter load / store or replace operations to transfer data between memory and vector registers.

[0089] Thus, when array register ZA88 is implemented as a set of vector registers ZAR, each storing one horizontal / vertical group of elements of a corresponding 2D array, to ensure that the square matrix constraint is met, it may be desirable for the array to span a number of vector registers equal to the number of data elements that can fit within one vector register. When supporting variable data element sizes as described above, the number of data elements that can fit within one vector register is variable, and therefore the number of vector registers that are grouped together to form a single array register ZA can also be variable.

[0090] One approach could be that each array register ZA (accessible as an architectural register by specifying an array register ID in an instruction) could correspond to a fixed number of vector registers corresponding to the maximum number of data elements that can fit within a single vector register at the minimum supported data element size. However, in this case, because the array registers are fixedly mapped onto the physical vector register storage, when the data element size is larger and fewer data elements fit within a single vector register, some of the fixed set of vector registers mapped to a particular array register identifier effectively becomes wasted as the array dimension shrinks.

[0091] Therefore, a more efficient implementation is to reduce the number of array registers N A may be variable depending on the data element size E, so that the physical register storage ZAR0 to ZAR(N) used to implement the array register ZA R −1) can be logically divided into different size groups depending on the data element size E, thereby fully utilizing the available physical storage regardless of the data element size. This is because, for a given array register identifier ZA0-ZA(N A -1) is not always the same, but varies depending on the current data element size E used for a given operation.

[0092] 7 to 11 show that the physical storage is A 7-11 illustrate different ways in which the vector registers MVL may be divided and referenced using the architecture register specifiers MVL-1. In the examples of Figures 7-11, the matrix vector length MVL is assumed to be 512 bits, but it will be understood that other implementations may use different matrix vector lengths, in which case the particular number of array registers ZA supported, or the particular grouping of vector registers ZAR that are mapped to a given array register, may vary. Also, this example assumes that the total number of vector registers ZAR provided to array (matrix) registers 88 is 64, but again, this may vary in other implementations of the ISA.

[0093] Figure 7 shows the partitioning of array register storage when the current data element size E is 32 bits. In this case, using 512-bit vector registers, it is possible to fit 16 elements, each 32 bits in size, into a single vector register. Thus, to represent a square 2D array, 16 vector registers are grouped together to represent array register identifiers ZA0 through ZA(N A This can represent a single 16x16 2D array identified by a given value of 0 (-1). For example, for array register ID ZA0, this represents the 0th element of array ZA0. th (0th) to 15th th (15th) horizontal group are mapped to vector registers ZAR0 to ZAR15, which can store the i th The (i)th vertical group is striped across the set of elements at position i in each of the vector registers ZAR0 to ZAR15 (alternatively, other implementations may place the vertical group of elements within a single vector register ZAR and stripe the horizontal group of elements across corresponding element positions in multiple vector registers ZAR).

[0094] Since 16 vector registers ZR are sufficient to represent a 16x16 tile of 32-bit elements, and there are 64 vector registers in total, this means that four separate 16x16 arrays can be stored within the available 64 vector registers, and therefore for a 32-bit element size, the number of array registers supported is N A is 4. That is, the physical storage is divided into four groups of 16 vector registers labeled with array identifiers ZA0-ZA3, which can be identified by data transfer instructions that transfer data between the array storage registers and memory.

[0095] 7, four separate 2D arrays ZA0-ZA3 can be simultaneously stored in array registers 88, allowing for some amortization of the load / store overhead associated with processing a given amount of matrix data. For example, four separate output tiles ZA0-ZA3 can be generated from different combinations of four vector operands (e.g., ZA0 based on the cross product of opa0 and opb0, ZA1 based on the cross product of opa0 and opb1, ZA2 based on the cross product of opa1 and opb0, and ZA3 based on the cross product of opa1 and opb1, as shown in FIG. 7). This can be useful because the matrix processing algorithm may reuse the same input vector in combination with many other input vectors, thus allowing multiple cross product results to be calculated from the same instance of the input vector stored in a vector register (one of Z0 to Z31), sharing the load overhead associated with loading the vector among a greater number of calculation operations and increasing the effective number of multiplications achieved per load, which can help improve performance compared to separately loading a pair of input operands opa, opb for each individual result tile ZA that is generated.

[0096] 8 shows an alternative division of the physical register storage when the current data element size E is 16 bits, meaning that 32 elements fit within one 512-bit vector register (MVL size in this example), and therefore two groups of 32 vector registers, ZAR0-ZAR31 and ZAR32-ZAR63, are mapped to array identifiers ZA0 and ZA1, respectively, representing 32×32 tiles of 16-bit elements. Using this approach, the array storage can support performing two separate cross-product operations based on a single set of loaded vector operands opa, opb0, and opb1 in the vector registers to generate two 32×32 tiles ZA0 and ZA1 based on the cross product of opa and opb0 and the cross product of opa and opb1, respectively. Thus, compared to FIG. 7, the number of elements in each tile is larger (32×32 instead of 16×16), but fewer tiles can be processed for a given set of loads.

[0097] Figure 9 shows another configuration where the data element size is 8 bits, and therefore 64 elements fit within one vector register, meaning that all 64 vector registers ZAR0-ZAR63 are grouped together to form a single 2D array ZA0. Figure 9 shows performing a single cross product operation on vectors opa and opb to produce a 64x64 array of 8-bit elements ZA0. However, in some implementations, 8-bit element results may not be supported for computational operations, but may be limited to use in array load / store data transfer or register move data transfer instructions that transfer data between array registers and either memory or vector registers, or when transposing data structures in memory row / column wise.

[0098] Similarly, Figures 10 and 11 show the partitioning of array storage for data element sizes of 64 bits and 128 bits, respectively.

[0099] Other matrix vector lengths MVL or other numbers N stored in array storage 88 RIt will be appreciated that a similar division can be performed for the vector registers of

[0100] A cross product instruction that controls processing circuitry to perform a cross product operation can specify vector register identifiers that identify which vector registers Z0-Z31 store the two vector operands for the cross product operation, and destination array register identifiers ZA0-ZA(N) that identify the tiles to be updated with the results of the cross product operation. A −1) can be specified. The matrix processing hardware 48, 86 of the processor can determine which physical vector register ZAR should be updated based on the cross product result, based on the current data element size E and the specified array register identifier ZAi, in accordance with the variable mapping as described above.

[0101] The ISA may also define array data transfer instructions for transferring portions of a 2D array to or from a selected array register ZAi. To simplify the hardware circuit logic implementation and reduce the amount of data that needs to be transferred for any individual instruction, it may be easier for a given data transfer instruction to operate on a single horizontal / vertical group of elements in a selected array register ZAi, rather than transferring the entire 2D array in one instruction. This also helps support the on-the-fly transpose function described above, since the instruction can select whether to read / write horizontally or vertically, depending on the parameters of the data transfer instruction. Thus, in addition to the selected array register, the data transfer instruction may also identify an index that identifies which horizontal / vertical group of elements should be transferred.

[0102] Figure 12 shows an exemplary encoding of an array data transfer instruction. In this example, the instruction is a store instruction to transfer data from 2D array register storage ZA 88 to memory 54. It is also possible to provide an array data transfer instruction that is a load instruction to load data from memory 54 into array register storage 88, with the instruction specifying its memory addressing information and register addressing information in the same manner as shown for the store instruction in Figure 12.

[0103] The top part of FIG. 12 shows an example syntax for an array data transfer instruction when written in assembly code, and the bottom part of FIG. 12 shows the binary encoding of the instruction with various bit fields allocated to represent different parameters specified in the assembler representation.

[0104] As shown at the top of Figure 12, the data transfer command specifies several parameters, including: register addressing information (operands) to identify the portion of array register storage 88 to be used for the data transfer; Memory addressing information (operands) to identify the target area of ​​memory from which data is to be loaded or to which data is to be stored. A predicate operand that provides a predicate value to control data transfer so that some data elements of the array can be invalidated to prevent memory (in the case of a store instruction) or register storage (in the case of a load instruction) from being updated for element positions corresponding to inactive elements indicated by the predicate. There are two predicate values ​​Ph, Pv corresponding respectively to horizontal and vertical groups of elements in the array.

[0105] The memory addressing operand can identify an address to be updated in memory according to any known addressing scheme. For example, the memory addressing operand can include one or more register identifiers of scalar registers used to derive the address of the load / store operation and zero, one, or more immediate values. For example, a first scalar register can provide a base address. An offset value can be represented by a value stored in a second scalar register or by an immediate value directly encoded in the instruction encoding, and the offset is added to the value in the base address register to generate the address for the data transfer. In some cases, the memory addressing operand can also include further operands to specify other information regarding the addressing mode, such as an operand indicating whether to increment the value in the base address register before calculating the address of the current load / store instruction or after calculating the address. The operand can also include a parameter specifying a shift amount to be applied to the offset represented by the second register or immediate before adding it to the base register value. In general, a wide variety of memory addressing modes are known in the art, and any such known addressing mode may be used to define the memory addressing operands for an array data transfer instruction.

[0106] The register addressing operand of an array data transfer instruction, if it is a store instruction, is used to identify which portion of array register storage 88 is to be transferred to memory (for load instructions, the register addressing operand identifies which portion of array register storage 88 is to be updated with the loaded data). The register addressing operand contains an array identifier (ID) ZAi (or "zai" in the assembler representation used by software), where i is the specific architectural array register ZA0 through ZA(N) selected for the current load / store instruction.A The register addressing operand also includes a direction identifier d, which indicates whether the identified array register ZAi should be accessed horizontally or vertically. The register addressing operand also includes an indication of the element size E, which is the current element size for the current operation, and the element size E may be selected from several different element sizes as described above. The register addressing operand also includes a base register Wx and an immediate value #y for generating a row / column index J, which indicates the location of the horizontal / vertical group of elements in the selected array register ZAi to which data should be transferred. The base register identifier Wx identifies a scalar register that provides a base value to be added to the offset represented by the immediate value #y, which is directly encoded in the instruction encoding of the data transfer instruction, to generate the index J. In this example, to ensure that the index J is within the range of element positions supported for a given vector length MVL and element size E, the index value J is set to (the value in Wx + #y)MODULO(MVL / E). The modulo operation refers to finding the remainder when (the value in Wx+#y) is divided by (MVL / E), but in practice, since MVL and E are powers of 2, the modulo operation can be performed by simply returning the low-order bits of the sum, since J is the least significant log2(dim) bits of (the value of Wx+#y) when dim=MVL / E. By using a combination of base registers and immediate values ​​to represent the row / column index, this can be scaled to different dimensions of matrix structures, which is useful for supporting software code that supports loop unrolling, as described further below.

[0107] In this example, the index value J is represented the same regardless of whether the selected access direction for array register ZAi is horizontal or vertical. The direction identifier d selects which particular element in the group of vector register ZAR corresponding to the selected array register ZAi is to be read / written. For example, if the direction identifier selects the horizontal direction, the element to be transferred is J in the group corresponding to ZAi. th If the Jth vector register ZAR is read from (or written to in the case of a load instruction) and the direction identifier selects the vertical direction, the transferred element is stored in the Jth vector register ZAR in each of the groups corresponding to ZAi. th The (Jth) element is read from (or written to that register in case of a load instruction) (or vice versa if the horizontal / vertical direction is transposed with respect to the layout in the vector register ZAR).

[0108] 12, the binary encoding of the instruction may include an opcode that identifies the instruction as an array load / store data transfer instruction, and several fields that correspond to various parameters specified in the assembler representation of the instruction, as described above. For example, fields in the instruction encoding may be allocated to represent a direction identifier D, a current data element size E, a base register identifier Wx that identifies a base register for generating row / column indices for register addressing operands, predicate registers Ph and Pv for providing horizontal and vertical predicate values, and various memory addressing operands.

[0109] In this example, the scalar register field Wx for identifying the base register of the register address specifier operand has a fixed number of bits L that is less than the number of bits K used for the scalar register fields in at least one other instruction supported by the decoder 30 and the processor (for example, integer ALU instructions can specify a K-bit register field for their source / destination registers). For example, in the example of FIG. 5, K = 5. However, in order to reduce the size of the base register field in the array load / store data transfer instruction, as shown in FIG. 12, the Wx field may have L bits (L < K) such that there are several scalar registers that are not permitted to be specified as the base register for generating the row / column index for the array data transfer instruction. For example, when L = 2, the data transfer instruction may be restricted to selecting from a limited subset of four scalar registers (for example, W12 to W15). This recognizes that the instruction already has a large number of parameters to be specified, and for the assumed use case in controlling the matrix processing loop, it is sufficient to define only a few different base registers for register addressing within a single program loop. Therefore, by restricting the size of the scalar register field for identifying the base register for generating the index J, the instruction coding is made more efficient and other bit spaces for representing other parameters are freed. Of course, this is not essential, and other implementations can provide a scalar register field Wx that supports any scalar register identified as the base register for the register address specifier operand.

[0110] While Figure 12 shows an example where the current data element size E is encoded directly within the instruction encoding using a particular bit field, another option may be that the current data element size is set by a previous instruction and stored in a control register that may be referenced when processing the array data transfer instruction to identify the current data element size; therefore, it may not be necessary to represent the current data element size E within the instruction encoding itself.

[0111] In this example, the array ID i and immediate value #y for generating the row / column index for the register addressing information are represented by a combined field in the instruction encoding of the data transfer instruction. This is shown in more detail in Figure 13. This combined encoding takes advantage of the fact that, for a variable data element size E, as the data element size increases, the number of separate 2D arrays that can fit within the available physical array storage increases while the dimensions of the individual arrays decrease. Thus, while the array ID and immediate value both depend on the data element size, they have an inverse scaling relationship, meaning that it can be efficient to represent the two parameters in a combined field with a fixed number of bits of the combined field that are variably mapped as part of the array ID for some data element sizes and as part of the immediate value for other data element sizes.

[0112] It is also recognized that in order to support vector-length agnostic code that can operate correctly across a range of processor implementations that may implement different sizes for the matrix-vector length MVL, it is desirable for the particular immediate value specified for the register addressing operand to be set to the same value by the code regardless of the particular matrix-vector length MVL implemented. In practice, this means that the minimum supported matrix-vector length MVL minThis means that in processor implementations operating in a 100-bit environment, there is no advantage to providing encoding space to support a number of encodings for #y that is greater than the maximum number of data elements that can fit within a single vector register ZAR. This is because, in implementations with vector lengths greater than the minimum, it is possible to reference more elements per vector register, but the code cannot directly reference those additional data elements in the immediate value #y; otherwise, the code would have to use the minimum vector length MVL. min This is because the number of distinct values ​​supported for immediate value #y is now vector length agnostic, which means that it will not work correctly on implementations that implement min / E or less (in other words, for N-bit immediate, 2 N ≦MVL min / E), e.g., the minimum vector length MVL supported by ISA. min is 128 bits, when the current data element size E is 8, 128 / 8=16 can be represented in 4 bits (i.e., 0 to 15), so 4 bits are sufficient to represent the immediate value.

[0113] Thus, as shown in the example of Figure 13, the 4-bit combine field of a data transfer instruction can represent both the array ID i (defining which array register ZAi should be accessed) to generate the horizontal / vertical index J, and the immediate value #y. With the smallest supported data element size (e.g., 8 bits), all 4 bits of the combine field can be allocated to represent the bits of the immediate value #y. This is because with this element size, the entire physical register storage ZAR0-ZAR63 corresponding to the array registers is mapped to a single 2D array ZA0, as shown in Figure 9, so there is no need to specify the array ID at all. In this case, there are 64 different element positions in the horizontal / vertical direction, but the immediate value #y is calculated using MVL=MVL. min= 128 bits, and to support implementations where only 16 8-bit elements can fit in a single vector register, we scale only in the range 0 to 15. To access element positions in the range 16 to 63, software code must specify the base value in register Wx as a non-zero value.

[0114] On the other hand, for larger data element sizes, fewer bits are required for the immediate value as the number of data elements of that size that can fit within a vector register of the minimum supported vector length decreases, but in these examples additional bits of the join field are allocated to represent the array ID i.

[0115] Figure 14 shows an example of program code that can utilize the array data transfer instructions described above. The left side of Figure 14 shows high-level program code written by a programmer in a high-level programming language to multiply two matrices A[N×K] and B[K×M] to give a result C[N×M]. A programmer might write a program loop designed to step through each row / column of two matrix structures stored in memory, load the row / column for processing, perform several cross-product operations on pairs of vectors corresponding to rows of one of the matrices and columns of the other, and write the resulting accumulation of several cross-product results back to memory.

[0116] For example, in FIG. 14, the high-level code shows a loop in which, in each iteration, two columns of matrix A and two rows of matrix B are loaded as input vectors for a cross-product operation. Four cross-product operations are performed on each pair of columns and rows (similar to the example shown in FIG. 7) to generate four separate 2D arrays of output data. The load / compute loop iterates over different row / column locations of the matrix structure in memory, so that ZA0-ZA3 accumulate the results of multiplying tiles from matrix A with tiles from matrix B. A subsequent store loop stores each row / column of result tiles ZA0-ZA3 back into the result matrix structure C in memory. The outer loop iterates over both the load / compute loop and the store loop, and iterates over other combinations of tiles from matrices A and B.

[0117] The right side of Figure 14 shows a compiled assembler representation of the high-level code on the left side of Figure 14. Within the inner loop (the load / compute loop) are several vector load instructions that load vector registers Z4-Z7 with respective columns or rows of matrices A / B in memory, and an outer product instruction FMOPA that generates an outer product result that is written to array registers ZA0-ZA3 from each pair of vector operands in vector registers Z4-Z7. In this example, the element size is 32 bits, so (considering the example of Figure 7), there are four tiles that can be generated within a single iteration of the inner loop. In this example, the data element size of E=32 bits is represented by having an element size identifier .s in the assembler representation of the various load / store and outer product instructions. The outer product instructions are outer product and accumulate instructions, so for example, the instruction "fmopa ZA0.s." adds the previous contents of each element of array register ZA0 to the element generated in the outer product operation performed on the vector operands in vector registers Z4 and Z6.

[0118] The bottom loop of the assembler code in Figure 14 includes array store data transfer instructions "st1w" used to transfer the generated 2D arrays from array registers ZA0-ZA3 to memory. These have the encoding described with respect to Figure 12. In this example, the direction identifier d specifies the horizontal direction (as indicated by zaih.s in the assembler representation), and therefore the base register W12 and immediate value #0 shown in the example of Figure 14 are used to generate an index value J that identifies the particular horizontal group of elements in the selected array register ZAi (one of ZA0-ZA3) to be transferred to memory in response to the corresponding store instruction. A loop is constructed in which the value in base register W12 is incremented with each iteration of the loop, with a store instruction stepping through each horizontal group of elements in the generated 2D arrays until all elements in each of the generated arrays ZA0-ZA3 have been stored in memory. The 'add' instruction at the bottom of the store loop increments the base registers x17 and w12 used for memory addressing information and register addressing information respectively, and the compare instruction 'cmp' compares the value in w12 (which also acts as the loop counter in this example) to allow the branch instruction 'blt' to determine whether to terminate the loop.

[0119] Figure 14 shows an example of assembler code where the compiler did not use loop unrolling when generating the store loop at the bottom of the code. In this example, the immediate value for each of the four store instructions is #0, and therefore the index value used to select the particular row / column to store from the given 2D array ZA0-ZA3 is simply identified by the value stored in base register W12.

[0120] However, in such an implementation of the code, there is a certain amount of overhead in each loop iteration of the store loop due to the "add" instruction to increment w12, as well as the compare and branch instructions "cmp" and "blt" used to determine whether to terminate the loop. The overhead associated with these loop control instructions can be reduced by performing loop unrolling, in which multiple iterations of a loop are unrolled into a single iteration of a larger loop that contains explicit instructions that would have corresponded to multiple iterations in the original loop. For example, the store loop shown in FIG. 14 can be replaced with code such as the following:

[0121] [Table 1]

[0122] In this example, four separate iterations of the original loop can be unrolled into a single iteration of the new loop, thereby reducing the number of times the "add" instruction to increment w12, as well as the compare and branch instructions, are executed. Further performance improvements can be achieved if the memory addressing information for generating the memory addresses uses a base+immediate addressing mode with an additional immediate offset indicating a multiple of the element size that is added to the base value to generate the target memory address; in this case, different store instructions can target different addresses for the unrolled loop iterations based on the single register x17, further eliminating three add instructions for incrementing registers X18-X20 in each loop iteration.

[0123] While the above code is merely an example, it will be appreciated that it helps to illustrate why using a base register and an immediate value in the register addressing information to represent the horizontal / vertical position index J can be useful to support loop unrolling by a compiler, as well as to support scalable code that can operate on different dimensions of data structures (see the variable dim shown in Figure 14, which represents the dimension of the ZA matrix tile that is calculated per iteration).

[0124] The example of FIG. 12 shows an array data transfer instruction that is a load / store instruction in which data is transferred between a target portion of array register storage 88 and memory 54 .

[0125] Another example of a data transfer instruction that uses register addressing information to access an array register 88 is shown in FIG. 15. FIG. 15 shows a register move instruction for transferring data between an array register 88 and a vector register 82. The opcode has a different value than the opcode of the load / store array data transfer instruction of FIG. 12. The register addressing information of the register move instruction is encoded in the same manner as the example of FIG. 12. However, instead of providing memory addressing information that identifies a target region of memory, the register move instruction specifies a vector register identifier Zk that specifies a selected vector register 82. Different variations of the register move instruction (represented by different opcodes) can be provided. For example, there may be a vector-to-array register move variation that controls processing circuitry to transfer a vector of elements from vector register Zk to a horizontal / vertical group of elements J of a selected array register ZAi identified based on array register addressing information including a direction identifier d, an array register ID i, an element size E, a base register Wx, and an immediate #y, in the same manner as described above for the example of FIG. 12. Similarly, there may be an array-to-vector register move variant that controls processing circuitry to move data from a horizontal / vertical group of elements J of a selected array register ZAi to a vector register Zk. Both forms of instructions may be useful to support certain matrix processing algorithms, which may require performing some manipulation of elements in a single row / column of a matrix before or after performing a 2D operation on the entire matrix. Register move instructions can support transferring elements to / from vector registers so that such single-row / column operations can be performed.

[0126] 16 shows a flow diagram illustrating the processing of a data transfer instruction, such as the array data transfer instruction described above. In step S200, the next instruction pending processing is decoded by instruction decoder 30, and in step S202, instruction decoder 30 identifies the type of the decoded instruction. If the instruction is not an array data transfer instruction, in step S204, the operation represented by the instruction is performed by processing circuitry under control of instruction decoder 30, and the method returns to step S200 to decode the next instruction.

[0127] If the instruction decoded by the instruction decoder 30 is identified as an array data transfer instruction, then in step S206, the instruction decoder 30 and / or the execution stage 36 of the CPU 60 or coprocessor 70 identifies a target portion of register storage to use for the data transfer operation using a target portion of register storage identified based on register addressing information of the data transfer instruction. The register addressing information includes a base register identifier and an immediate value. The processing circuitry generates an index value J based on adding a value represented by the immediate value and a value held in a base register identified by the base register identifier. The index value J is used to select the target portion of register storage to which the data transfer is to be performed.

[0128] In step S208, processing circuitry (under control of the instruction decoder) identifies the type of the decoded array data transfer instruction. Step S208 is shown after step S206 for simplicity, but in other examples may be performed before step S206, in which case step S206 appears in both alternative branches of processing following step S208.

[0129] If the data transfer instruction is a load / store instruction similar to the example of Figure 12, then in step S210 the processing circuitry determines the target portion of memory to be used for the data transfer based on memory addressing information specified by the instruction. This may be done according to any known addressing mode and may be based on either a register identified by the instruction or an immediate value identified by the instruction encoding.

[0130] In step S212, the processing circuitry is then controlled by the instruction decoder 30 to perform a data transfer operation to transfer data between the target portion of register storage and the target portion of memory. If the instruction is a load instruction, the data transfer operation involves loading data from the target portion of memory and storing it in the target portion of register storage. If the instruction is a store instruction, the data transfer involves storing data from the target portion of register storage to the target portion of memory. The method then returns to step S200 to decode the next instruction.

[0131] If, in step S208, it is determined that the array data transfer instruction is a register move instruction (similar to FIG. 15), then in step S214 a further portion of register storage is identified based on the further register addressing information (e.g., based on a register field Zk in the instruction encoding that identifies which registers are the further portion of register storage). In step S216, a data transfer operation is performed (in either direction depending on the particular instruction type being executed) to transfer data between the target portion of register storage identified based on the base register Wx and immediate #y and the further portion of register storage. Again, the method returns to step S200 to decode the next instruction.

[0132] 12 and 15 show array data transfer instructions that include register addressing information that uses a base register and an immediate value to represent an index value used to select a target portion of array register storage 88 to use in the data transfer. However, encoding the register addressing information in this manner can also be used for other types of instructions that access types of registers other than array registers 88 for storing 2D arrays of data. More generally, encoding the register addressing information in this manner can be useful for instructions intended to process portions of data that may have variable dimensionality while supporting loop unrolling.

[0133] FIG. 17 illustrates a simulator implementation that may be used. While the above embodiments implement the present invention in terms of apparatus and methods for operating specific processing hardware that supports the techniques, it is also possible to provide an instruction execution environment according to the embodiments described herein implemented through the use of a computer program. Such computer programs are often referred to as simulators, insofar as they provide a software-based implementation of a hardware architecture. Various simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 330, optionally running a host operating system 320 that supports the simulator program 310. In some arrangements, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or there may be multiple different instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that run at reasonable speeds, but such an approach may be justified in certain situations, such as when it is desirable to execute code native to another processor for compatibility or reuse reasons. For example, a simulator implementation may provide an instruction execution environment with additional functionality not supported by the host processor hardware, or may provide an instruction execution environment typically associated with a different hardware architecture. An overview of simulation is given in "Some Efficient Architecture Simulation Techniques," Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0134] While embodiments have been described above with reference to particular hardware components or features, equivalent functionality may be provided in the simulated embodiments by appropriate software components or features. For example, particular circuitry may be implemented as computer program logic in the simulated embodiments. Similarly, memory hardware such as registers or caches may be implemented as software data structures in the simulated embodiments. In arrangements where one or more of the hardware elements referenced in the foregoing embodiments reside in host hardware (e.g., host processor 330), some simulated embodiments may use the host hardware where appropriate.

[0135] Simulator program 310 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provide target code 300 (which may include applications, an operating system, and a hypervisor) with a program interface (an instruction execution environment) that is the same as the interface of the hardware architecture modeled by simulator program 310. Thus, program instructions of target code 300, including the mixed element size instructions described above, may be executed from within an instruction execution environment using simulator program 310, thereby allowing host computer 330, which does not actually have the hardware characteristics of the devices described above, to emulate those characteristics.

[0136] Thus, one example provides a simulator computer program 310 that, when executed on a host data processing apparatus, controls the host data processing apparatus to provide an instruction execution environment for executing instructions of a target code. The computer program includes instruction decoding program logic 312 that decodes program instructions to control the host data processing apparatus to perform data processing in response to the program instructions, and register emulating program logic 314 that maintains data structures in host storage of host hardware 330 to emulate architectural registers 80, 82, 88 defined in a simulated ISA supported by the target code. The computer program may be stored on a computer-readable recording medium. The recording medium may be a non-transitory recording medium.

[0137] For example, the instruction decode program logic 312 may include instructions that examine the instruction encoding of the program instructions of the target code and map each type of instruction to a corresponding set of one or more program instructions in a native instruction set supported by the host hardware 330 that executes functionality corresponding to the functionality represented by the decoded instruction. The register emulating program logic 314 may include an instruction set that maintains data structures within the virtual address space of the host data processing device 330 and / or within registers of the host device 330, where the register emulating data structures represent the contents of registers 80, 82, 88 that the target code assumes are provided in hardware but that are not actually provided in hardware of the host device 330. Instructions in the target code 300 that reference particular registers in the simulated instruction set architecture may cause the register emulating program logic 314 to access registers of the host 330 or generate load / store instructions in the native instruction set of the host device to read / write the corresponding simulated register state.

[0138] The instruction decode program logic 312 can support data transfer instructions that use register addressing information defined using a base register and an immediate in the same manner as described above for the hardware embodiment. In the simulator example of Figure 17, when the instructions processed in the target code are load / store form of data transfer instructions, in response to a load / store data transfer instruction specifying register addressing information to identify a target portion of register storage and memory addressing information to identify a target portion of simulated memory, the instruction decode program logic 312 controls the host 330 to perform a data transfer operation to transfer data between a location in the register-emulating data structure that is mapped to the target portion of register storage and a location in the host storage of the host data processing apparatus that is mapped to the target portion of simulated memory.

[0139] In this application, the term "configured to..." is used to mean that elements of an apparatus have a configuration that allows them to perform a defined operation. In this context, "configuration" refers to a way of arranging or interconnecting hardware or software. For example, an apparatus may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that the apparatus elements need to be modified in any way to provide the defined operation.

[0140] Although exemplary embodiments of the present invention are described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to these precise embodiments and that various changes and modifications can be made in these embodiments by those skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims.

Claims

1. an instruction decoding circuit configuration for decoding an instruction; a register storage for storing data; processing circuitry for performing data processing in response to instructions decoded by the instruction decode circuitry to generate a processing result to be written to at least one register of the register storage, the instruction decode circuitry is configured to control the processing circuitry to perform a data transfer operation to transfer data to or from the target portion of the register storage in response to a data transfer instruction that specifies register addressing information to identify a target portion of the register storage; the register addressing information is a base register identifier identifying a base register in said register storage for storing a base value; an immediate value specified in an encoding of the data transfer instruction, the immediate value representing a value to be added to the base value to provide an index value for selecting the target portion of the register storage; Device.

2. the register storage includes a two-dimensional (2D) array register storage for storing at least one 2D array of data; The apparatus of claim 1 , wherein the target portion of the register storage comprises a target portion of the 2D array register storage.

3. 3. The apparatus of claim 2, wherein the data transfer operation includes transferring a subportion of a target 2D array to or from the target portion of the 2D array register storage, and the index value identifies which subportion of the target 2D array is to be transferred.

4. The apparatus of claim 3 , wherein the sub-portion comprises a single horizontal group of elements sharing the same vertical position in the target 2D array or a single vertical group of elements sharing the same horizontal position in the target 2D array.

5. the data transfer command specifies an arrangement direction identifier that identifies one of a horizontal direction and a vertical direction; when the array orientation identifier identifies the horizontal orientation, the sub-portion of the target 2D array includes at least one horizontal group of elements of the target 2D array identified by the index value, each horizontal group of elements including elements that share the same vertical position within the target 2D array; 5. The apparatus of claim 3 or 4, wherein when the array orientation identifier identifies the vertical direction, the sub-portion of the target 2D array includes at least one vertical group of elements of the target 2D array identified by the index value, each vertical group of elements including elements that share the same horizontal position within the target 2D array.

6. 6. The apparatus of claim 3, wherein the data transfer instruction is associated with a current data element size E specified for the data transfer instruction from among a plurality of data element sizes supported by the processing circuitry, the current data element size E identifying a data element size associated with each element of the target 2D array.

7. The immediate value is N in the instruction encoding of the data transfer instruction. ｉｍｍ is encoded using N bits, ｉｍｍ is variable depending on the current data element size E, and N ｉｍｍ 7. The apparatus of claim 6, wherein increases as E decreases.

8. The 2D array register storage includes N registers each containing an MVL bit. Ｒ vector registers, The instruction decode circuitry is configured to decode the N Ｒ and configured to decode instructions according to an instruction set architecture that supports a variable vector length MVL for vector registers, wherein the minimum vector length supported by the instruction set architecture is ｍｉｎ and For the data transfer instruction in which elements of the target 2D array have a data element size E, the number of different numeric values ​​that can be encoded as the immediate values ​​in the instruction encoding of the data transfer instruction is MVL ｍｉｎ 8. The device of claim 3, wherein the .lambda. / E is less than .lambda. / E.

9. the 2D array register storage may be logically divided into at least two array storage areas, each array storage area for storing a respective 2D array; 9. The apparatus of claim 2, wherein the register addressing information also includes an array identifier that identifies a selected array storage area of ​​the 2D array register storage, and wherein the index value identifies which sub-portion of the selected array storage area is the target portion of the register storage.

10. 10. The apparatus of claim 9, wherein the processing circuitry is configured to identify which portion of the 2D array register storage is the array storage region corresponding to a given value of the array identifier based on a variable mapping, the variable mapping being dependent on a current data element size E specified for the data transfer operation.

11. The 2D array register storage is Ａ The array storage area is logically divided into N Ａ varies depending on the current data element size E, and N Ａ 11. The apparatus of claim 10, wherein increases as E increases.

12. the array identifier and the immediate value are encoded using a shared portion of bits of an instruction encoding of the data transfer instruction; 12. The apparatus of claim 9, wherein for a given bit of the shared portion, the instruction decode circuitry is configured to change whether the given bit is interpreted as an indication portion of the array identifier or an indication portion of the immediate value in response to a current data element size E specified for the data transfer instruction.

13. 13. The apparatus of claim 12, wherein a total number of bits of the instruction encoding of the data transfer instruction used to encode the array identifier and the immediate value is constant regardless of the current data element size E.

14. 14. The apparatus of claim 1, wherein when the data transfer instruction is a load / store instruction that specifies the register addressing information and memory addressing information to identify a target portion of memory, the data transfer operation comprises transferring data between the target portion of the register storage and the target portion of memory.

15. 15. Apparatus according to any one of claims 1 to 14, wherein when the data transfer instruction is a register move instruction that specifies the register addressing information and further register addressing information to identify a further portion of the register storage, the data transfer operation comprises transferring data between the target portion of the register storage and the further portion of the register storage.

16. 16. Apparatus according to any one of claims 1 to 15, wherein the base register is a scalar register.

17. the instruction decode circuitry is configured to support at least one scalar computation instruction having a K-bit scalar register field for specifying a source or destination register; 17. The apparatus of claim 1, wherein the data transfer instruction specifies the base register using a scalar register field of L bits, and wherein L<K such that at least one scalar register specifiable as the source or destination register of the at least one scalar computation instruction cannot be specified as the base register of the register addressing information for the data transfer instruction.

18. Decoding instructions. and controlling processing circuitry to perform data processing to generate a processing result to be written to at least one register of a register storage in response to the decoded instruction, in response to a data transfer instruction specifying register addressing information to identify a target portion of the register storage, the processing circuitry is controlled to perform a data transfer operation to transfer data to or from the target portion of the register storage; the register addressing information is a base register identifier identifying a base register in said register storage for storing a base value; an immediate value specified in an encoding of the data transfer instruction, the immediate value representing a value to be added to the base value to provide an index value for selecting the target portion of the register storage; method.

19. 1. A computer program for controlling a host data processing apparatus to provide an instruction execution environment for executing instructions of a target code, comprising: instruction decode program logic for controlling the host data processing apparatus to decode instructions of the target code and to perform processing operations corresponding to the decoded instructions; register-emulating program logic that maintains a register-emulating data structure in host storage of the host data processing apparatus to emulate register storage of a target instruction set architecture associated with the target code; the instruction decode program logic is configured to, in response to a data transfer instruction of the target code specifying register addressing information to identify a target portion of the register storage, control the host data processing apparatus to perform a data transfer operation to transfer data to or from a location of the register-emulating data structure corresponding to the target portion of the register storage; the register addressing information is a base register identifier identifying a base register in said register storage for storing a base value; an immediate value specified in an encoding of the data transfer instruction, the immediate value representing a value to be added to the base value to provide an index value for selecting the target portion of the register storage.

20. 20. A storage medium having stored thereon a computer program according to claim 19.

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