MEMORY SYSTEM AND METHOD FOR OPERATION THEREOF, MEMORY CONTROLLER, AND MEMORY

Abstract

The embodiments of the present disclosure disclose a memory system and an operation method thereof, a memory controller, and a memory. The memory system includes a memory. The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, where m is a positive integer greater than 1. The operation method includes the steps of: determining, by the peripheral circuit, a (n+1)th group of page data according to a received prefix command and the received n groups of page data, where n is a positive integer and n+1 is a positive integer less than or equal to m; and determining, by the peripheral circuit, a (n+1)th group of page data according to a received prefix command and the received n groups of page data, where n is a positive integer and n+1 is a positive integer less than or equal to m; n and writing the n groups of the page data and the (n+1)th group of the page data to the memory cell array to generate n different data states.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application is based on Chinese Patent Application No. 202211275605.2, entitled "Memory System and Operation Method Thereof, Memory Controller and Memory," filed on October 18, 2022, which claims priority to Chinese Patent Application No. 202211275605.2, the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD Embodiments of the present disclosure relate to, but are not limited to, the field of semiconductors, and in particular to memory systems, methods of operation thereof, memory controllers, and memories. [Background technology]

[0003] NAND memory cells include single-level cells that store one bit of data and multi-level cells that store at least two bits of data. NAND memory with single-level cells can achieve faster write speeds and higher reliability, but has lower storage capacity and higher cost. NAND memory with multi-level cells has higher storage capacity and lower cost, but has slower write speeds and lower reliability.

[0004] However, in some applications, NAND memory needs to achieve not only the high write speed and high reliability of single-level cells, but also the large storage capacity and low cost of multi-level cells. Therefore, flexible configuration of NAND memory to realize multiple memory cell modes has become an urgent technical challenge to be solved. Summary of the Invention [Means for solving the problem]

[0005] According to a first aspect of an embodiment of the present disclosure, there is provided an operating method for a memory system, the memory system including a memory, the memory including a memory cell array and a peripheral circuit coupled to the memory cell array, the memory cell array including memory cells capable of storing m bits of information, m being a positive integer greater than 1, and the operating method includes: determining, by a peripheral circuit, an (n+1)th group of page data according to the received prefix command and the received n groups of page data, where n is a positive integer and n+1 is a positive integer less than or equal to m; 2 in the memory cell array n and writing the n groups of page data and the (n+1)th group of page data to the memory cell array to generate n different data states.

[0006] According to a second aspect of an embodiment of the present disclosure, there is provided a memory controller, the memory controller coupled to a memory, the memory including a memory cell array and a peripheral circuit coupled to the memory cell array, the memory cell array including memory cells capable of storing m bits of information, m being a positive integer greater than 1, and the memory controller: The peripheral circuit determines the (n+1)th group of page data according to the prefix command and the n groups of page data, and stores two pages in the memory cell array. n The memory device is configured to send a prefix command and n groups of page data to the peripheral circuitry to enable generation of n different data states, where n is a positive integer and n+1 is a positive integer less than or equal to m.

[0007] According to a third aspect of an embodiment of the present disclosure, there is provided a memory, the memory comprising: a memory cell array including memory cells capable of storing m bits of information; peripheral circuitry coupled to the memory cell array; Including, The peripheral circuit is configured to determine an (n+1)th group of page data according to the received prefix command and the received n groups of page data, where n is a positive integer and n+1 is a positive integer less than or equal to m; The peripheral circuit is located in the memory cell array. n The memory cell array is further configured to write the n groups of page data and the (n+1)th group of page data to generate n different data states.

[0008] According to a fourth aspect of an embodiment of the present disclosure, there is provided a memory system, the memory system comprising: a memory according to a third aspect of an embodiment of the present disclosure; a memory controller according to a second aspect of an embodiment of the present disclosure, coupled to the memory and configured to control the memory; Includes.

[0009] In an embodiment of the present disclosure, the peripheral circuit determines an (n+1)th group of page data according to the received prefix command and the received n groups of page data, writes the n groups of page data together with the (n+1)th group of page data into the memory cell array, and writes 2 n NAND memory can generate multiple data states, i.e., a portion of the memory's storage space can be used as at least one of SLC, MLC, TLC, and QLC. In this way, NAND memory can be flexibly configured to realize multiple modes of memory cells, offering advantages such as fast write speeds, high reliability, large storage capacity, and low cost.

[0010] In order to more clearly show the detailed description of the present disclosure or the technical solutions in the prior art, the drawings that need to be used in the detailed description or the description of the prior art are briefly introduced below. The accompanying drawings in the following description are some implementation forms of the present disclosure, and it is obvious that other drawings can be obtained for those skilled in the art according to these drawings without creative work. [Brief explanation of the drawings]

[0011] [Figure 1] 2 is a schematic diagram of different data states of a memory shown in accordance with an example embodiment. [Figure 2] 1 is a flowchart of a method for writing to a memory system according to an example embodiment. [Figure 3] FIG. 1 is a schematic diagram of a memory system shown in accordance with an example embodiment. [Figure 4] FIG. 2 is a schematic diagram of a memory write state shown in accordance with an exemplary embodiment. [Figure 5] 1 is a flowchart of a method of operating a memory system according to an embodiment of the present disclosure. [Figure 6] 3A-3C are schematic diagrams of write commands executed by a memory shown in accordance with an embodiment of the present disclosure. [Figure 7] FIG. 4 is a timing diagram of a write operation performed by a memory shown in accordance with an embodiment of the present disclosure. [Figure 8] FIG. 2 is a schematic diagram illustrating a write state of a memory shown in accordance with an embodiment of the present disclosure. [Figure 9] 2 is a partial schematic diagram of peripheral circuits of a memory shown in accordance with an embodiment of the present disclosure. [Figure 10] FIG. 1 is a schematic diagram of a memory shown in accordance with an embodiment of the present disclosure. [Figure 11] FIG. 2 is a cross-sectional view of a NAND memory string shown in accordance with an embodiment of the present disclosure. [Figure 12] 1 is a block diagram of a memory including a memory cell array and peripheral circuits shown in accordance with an embodiment of the present disclosure. [Figure 13]FIG. 1 is a schematic diagram of a memory system shown in accordance with an embodiment of the present disclosure. [Figure 14a] 1 is a schematic diagram of a memory card shown in accordance with an embodiment of the present disclosure. [Figure 14b] 1 is a schematic diagram of a solid-state drive (SSD) shown in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] The following examples are provided for a better understanding of the present disclosure, and are not limited to the best implementation mode, and do not limit the content and protection scope of the present disclosure. Any products identical or similar to the present disclosure obtained under the teaching of the present disclosure or by combining the present disclosure with other prior art features fall within the protection scope of the present disclosure.

[0013] It should be noted that in describing the present disclosure, orientations or positional relationships indicated by terms such as "upper," "lower," "inner," and "outer" are based on orientations or positional relationships shown in the drawings, are intended solely for the convenience of describing the present disclosure, and do not suggest or imply that the referenced devices or elements must have a particular orientation, be constructed, or operate in a particular orientation, and therefore should not be construed as limiting the present disclosure. In addition, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as suggesting or implying relative importance.

[0014] 1 is a schematic diagram illustrating different data states of a memory according to an exemplary embodiment. Referring to FIG. 1, with the development of NAND memory, the number of bits in a memory cell has increased from 1 bit to 2 bits, 3 bits, and 4 bits, and thus the memory cell has evolved from a single level cell (SLC) to a multi-level cell (MLC), a triple level cell (TLC), and a quad-level cell (QLC). In response, the number of data states in the memory has increased from 2 to 4, 8, and 16, so that the capacity of the memory is increased and the cost is reduced.

[0015] Referring to Figure 1(a), a memory cell of an SLC memory stores one bit of data. The data states of an SLC memory include one erased state and one programmed state. The erased state is marked with E, and the programmed state is marked with P. The threshold voltage of the programmed state P is higher than that of the erased state E.

[0016] Referring to Figure 1(b), a memory cell of an MLC memory stores two bits of data. The data states of an MLC memory include one erased state and three programmed states. The erased state is marked with E, and the programmed states are marked with P1, P2, and P3, respectively, from the first state to the third state. The threshold voltage gradually increases from the P1 state to the P3 state.

[0017] Referring to Figure 1(c), a memory cell of a TLC memory stores three bits of data. The data states of a TLC memory include one erased state and seven programmed states. The erased state is marked with E, and the programmed states are marked with P1, P2, P3, P4, P5, P6, and P7, in order from the first state to the seventh state. The threshold voltage gradually increases from the P1 state to the P7 state.

[0018] Referring to Figure 1(d), a memory cell of a QLC memory stores four bits of data. The data states of a QLC memory include one erased state and 15 programmed states. The erased state is marked with E, and the programmed states are marked with P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, and P15, in order from the first state to the fifteenth state. The threshold voltage gradually increases from the P1 state to the P15 state.

[0019] With the development of 3D NAND technology, the number of stacked layers in memory continues to increase. When the number of stacked layers is 64 or more, MLC memory does not exist. Currently, the main 3D NAND product is TLC memory, but when the number of stacked layers is 300 or more, the main 3D NAND product will be QLC memory.

[0020] New 3D NAND product technology nodes are costly to develop, especially when the number of stacked layers increases. From a customer demand perspective, for example, in the automotive industry, low-bit memory is still needed to meet better reliability requirements. However, the market size is not large. From a cost perspective, it is not worth developing dedicated low-bit memory. For example, if mainstream NAND is TLC memory, there will still be some application needs for MLC memory. If mainstream NAND is QLC memory, there will still be some application needs for TLC memory and MLC memory. From an application program perspective, this is a mismatch.

[0021] One solution is to develop a general-purpose NAND memory that supports all cell levels (SLC / MLC / TLC / QLC). However, such a solution imposes a heavy burden on all development teams, including design, verification, validation, and testing. Furthermore, the cost of this work is three times that of SLC memory, especially for the test and certification teams.

[0022] 2 is a flowchart of a write method for a memory system according to an exemplary embodiment, and FIG. 3 is a schematic diagram of a memory system 10 according to an exemplary embodiment. As shown in FIGS. 2 and 3, the write method includes at least the following steps: S101: receiving lower page (LP) data and upper page (UP) data by the controller 11; S102: Enabling the scrambler 13 to randomize the LP data and the UP data; S103: Enabling an Error Correction Code (ECC) 14 to perform a parity check on the randomized LP data and UP data; S104: After performing a parity check, send the LP data and the UP data to a memory, for example, a page buffer; S105: Disabling the descrambler 16 and the ECC decoder 15; S106: transmitting the LP data and the UP data from the memory to the controller 11; S107: Executing firmware (FW) by a central processing unit (CPU) at the host side to perform an exclusive OR (NXOR) operation on the LP data and the UP data to generate intermediate page (MP) data, where the executing firmware may be stored in memory; S108: Disable the scrambler 13 and the ECC decoder 14, and send the LP / MP / UP data to a memory, for example, a page buffer; S109: Send a write command (e.g., 10h) to start the execution of a write operation, for example, writing LP / MP / UP data from the page buffer to the memory cell array 12; Includes.

[0023] FIG. 4 is a schematic diagram of a memory write state shown in accordance with an exemplary embodiment. Referring to FIG. 4, LP / MP / UP data is written to memory cell array 12 by a normal write method, and three bits of data can be written into memory cells of the TLC memory to generate eight different data states, namely, erased state E and programmed states P1 to P7. LP / MP / UP data is written to memory cell array 12 by performing the method shown in FIG. 2. Three bits of data can be stored in memory cells of the TLC memory to generate four different data states, namely, erased state E and programmed states P2, P4, and P6. That is, by performing the method shown in FIG. 2, at least a portion of the storage space in the TLC memory can be used as MLC to meet the needs of applications requiring MLC memory.

[0024] However, this method needs to be executed by the CPU on the host side, resulting in a complicated operation mode and firmware needs to be executed to use the CPU to perform NXOR operations on raw data (e.g., LP data and UP data) to generate MP data, resulting in low efficiency.

[0025] In this regard, embodiments of the present disclosure provide a memory system and method of operation thereof.

[0026] 5 is a flowchart of a method of operating a memory system according to an embodiment of the present disclosure. The memory system includes a memory including a memory cell array and peripheral circuits coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, where m is a positive integer greater than 1. Referring to FIG. 5, the method of operation includes at least the following steps: S201: determining, by a peripheral circuit, an (n+1)th group of page data according to a received prefix command and n groups of received page data, where n is a positive integer, and n+1 is a positive integer less than or equal to m; S202: There are two memory cell arrays n writing n groups of page data and an (n+1)th group of page data to the memory cell array to generate n different data states; Includes.

[0027] The memory includes a memory cell array and peripheral circuits coupled to the memory cell array. The memory cell array includes a plurality of memory cells, each capable of storing m bits of information. For example, the memory is an MLC memory, i.e., m=2. As another example, the memory is a TLC memory, i.e., m=3. As yet another example, the memory is a QLC memory, i.e., m=4. The peripheral circuits include a logic control unit, a command register, a cache register, a data register, etc.

[0028] In step S201, a logic control unit in the peripheral circuit may read a prefix command stored in a command register, determine an (n+1)th group of page data according to the read prefix command and the n groups of page data, and store the (n+1)th group of page data in a cache register or a data register. The n groups of page data include at least one of LP data, MP data, UP data, and extra page (XP) data. In a particular embodiment, the peripheral circuit may perform a logical operation on the n groups of page data to generate the (n+1)th group of page data.

[0029] In step S202, upon receiving a write command, n groups of page data and the (n+1)th group of page data are written sequentially into the memory cell array. n Different data states are created in the memory cell array.

[0030] In one example, the memory is an MLC memory. When a portion of the storage space in the MLC memory needs to be used as an SLC, the peripheral circuit determines MP data according to the received prefix command and LP data, and writes the LP data and MP data to the memory cell array to generate two different data states in the memory cell array.

[0031] In one example, the memory is a TLC memory. When a portion of the storage space in the TLC memory needs to be used as an MLC, the peripheral circuit determines UP data according to the received prefix command, LP data, and MP data, and writes the LP data, MP data, and UP data to the memory cell array to generate four different data states in the memory cell array.

[0032] In one example, the memory is a TLC memory. When a portion of the storage space in the TLC memory needs to be used as an SLC, the peripheral circuit determines MP data according to the received prefix command and LP data, and writes at least the LP data and the MP data to the memory cell array to generate two different data states in the memory cell array.

[0033] In one example, the memory is a QLC memory. When a portion of the storage space in the QLC memory needs to be used as a TLC, the peripheral circuit determines XP data according to the received prefix command, LP data, MP data, and UP data, and writes the LP data, MP data, UP data, and XP data to the memory cell array to generate eight different data states in the memory cell array.

[0034] In one example, the memory is a QLC memory. When a portion of the storage space in the QLC memory needs to be used as an MLC, the peripheral circuit determines UP data according to the received prefix command, LP data, and MP data, and writes at least the LP data, MP data, and UP data to the memory cell array to generate four different data states in the memory cell array.

[0035] In one example, the memory is a QLC memory. When a portion of the storage space in the QLC memory needs to be used as an SLC, the peripheral circuit determines MP data according to the received prefix command and LP data, and writes at least the LP data and the MP data to the memory cell array to generate two different data states in the memory cell array.

[0036] In an embodiment of the present disclosure, the peripheral circuit determines an (n+1)th group of page data according to the received prefix command and the received n groups of page data, writes the n groups of page data and the (n+1)th group of page data into the memory cell array, and writes 2 n NAND memory can generate multiple data states. That is, a portion of the memory's storage space can be used as at least one of SLC, MLC, TLC, and QLC. In this way, NAND memory can be flexibly configured to realize multiple memory cell modes, offering advantages such as fast write speeds, high reliability, large storage capacity, and low cost.

[0037] In addition, the operational mode of determining the (n+1)th group of page data via peripheral circuits inside the memory in the embodiments of the present disclosure is simpler than the logical operations performed by the CPU on the host side, which is beneficial for improving the operational efficiency of the memory while implementing multiple modes of the memory cells.

[0038] Furthermore, compared to the solution of developing a general-purpose NAND memory, the use of prefix commands in the operation method provided by the embodiments of the present disclosure may be easier to use and compatible with existing NAND protocols, leading to savings in development costs.

[0039] In some embodiments, when n+1 is equal to m, the prefix command includes a first sub-prefix command A, where the first sub-prefix command A indicates to perform an XOR operation on n groups of page data.

[0040] The above step S201 includes performing, by the peripheral circuitry, an XOR operation on the n groups of page data according to the first sub-prefix command A to generate the mth group of page data.

[0041] The above step S202 includes writing n groups of page data and the mth group of page data to the memory cell array to store m bits of information in the memory cells.

[0042] Taking QLC memory as an example, the memory controller sends a first sub-prefix command A, LP data, MP data, and UP data to the peripheral circuit, and the peripheral circuit performs an XOR operation on the LP data, MP data, and UP data according to the first sub-prefix command A to generate XP data. The memory controller sends a write command (e.g., 80h) to the peripheral circuit, and the peripheral circuit starts to write the LP data, MP data, UP data, and XP data to the memory cell array to store 4 bits of information in the memory cell, generating eight different data states, i.e., a part of the storage space in the QLC memory is used as TLC, as shown in (2) in Figure 6.

[0043] Note that the first sub-prefix command A is sent before the 80h command. Specifically, FIG. 7(b) shows a write timing diagram for using a portion of the storage space in a QLC memory as TLC. The timing diagram includes a data type signal Cycle Type and a data signal DQx. When writing TLC mode data in a QLC memory, the first sub-prefix command A is sent first, and then the 80h command is sent after determining the XP data. Then, address signals C1, C2, R1, R2, and R3 are sent during the address period. The address signals determine the logical address of the memory cell to be written, and the LP data, MP data, UP data, and XP data are written to the memory cell. Here, the logical address includes a logical unit number (lun), a plane, a block, and a page address.

[0044] In a specific example, as shown in FIG. 8(a), the LP data is a (1111111100000000) sequence, the MP data is a (1111000000001111) sequence, and the UP data is a (1100001111000011) sequence. The peripheral circuit performs an XOR operation on the LP data, MP data, and UP data according to the first sub-prefix command A to generate XP data as a (1100110011001100) sequence, and writes the LP data, MP data, UP data, and XP data into the memory cell array, generating eight data states in the memory cell array, as shown in FIG. 8(b), where the eight data states are erased state E (1111), programmed state P2 (1100), programmed state P4 (1001), programmed state P6 (1010), programmed state P8 (0011), programmed state P10 (0000), programmed state P12 (0101), and programmed state P14 (0110).

[0045] In this example, for the purpose of conveying the present disclosure to those skilled in the art, the LP data is, for example, a (1111111100000000) sequence, the MP data is a (1111000000001111) sequence, and the UP data is (1100001111000011), but it should be noted that the present disclosure is not limited thereto. The LP data, MP data, and UP data can also be other sequences of "1" and "0", as long as any eight different data states from the erased state E to the programmed state P15 can be generated in the QLC memory after the XP data is generated by executing the first prefix command A on the LP data, MP data, and UP data.

[0046] Preferably, the LP data is a (1111111100000000) sequence, the MP data is a (1111000000001111) sequence, and the UP data is a (1100001111000011) sequence. As shown in Figure 8(b), when a portion of the storage space in the QLC memory is used as TLC, the threshold voltage difference M2 between two adjacent data states is basically the same, that is, the read margin distribution is relatively uniform, which is beneficial to ensuring the accuracy of the read operation when used as TLC.

[0047] In an embodiment of the present disclosure, when n+1 is equal to m, the peripheral circuit may perform an XOR operation on the n groups of page data according to the first sub-prefix command to generate an m-th group of page data, and write the n groups of page data and the m-th group of page data to the memory cell array. nFor example, if the memory is QLC, part of the storage space within the QLC memory can be used as TLC so that the memory has at least two modes of memory cells, which helps increase the application scenarios of the memory and can better meet customer needs while being compatible with mainstream memory.

[0048] In other embodiments, when n+1 is equal to m, the peripheral circuit may also perform an NXOR operation or a copy operation on the n groups of page data according to the prefix command to generate the mth group of page data, where the selection can be made according to actual circumstances, and the present disclosure has no special restrictions in this regard.

[0049] In some embodiments, before performing step S202, the above operating method further includes the steps of storing n groups of page data in a plurality of data registers, respectively, where each data register is used to store a group of page data, and storing the mth group of page data in a cache register. The peripheral circuit may include a page buffer, and the data register or the cache register may be arranged in the page buffer to buffer the page data.

[0050] 9, the LP data (1111111100000000) is stored in data register 1, the MP data (1111000000001111) is stored in data register 2, and the UP data (1100001111000011) is stored in data register 3. After the XP data (1100110011001100) is generated, the XP data is stored in the cache register, and after receiving the 80h command, the LP data stored in data register 1, the MP data stored in data register 2, the UP data stored in data register 3, and the XP data stored in the cache register are sequentially written to the memory cell array.

[0051] In some embodiments, if the difference between m and n is 2, the prefix command includes a second sub-prefix command B, which indicates to perform an NXOR operation on n groups of page data.

[0052] The above step S201 includes performing, by the peripheral circuitry, an NXOR operation on the n groups of page data according to the second sub-prefix command B to generate the (n+1)th group of page data.

[0053] The above operating method further includes writing an m-th group of page data to the memory cell array to store m bits of information in the memory cells, where the m-th group of page data is a sequence of all 0s or a sequence of all 1s.

[0054] Still taking QLC memory as an example, the memory controller sends a second sub-prefix command B, LP data, and MP data to the peripheral circuit, and the peripheral circuit performs an NXOR operation on the LP data and MP data according to the second sub-prefix command B to generate UP data. A write command (e.g., 80h) is sent to the peripheral circuit, and the peripheral circuit starts writing the LP data, MP data, UP data, and XP data to the memory cell array to store 4 bits of information in the memory cell and generate four different data states, that is, a part of the storage space in the QLC memory is used as MLC, as shown in (3) in Figure 6. Here, the XP data is a sequence of all 0s or a sequence of all 1s.

[0055] Note that the second sub-prefix command B is sent before the 80h command. Specifically, FIG. 7(c) shows a timing diagram for using part of the storage space in a QLC memory as MLC. When writing MLC mode data to a QLC memory, the second sub-prefix command B is sent first, and then the 80h command is sent after determining the UP data. Then, address signals C1, C2, R1, R2, and R3 are sent during the address period. The address signals determine the logical address of the memory cell to be written, and the LP data, MP data, UP data, and XP data are written to the memory cell.

[0056] In a specific example, as shown in Figure 8(a), the LP data is a (1111111100000000) sequence, and the MP data is a (1111000000001111) sequence. The peripheral circuit performs an NXOR operation on the LP data and the MP data according to the second sub-prefix command B to generate the UP data as a (1111000011110000) sequence and the XP data as a (1111111111111111) sequence, and writes the LP data, MP data, UP data, and XP data into the memory cell array to generate four data states in the memory cell array, as shown in Figure 8c, where the four data states are erased state E (1111), programmed state P4 (1001), programmed state P8 (0011), and programmed state P12 (0101).

[0057] In this example, the LP data is a (1111111100000000) sequence, the MP data is a (1111000000001111) sequence, and the XP data is a (111111111111111) sequence, and it should be noted that these are taken as illustrative examples to convey the present disclosure to those skilled in the art. However, the present disclosure is not limited thereto. The LP data and MP data can also be other sequences composed of "1"s and "0"s, or the XP data can be a sequence of all 0s, as long as any four different data states from the erased state E to the programmed state P15 can be generated in the QLC memory after the second prefix command B is executed on the LP data and MP data to generate the UP data.

[0058] Preferably, the LP data is a (1111111100000000) sequence, the MP data is a (1111000000001111) sequence, and the XP data is a (1111111111111111) sequence. As shown in Figure 8(b), when a portion of the storage space in the QLC memory is used as MLC, the threshold voltage difference M3 between two adjacent data states is basically the same, that is, the read margin distribution is relatively uniform, which is beneficial to ensuring the accuracy of the read operation when used as MLC.

[0059] In an embodiment of the present disclosure, if the difference between m and n is 2, the peripheral circuit may perform an XOR operation on the n groups of page data according to the second sub-prefix command to generate an (n+1)th group of page data, and write the n groups of page data, the (n+1)th group of page data, and the mth group of page data to the memory cell array. nFor example, if the memory is QLC, part of the storage space within the QLC memory can be used as MLC so that the memory has at least two modes of memory cells, which helps increase the application scenarios of the memory and can better meet customer needs while being compatible with mainstream memory.

[0060] In other embodiments, when the difference between m and n is 2, the peripheral circuit may further perform an XOR operation or a copy operation on the n groups of page data according to the prefix command to generate the (n+1)th group of page data, where the selection can be made according to actual circumstances, and the present disclosure has no special restrictions in this regard.

[0061] In some embodiments, before performing step S202, the above operating method further includes a step of storing the n groups of page data and the (n+1)th group of page data in a plurality of data registers, respectively, where each data register is used to store a group of page data; and before writing the mth group of page data to the memory cell array, the above operating method further includes a step of storing the mth group of page data in a cache register.

[0062] 9, the LP data (1111111100000000) is stored in data register 1, the MP data (1111000000001111) is stored in data register 2, and the XP data (11111111111111111) is stored in the cache register. After the UP data is generated, the UP data (1111000011110000) is stored in data register 3. After receiving the 80h command, the LP data stored in data register 1, the MP data stored in data register 2, the UP data stored in data register 3, and the XP data stored in the cache register are sequentially written to the memory cell array.

[0063] In some embodiments, if the difference between m and n is 3, the prefix command includes a third sub-prefix command C, which indicates that the (n+1)th group of page data is equal to the nth group of page data.

[0064] The above step S201 includes performing, by the peripheral circuitry, copy operations on n groups of page data according to the third sub-prefix command C to generate the (n+1)th group of page data.

[0065] The above operating method further includes writing the (n+2)th group of page data and the mth group of page data to the memory cell array to store m bits of information in the memory cells, where the (n+2)th group of page data and the mth group of page data are a sequence of all 0s or a sequence of all 1s.

[0066] Still taking QLC memory as an example, the memory controller sends a third sub-prefix command C and LP data to the peripheral circuit, and the peripheral circuit performs a copy operation on the LP data according to the third sub-prefix command C to generate MP data. That is, the MP data is the same as the LP data. A write command (e.g., 80h) is sent to the peripheral circuit, and the peripheral circuit starts writing the LP data, MP data, UP data, and XP data to the memory cell array to store 4 bits of information in the memory cell and generate two different data states, that is, a part of the storage space in the QLC memory is used as SLC, as shown in (4) in FIG. 6 . Here, the UP data and XP data are a sequence of all 0s or a sequence of all 1s.

[0067] Note that the third sub-prefix command C is sent before the 80h command. Specifically, FIG. 7(d) shows a timing diagram for using a portion of the storage space in a QLC memory as an SLC. When writing SLC mode data to a QLC memory, the third sub-prefix command C is sent first, and then the 80h command is sent after determining the UP data. Then, address signals C1, C2, R1, R2, and R3 are sent during the address period. The address signals determine the logical address of the memory cell to be written, and the LP data, MP data, UP data, and XP data are written to the memory cell.

[0068] In a specific example, as shown in FIG. 8(a), the LP data is a (1111111100000000) sequence, and the peripheral circuit performs a copy operation on the LP data according to the third sub-prefix command C to generate MP data as a (111111111111111) sequence, UP data as a (11111111111111) sequence, and XP data as a (111111111111111) sequence, and writes the LP data, MP data, UP data, and XP data into the memory cell array to generate two data states in the memory cell array, which are an erased state E(1111) and a programmed state P8(0011), respectively, as shown in FIG. 8(d).

[0069] In this example, the LP data is a (1111111100000000) sequence, the UP data is a (111111111111111) sequence, and the XP data is a (111111111111111) sequence, and it should be noted that these are taken as illustrative examples to convey the present disclosure to those skilled in the art. However, the present disclosure is not limited thereto. The LP data can also be other sequences composed of "1"s and "0"s, or the UP data and XP data can be sequences of all 0s, as long as any two different data states from the erased state E to the programmed state P15 can be generated in the QLC memory after the third prefix command C is executed on the LP data to generate the MP data.

[0070] Preferably, the LP data is in the (1111111100000000) sequence, the UP data is in the (1111111111111111) sequence, and the XP data is in the (1111111111111111) sequence. As shown in Figure 8(b), when part of the storage space in the QLC memory is used as SLC, the threshold voltage difference M4 between the erased state E and the programmed state P8 is relatively large, which means that This is useful for ensuring the accuracy of the read operation when used as an MLC.

[0071] In an embodiment of the present disclosure, when the difference between m and n is 3, the peripheral circuit may perform copy operations on the n groups of page data according to the third sub-prefix command to generate the (n+1)th group of page data, and write the n groups of page data, the (n+1)th group of page data, the (n+2)th group of page data, and the mth group of page data to the memory cell array. nFor example, if the memory is QLC, part of the storage space within the QLC memory can be used as SLC so that the memory has at least two modes of memory cells, which helps increase the application scenarios of the memory and can better meet customer needs while being compatible with mainstream memory.

[0072] In some embodiments, before performing step S202, the above operating method further includes a step of storing the n groups of page data and the (n+1)th group of page data in a plurality of data registers, respectively, wherein each data register is used to store a group of page data.

[0073] Before writing the (n+2)th group of page data and the mth group of page data to the memory cell array, the above operating method further includes storing the (n+2)th group of page data in a data register and storing the mth group of page data in a cache register.

[0074] 9, the LP data (1111111100000000) is stored in data register 1, the UP data (111111111111111) is stored in data register 3, and the XP data (1111111111111111) is stored in the cache register. After the MP data is generated, the MP data (1111111110000000) is stored in data register 2. After receiving the 80h command, the LP data stored in data register 1, the MP data stored in data register 2, the UP data stored in data register 3, and the XP data stored in the cache register are sequentially written to the memory cell array.

[0075] In some embodiments, before determining the (n+1)th group of page data, the above operating method further comprises: determining whether the peripheral circuit has received a prefix command and generating a determination result; When the determination result indicates that the peripheral circuit has received a prefix command, determining an (n+1)th group of page data according to the received prefix command and the n groups of page data; If the result of the determination indicates that the peripheral circuit has not received the prefix command, m writing m groups of page data to the memory cell array to generate m different data states; Further includes:

[0076] Still taking QLC memory as an example, the logic control unit in the peripheral circuit can read the command register and determine whether the command register stores a prefix command (e.g., a first sub-prefix command, a second sub-prefix command, or a third sub-prefix command) based on the read result. If the read result indicates that a prefix command is stored in the command register, the peripheral circuit determines an (n+1)th group of page data according to the prefix command and the n groups of page data, that is, a portion of the storage space of the QLC memory is used as TLC, MLC, or SLC.

[0077] If the read result indicates that there is no prefix command stored in the command register, the 80h command is sent to the peripheral circuit, which stores m bits of information in the memory cell and 2 bits in the memory cell array. m To generate m different data states, m groups of page data are written to a memory cell array, where the storage space for writing the m groups of page data is used as a QLC, as shown in (1) in Figure 6.

[0078] In a specific example, as shown in FIG. 8(a), the LP data is a (1111111100000000) sequence, the MP data is a (1111000000001111) sequence, the UP data is a (1100001111000011) sequence, and the XP data is a (1001100110011001) sequence. The peripheral circuit writes LP data, MP data, UP data, and XP data to the memory cell array according to the 80h command, and generates 16 data states in the memory cell array, as shown in FIG. 8(a), which are erased state E (1111), program state P1 (1110), program state P2 (1100), program state P3 (1101), program state P4 (1001), program state P5 (1000), program state P6 (1010), program state P7 (1011), program state P8 (0011), program state P9 (0010), program state P10 (0000), program state P11 (0001), program state P12 (0101), program state P13 (0100), program state P14 (0110), and program state P15 (0111).

[0079] In an embodiment of the present disclosure, by determining whether the peripheral circuit receives a prefix command and generating a determination result, it is determined whether to use a portion of the storage space of the QLC memory as at least one of SLC, MLC, and TLC according to the determination result, which is useful for accurately configuring the NAND memory.

[0080] In some embodiments, the method further includes storing, by the peripheral circuitry, a group of the page data of the n groups of page data in a spare data register if the data register is corrupted. For example, referring to FIG. 9 , if data register 1 is corrupted, the peripheral circuitry stores the LP data in spare data register 4, and / or if data register 2 is corrupted, the peripheral circuitry stores the MP data in spare data register 5, etc.

[0081] It should be noted that in this example, only two spare data registers are shown, and the number of spare data registers in the memory is not limited to 2, but can be 1, 3, or more, which is not limited in the present disclosure. In practical applications, the number of spare data registers can be reasonably set according to requirements.

[0082] An embodiment of the present disclosure also provides a memory controller. The memory controller is coupled to a memory. The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, where m is a positive integer greater than 1. The memory controller controls the peripheral circuit to determine an (n+1)th group of page data according to a prefix command and n groups of page data, and to store 2 bits of information in the memory cell array. n The memory device is configured to send a prefix command and n groups of page data to the peripheral circuitry to generate n different data states, where n is a positive integer and n+1 is a positive integer less than or equal to

[0083] In some embodiments, the prefix command includes a first sub-prefix command that is used to indicate that an XOR operation is to be performed on n groups of page data.

[0084] The memory controller is specifically configured to send the first sub-prefix command and the n groups of page data to the peripheral circuitry to cause the peripheral circuitry to perform an XOR operation on the n groups of page data in accordance with the first sub-prefix command to generate an mth group of page data, where n+1 is equal to m.

[0085] In some embodiments, the prefix command includes a second sub-prefix command that is used to indicate that an NXOR operation is to be performed on n groups of page data.

[0086] The memory controller is specifically configured to send the second sub-prefix command and the n groups of page data to the peripheral circuitry to cause the peripheral circuitry to perform an XOR operation on the n groups of page data in accordance with the second sub-prefix command to generate the (n+1)th group of page data.

[0087] The memory controller is further configured to send the mth group of page data to the peripheral circuitry, where the mth group of page data is a sequence of all 0s or a sequence of all 1s, and the difference between m and n is 2.

[0088] In some embodiments, the prefix command includes a third sub-prefix command that is used to indicate that the (n+1)th group of page data is equal to the nth group of page data.

[0089] The memory controller is specifically configured to send a third sub-prefix command and the n groups of page data to the peripheral circuitry to cause the peripheral circuitry to perform a copy operation on the n groups of page data in accordance with the third sub-prefix command to generate the (n+1)th group of page data.

[0090] The memory controller is further configured to send the (n+2)th group of page data and the mth group of page data to the peripheral circuitry, where the (n+2)th group of page data and the mth group of page data are a sequence of all 0s or a sequence of all 1s, and the difference between m and n is 3.

[0091] In some embodiments, after sending the prefix command, the memory controller is further configured to send a write command to the peripheral circuitry to cause the peripheral circuitry to write at least the n groups of page data and the (n+1)th group of page data to the memory cell array according to the write command.

[0092] 10 is a schematic diagram of a memory 100 shown in accordance with an embodiment of the present disclosure. Referring to FIG. 10, the memory 100 includes: a memory cell array 101 including memory cells 106 capable of storing m bits of information; a peripheral circuit 102 coupled to the memory cell array 101; Including, the peripheral circuit 102 is configured to determine an (n+1)th group of page data according to the received prefix command and the received n groups of page data, where n is a positive integer and n+1 is a positive integer less than or equal to m; The peripheral circuit 102 is provided in the memory cell array 101. n The memory cell array 101 is further configured to write the n groups of page data and the (n+1)th group of page data to generate n different data states.

[0093] The memory cell array 101 may be an array of NAND flash memory cells. The memory cell array 101 is provided in the form of an array of NAND memory strings 108, with each NAND memory string 108 extending vertically. In some implementations, each NAND memory string 108 includes multiple memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped within the region of the memory cell 106. Each memory cell 106 may be a floating-gate type memory cell including a floating-gate transistor or a charge-trap type memory cell including a charge-trap transistor.

[0094] In some implementations, each memory cell 106 is a single-level cell that has two possible data states and can therefore store one bit of data. For example, a first data state "0" may correspond to a first voltage range, and a second data state "1" may correspond to a second voltage range.

[0095] In some embodiments, each memory cell 106 is a cell that can store two or more bits of data in five or more data states. For example, two bits can be stored per cell (also called a multi-level cell), three bits can be stored per cell (also called a triple-level cell), or four bits can be stored per cell (also called a quad-level cell). Each multi-level cell can be programmed to assume a range of possible nominal storage values. In one example, if each multi-level cell stores two bits of data, the multi-level cell can be programmed to assume one of three possible data states from the erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0096] 10, each NAND memory string 108 may include a source select transistor (SST) 110 at its source terminal and a drain select transistor (DST) 112 at its drain terminal. The source select transistor 110 and the drain select transistor 112 may be configured to activate a selected NAND memory string 108 (column of the array) during read and write operations.

[0097] In some implementations, the sources of the NAND memory strings 108 in the same memory block 104 are coupled via the same source line (SL) 114. In other words, according to some implementations, all the NAND memory strings 108 in the same memory block 104 have an array common source (ACS).

[0098] According to some implementations, the drain select transistor 112 of each NAND memory string 108 is coupled to a corresponding bit line 116 from which data can be read and written via an output bus (not shown).

[0099] In some implementations, each NAND memory string 108 is configured to apply a select voltage (e.g., higher than the threshold voltage of the drain select transistor 112) or a non-select voltage (e.g., 0V) to a corresponding drain select gate via one or more drain select gate lines 111, where the select voltage is used to turn on the drain select transistor 112 and the non-select voltage is used to turn off the drain select transistor 112. And / or, in some implementations, each NAND memory string 108 is configured to apply a select voltage (e.g., higher than the threshold voltage of the source select transistor 110) or a non-select voltage (e.g., 0V) to a corresponding source select gate via one or more source select gate lines 115, where the select voltage is used to turn on the source select transistor 110 and the non-select voltage is used to turn off the source select transistor 110.

[0100] 10, a NAND memory string 108 may be organized into multiple memory blocks 104, each of which may have a common source line 114 (e.g., coupled to ground). In some implementations, each memory block 104 is the basic data unit for an erase operation. That is, all memory cells on the same memory block 104 are erased simultaneously.

[0101] In some examples, erase operations may be performed at a half-block level, a quarter-block level, or any suitable number of blocks or percentages of blocks. Memory cells 106 of adjacent NAND memory strings 108 may be coupled by word lines 118 that select which rows of memory cells 106 are affected by read and write operations.

[0102] In some implementations, each word line 118 is referred to as a memory page 120. The size of a memory page 120 in bits may be related to the number of NAND memory strings 108 coupled by the word line 118 in the memory block 104. Each word line 118 may include multiple control gates (gate electrodes) at each memory cell 106 in the corresponding memory page 120 and gate lines coupling the control gates. A row of memory cells may be understood to be multiple memory cells 106 arranged within the same memory page 120.

[0103] 11 is a cross-sectional view of a NAND memory string 108 shown in accordance with an embodiment of the present disclosure. As shown in FIG. 11, the NAND memory string 108 may extend vertically through memory stack layers 204 and onto a substrate 202. The substrate 202 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0104] The memory stack layers 204 may include alternating gate conductive layers 206 and gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate dielectric layers 208 in the memory stack layers 204 may determine the number of memory cells 106 in the memory cell array 101.

[0105] The gate conductive layers 206 may include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate conductive layer 206 may include a metal layer, such as a tungsten layer. In some implementations, each gate conductive layer 206 may include a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding a memory cell 106, and may extend laterally across the top of the memory stack layers 204 as a drain select gate line 111, across the bottom of the memory stack layers 204 as a source select gate line 115, or between the drain select gate line 111 and the source select gate line 115 as a word line 118.

[0106] As shown in FIG. 11 , the NAND memory string 108 includes a channel structure 212 that extends vertically through the memory stack layers 204. In some embodiments, the channel structure 212 includes a channel hole filled with a semiconductor material (e.g., as the semiconductor channel 220) and a dielectric material (e.g., as the storage film 218). In some embodiments, the semiconductor channel 220 includes silicon, e.g., polysilicon. In some embodiments, the storage film 218 is a composite dielectric layer including a tunnel layer 226, a storage layer 224 (also referred to as a “charge trap / storage layer”), and a barrier layer 222. The channel structure 212 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 220, the tunnel layer 226, the storage layer 224, and the barrier layer 222 are radially arranged in this order from the center of the cylinder toward the outer surface of the cylinder. The tunnel layer 226 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 224 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 222 may include silicon oxide, silicon oxynitride, a high-dielectric constant (high-k) dielectric, or any combination thereof. In one example, the storage film 218 may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0107] 11, a well 214 (e.g., a P-well and / or an N-well) is formed in the substrate 202, and the source terminal of the NAND memory string 108 is in contact with the well 214. In some implementations, the NAND memory string 108 further includes a channel plug 216 at the drain terminal of the NAND memory string 108. Although not shown in FIG. 11, it should be understood that additional components of the memory cell array 101 may be formed, including, but not limited to, gate line gap / source contacts, local contacts, interconnect layers, etc.

[0108] 10 , the peripheral circuitry 102 may be coupled to the memory cell array 101 via bit lines 116, word lines 118, source lines 114, source select gate lines 115, and drain select gate lines 111. The peripheral circuitry 102 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to and sensing voltage and / or current signals from each memory cell 106 via the bit lines 116, word lines 118, source lines 114, source select gate lines 115, and drain select gate lines 111 to facilitate operation of the memory cell array 101.

[0109] In some embodiments, when n+1 is equal to m, the prefix command includes a first sub-prefix command, where the first sub-prefix command indicates to perform an XOR operation on n groups of page data.

[0110] The peripheral circuit 102 is specifically configured to perform an XOR operation on the n groups of page data according to the first sub-prefix command to generate an mth group of page data.

[0111] The peripheral circuit 102 is also specifically configured to write n groups of page data and an mth group of page data to the memory cell array to store m bits of information in the memory cells.

[0112] In some embodiments, the peripheral circuitry 102 includes: a plurality of data registers used to store n groups of page data, each data register used to store a group of page data; a cache register used to store the mth group of page data; Includes.

[0113] In some embodiments, the peripheral circuitry 102 includes: A spare data register is included which is used to store a group of page data in the n groups of page data when a data register is corrupted.

[0114] In some embodiments, if the difference between m and n is 2, the prefix command includes a second sub-prefix command, which indicates to perform an NXOR operation on n groups of page data.

[0115] The peripheral circuit 102 is specifically configured to perform an NXOR operation on the n groups of page data according to the second sub-prefix command to generate the (n+1)th group of page data.

[0116] The peripheral circuit 102 is further configured to write an mth group of page data to the memory cell array to store m bits of information in the memory cells, where the mth group of page data is a sequence of all 0s or a sequence of all 1s.

[0117] In some embodiments, the peripheral circuitry 102 includes: a plurality of data registers used to store n groups of page data and an (n+1)th group of page data, each data register used to store a group of page data; a cache register used to store the mth group of page data; Includes.

[0118] In some embodiments, if the difference between m and n is 3, the prefix command includes a third sub-prefix command, and the third sub-prefix command indicates that the (n+1)th group of page data is equal to the nth group of page data.

[0119] The peripheral circuit 102 is specifically configured to perform copy operations on the n groups of the page data according to the third sub-prefix command to generate the (n+1)th group of the page data.

[0120] The peripheral circuit 102 is further configured to write the (n+2)th group of page data and the mth group of page data to the memory cell array to store m bits of information in the memory cells, where the (n+2)th group of page data and the mth group of page data are a sequence of all 0s or a sequence of all 1s.

[0121] In some embodiments, the peripheral circuitry 102 includes: a plurality of data registers used to store n groups of page data, an (n+1)th group of page data, and an (n+2)th group of page data, each data register used to store a group of page data; a cache register used to store the mth group of page data; Includes.

[0122] In some embodiments, the peripheral circuitry 102 includes: Before determining the (n+1)th group of page data, determining whether a prefix command is received and generating a determination result; If the determination result indicates that a prefix command is received, determine an (n+1)th group of page data according to the received prefix command and the n groups of page data; If the determination result indicates that the prefix command has not been received, then 2 m Writing m groups of page data to the memory cell array to generate m different data states It is further configured as follows.

[0123] The peripheral circuits 102 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG. 12 shows some exemplary peripheral circuits 102, including a page buffer / sense amplifier 304, a column decoder / bitline (BL) driver 306, a row decoder / wordline (WL) driver 308, a voltage generator 310, a control logic unit 312, a register 314, an interface 316, and a data bus 318. It should be understood that in some examples, additional peripheral circuits not shown in FIG. 12 may also be included.

[0124] The page buffer / sense amplifier 304 may be configured to read data from and write (program) data to the memory cell array 101 according to control signals from the control logic unit 312. In one example, the page buffer / sense amplifier 304 may store a page of write data (programmed data) to be programmed into one memory page 120 of the memory cell array 101. In another example, the page buffer / sense amplifier 304 may perform a program verify operation to ensure that data has been correctly programmed into the memory cells 106 coupled to a selected word line 118. In yet another example, the page buffer / sense amplifier 304 may further sense low-power signals from the bit lines 116 representing data bits stored in the memory cells 106 and amplify small voltage swings to recognizable logic levels during read operations. The column decoder / bit line driver 306 may be controlled by the control logic unit 312 and configured to select one or more NAND memory strings 108 by applying bit line voltages generated from the voltage generator 310.

[0125] The row decoder / word line driver 308 may be controlled by a control logic unit 312 and configured to select / deselect memory blocks 104 of the memory cell array 101 and select / deselect word lines of the memory blocks 104. The row decoder / word line driver 308 receives a word line voltage (V WL) to drive the word lines 118. In some implementations, the row decoder / word line driver 308 can also select / deselect and drive the source select gate lines 115 and the drain select gate lines 111. As described in more detail below, the row decoder / word line driver 308 is configured to perform an erase operation on the memory cells 106 coupled to the selected word lines 118. The voltage generator 310 is controlled by the control logic unit 312 and can be configured to generate word line voltages (e.g., read voltages, write voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 101.

[0126] The control logic unit 312 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 314 may be coupled to the control logic unit 312 and may include a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 316 may be coupled to the control logic unit 312 and may function as a control buffer that buffers control commands received from a host (not shown) and relays them to the control logic unit 312, and buffers status information received from the control logic unit 312 and relays it to the host. The interface 316 may also be coupled to the column decoder / bit line driver 306 via a data bus 318 and may function as a data I / O interface and a data buffer that buffers data to and from the memory cell array 101.

[0127] It should be emphasized that the peripheral circuitry 102 is configured to perform write operations provided by embodiments of the present disclosure on selected rows of memory cells among a plurality of rows of memory cells.

[0128] 13 is a schematic diagram of a memory system 400 shown in accordance with an embodiment of the present disclosure. Referring to FIG. 13, the memory system 400 includes: one or more memories 100 as described in the above embodiments; a memory controller 406, as described in the above embodiments, coupled to the memory 100 and configured to control the memory 100; Includes.

[0129] System 400 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a pointing device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0130] 13, the system 400 may include a host 408 and a storage subsystem 402 having one or more memories 100. The storage subsystem further includes a memory controller 406. The host 408 may be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 408 may be configured to send data to the memory 100. Alternatively, the host 408 may be configured to receive data from the memory 100.

[0131] Memory 100 can be any memory device disclosed in this disclosure. Memory 100 (e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)) can reduce leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further size reduction of the drive transistors.

[0132] According to some implementations, the memory controller 406 is further coupled to a host 408. The memory controller 406 may manage data stored in the memory 100 and communicate with the host 408.

[0133] In some implementations, the memory controller 406 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, CompactFlash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0134] In some implementations, the memory controller 406 is designed for operation in a high duty cycle environment with a solid-state drive (SSD) or embedded multimedia card (eMMC), which are used as data storage in mobile devices such as smartphones, tablet computers, laptop computers, and enterprise memory arrays.

[0135] Memory controller 406 may be configured to control operations of memory 100, such as read, erase, and program operations. Memory controller 406 may be further configured to manage various functions related to data stored or to be stored in memory 100, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, memory controller 406 is further configured to process error correcting codes (ECC) on data read from or written to memory 100.

[0136] The memory controller 406 may further perform any other suitable functions, such as formatting the memory 100. The memory controller 406 may communicate with an external device (e.g., a host 408) according to a particular communication protocol. For example, the memory controller 406 may communicate with an external device via at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Device Electronics (IDE) protocol, a Firewire protocol, etc.

[0137] The memory controller 406 and one or more memories 100 may be integrated into various types of storage devices, for example, contained within the same package (e.g., a universal flash storage (UFS) package or an eMMC package), i.e., the memory system 400 may be implemented and packaged in various types of end electronic products.

[0138] 14, the memory controller 406 and the single memory 100 may be integrated into a memory card 502. The memory card 502 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a memory stick, a multimedia card (MMC, ES-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 502 may further include a memory card connector 504 that couples the memory card 502 to a host (e.g., host 408 in FIG. 13).

[0139] 14b, the memory controller 406 and the plurality of memories 100 may be integrated into a solid-state drive (SSD) 506. The solid-state drive 506 may further include a solid-state drive connector 508 that couples the solid-state drive 506 to a host (e.g., the host 408 in FIG. 13). In some implementations, the storage capacity and / or operating speed of the solid-state drive 506 is greater than the storage capacity and / or operating speed of the memory card 502.

[0140] It can be understood that the memory controller 406 can perform the operational methods provided by any embodiment of the present disclosure.

[0141] Obviously, the above-described embodiments are not limiting implementation forms, but merely examples for clear explanation. Those skilled in the art can make other changes or modifications in various forms based on the above description. It is not necessary or possible to comprehensively list all implementation forms in this specification. Any obvious changes or modifications derived therefrom fall within the scope of protection created by the present disclosure. [Explanation of symbols]

[0142] 1 Data Register 2 Data Registers 3 Data Register 4 Reserved Data Registers 5 Reserved Data Registers 10 Memory System 11 Controller 12 Memory Cell Array 13 Scrambler 14 ECC Encoder 15 ECC Decoder 16 Descrambler 100 memory 101 memory cell array 102 Peripheral Circuit 104 memory blocks 106 memory cells 108 NAND memory strings 110 Source select transistor (SST), source select transistor 111 drain select gate line 112 Drain select transistor (DST), drain select transistor 114 Source Line (SL), Source Line 115 Source Select Gate Line 116 bit lines 118 Word Line 120 memory pages 202 Substrate 204 Memory Stack Layer 206 Gate conductive layer 208 Gate dielectric layer 212 Channel Structure 214 wells 216 Channel Plug 218 Memory Membrane 220 semiconductor channels 222 Barrier Layer 224 Memory layer 226 Tunnel Layer 304 Page Buffer / Sense Amplifier 306 Column Decoder / Bit Line (BL) Driver 308 Row Decoder / Wordline (WL) Driver 310 Voltage Generator 312 Control Logic Unit 314 registers 316 Interface 318 Data Bus 400 Memory System 402 Memory Subsystem 406 Memory Controller 408 Host 502 memory card 504 memory card connector 506 Solid State Drive (SSD), Solid State Drive 508 Solid State Drive Connector

Claims

1. 1. A method of operating a memory system, the memory system comprising a memory, the memory comprising a memory cell array and a peripheral circuit coupled to the memory cell array, the memory cell array comprising memory cells capable of storing m bits of information, m being a positive integer greater than 1, the method comprising: determining, by the peripheral circuit, according to the received prefix command and the received n groups of page data, an (n+1)th group of page data by performing an operation according to the prefix command on the n groups of page data, where n is a positive integer and n+1 is a positive integer less than or equal to m; There are two memory cell arrays n writing the n groups of page data and the (n+1)th group of page data to the memory cell array to generate n different data states; , including a method of operation.

2. if n+1 is equal to m, the prefix command includes a first sub-prefix command, the first sub-prefix command indicating to perform an XOR operation on n groups of the page data; determining, by the peripheral circuit, the (n+1)th group of page data according to the received prefix command and the n groups of page data; performing, by the peripheral circuitry, the XOR operation on the n groups of the page data in accordance with the first sub-prefix command to generate an mth group of page data; writing the n groups of page data and the (n+1)th group of page data to the memory cell array; 2. The method of claim 1, comprising writing the n groups of page data and the mth group of page data to the memory cell array to store m bits of information in the memory cells.

3. Before writing the n groups of page data and the m-th group of page data to the memory cell array, the operating method includes: storing the n groups of page data in a plurality of data registers, each of the data registers being used to store a group of page data; storing the mth group of page data in a cache register; The method of claim 2 further comprising:

4. if the difference between m and n is 2, the prefix command includes a second sub-prefix command, the second sub-prefix command indicating to perform an NXOR operation on n groups of the page data; determining, by the peripheral circuit, the (n+1)th group of page data according to the received prefix command and the n groups of page data; performing, by the peripheral circuitry, the NXOR operation on the n groups of the page data in accordance with the second sub-prefix command to generate an (n+1)th group of the page data; The operating method comprises:

2. The method of claim 1, further comprising writing an mth group of page data to the memory cell array to store m bits of information in the memory cells, wherein the mth group of page data is a sequence of all 0s or a sequence of all 1s.

5. if the difference between m and n is 3, the prefix command includes a third sub-prefix command, and the third sub-prefix command indicates that the (n+1)th group of page data is equal to the nth group of page data of the n groups of page data; determining, by the peripheral circuit, the (n+1)th group of page data according to the received prefix command and the n groups of page data; performing, by the peripheral circuitry, a copy operation on the n groups of the page data in accordance with the third sub-prefix command to generate an (n+1)th group of the page data; The operating method comprises:

2. The method of claim 1, further comprising writing an (n+2)th group of page data and an mth group of page data to the memory cell array to store m bits of information in the memory cells, wherein the (n+2)th group of page data and the mth group of page data are a sequence of all 0s or a sequence of all 1s.

6. Before determining the (n+1)th group of page data, the method further comprises: determining whether the prefix command has been received and generating a determination result; if the determining result indicates that the prefix command has been received, determining an (n+1)th group of the page data according to the received prefix command and the n groups of page data; The method of claim 1 further comprising:

7. If the determination result indicates that the prefix command has not been received, m 7. The method of claim 6, wherein m groups of page data are written to the memory cell array to generate m different data states.

8. A memory controller, the memory controller coupled to a memory, the memory comprising a memory cell array and a peripheral circuit coupled to the memory cell array, the memory cell array including memory cells capable of storing m bits of information, m being a positive integer greater than 1, the memory controller comprising at least: and causing the peripheral circuit to determine an (n+1)th group of page data by performing an operation according to the prefix command on the n groups of page data in accordance with the prefix command, and storing two (n+1)th groups of page data in the memory cell array. n and configured to send the prefix command and n groups of the page data to the peripheral circuitry to generate n different data states, where n is a positive integer and n+1 is a positive integer less than or equal to m.

9. the prefix command includes a first sub-prefix command, the first sub-prefix command being used to indicate that an XOR operation is to be performed on n groups of the page data; 9. The memory controller of claim 8, wherein the memory controller is configured to send the first sub-prefix command and the n groups of page data to the peripheral circuitry to cause the peripheral circuitry to perform the XOR operation on the n groups of page data in accordance with the first sub-prefix command to generate an mth group of page data.

10. the prefix command includes a second sub-prefix command, the second sub-prefix command being used to indicate that an NXOR operation is to be performed on n groups of the page data; the memory controller is configured to send the second sub-prefix command and the n groups of page data to the peripheral circuitry to cause the peripheral circuitry to perform the NXOR operation on the n groups of page data in accordance with the second sub-prefix command to generate an (n+1)th group of the page data; 10. The memory controller of claim 8, wherein the memory controller is further configured to send an mth group of page data to the peripheral circuitry, wherein the mth group of page data is a sequence of all 0s or a sequence of all 1s, and wherein a difference between m and n is 2.

11. the prefix command includes a third sub-prefix command, the third sub-prefix command being used to indicate that the (n+1)th group of page data is equal to the nth group of page data; the memory controller is configured to send the third sub-prefix command and the n groups of page data to the peripheral circuitry to cause the peripheral circuitry to perform a copy operation on the n groups of page data in accordance with the third sub-prefix command to generate an (n+1)th group of the page data; 9. The memory controller of claim 8, wherein the memory controller is further configured to send an (n+2)th group of page data and an mth group of page data to the peripheral circuitry, wherein the (n+2)th group of page data and the mth group of page data are a sequence of all 0s or a sequence of all 1s, and wherein a difference between m and n is 3.

12. The memory controller:

9. The memory controller of claim 8, further configured: after sending the prefix command, to send the write command to the peripheral circuitry to cause the peripheral circuitry to write at least the n groups of the page data and the (n+1)th group of the page data to the memory cell array according to the write command.

13. a memory cell array including memory cells capable of storing m bits of information; peripheral circuitry coupled to the memory cell array; A memory comprising: the peripheral circuit is configured to determine an (n+1)th group of page data according to a received prefix command and the received n groups of page data by performing an operation according to the prefix command on the n groups of page data, where n is a positive integer and n+1 is a positive integer less than or equal to m; The peripheral circuit has two n the memory further configured to write the n groups of page data and the (n+1)th group of page data to the memory cell array to generate n different data states.

14. if n+1 is equal to m, the prefix command includes a first sub-prefix command, the first sub-prefix command indicating to perform an XOR operation on n groups of the page data; the peripheral circuitry is specifically configured to perform the XOR operation on the n groups of the page data according to the first sub-prefix command to generate an m group of page data; 14. The memory of claim 13, wherein the peripheral circuitry is further configured to: write the n groups of page data and the mth group of page data to the memory cell array, specifically to store m bits of information in the memory cells.

15. The peripheral circuitry a plurality of data registers used to store n groups of the page data, each of the data registers being used to store a group of page data; a cache register used to store the mth group of page data; The memory of claim 14, comprising:

16. The peripheral circuitry a spare data register used to store the n groups of page data when the data register is corrupted; 16. The memory of claim 15, comprising:

17. if the difference between m and n is 2, the prefix command includes a second sub-prefix command, the second sub-prefix command indicating to perform an NXOR operation on n groups of the page data; the peripheral circuitry is specifically configured to perform the NXOR operation on the n groups of the page data in accordance with the second sub-prefix command to generate an (n+1)th group of the page data; 14. The memory of claim 13, wherein the peripheral circuitry is further configured to write an mth group of page data to the memory cell array to store m bits of information in the memory cells, the mth group of page data being a sequence of all 0s or a sequence of all 1s.

18. if the difference between m and n is 3, the prefix command includes a third sub-prefix command, and the third sub-prefix command indicates that the (n+1)th group of page data is equal to the nth group of page data; the peripheral circuitry is specifically configured to perform copy operations on the n groups of the page data according to the third sub-prefix command to generate an (n+1)th group of the page data; 14. The memory of claim 13, wherein the peripheral circuitry is further configured to write an (n+2)th group of page data and an mth group of page data to the memory cell array to store m bits of information in the memory cells, wherein the (n+2)th group of page data and the mth group of page data are a sequence of all 0s or a sequence of all 1s.

19. The peripheral circuitry Before determining the (n+1)th group of page data, determine whether the prefix command is received and generate a determination result; If the determination result indicates that the prefix command has been received, determine the (n+1)th group of page data according to the received prefix command and the n groups of page data.

14. The memory of claim 13, further configured to:

20. If the determination result indicates that the prefix command has not been received, the peripheral circuit m 20. The memory of claim 19, further configured to write m groups of page data to the memory cell array to generate m different data states.

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