Memory control device, control method and program for memory control device

Abstract

To enable the reduction of performance overhead and power consumption overhead.SOLUTION: A memory control device accesses a memory which needs synchronization between a clock signal for command transfer and a clock signal for data transfer, the clock signal for command transfer being independent of the clock signal for data transfer. The memory control device has output means for switching an output mode of the clock signal for data transfer in accordance with a state of memory access, and outputting the clock signal for data transfer to the memory in accordance with the output mode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a memory control device, a control method for a memory control device, and a program. [Background technology]

[0002] DRAM is generally used as the main memory of computer systems. As computer systems become more sophisticated and powerful, the performance requirements for DRAM are increasing, and it is necessary to maximize its performance.

[0003] As in Patent Document 1, in the recently formulated LPDDR5, the clock signal is separated into a clock signal for command transfer and a clock signal for data transfer. This means that the clock signal for data transfer and the clock signal for command transfer must be synchronized, and a CAS command must be issued prior to a read command or a write command. In addition, there is a mode in which the clock signal for data transfer is always output, eliminating the need to issue a CAS command to synchronize the clock signal for data transfer and the clock signal for command transfer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-96739 Summary of the Invention [Problem to be solved by the invention]

[0005] In a mode in which the data transfer clock signal is output only when necessary, a CAS command must be issued before a read or write command, which can cause performance overhead. Also, when switching the rank to be accessed, a CAS command for the rank to be accessed later must be issued taking into account the timing when the previously accessed rank loses synchronization, which can cause performance overhead.

[0006] On the other hand, in a mode in which the data transfer clock signal is constantly output, the data transfer clock signal alternates between high and low levels even during periods when no data is being transferred, which causes overhead in terms of power consumption.

[0007] The objective of the present disclosure is to enable a reduction in performance overhead and power consumption overhead. [Means for solving the problem]

[0008] The memory control device is a memory control device that accesses a memory in which a command transfer clock signal and a data transfer clock signal are independent and synchronization between the command transfer clock signal and the data transfer clock signal is required, and has output means that switches the output mode of the data transfer clock signal depending on the state of memory access, and outputs the data transfer clock signal to the memory depending on the output mode. [Effects of the Invention]

[0009] According to the present disclosure, it is possible to reduce overhead in terms of performance and power consumption. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a diagram illustrating an example of the configuration of a memory control circuit. [Figure 2] FIG. 10 is a transition diagram of the memory effective bandwidth and the data transfer clock signal output mode. [Figure 3]10A and 10B are diagrams illustrating operation waveforms of a memory control circuit. [Figure 4] 10A and 10B are diagrams showing operational waveforms when the data transfer clock signal output mode is changed. [Figure 5] 10A and 10B are diagrams showing operational waveforms when the data transfer clock signal output mode is changed. [Figure 6] 10A and 10B are diagrams illustrating waveforms of a command, a clock signal for data transfer, and data. [Figure 7] 10A and 10B are diagrams illustrating waveforms of a command, a clock signal for data transfer, and data. [Figure 8] 10A and 10B are diagrams illustrating waveforms of a command, a clock signal for data transfer, and data. [Figure 9] 10A and 10B are diagrams illustrating waveforms of a command, a clock signal for data transfer, and data. [Figure 10] FIG. 2 is a diagram illustrating an example of the configuration of a memory control circuit. [Figure 11] FIG. 10 is a transition diagram of a data transfer clock signal output mode. DETAILED DESCRIPTION OF THE INVENTION

[0011] (First embodiment) 1 is a diagram showing an example of the configuration of a memory control circuit 100 according to the first embodiment. A memory 900 is connected to the memory control circuit 100. The memory control circuit 100 is a memory control device, and outputs a memory command and a data transfer clock signal WCK to the memory 900.

[0012] The memory 900 is, for example, an SDRAM conforming to the LPDDR5 standard. LPDDR5 is a standard for low-power consumption SDRAM. LPDDR5 separates a command transfer clock signal CK and a data transfer clock signal WCK. The memory control circuit 100 issues a CAS command to synchronize the command transfer clock signal CK and the data transfer clock signal WCK, and operates the data transfer clock signal WCK only during periods when data transfer is required, thereby reducing power consumption. The memory 900 has multiple ranks. Each of the multiple ranks has, for example, multiple SDRAM modules.

[0013] The memory control circuit 100 includes an access holding circuit 101, a memory command generation circuit 102, a memory bandwidth measurement circuit 103, a memory access state determination circuit 104, and a WCK generation circuit 105. The WCK generation circuit 105 is a clock signal generation circuit for data transfer.

[0014] The access holding circuit 101 holds a plurality of access commands received from the outside. The memory command generation circuit 102 generates a memory command from the access command held by the access holding circuit 101 and issues the memory command to the memory 900. The memory command is a read command or a write command. Furthermore, the memory command generation circuit 102 determines whether to issue a CAS command prior to issuing a read command or a write command, depending on the data transfer clock signal output mode (WCK output mode) from the WCK generation circuit 105. The CAS command is a synchronization command for synchronizing the data transfer clock signal WCK and the command transfer clock signal CK.

[0015] The memory bandwidth measurement circuit 103 counts the number of read commands and write commands issued by the memory command generation circuit 102. The memory bandwidth measurement circuit 103 also resets the counted number of commands at regular intervals. Therefore, the memory bandwidth measurement circuit 103 counts the number of read commands and write commands at regular intervals.

[0016] The memory access state determination circuit 104 determines whether the memory access state is busy or not based on the number of commands measured by the memory bandwidth measurement circuit 103 and the command number threshold. The memory access state determination circuit 104 determines that the memory access state is busy if the number of commands measured by the memory bandwidth measurement circuit 103 is equal to or greater than the command number threshold. Furthermore, the memory access state determination circuit 104 determines that the memory access state is non-busy if the number of commands measured by the memory bandwidth measurement circuit 103 is less than the command number threshold.

[0017] The WCK generation circuit 105 is a data transfer clock signal generation circuit. When the memory access state determined by the memory access state determination circuit 104 is a busy state, the WCK generation circuit 105 sets the WCK output mode to a constant output mode, and constantly outputs the data transfer clock signal WCK to the memory 900. When the memory access state determined by the memory access state determination circuit 104 is not a busy state, the WCK generation circuit 105 sets the WCK output mode to a mode that outputs the WCK only when necessary. In the only when necessary output mode, the WCK generation circuit 105 outputs the data transfer clock signal WCK to the memory 900 in accordance with the timing at which the memory command generation circuit 102 issues a read command or a write command.

[0018] FIG. 2 is a time series diagram showing the effective bandwidth and WCK output mode of the memory 900 according to this embodiment. Here, the memory bandwidth measurement circuit 103 measures the effective bandwidth of the memory 900 at regular intervals. The regular interval is, for example, 0.5 ms. The initial value of the WCK output mode is a mode in which the WCK is output only when necessary. If the effective bandwidth of the memory 900 measured by the memory bandwidth measurement circuit 103 is equal to or greater than the effective bandwidth threshold, the memory access state determination circuit 104 determines that the memory access state is busy. The effective bandwidth threshold is set to 60%. The control method of the memory control circuit 100 will be described below.

[0019] Before period P1, the WCK output mode is the output mode only when necessary. During period P1, the memory access state determination circuit 104 determines that the memory access state is busy because the effective bandwidth of the memory 900 is equal to or greater than the effective bandwidth threshold. Then, the WCK generation circuit 105 changes the WCK output mode to a mode in which the WCK is always output from the next period.

[0020] In period P8, the memory access state determination circuit 104 determines that the memory access state is non-busy because the effective bandwidth of the memory 900 is less than the effective bandwidth threshold. Then, from the next period, the WCK generation circuit 105 changes the WCK output mode to a mode in which the WCK is output only when necessary.

[0021] In period P16, the memory access state determination circuit 104 determines that the memory access state is busy because the effective bandwidth of the memory 900 is equal to or greater than the effective bandwidth threshold. Then, the WCK generation circuit 105 changes the WCK output mode to a mode in which the WCK is always output from the next period.

[0022] In period P23, the memory access state determination circuit 104 determines that the memory access state is non-busy because the effective bandwidth of the memory 900 is less than the effective bandwidth threshold. Then, from the next period, the WCK generation circuit 105 changes the WCK output mode to a mode in which the WCK is output only when necessary.

[0023] In this embodiment, the effective bandwidth of the memory 900 is defined as the number of read commands and write commands issued to the memory 900. If the frequency of the clock signal CK for command transfer of the memory 900 is 800 MHz, a period of 0.5 ms is 400 cycles. If a read command or write command can be issued at a maximum rate of one every two cycles, a maximum of 200 read commands or write commands can be issued in a period of 0.5 ms. In other words, when 200 read commands or write commands are issued in a period of 0.5 ms, the effective bandwidth of the memory 900 is 100%. Because the effective bandwidth threshold is 60%, when 120 or more read commands or write commands are issued in a period of 0.5 ms, the effective bandwidth of the memory 900 is equal to or greater than the effective bandwidth threshold. Furthermore, when fewer than 120 read commands or write commands are issued in a period of 0.5 ms, the effective bandwidth of the memory 900 is less than the effective bandwidth threshold. Therefore, the command number threshold is 120.

[0024] FIG. 3 shows the number of commands measured by the memory bandwidth measurement circuit 103, the memory access state determined by the memory access state determination circuit 104, and the WCK output mode set by the WCK generation circuit 105, taking the period P7 to the period P9 as an example.

[0025] In period P7, the number of commands measured by the memory bandwidth measurement circuit 103 is 140. In period P8, the number of commands measured by the memory bandwidth measurement circuit 103 is 110. In period P9, the number of commands measured by the memory bandwidth measurement circuit 103 is 100.

[0026] The memory access state determination circuit 104 sets the memory access state to a busy state during period P8 because the number of commands (140) measured during period P7 is equal to or greater than the command number threshold (120). Also, the memory access state determination circuit 104 sets the memory access state to a non-busy state during period P9 because the number of commands (110) measured during period P8 is less than the command number threshold (120).

[0027] When the memory access state is busy, the WCK generation circuit 105 sets the WCK output mode to a mode in which the WCK is always output, and when the memory access state is non-busy, sets the WCK output mode to a mode in which the WCK is output only when necessary.

[0028] When the WCK output mode changes from a mode in which the WCK is output only when necessary to a mode in which the WCK is always output, the memory command generation circuit 102 issues an MRW command to change the settings of the memory 900. This is shown in FIG. 4. The memory 900 has, for example, ranks R1 and R2. At time T1, the WCK output mode changes from a mode in which the WCK is output only when necessary to a mode in which the WCK is always output. Accordingly, at time T2, the memory command generation circuit 102 issues an MRW command to ranks R1 and R2 of the memory 900. Thereafter, at time T5, the memory command generation circuit 102 issues a CAS command to rank R1 of the memory 900 prior to the first read command RD (or write command). The CAS command is a synchronization command for synchronizing the data transfer clock signal WCK and the command transfer clock signal CK. At time T6, the memory command generation circuit 102 issues the first read command RD to rank R1 of the memory 900. A period tWCKENL_RD after the CAS command issuance time T5, the WCK generation circuit 105 starts outputting the data transfer clock signal WCK to the memory 900. During a period tWCKPRE_Static, the WCK generation circuit 105 fixes the data transfer clock signal WCK to a low level (or a high level). After that, during a period tWCKPRE_Toggle_RD, the WCK generation circuit 105 starts repeating the high and low levels of the data transfer clock signal WCK.

[0029] Furthermore, when the WCK output mode changes from a mode in which the WCK is always output to a mode in which the WCK is only output when necessary, the memory command generation circuit 102 issues a CAS command to stop the output of the data transfer clock signal WCK. Then, after the output of the data transfer clock signal WCK stops, the memory command generation circuit 102 issues an MRW command to change the register settings of the memory 900. This is shown in FIG. 5. At time T1, the WCK output mode changes from a mode in which the WCK is always output to a mode in which the WCK is only output when necessary. Accordingly, at time T2, the memory command generation circuit 102 issues a CAS command to ranks R1 and R2 of the memory 900 to stop the output of the data transfer clock signal WCK. After a period tWCKPST, the output of the data transfer clock signal WCK stops, so at time T5, the memory command generation circuit 102 issues an MRW command to ranks R1 and R2 of the memory 900. Thereafter, at time T8, the memory command generation circuit 102 issues a CAS command to rank R1 of the memory 900 prior to a read command RD (or a write command). The CAS command is a synchronization command for synchronizing the data transfer clock signal WCK and the command transfer clock signal CK. At time T9, the memory command generation circuit 102 issues a read command RD to rank R1 of the memory 900. After a period tWCKENL_RD from the time T8 at which the CAS command is issued, the WCK generation circuit 105 starts outputting the data transfer clock signal WCK to the memory 900. During a period tWCKPRE_Static, the WCK generation circuit 105 fixes the data transfer clock signal WCK to a low level (or a high level). Thereafter, during a period tWCKPRE_Toggle_RD, the WCK generation circuit 105 starts repeating the high and low levels of the data transfer clock signal WCK.

[0030] Figures 6 to 9 show examples of waveforms for each WCK output mode, one for issuing two read commands RD to the same rank R1, and one for issuing two read commands RD to different ranks R1 and R2. Each read command RD is accompanied by 16 beats of data. A 16-beat data transfer requires two cycles of the command transfer clock signal CK. Therefore, read commands RD must be issued with an interval of at least two cycles of the command transfer clock signal CK. Read commands to different ranks R1 and R2 must be issued with an interval of at least three cycles of the command transfer clock signal CK to avoid data collisions.

[0031] FIG. 6 shows waveforms when the WCK output mode is a mode in which output is performed only when necessary, and when it is necessary to issue a CAS command between the issuance of two read commands RD to the same rank R1 of the memory 900.

[0032] At time T0, the memory command generation circuit 102 issues a CAS command to rank R1 of the memory 900 to synchronize the data transfer clock signal WCK and the command transfer clock signal CK. At time T1, the memory command generation circuit 102 issues a read command RD to rank R1 of the memory 900. A period tWCKENL_RD has elapsed since the CAS command issuance time T0, and the WCK generation circuit 105 starts outputting the data transfer clock signal WCK to the memory 900. During a period tWCKPRE_Static, the WCK generation circuit 105 fixes the data transfer clock signal WCK to a low level (or a high level). Thereafter, during a period tWCKPRE_Toggle_RD, the WCK generation circuit 105 starts repeating high and low levels of the data transfer clock signal WCK. Thereafter, during a period tWCKENL_RD, the WCK generation circuit 105 continues repeating high and low levels of the data transfer clock signal WCK.

[0033] At time T6, when the memory command generation circuit 102 attempts to issue a read command RD to rank R1 of the memory 900, it is necessary to synchronize the data transfer clock signal WCK and the command transfer clock signal CK. At time T6, the memory command generation circuit 102 issues a CAS command to rank R1 of the memory 900. At time T7, the memory command generation circuit 102 issues a read command RD to rank R1 of the memory 900. During a period tWCKPRE_Static that follows a period tWCKENL_RD from the time T6 when the CAS command is issued, the WCK generation circuit 105 fixes the data transfer clock signal WCK to a low level (or a high level). Thereafter, during a period tWCKPRE_Toggle_RD, the WCK generation circuit 105 starts repeating the high and low levels of the data transfer clock signal WCK.

[0034] FIG. 7 shows waveforms when the WCK output mode is a mode in which output is always performed and there is no need to issue a CAS command between issuing two read commands RD to the same ranks R1 and R2 of the memory 900.

[0035] At time T0, the memory command generation circuit 102 issues a CAS command to rank R1 of the memory 900 to synchronize the data transfer clock signal WCK and the command transfer clock signal CK. At time T1, the memory command generation circuit 102 issues a read command RD to rank R1 of the memory 900. A period tWCKENL_RD has elapsed since the CAS command issuance time T0, and the WCK generation circuit 105 starts outputting the data transfer clock signal WCK to the memory 900. During a period tWCKPRE_Static, the WCK generation circuit 105 fixes the data transfer clock signal WCK to a low level (or a high level). Thereafter, during a period tWCKPRE_Toggle_RD, the WCK generation circuit 105 starts repeating high and low levels of the data transfer clock signal WCK. Thereafter, the WCK generation circuit 105 continues repeating high and low levels of the data transfer clock signal WCK.

[0036] At time T6, if the memory command generation circuit 102 attempts to issue a read command RD to rank R1 of the memory 900, it can immediately issue the read command RD. At time T6, the memory command generation circuit 102 does not issue a CAS command, but issues a read command RD to rank R1 of the memory 900. After that, the WCK generation circuit 105 continues to alternate between high and low levels of the data transfer clock signal WCK.

[0037] FIG. 8 shows waveforms when the WCK output mode is a mode in which output is performed only when necessary, and when it is necessary to issue a CAS command between issuing two read commands RD to different ranks R1 and R2 of the memory 900.

[0038] At time T0, the memory command generation circuit 102 issues a CAS command to rank R1 of the memory 900 to synchronize the data transfer clock signal WCK and the command transfer clock signal CK. At time T1, the memory command generation circuit 102 issues a read command RD to rank R1 of the memory 900. A period tWCKENL_RD has elapsed since the CAS command issuance time T0, and the WCK generation circuit 105 starts outputting the data transfer clock signal WCK to the memory 900. During a period tWCKPRE_Static, the WCK generation circuit 105 fixes the data transfer clock signal WCK to a low level (or a high level). Thereafter, during a period tWCKPRE_Toggle_RD, the WCK generation circuit 105 starts repeating high and low levels of the data transfer clock signal WCK. Thereafter, during a period tWCKENL_RD, the WCK generation circuit 105 continues repeating high and low levels of the data transfer clock signal WCK.

[0039] When the memory command generation circuit 102 attempts to issue a read command RD to rank R2 of the memory 900 after time T2, it is necessary for the memory command generation circuit 102 to synchronize the data transfer clock signal WCK and the command transfer clock signal CK. It is necessary to prevent a collision between the timing at which the repetition of high and low levels of the data transfer clock signal WCK to rank R1 of the memory 900 ends and the timing at which the data transfer clock signal WCK starts to be output to rank R2 of the memory 900. Therefore, at time T6, the memory command generation circuit 102 issues a CAS command to rank R2 of the memory 900. At time T7, the memory command generation circuit 102 issues a read command RD to rank R2 of the memory 900. During a period tWCKPRE_Static, which is after a period tWCKENL_RD from time T6 when the CAS command is issued, the WCK generation circuit 105 fixes the data transfer clock signal WCK to a low level (or a high level). Thereafter, during a period tWCKPRE_Toggle_RD, the WCK generation circuit 105 starts repeating high and low levels of the data transfer clock signal WCK.

[0040] FIG. 9 shows waveforms in a case where the WCK output mode is a mode in which output is always performed and there is no need to issue a CAS command between issuing two read commands RD to different ranks R1 and R2 of the memory 900.

[0041] At time T0, the memory command generation circuit 102 issues a CAS command to rank R1 of the memory 900 to synchronize the data transfer clock signal WCK and the command transfer clock signal CK. At time T1, the memory command generation circuit 102 issues a read command RD to rank R1 of the memory 900. A period tWCKENL_RD has elapsed since the CAS command issuance time T0, and the WCK generation circuit 105 starts outputting the data transfer clock signal WCK to the memory 900. During a period tWCKPRE_Static, the WCK generation circuit 105 fixes the data transfer clock signal WCK to a low level (or a high level). Thereafter, during a period tWCKPRE_Toggle_RD, the WCK generation circuit 105 starts repeating high and low levels of the data transfer clock signal WCK. Thereafter, the WCK generation circuit 105 continues repeating high and low levels of the data transfer clock signal WCK.

[0042] After time T2, when the memory command generation circuit 102 attempts to issue a read command RD to rank R2 of the memory 900, there is no need to synchronize the data transfer clock signal WCK with the command transfer clock signal CK. Therefore, at time T4, the memory command generation circuit 102 does not issue a CAS command, but issues a read command RD to rank R2 of the memory 900. Thereafter, the WCK generation circuit 105 continues to alternate between high and low levels of the data transfer clock signal WCK.

[0043] 7 and 9, when the WCK output mode is the constant output mode, the memory command generation circuit 102 does not need to issue a CAS command before the second read command RD, which is advantageous in terms of performance. However, when the WCK output mode is the constant output mode, the WCK generation circuit 105 continues to repeat high and low levels of the data transfer clock signal WCK, which is a disadvantage in that power consumption increases.

[0044] In this embodiment, the WCK generation circuit 105 can reduce overhead in terms of performance by switching the WCK output mode to a mode in which the WCK is always output when the effective bandwidth of the memory 900 is equal to or greater than the effective bandwidth. Also, when the effective bandwidth of the memory 900 is less than the effective bandwidth threshold, the WCK generation circuit 105 can reduce overhead in terms of power consumption by switching the WCK output mode to a mode in which the WCK is output only when necessary.

[0045] Although an example of the method by which the memory bandwidth measurement circuit 103 measures the effective bandwidth of the memory 900 has been described in which the number of commands issued is measured, the method is not limited to this and any method may be used as long as it measures the effective bandwidth of the memory 900 or something similar.

[0046] As described above, the memory control circuit 100 accesses the memory 900 in which the command transfer clock signal CK and the data transfer clock signal WCK are independent and require synchronization between the command transfer clock signal CK and the data transfer clock signal WCK.

[0047] The WCK generation circuit 105 is an output unit that switches the WCK output mode of the data transfer clock signal WCK according to the state of memory access, and outputs the data transfer clock signal WCK to the memory 900 according to the WCK output mode.

[0048] Specifically, when the memory access state is busy, the WCK generation circuit 105 sets the WCK output mode to the "always output" mode. In the "always output" mode, the WCK generation circuit 105 always outputs the data transfer clock signal WCK to the memory 900.

[0049] Furthermore, when the memory access state is non-busy, the WCK generation circuit 105 sets the WCK output mode to "output only when necessary" mode. In the "output only when necessary" mode, the WCK generation circuit 105 outputs the data transfer clock signal WCK to the memory 900 only when necessary.

[0050] The memory access state determination circuit 104 determines that the memory access state is busy if the effective bandwidth of the memory 900 for each fixed period is equal to or greater than the effective bandwidth threshold, and determines that the memory access state is non-busy if the effective bandwidth of the memory 900 for each fixed period is less than the effective bandwidth threshold.

[0051] The memory command generation circuit 102 is an issuing unit that can issue a read command, a write command, or a CAS command to the memory 900. The CAS command is a synchronization command for synchronizing the command transfer clock signal CK and the data transfer clock signal WCK.

[0052] The memory bandwidth measurement circuit 103 measures the total number of read commands and write commands issued by the memory command generation circuit 102 per fixed period. The memory access state determination circuit 104 determines that the memory access state is busy if the total number of read commands and write commands issued by the memory command generation circuit 102 per fixed period is equal to or greater than the command number threshold. Furthermore, the memory access state determination circuit 104 determines that the memory access state is non-busy if the total number of read commands and write commands issued by the memory command generation circuit 102 per fixed period is less than the command number threshold.

[0053] 6 and 8 show the case where the WCK output mode is "output only when necessary." In FIGS. 6 and 8, the memory command generation circuit 102 issues a CAS command between the issuance of the previous read command or write command and the issuance of the current read command or write command. The CAS command is a synchronization command for synchronizing the command transfer clock signal CK and the data transfer clock signal WCK.

[0054] 6, at time T1, the memory command generation circuit 102 issues the previous read command or write command to rank R1 of the memory 900. At time T7, the memory command generation circuit 102 issues the current read command or write command to rank R1 of the memory 900. At time T6, the memory command generation circuit 102 issues the above-mentioned CAS command to rank R1 of the memory 900.

[0055] 8, at time T1, the memory command generation circuit 102 issues the previous read command or write command to rank R1 of the memory 900. At time T7, the memory command generation circuit 102 issues the current read command or write command to rank R2 of the memory 900. Rank R2 is a different rank from rank R1. At time T6, the memory command generation circuit 102 issues the above-mentioned CAS command to rank R2 of the memory 900.

[0056] 7 and 9 show a case where the WCK output mode is the "always output" mode. In these figures, the memory command generation circuit 102 does not issue a CAS command between the issuance of the previous read command or write command and the issuance of the current read command or write command.

[0057] As described above, according to this embodiment, when memory access is performed frequently, the memory control circuit 100 can reduce overhead in terms of performance by switching to a mode in which the data transfer clock signal WCK is always output. Also, when memory access is not performed frequently, the memory control circuit 100 can reduce overhead in terms of power consumption by switching to a mode in which the data transfer clock signal WCK is output only when necessary.

[0058] (Second embodiment) FIG. 10 is a diagram illustrating an example of the configuration of a memory control circuit 100 according to the second embodiment. The memory control circuit 100 in FIG. 10 is configured by deleting the memory bandwidth measurement circuit 103 and the memory access state determination circuit 104 from the memory control circuit 100 in FIG. 1 and adding a memory access state determination circuit 204. Differences between the second embodiment and the first embodiment will be described below. The access holding circuit 101, memory command generation circuit 102, and WCK generation circuit 105 in FIG. 10 are the same as those in FIG. 1, and therefore their description will be omitted. The memory access state determination circuit 204 determines whether the memory access state is busy based on the number of access commands held by the access holding circuit 101 and the access command count threshold, and outputs the memory access state to the WCK generation circuit 105. If the number of access commands held by the access holding circuit 101 is equal to or greater than the access command count threshold, the memory access state determination circuit 204 determines that the memory access state is busy. Furthermore, if the number of access commands held by the access holding circuit 101 is less than the access command number threshold, the memory access state determination circuit 204 determines that the memory access state is a non-busy state.

[0059] 11 shows the number of access commands held by the access holding circuit 101, the memory access state determined by the memory access state determination circuit 204, and the WCK output mode set by the WCK generation circuit 105. Here, the explanation will be given assuming that the access command number threshold is 5.

[0060] The access holding circuit 101 holds access commands received from the outside. The number of access commands held by the access holding circuit 101 increases over time. The memory access state determination circuit 204 determines that the memory access state is non-busy when the number of access commands held by the access holding circuit 101 is less than an access command number threshold (for example, 5). When the memory access state is non-busy, the WCK generation circuit 105 sets the WCK output mode to a mode in which the WCK is output only when necessary.

[0061] The memory access state determination circuit 204 determines that the memory access state is busy when the number of access commands held by the access holding circuit 101 is equal to or greater than an access command number threshold (for example, 5). When the memory access state is busy, the WCK generation circuit 105 sets the WCK output mode to a mode in which the WCK is always output.

[0062] The memory command generation circuit 102 generates memory commands based on the access commands held by the access holding circuit 101. As a result, the number of access commands held by the access holding circuit 101 decreases. The number of access commands decreases over time.

[0063] The memory access state determination circuit 204 determines that the memory access state is non-busy when the number of access commands held by the access holding circuit 101 is less than an access command number threshold (for example, 5). When the memory access state is non-busy, the WCK generation circuit 105 sets the WCK output mode to a mode in which the WCK is output only when necessary.

[0064] As in this embodiment, the WCK generation circuit 105 can reduce overhead in terms of performance by switching the WCK output mode to a mode in which the WCK is always output when the number of access commands held by the access holding circuit 101 is equal to or greater than the access command number threshold. Also, when the number of access commands held by the access holding circuit 101 is less than the access command number threshold, the WCK generation circuit 105 can reduce overhead in terms of power consumption by switching the WCK output mode to a mode in which the WCK is output only when necessary.

[0065] As described above, the memory 900 has independent clock signals CK and WCK for transferring commands and data, and the clock signals CK and WCK for transferring commands and data must be synchronized. The memory control circuit 100 can access such a memory 900.

[0066] The access holding circuit 101 is a holding unit that holds an access command received from the outside. The memory command generation circuit 102 issues a read command or a write command to the memory 900 based on the access command held in the access holding circuit 101.

[0067] The memory access state determination circuit 204 determines that the memory access state is busy when the number of access commands held in the access holding circuit 101 is equal to or greater than the access command number threshold, and determines that the memory access state is non-busy when the number of access commands held in the access holding circuit 101 is less than the access command number threshold.

[0068] As described above, according to this embodiment, when memory access is performed frequently, the memory control circuit 100 can reduce overhead in terms of performance by switching to a mode in which the data transfer clock signal WCK is always output. Also, when memory access is not performed frequently, the memory control circuit 100 can reduce overhead in terms of power consumption by switching to a mode in which the data transfer clock signal WCK is output only when necessary.

[0069] (Other embodiments) The present disclosure can also be realized by a process in which a program that realizes one or more functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in the computer of the system or device read and execute the program. The present disclosure can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0070] It should be noted that the above-described embodiments merely illustrate specific examples of implementing the present disclosure, and the technical scope of the present disclosure should not be construed as being limited by these embodiments. In other words, the present disclosure can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0071] 100: Memory control circuit, 101: Access holding circuit, 102: Memory command generation circuit, 103: Memory bandwidth measurement circuit, 104: Memory access state determination circuit, 105: WCK generation circuit, 204: Memory access state determination circuit, 900: Memory

Claims

1. A memory control device for accessing a memory in which a command transfer clock signal and a data transfer clock signal are independent and require synchronization between the command transfer clock signal and the data transfer clock signal, a clock signal for transmitting data to the memory in response to the selected output mode;

2. The output means when the memory access state is a busy state, a first output mode is set, and in the first output mode, the data transfer clock signal is always output to the memory; 2. The memory control device according to claim 1, wherein when the memory access state is a non-busy state, a second output mode is set, and in the second output mode, the data transfer clock signal is output to the memory only when necessary.

3. 3. The memory control device according to claim 1, wherein the memory access state is a busy state when the effective bandwidth of the memory for each fixed period is equal to or greater than a first threshold, and a non-busy state when the effective bandwidth of the memory for each fixed period is less than the first threshold.

4. 4. The memory control device according to claim 1, further comprising an issuing unit for issuing a read command or a write command to said memory.

5. 5. The memory control device according to claim 4, wherein the memory access state is a busy state when the total number of read commands and write commands issued by the issuing means per fixed period is equal to or greater than a second threshold, and a non-busy state when the total number of read commands and write commands issued by the issuing means per fixed period is less than the second threshold.

6. 4. The memory control device according to claim 1, further comprising a holding unit for holding a received access command.

7. 7. The memory control device according to claim 6, further comprising an issuing means for issuing a read command or a write command to said memory based on the access command held in said holding means.

8. 8. The memory control device according to claim 6, wherein the state of the memory access is a busy state when the number of access commands held in the holding means is equal to or greater than a third threshold, and a non-busy state when the number of access commands held in the holding means is less than the third threshold.

9. 8. The memory control device according to claim 4, wherein said issuing means issues a synchronization command to said memory for synchronizing said command transfer clock signal with said data transfer clock signal.

10. The output means when the memory access state is a busy state, a first output mode is set, and in the first output mode, the data transfer clock signal is always output to the memory; when the memory access state is a non-busy state, a second output mode is set, and in the second output mode, the data transfer clock signal is output to the memory only when necessary; The issuing means In the first output mode, a synchronization command for synchronizing the command transfer clock signal and the data transfer clock signal is not issued between the issuance of the previous read command or write command and the issuance of the current read command or write command, 10. The memory control device according to claim 9, wherein in the second output mode, a synchronization command is issued to synchronize the command transfer clock signal and the data transfer clock signal between the issuance of a previous read command or write command and the issuance of a current read command or write command.

11. 11. The memory control device according to claim 10, wherein, in the second output mode, the issuing means issues the previous read command or write command to a first rank of the memory, issues the current read command or write command to the first rank of the memory, and issues the synchronization command to the first rank of the memory.

12. 11. The memory control device according to claim 10, wherein, in the second output mode, the issuing means issues the previous read command or write command to a first rank of the memory, issues the current read command or write command to a second rank of the memory that is different from the first rank, and issues the synchronization command to the second rank of the memory.

13. 1. A control method for a memory control device that accesses a memory in which a command transfer clock signal and a data transfer clock signal are independent and require synchronization between the command transfer clock signal and the data transfer clock signal, comprising: A control method for a memory control device, comprising an output step of switching an output mode of the data transfer clock signal depending on the state of memory access, and outputting the data transfer clock signal to the memory depending on the output mode.

14. A program for causing a computer to function as each of the means of the memory control device according to any one of claims 1 to 12.

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