Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device and a manufacturing method of the semiconductor device, capable of suppressing increase in electric conductivity of a semi-insulating film.SOLUTION: According to one embodiment, a semiconductor device includes a semiconductor layer, a conductive film, a first insulating film, and a second insulating film. The semiconductor layer has an element region where a semiconductor element is provided and a termination region surrounding the element region. The conductive film is provided on the element region and the termination region. The first insulating film is provided on the conductive film on the termination region and on a portion of the element region adjacent to the termination region. The second insulating film is provided on the first insulating film and has a resistivity lower than the resistivity of the first insulating film and higher than the resistivity of the conductive film.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] In the termination structure of power semiconductors, a semi-insulating film (SInSiN film: Semi-Insulating Silicon Nitride film) is sometimes formed on the metal film of electrodes, wiring, etc. to ensure voltage resistance. However, there is a concern that the metal in the metal film and the Si in the semi-insulating film react during the deposition of the semi-insulating film, increasing the conductivity of the semi-insulating film and causing short circuits between the electrodes and wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5921784 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of suppressing an increase in the conductivity of a semi-insulating film and a method for manufacturing the semiconductor device are provided. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a semiconductor layer, a conductive film, a first insulating film, and a second insulating film. The semiconductor layer has an element region in which a semiconductor element is provided and a termination region surrounding the element region. The conductive film is provided on the element region and the termination region. The first insulating film is provided on the conductive film in the termination region and in a portion of the element region adjacent to the termination region. The second insulating film is provided on the first insulating film and has a resistivity lower than that of the first insulating film and higher than that of the conductive film. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2A] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 2B] FIG. 2B is an enlarged cross-sectional view of a portion of FIG. 2A. [Figure 3] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4A to 4C are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment, following FIG. 3. [Figure 5] 5A to 5C are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment, following FIG. 4. [Figure 6] 6A to 6C are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment, following FIG. 5. [Figure 7] 7A to 7C are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment, following FIG. 6. [Figure 8] 8A to 8C are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment, following FIG. 7. [Figure 9] FIG. 10 is a plan view showing a semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 11] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 12] FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] (First embodiment) A first embodiment of the present invention will be described below with reference to the drawings. Fig. 1 is a plan view showing a semiconductor device 1 according to the first embodiment. Fig. 2A is a cross-sectional view showing the semiconductor device 1 according to the first embodiment. Fig. 2A is a cross-sectional view taken along II-II in Fig. 1.

[0008] The following description will be given taking as an example a case where the first conductivity type is N-type and the second conductivity type is P-type. In the following description, the notations N-, N+, N, P-, P+, and P indicate the relative relationship of the impurity concentration of each conductivity type. That is, + indicates that the N-type impurity concentration is relatively higher than N, and N- indicates that the N-type impurity concentration is relatively lower than N. Also, P+ indicates that the P-type impurity concentration is relatively higher than P, and P- indicates that the P-type impurity concentration is relatively lower than P. Note that N+ type and N- type may be simply referred to as N-type, P+ type, and P- type may be simply referred to as P-type.

[0009] The semiconductor device 1 according to the first embodiment can be applied to, for example, an IGBT (Insulated Gate Bipolar Transistor). The semiconductor device 1 may also be applied to an FRD (Fast Recovery Diode) (see FIG. 12). As shown in FIG. 2A, the semiconductor device 1 includes a semiconductor layer 2, an interlayer insulating film 3, a conductive film 4, a first insulating film 5, a SIN SiN film (second insulating film) 6, a SiN film 7 (third insulating film), and a collector electrode 8. The conductive film 4 has an emitter electrode 41, a gate wiring 42, and a field plate 43.

[0010] In the following description, the direction from the collector electrode 8 toward the semiconductor layer 2 is referred to as the Z direction (first direction). The direction perpendicular to the Z direction is referred to as the X direction (second direction), and the direction perpendicular to the X and Z directions is referred to as the Y direction (third direction). The semiconductor device 1 shown in FIG. 1 shows a cross-sectional view in the XY plane. The semiconductor device 1 shown in FIGS. 2A and 2B shows a cross-sectional view in the XZ plane. Note that, although the X direction, Y direction, and Z direction are shown in an orthogonal relationship in this embodiment, they are not limited to being orthogonal, and may be in a mutually intersecting relationship. In the following description, the direction from the collector electrode 8 toward the semiconductor layer 2 is referred to as "up," and the opposite direction is referred to as "down."

[0011] As shown in FIG. 1, the semiconductor layer 2 has an element region R1 in which a semiconductor element (in the first embodiment, a transistor having the semiconductor layer 2, a gate electrode 23, an emitter electrode 41, and a collector electrode 8, which will be described later) is provided, and a termination region R2 surrounding the element region R1. The semiconductor layer 2 contains N-type impurities. As shown in FIG. 2A, an impurity layer (barrier layer) 21 containing N-type impurities at a concentration (N) higher than the concentration (N-) of the N-type impurity in the semiconductor layer 2 is provided on the element region R1 of the semiconductor layer 2. By providing the barrier layer 21 with a higher N-type impurity concentration than the semiconductor layer 2 on the emitter electrode 41 side, when the semiconductor device 1 is in an on-state, the discharge of holes in the semiconductor layer 2 to the emitter electrode 41 is restricted. This increases the carrier concentration on the emitter electrode 41 side of the semiconductor layer 2. This reduces the on-resistance of the semiconductor device 1. Note that this embodiment can be implemented without providing the impurity layer 21. A well layer 22 containing P-type impurities is provided on the impurity layer 21.

[0012] FIG. 2B is a partially enlarged cross-sectional view of FIG. 2A. In FIG. 2B, the semiconductor layer 2 and the impurity regions provided in the semiconductor layer 2 are indicated by their respective conductivity types. As shown in FIG. 2B, an emitter layer 221 containing N-type impurities and a contact layer 222 containing P-type impurities are selectively provided on the well layer 22. In the element region R1, the emitter layer 221 and the contact layer 222 are in ohmic contact with the emitter electrode 41. More specifically, the emitter layer 221 and the contact layer 222 are in ohmic contact with the emitter electrode 41 via a contact 41c of the emitter electrode 41 that penetrates the interlayer insulating film 3. Furthermore, in the element region R1 of the semiconductor layer 2, a gate electrode 23 is provided, extending from the upper surface of the semiconductor layer 2 through the well layer 22 and the impurity layer 21 to the interior of the semiconductor layer 2 (i.e., the drift region). A plurality of gate electrodes 23 are provided at intervals in the X direction. Each gate electrode 23 extends in the Y direction. A gate insulating film 231 is provided on a side surface of the gate electrode 23. That is, in the X direction, the gate electrode 23 is in contact with the well layer 22 via the gate insulating film 231. In the example shown, the gate electrode 23 is also in contact with a part of the emitter layer 221, the impurity layer 21, and a part of the semiconductor layer 2 via the gate insulating film 231. The gate electrode 23 is electrically insulated from the emitter electrode 41 by the gate insulating film 231 and an interlayer insulating film 3, which will be described later. Note that the gate insulating film 231 is not shown in FIG. 2A .

[0013] Furthermore, a guard ring 25 containing P-type impurities is provided on the semiconductor layer 2, surrounding the element region R1 from the outer edge of the element region R1 to the inner edge of the termination region R2. The concentration of P-type impurities (P+) in the guard ring 25 may be higher than the concentration of P-type impurities (P) in the well layer 22. The provision of the guard ring 25 can prevent electric field concentration at the bottom of the outermost gate electrode 23, thereby effectively maintaining the breakdown voltage of the semiconductor device 1.

[0014] Furthermore, a resurf region 26 containing P-type impurities at a concentration (P-) lower than the concentration (P+) of P-type impurities in the guard ring 25 is provided in the termination region R2 on the semiconductor layer 2. The resurf region 26 is provided to surround the element region R1. The resurf region 26 is in contact with the outer edge of the guard ring 25. The provision of the resurf region 26 can reduce the electric field at the outer edge of the guard ring 25, allowing the breakdown voltage of the semiconductor device 1 to be maintained more effectively.

[0015] In addition, a buffer layer 28 containing N-type impurities at a concentration (N) higher than the concentration (N-) of N-type impurities in the semiconductor layer 2 is provided below the semiconductor layer 2. The buffer layer 28 has the function of suppressing the extension of a depletion layer when the semiconductor device 1 is in an off state. A collector layer 29 containing P-type impurities is provided below the buffer layer 28. A collector electrode 8 is provided on the lower surface of the semiconductor layer 2 so as to be in contact with the collector layer 29. The collector electrode 8 is electrically connected to the collector layer 29.

[0016] 2A, the interlayer insulating film 3 is partially provided on the semiconductor layer 2 so as to be in contact with the upper surface of the semiconductor layer 2. In the example shown in FIG. 2A, the interlayer insulating film 3 is partially provided on the semiconductor layer 2 except for a position where a contact 41c of the emitter electrode 41 is provided, a position where a contact 43a of a field plate 43 (described later) is provided, and a position where a portion of the SINSiN film 6 is provided in direct contact with the upper surface of the semiconductor layer 2. The interlayer insulating film 3 may be, for example, a silicon oxide film.

[0017] The conductive film 4 has an emitter electrode 41, a gate wiring 42, and a field plate 43. The conductive film 4 is provided on the interlayer insulating film 3 and on the semiconductor layer 2.

[0018] The emitter electrode 41 is provided on the interlayer insulating film 3 and the semiconductor layer 2 in the element region R1. The emitter electrode 41 has an outer edge portion 41a provided on the termination region R2 side and a central portion 41b provided on the element region R1 side. The outer edge portion 41a of the emitter electrode 41 is provided between the interlayer insulating film 3 and the semiconductor layer 2 and a first insulating film 5, which will be described later. A part of the central portion 41b of the emitter electrode 41 is provided on the SiN film 7, which will be described later, on the termination region R2 side. As shown in FIG. 2A, the outer edge portion 41a of the emitter electrode 41 is thinner in the Z direction than the central portion 41b of the emitter electrode 41. The emitter electrode 41 is, for example, an aluminum electrode.

[0019] The gate wiring 42 is provided on the interlayer insulating film 3 in the termination region R2. The gate wiring 42 is provided outside the emitter electrode 41 at a distance from the emitter electrode 41. The gate wiring 42 is provided along the outer periphery of the element region R1 so as to surround the element region R1. The gate wiring 42 is electrically connected to the gate electrode 23 at the end of the gate electrode 23 in the Y direction. The gate wiring 42 is connected to a gate pad (not shown). The gate wiring 42 is electrically isolated from the emitter electrode 41 by the interlayer insulating film 3. The gate wiring 42 is, for example, an aluminum electrode.

[0020] The field plate 43 is provided outside the gate wiring 42 in the termination region R2 at a distance from the gate wiring 42. The field plate 43 is provided along the outer periphery of the element region R1 so as to surround the element region R1. The field plate 43 is in contact with the guard ring 25 via a contact 43a that penetrates the interlayer insulating film 3. The field plate 43 promotes the extension of the depletion layer on the upper surface of the semiconductor layer 2. The field plate 43 is, for example, an aluminum electrode.

[0021] The first insulating film 5 is provided on the conductive film 4 in the termination region R2 and in a portion of the element region R1 adjacent to the termination region R2. That is, the first insulating film 5 is provided on the termination region R2 and on the outer edge of the element region R1. The first insulating film 5 is, for example, a silicon oxide film. The silicon oxide film may be a tetraethyl orthosilicate film (TEOS film).

[0022] The SINSiN film 6 is provided on the first insulating film 5. The SINSiN film 6 is a semi-insulating silicon nitride film having a resistivity lower than that of the first insulating film 5 and higher than that of the conductive film 4. The resistivity of the SINSiN film 6 may be higher than that of the drift region of the semiconductor layer 2. A sidewall 6a of the SINSiN film 6 on the device region R1 side is connected to (i.e., in contact with) the emitter electrode 41 in the X direction. The SINSiN film 6 is provided on the termination region R2, extending outside the conductive film 4 and the first insulating film 5. That is, the SINSiN film 6 is provided on the first insulating film 5 and on a portion of the semiconductor layer 2 that is more distant from the device region R1 than the first insulating film 5. An end of the SINSiN film 6 on the termination region R2 side is connected, for example, to an EQPR (Equipotential Ring) electrode (not shown). Being connected to the emitter electrode 41, the SINSiN film 6 is maintained at the same potential as the emitter electrode 41. This allows the SINSiN film 6 to alleviate electric field concentration and more effectively maintain the breakdown voltage of the semiconductor device 1. The SINSiN film 6 is in contact with the upper surface of the semiconductor layer 2 on the semiconductor layer 2 outside the first insulating film 5, which is spaced apart from the element region R1. That is, the SINSiN film 6 outside the first insulating film 5 is in direct contact with the upper surface of the semiconductor layer 2. By bringing the SINSiN film 6 into direct contact with the semiconductor layer 2, the breakdown voltage of the semiconductor device 1 can be stably maintained.

[0023] The SiN film 7 is provided on the SINSiN film 6. The first insulating film 5, the SINSiN film 6, and the SiN film 7 have an edge provided between an outer edge portion 41a of the emitter electrode 41 and a part of a central portion 41b of the emitter electrode 41 on the element region side.

[0024] Next, a method for driving the semiconductor device 1 according to the first embodiment will be described. In the element region R1, when a high potential is applied to the collector electrode 8 and a low potential is applied to the emitter electrode 41, and a control voltage equal to or greater than the threshold is applied to the gate electrode 23, an inversion layer (n-channel) is formed in the well layer 22 near the interface with the gate insulating film 231. The formation of the inversion layer causes electrons to be injected from the emitter layer 221 into the semiconductor layer 2 through the inversion layer, turning the transistor on. At this time, holes are also injected from the collector layer 29 into the semiconductor layer 2, reducing the resistance of the semiconductor layer 2. This causes a current to flow from the collector electrode 8 to the emitter electrode 41. On the other hand, when the control voltage becomes lower than the threshold, the inversion layer formed in the well layer 22 near the interface with the gate insulating film 231 disappears. This stops the injection of electrons from the emitter layer 221 into the semiconductor layer 2, and also stops the injection of holes from the collector layer 29 into the semiconductor layer 2. Thereafter, electrons continue to be discharged from the emitter layer 221 to the semiconductor layer 2, and holes continue to be discharged from the collector layer 29 into the semiconductor layer 2, thereby depleting the first semiconductor layer 11. This causes the semiconductor device 1 to enter an off state.

[0025] Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described. In the following description, a method for manufacturing the structure on the upper surface side of the semiconductor layer 2 will be described, and a description of a method for manufacturing the structure on the lower surface side will be omitted.

[0026] FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device 1 according to the first embodiment. Note that in FIG. 3, the semiconductor layer 2 and the impurity regions have already been formed. First, as shown in FIG. 3, the interlayer insulating film 3 is formed on the upper surface of the semiconductor layer 2 (i.e., on the upper surfaces of the impurity layers 22, 25, and 26). The interlayer insulating film 3 is formed by, for example, chemical vapor deposition (CVD). After the interlayer insulating film 3 is formed, it is processed so as to expose a part of the emitter layer 221, a part of the contact layer 222, and a part of the guard ring 25. The interlayer insulating film 3 is processed by, for example, etching using a resist film patterned by photolithography as a mask. After the interlayer insulating film 3 is processed, a first conductive film 401 is formed on the interlayer insulating film 3 and on the exposed semiconductor layer 2 (i.e., on a part of the emitter layer 221, a part of the contact layer 222, and a part of the guard ring 25). The first conductive film 401 is formed by, for example, sputtering.

[0027] FIG. 4 is a cross-sectional view illustrating the manufacturing method of the semiconductor device 1 according to the first embodiment, following FIG. 3 . After the first conductive film 401 is formed, etching is performed using a resist film patterned by, for example, photolithography as a mask. Specifically, the first conductive film 401 located near the boundary between the active region R1 and the termination region R2 is etched to form a portion of the emitter electrode 41 in the active region R1. A portion of the first conductive film 401 in the termination region R2 is also etched to form the gate wiring 42 and the field plate 43, arranged in this order, from the active region R1 toward the termination region R2. Through the above steps, a portion of the emitter electrode 41, the gate wiring 42, and the field plate 43 are formed, as shown in FIG. 4 . Note that the portion of the emitter electrode 41 closest to the termination region R2 becomes the outer edge portion 41a. Furthermore, the outermost portion of the first conductive film 401, i.e., the portion located closer to the termination region than the field plate 43, is also etched to expose the interlayer insulating film 3, forming a region to which the SINSiN film 6, described later, is directly attached.

[0028] Fig. 5 is a cross-sectional view showing the method for manufacturing the semiconductor device 1 according to the first embodiment, following Fig. 4. After processing the first conductive film 401, a first insulating film 5 is formed on the first conductive film 401 and on the interlayer insulating film 3 exposed from the first conductive film 401, as shown in Fig. 5.

[0029] 6 is a cross-sectional view illustrating the method for manufacturing the semiconductor device 1 according to the first embodiment, subsequent to FIG. 5. After forming the first insulating film 5, the interlayer insulating film 3 and the first insulating film 5 are processed so as to expose the upper surface of the semiconductor layer 2 in an area corresponding to the direct-bonding portion of the SINSiN film 6 (described later) (i.e., the upper surface of the semiconductor layer 2 located closer to the termination than the field plate 43), as shown in FIG. 6. Specifically, a resist film 100 is first formed on the first insulating film 5. After forming the resist film 100, a pattern is formed in the resist film 100 using photolithography to expose the first insulating film 5 in an area corresponding to the direct-bonding portion of the SINSiN film 6 (described later). After forming the pattern, the first insulating film 5 and the interlayer insulating film 3 are etched using the patterned resist film 100 as a mask.

[0030] 7 is a cross-sectional view showing the method for manufacturing the semiconductor device 1 according to the first embodiment, following FIG. 6. After processing the interlayer insulating film 3 and the first insulating film 5, the semiconductor layer 2 is cleaned with dilute hydrofluoric acid. After cleaning the semiconductor layer 2, as shown in FIG. 7, a SINSiN film 6 is formed on the first insulating film 5, on the RESURF region 26 exposed from the first insulating film 5, and on the upper surface of the semiconductor layer 2.

[0031] After the SINSiN film 6 is formed, a SiN film 7 is formed on the SINSiN film 6 .

[0032] 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment, subsequent to FIG. 7. After forming the SiN film 7, the first insulating film 5, the SINSiN film 6, and the SiN film 7 are processed so as to expose the first conductive film 401 located inside the outer edge of the element region R1, as shown in FIG. 8. After processing the first insulating film 5, the SINSiN film 6, and the SiN film 7, a second conductive film 402 is formed on the exposed first conductive film 401 in the element region R1, as shown in FIG. 8. This forms the conductive film 4, and the emitter electrode 41. At this time, the sidewall 6a of the SINSiN film 6 on the element region R1 side is connected to the emitter electrode 41.

[0033] Next, advantages of the semiconductor device according to the embodiment will be described. In the first embodiment, the first insulating film 5 is provided between the SINSiN film 6 and the first conductive film 401. The provision of the first insulating film 5 makes it possible to prevent the Si of the SINSiN film 6 from reacting with the metal (e.g., aluminum) of the first conductive film 401 during the formation of the SINSiN film 6, thereby preventing the formation of a highly conductive reaction layer within the SINSiN film 6. Preventing an increase in the conductivity of the SINSiN film 6 makes it possible to prevent short-circuiting of the conductive film 4 (e.g., short-circuiting between the emitter electrode 41 and the gate wiring 42).

[0034] Furthermore, conventionally, the reaction between the metal of the conductive film 4 and the Si of the SINSiN film 6 is promoted as the refractive index of the SINSiN film 6 increases and the deposition temperature of the SINSiN film 6 increases. However, according to the first embodiment, by providing the first insulating film 5 between the conductive film 4 and the SINSiN film 6, it is possible to prevent an increase in the conductivity of the SINSiN film 6 even when the refractive index of the SINSiN film 6 is high and the deposition temperature of the SINSiN film 6 is high. This allows the use of a SINSiN film 6 with a high refractive index (e.g., 3.0 or higher) and also allows the use of a high temperature (e.g., 350°C or higher) for the deposition temperature of the SINSiN film 6 or for the heat treatment temperature after the deposition of the SINSiN film 6. Therefore, according to the first embodiment, the number of options for the refractive index of the SINSiN film 6 and the heat treatment temperature can be increased, thereby improving the design flexibility of the semiconductor device 1.

[0035] Furthermore, according to the first embodiment, the first insulating film 5 is provided so as to cover the emitter electrode 41, the gate wiring 42, the field plate 43, the semiconductor layer 2 between the emitter electrode 41 and the gate wiring 42, and the semiconductor layer 2 between the gate wiring 42 and the field plate 43. This makes it possible to more effectively prevent short-circuiting of the conductive film 4.

[0036] (Second embodiment) Next, a semiconductor device 1 according to a second embodiment in which the upper surface of the SINSiN film 6 is connected to the emitter electrode 41 will be described.

[0037] Fig. 9 is a plan view showing the semiconductor device 1 according to the second embodiment. Fig. 10 is a cross-sectional view taken along line XX in Fig. 9 showing the semiconductor device 1 according to the second embodiment. Fig. 11 is a cross-sectional view showing a method for manufacturing the semiconductor device 1 according to the second embodiment.

[0038] As shown in FIG. 11 , in the second embodiment, the SiN film 7 is provided on the SINSiN film 6 except for a portion of the edge of the SINSiN film 6 on the element region R1 side. The SINSiN film 6 is connected to the emitter electrode 41 at the sidewall 6 a on the element region R1 side and at the upper surface 6 b of a portion of the edge of the SINSiN film 6. As shown in FIG. 9 , the upper surface 6 b of the portion of the edge of the SINSiN film 6 has a groove shape along the outer periphery of the emitter electrode 41 (i.e., the boundary between the element region R1 and the termination region R2). In the example shown in FIG. 10 , the upper surface 6 b of the portion of the edge of the SINSiN film 6 is spaced from the sidewall 6 a of the SINSiN film 6 on the element region R1 side toward the termination region R2. However, without being limited to the example of FIG. 10 , the upper surface 6 b continuous with the sidewall 6 a may be connected to the emitter electrode 41. Such a configuration can be obtained by forming the SiN film 7 so that the sidewall of the SiN film 7 on the element region R1 side is located closer to the termination region R2 side than the sidewall of the SINSiN film 6 on the element region R1 side.

[0039] 11, in order to manufacture the semiconductor device 1 of the second embodiment, before forming the second conductive film 402, the SiN film 7 is processed so as to partially expose the upper surface 6b of the SINSiN film 6. Specifically, first, a resist film 200 is formed on the semiconductor layer 2. After forming the resist film 200, a pattern is formed in the resist film 200 using a photolithography method to expose the SiN film 7 in an area corresponding to the upper surface 6b of the SINSiN film 6 that should be exposed from the SiN film 7 (i.e., part of the edge of the SINSiN film 6). After forming the pattern, the SiN film 7 is etched using the patterned resist film 200 as a mask.

[0040] According to the second embodiment, the connection area between the SINSiN film 6 and the emitter electrode 41 can be increased, and therefore the SINSiN film 6 can be more effectively maintained at the same potential as the emitter electrode 41. Therefore, according to the second embodiment, the breakdown voltage of the semiconductor device 1 can be more effectively maintained.

[0041] (Third embodiment) FIG. 12 shows an example of application of a semiconductor device 1 according to the third embodiment to an FRD. Components similar to those of the first and second embodiments are designated by the same reference numerals as those of the first and second embodiments, and detailed descriptions thereof will be omitted. In the semiconductor device 1 according to the third embodiment, an impurity layer 201 (P layer) containing P-type impurities is provided on an element region R1 in a semiconductor layer 2 (N layer) containing N-type impurities. The impurity layer 201 is in ohmic contact with an anode electrode 44 constituting at least a part of the conductive film 4. A first insulating film 5 is provided on a part of the anode electrode 44 (i.e., between a part of the anode electrode 44 and the SINSiN film 6) in the element region R1 adjacent to the termination region R2. A cathode electrode 80 is disposed at the lower end of the semiconductor layer 2. The cathode electrode 80 is electrically connected to the semiconductor layer 2. That is, in the third embodiment, a transistor including a semiconductor layer 2, an anode electrode 44, and a cathode electrode 80 is provided as a semiconductor element in the element region R1. Other configurations are essentially the same as those of the first and second embodiments. As in the first and second embodiments, a field plate 43 constituting part of the conductive film may be provided on the termination region R2, and a first conductive film 51 may be provided between the field plate 43 and the SINSiN film 6. In the semiconductor device 1 according to the third embodiment, when a forward voltage is applied between the anode electrode 44 and the cathode electrode 80, a forward current flows from the anode electrode 44 to the cathode electrode 80. When a reverse voltage is applied between the anode electrode 44 and the cathode electrode 80, a reverse current flowing from the cathode electrode 80 to the anode electrode 44 is suppressed. The FRD has a thick N layer in the semiconductor layer 2 that shortens the reverse recovery time compared to a typical diode, allowing for rapid suppression of reverse current. The semiconductor device 1 according to the third embodiment can also prevent an increase in the conductivity of the SINSiN film 6 during its formation, even when applied to an FRD.

[0042] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and method described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications may be made to the forms of the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0043] 1: semiconductor device, 2: semiconductor layer, 4: conductive film, 5: insulating film, 6: SINSiN film

Claims

1. a semiconductor layer having an element region in which a semiconductor element is provided and a termination region surrounding the element region; a conductive film provided on the element region and the termination region; a first insulating film provided on the conductive film in the termination region and in a portion of the element region adjacent to the termination region; a first insulating film provided on the first insulating film, the first insulating film having a resistivity lower than that of the first insulating film, and the conductive film a second insulating film having a resistivity higher than that of the first insulating film; a third insulating film provided on the second insulating film excluding at least a portion of the second insulating film on the element region side; Equipped with The second insulating film is connected to the conductive film on a sidewall of the second insulating film on the element region side.

2. 2. The semiconductor device according to claim 1, wherein said second insulating film is further connected to said conductive film on at least a part of an upper surface of said second insulating film.

3. a semiconductor layer having an element region in which a semiconductor element is provided and a termination region surrounding the element region; a conductive film provided on the element region and the termination region; a first insulating film provided on the conductive film in the termination region and in a portion of the element region adjacent to the termination region; a second insulating film provided on the first insulating film and having a resistivity lower than that of the first insulating film and higher than that of the conductive film; a third insulating film provided on the second insulating film excluding at least a part of an edge portion of the second insulating film on the element region side; A semiconductor device comprising:

4. a semiconductor layer having an element region in which a semiconductor element is provided and a termination region surrounding the element region; a conductive film provided on the element region and the termination region; a first insulating film provided on the conductive film in the termination region and in a portion of the element region adjacent to the termination region; a second insulating film provided on the first insulating film and having a resistivity lower than that of the first insulating film and higher than that of the conductive film; the second insulating film is provided on the first insulating film and on the semiconductor layer at a position farther away from the element region than the first insulating film; the second insulating film is in contact with the semiconductor layer on a portion of the semiconductor layer spaced apart from the element region.

5. The semiconductor device according to claim 1 , wherein the conductive film has a first electrode provided on the element region.

6. 6. The semiconductor device according to claim 5, wherein the conductive film further comprises a wiring portion provided on the termination region and spaced apart from the first electrode, the wiring portion being connected to a second electrode provided in the element region.

7. 7. The semiconductor device according to claim 6, wherein the first insulating film is provided on the first electrode, the wiring portion, and the semiconductor layer between the first electrode and the wiring portion.

8. forming a first conductive film on an element region and a termination region of a semiconductor layer; processing the first conductive film to form at least a portion of an electrode; forming a first insulating film on the processed first conductive film; forming a second insulating film on the first insulating film, the second insulating film having a resistivity lower than that of the first insulating film and higher than that of the first conductive film; forming a third insulating film on the second insulating film; removing a portion of the first insulating film, a portion of the second insulating film, and a portion of the third insulating film to expose a sidewall of the second insulating film on the element region and to expose a portion of the first conductive film on the element region; a third insulating film formed on the second insulating film adjacent to the element region, the third insulating film being formed on the second insulating film so as to expose an upper surface of the second insulating film in at least a portion of the second insulating film adjacent to the element region;

9. forming a first conductive film on an element region and a termination region of a semiconductor layer; processing the first conductive film to form at least a portion of an electrode; forming a first insulating film on the processed first conductive film; forming a second insulating film on the first insulating film, the second insulating film having a resistivity lower than that of the first insulating film and higher than that of the first conductive film; removing a portion of the first insulating film and a portion of the second insulating film to expose a portion of the first conductive film on the element region; forming a third insulating film on the second insulating film; processing the third insulating film so as to expose an upper surface of the second insulating film in at least a portion of the second insulating film on the element region side; forming a second conductive film so as to be in contact with a sidewall of the second insulating film on the element region side and an upper surface of the second insulating film exposed from the third insulating film, and to be in contact with the first conductive film above the element region.

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