Semiconductor device and inkjet recording element substrate

Abstract

To provide a semiconductor device capable of preventing an error writing to a specific variable element due to a power supply noise, and an inkjet recording element substrate.SOLUTION: A semiconductor device comprises a memory part 103 in which a writing voltage is output from an output terminal of a voltage generation circuit 101, a voltage of a predetermined voltage or larger is applied to an anti-fuse element (characteristic variable element) Ca is applied when a writing control switch is in an MND 1 conductive state, and an electric characteristic of the anti-fuse element is changed. The semiconductor device comprises: a wiring used for applying a voltage that is a predetermined voltage or larger to the anti-fuse element; a noise detection circuit 102 that detects a noise of the power supply and outputs a detection signal Vgn1; and a noise discharge switch MND2 that enables a discharge of a noise current from a wiring A when the noise detection circuit detects the noise of the power supply.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and an inkjet recording element substrate. [Background technology]

[0002] In recent years, semiconductor devices have been using OTP (One Time Programmable) memories to record product-specific information such as chip IDs and setting parameters after the product is completed. There are two types of OTP memories: those that use fuse elements and those that use anti-fuse elements. Patent Document 1 discloses a substrate that includes an anti-fuse element and a voltage application circuit for applying a voltage to the anti-fuse element. In this substrate, writing to the anti-fuse element can be performed by applying a voltage of a predetermined value or higher to the anti-fuse element using the voltage application circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-138607 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the substrate disclosed in Patent Document 1, there is a possibility that erroneous writing to the anti-fuse element may occur due to power supply noise. For example, a surge voltage caused by electrostatic discharge or lightning may pass through the voltage generating circuit and reach the anti-fuse element, causing erroneous writing to the anti-fuse element. This also applies to characteristic variable elements other than anti-fuse elements.

[0005] The present disclosure has been made in view of the above points, and aims to prevent erroneous writing to a characteristic variable element due to power supply noise. [Means for solving the problem]

[0006] One aspect of the present disclosure is a semiconductor device comprising: a characteristic variable element whose electrical characteristics change when a voltage equal to or greater than a predetermined voltage is applied thereto; a write control switch that switches between a conductive state and a non-conductive state based on a first write control signal for controlling writing to the characteristic variable element; and a voltage generation circuit that outputs a write voltage from an output terminal based on a power supply and a second write control signal for controlling writing to the characteristic variable element, wherein when the write voltage is output from the output terminal of the voltage generation circuit and the write control switch is in a conductive state, a voltage equal to or greater than the predetermined voltage is applied to the characteristic variable element, thereby changing the electrical characteristics of the characteristic variable element; the semiconductor device also comprises: wiring used to apply the voltage equal to or greater than the predetermined voltage to the characteristic variable element; a noise detection circuit that detects noise in the power supply; and a noise discharge switch that enables noise current to be discharged from the wiring when the noise detection circuit detects noise in the power supply. a read circuit for reading out the electrical characteristics of the characteristic variable element; Further equipped with The voltage generating circuit and the readout circuit are electrically connected exclusively to the wiring. It is a semiconductor device. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to prevent erroneous writing to a characteristic variable element due to power supply noise. [Brief explanation of the drawings]

[0008] [Figure 1] Circuit Configuration Example 1 of the Semiconductor Device of the First Embodiment [Figure 2] Circuit Configuration Example 2 of the Semiconductor Device of the First Embodiment [Figure 3] Circuit Configuration Example 3 of the Semiconductor Device of the First Embodiment [Figure 4] Circuit configuration example of comparative example [Figure 5] Graph showing an example of operational waveforms of the circuit of the first embodiment. [Figure 6] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment; [Figure 7]Graph showing an example of an operation waveform of the circuit of the second embodiment. [Figure 8] Circuit configuration example of inkjet recording element substrate according to the second embodiment [Figure 9] Layout example of inkjet recording element substrate according to the second embodiment [Figure 10] Circuit configuration example of semiconductor device according to third embodiment DETAILED DESCRIPTION OF THE INVENTION

[0009] First Embodiment FIG. 1 shows an example of the circuit configuration of a semiconductor device, showing the state before information is written into an anti-fuse element (also called a "characteristic variable element") Ca.

[0010] The semiconductor device of this embodiment includes a memory unit 103 having transistors MP1, MN1, and MND1, and an antifuse element Ca. The antifuse element Ca has a first resistance value before information is written thereto and a second resistance value smaller than the first resistance value after the information is written thereto. The resistance value of the antifuse element Ca changes depending on the information writing operation. A larger first resistance value is preferable. Ideally, the first resistance value may be infinite. Furthermore, a larger difference between the first resistance value and the second resistance value is preferable. For example, the antifuse element Ca functions as a capacitive element before information is written thereto and functions as a resistive element after information is written thereto. FIG. 1 illustrates the state before information is written to the antifuse element Ca, and therefore the antifuse element Ca is represented by a circuit symbol for a capacitive element. With this configuration, information written to the antifuse element Ca can be retained based on changes in the resistance value of the antifuse element Ca.

[0011] In FIG. 1, the transistor MP1 is a P-type transistor, the transistor MN1 is an N-type transistor, and a first write control signal Sig1 is input to the gates of the transistors MP1 and MN1.

[0012] A power supply voltage VDD (e.g., 3.3 V) is supplied to the source and back gate of transistor MP1, and the drain is connected to the drain of transistor MN1 and the gate of transistor MND1. The source and back gate of transistor MN1 are connected to ground GND. Transistors MP1 and MN1 form a logic circuit (a logic inversion circuit in FIG. 1) that outputs a signal Vg, which is the logical inversion of the first write control signal Sig1, to the gate of transistor MND1.

[0013] The transistor MND1 is an N-type high-voltage transistor that controls the application of voltage to the anti-fuse element Ca. For example, the transistor MND1 can be an NMOS transistor. Here, a high-voltage transistor is a transistor with a higher withstand voltage than transistors used in logic circuits (such as the transistor MP1 and the transistor MN1). The high-voltage transistor is preferably formed so as not to break down even when a high voltage (e.g., 32 V) that cannot be withstood by transistors in general logic circuits such as control units is applied. Furthermore, by using transistors MP1 and MN1 that constitute the logic circuit as transistors with a lower withstand voltage than the transistor MND1, the logic circuit can be operated at high speed.

[0014] The antifuse element Ca is connected to the second terminal BB via the transistor MND1. For example, an antifuse element having a MOS (Metal Oxide Semiconductor) structure can be used as the antifuse element Ca. The upper electrode of the antifuse element Ca is connected to the first terminal AA, and the lower electrode is connected to the drain of the transistor MND1. The source of the transistor MND1 is connected to the second terminal BB. Therefore, the antifuse element Ca and the transistor MND1 are connected in series between the first terminal AA and the second terminal BB.

[0015] The first terminal AA and the second terminal BB are connection parts for electrically connecting the memory unit 103 to an external circuit, and are terminals for applying a voltage to the anti-fuse element Ca or measuring the voltage generated in the anti-fuse element Ca. For example, the potential of the first terminal AA can be set to a high voltage (e.g., 32 V) when writing information. The second terminal BB is connected to ground GND.

[0016] Based on the second write control signal Sig2, the voltage generation circuit 101 switches whether or not to output a high voltage (e.g., 32 V) applied to the VH terminal, which is an external connection terminal, to the wiring A. Here, as shown in FIG. 1, the wiring A is a wiring for interconnecting the output terminal of the voltage generation circuit 101 and the first terminal AA. The voltage generation circuit 101 can be configured to include a P-type high-voltage transistor MPD1, as shown in FIG. 2, for example. Alternatively, as shown in FIG. 3, the high-voltage transistor MPD1 may be configured to perform a switching operation based on a second write control signal Sig4 output from a separately provided write / read control circuit 307. The write / read control circuit 307 may include a boost circuit that boosts the voltage of the second write control signal Sig4, which has the logic circuit power supply voltage VDD, to a voltage corresponding to the operating voltage of the high-voltage transistor MPD1. Furthermore, if the anti-fuse element write voltage is lower than the high voltage applied to the VH terminal, the voltage generating circuit 101 may include a step-down circuit that steps down the voltage of the VH terminal (for example, 32 V) to the write voltage (for example, 24 V).

[0017] When writing information to the anti-fuse element Ca, the potential difference between the source and drain of the conductive transistor MND1 is nearly zero, so a voltage nearly equal to the potential difference between terminals AA and BB is applied to the anti-fuse element Ca. Here, the potential of terminal BB is the circuit GND potential, and during writing, a write voltage based on the circuit GND potential is applied to terminal AA. Therefore, during writing, the value of the potential difference between terminals AA and BB is nearly equal to the write voltage. Therefore, the write voltage can be set to a voltage equal to or greater than the predetermined voltage required to write information to the anti-fuse element Ca.

[0018] The above-mentioned 32V given as an example of the write voltage is more than three times the 10V voltage, which is the predetermined voltage required to write information to the antifuse element Ca according to the embodiment. This is to shorten the time required for writing from one to several seconds to several milliseconds. Furthermore, the above-mentioned 24V given as another example of the write voltage is more than twice the 10V voltage, which is the predetermined voltage required to write information to the antifuse element Ca according to the embodiment. This is also to shorten the time required for writing from one to several seconds to several milliseconds, but the shortened time is shorter than in the case of 32V.

[0019] When reading whether the anti-fuse element Ca is in a write state, the voltage of the VID terminal electrically connected to the first terminal AA may be detected from outside the semiconductor device, as shown in FIG. 2. Alternatively, the write state may be detected by the read circuit 204, as shown in FIG. 2. When the read circuit 204 is mounted on the same semiconductor device as the memory unit 103, a high-voltage transistor MND3 is preferably connected between the read circuit 204 and the wiring C, and the read circuit 204 and the wiring C are preferably electrically isolated except during read operations. The read control signal Sig3 of the transistor MND3 may be replaced with a read control signal Sig5 as shown in FIG. 3. Here, the read control signal Sig5 is output from the write / read control circuit 307 in combination with the second write control signal Sig4 of the voltage generation circuit 101, as shown in FIG. 3. If the high-voltage transistor MPD1 and the transistor MND3 are turned on simultaneously, the voltages output from the voltage generation circuit 101 and the read circuit 204 may interfere with each other on the wiring C, potentially causing a malfunction. Furthermore, if the read circuit 204 is configured with low-voltage transistors used in logic circuits, the high voltage applied to the VH terminal may be applied to the low-voltage transistors, potentially destroying the read circuit 204. To avoid this, the write / read control circuit 307 uses the second write control signal Sig4 and the read control signal Sig5 to control the high-voltage transistor MPD1 and the transistor MND3 to be exclusively turned on. When the high-voltage transistor MPD1 and the transistor MND3 are not turned on, their outputs have high impedance and are not electrically connected to the wiring C.

[0020] 3, a plurality of memory units 303 are provided, each of which includes a characteristic variable element Ca, a parallel resistance element Rp, a write control switch MND1, and logic inverters MP1 and MN1, for one set of a voltage generation circuit 101, a noise detection circuit 302, and a noise discharge switch MND4. The parallel resistance element Rp will be described later. The write control signal generation unit 308 generates first write control signals Sig10 to SigN based on the input signal Sigcont10. The first write control signals Sig10 to SigN are used as first write control signals in each memory unit 303.

[0021] Next, the operation of writing information to the antifuse element Ca will be described with reference to FIG. 2. When writing information to the antifuse element Ca, the high-voltage transistor MPD1 of the voltage generating circuit 101 is turned on. This causes the high voltage (e.g., 32 V) applied to the VH terminal to be applied to the wiring C connected to the antifuse element Ca via the first terminal AA. At this time, the transistor MND3 is turned off (high impedance state), and the read circuit 204 and the wiring C are electrically isolated. Next, the first write control signal Sig1 corresponding to the antifuse element Ca to be written is set to a low level (e.g., GND potential), switching the transistor MND1 from the off state (i.e., non-conductive state) to the on state (i.e., conductive state). This applies the high voltage applied to the VH terminal to the gate insulating film between the upper and lower electrodes of the antifuse element Ca. As a result, the gate insulating film of the antifuse element Ca undergoes dielectric breakdown, significantly reducing the resistance value of the antifuse element Ca. Therefore, while the anti-fuse element Ca was a capacitive element before writing, the anti-fuse element Ca becomes a resistive element after writing. In this way, the transistor MND1 is switched between a conductive state and a non-conductive state by the first write control signal Sig1. Then, when the transistor MND1 is turned on by the first write control signal Sig1 during the period in which a write voltage is applied to the terminal AA, information is written to the anti-fuse element Ca. Therefore, the transistor MND1 functions as a write control switch.

[0022] Next, referring to FIG. 2, an information read operation will be described when the read circuit 204 is mounted on the same semiconductor device as the antifuse element Ca. Before reading information, the high-voltage transistor MPD1 must be turned off (high impedance state) to electrically isolate the voltage at the VH terminal from the wiring C connected to the antifuse element Ca. Furthermore, the transistor MND3 is turned on, electrically connecting the read circuit 204 to the wiring C. In this state, the first write control signal Sig1 corresponding to the antifuse element Ca from which information is to be read is set to a low level signal, thereby turning on the transistor MND1. This causes a read current Iread to be supplied to the antifuse element Ca from the current source 205 in the read circuit 204. As a result, if the resistance of the antifuse element Ca is Ra, a read voltage Vread (Iread×Ra) is input to the non-inverting input terminal of the voltage comparator 206 in the read circuit 204 via the wiring C. In the voltage comparator 206, the read voltage Vread is compared with the reference voltage Vref input to the inverting input terminal. If the read voltage Vread is greater than the reference voltage Vref, an output signal having a logic "High" is output from the output terminal OUT. On the other hand, if the read voltage Vread is less than the reference voltage Vref, an output signal having a logic "Low" is output. Because the antifuse element Ca is generally made of an insulating film, it has a high resistance value in the unwritten state. When the insulating film is destroyed by writing, it becomes conductive and its resistance value decreases. In the circuit shown in FIG. 2, an output signal having a logic "High" is output if the element is unwritten, and an output signal having a logic "Low" is output if the element has been written. Note that an output signal with an inverted logic may be output by adding a logic inverter or by swapping the non-inverting and inverting input terminals. Furthermore, the configuration of the read circuit 204 may use a method other than the resistance detection method using a current source as described in this embodiment.

[0023] During the manufacturing process, an extremely large surge voltage may enter the semiconductor device through the VH terminal due to electrostatic discharge (ESD) or a lightning surge that penetrates the building's AC power supply. The same phenomenon may also occur depending on the user's operating environment. In particular, during information readout, the high-voltage transistor MPD1 shown in FIG. 2 is in an off state. However, if a surge voltage is applied to the VH terminal, the surge voltage may enter the wiring C via the parasitic capacitance Cp formed between the source and drain of the P-type high-voltage transistor MPD1 in the semiconductor substrate. Since the transistor MND3 is in an on state at this time, a high surge voltage is applied to the readout circuit 204, which may destroy the readout circuit 204.

[0024] Furthermore, during information read, the transistor MND1 is in an on state, which connects the lower electrode of the anti-fuse element Ca to ground GND. Therefore, even a relatively small surge voltage of about 10 V, which is the insulating film breakdown voltage of the anti-fuse element Ca, may cause information to be written to the anti-fuse element Ca when that surge voltage is applied to the upper electrode. As a result, writing may occur to an anti-fuse element Ca that was not intended to be written to, potentially changing the information recorded in the semiconductor device.

[0025] The destruction of the read circuit 204 or the erroneous writing can occur during electrical measurements in the product shipping inspection process, for example, during confirmation of the soundness of the anti-fuse element Ca or during confirmation of the operation of the read circuit.

[0026] FIG. 4 shows a circuit diagram for a comparative example. While a voltage generation circuit 401 is generally composed of transistors, FIG. 4 specifically illustrates an example in which the voltage generation circuit 401 is composed of a MOS transistor MP202. The MOS transistor MP202 is off except during write operations, electrically isolating the anti-fuse element Ca from the VH terminal, which is the power supply pad. In this state, a separate read circuit 404 performs other operations, such as reading and determining the status. The MOS transistor MP202 can normally maintain its off state in an environment where the power and ground voltages are stable. However, if high-frequency noise or a surge voltage from the outside, such as an electrostatic discharge or a lightning surge, penetrates the VH terminal, it may pass through the MOS transistor MP202 due to parasitic capacitance Cp201 formed in the MOS transistor MP202 and reach the wiring Z. In particular, if the surge voltage penetrates the wiring Z during a read operation, the read circuit 404 may be destroyed or erroneous writing may occur to the anti-fuse element Ca.

[0027] Therefore, in this embodiment, as shown in FIG. 1 , a noise detection circuit 102 is connected near the VH terminal, through which noise voltages such as surge voltages enter. Then, to protect the anti-fuse element Ca from noise voltages, a transistor MND2 (hereinafter also referred to as the noise discharge switch MND2) functioning as a noise discharge switch is connected to the wiring A to provide noise countermeasures. Specifically, noise countermeasures are implemented by connecting a first connection terminal of the noise discharge switch MND2 to an intermediate node CC on the wiring A between the output terminal of the voltage generation circuit 101 and the terminal AA, and connecting a second connection terminal to ground GND. In this configuration, the noise detection circuit 102 detects noise voltages entering from the VH terminal and outputs a detection signal Vgn1. The noise discharge switch MND2 is turned on in response to the detection signal Vgn1. This enables the noise discharge switch MND2 to discharge noise currents in response to the detection signal Vgn1. This allows the noise discharge switch MND2 to discharge noise currents entering the wiring A to ground GND. This prevents the voltage rise on the wiring A from occurring before the surge voltage reaches the anti-fuse element Ca.

[0028] The GND potential is the GND potential of the substrate on which the circuit shown in FIGS. 1 to 3 is mounted. As will be described later, when such a circuit is mounted on an inkjet recording element substrate, the GND potential is the GND potential of the inkjet recording element substrate. The GND wiring of the substrate is usually electrically connected to the housing of the device on which the substrate is mounted (an image forming apparatus or multifunction peripheral for the inkjet recording element substrate described later), either directly or via another substrate. The housing is also grounded to the earth via a ground wire. Therefore, when the noise discharge switch MND2 is in a conductive state, the current flowing from terminal CC to the GND of the substrate is discharged to the earth via the housing of the device. The potential of the housing relative to the earth potential is not necessarily zero volts. Furthermore, the GND potential of the substrate relative to the earth potential and the GND potential of the substrate relative to the housing potential are not necessarily zero volts. The write voltage is based on the GND potential of the substrate. The circuits shown in FIGS. 1 to 3 may be provided in a single semiconductor device or across multiple semiconductor devices. In either case, all semiconductor devices are grounded to the substrate. However, taking into consideration noise generated in the housing, it is not necessary to connect the GND of the board to the housing. In such a case, for example, the GND of the board may be given a large capacitance so that the noise current is absorbed by this.

[0029] Based on the circuit diagram of FIG. 2, a more detailed voltage waveform will be explained using the example of FIG. 5. The noise voltage applied to the VH terminal is shown in the VH waveform. A high voltage (e.g., 32 V) is applied to the VH terminal, to which a voltage is supplied as a write voltage, in a steady state. When reading information, the high-voltage transistor MPD1 of the voltage generation circuit 101 is in an off state, so the voltage value of the line C becomes equal to the power supply voltage VDD or the read voltage value of the anti-fuse element Ca.

[0030] If a noise voltage of several tens of megahertz and 60 V peak is applied to the VH terminal, the high-frequency components will be transmitted to the wiring C via the parasitic capacitance Cp. In particular, without the noise suppression circuit of this embodiment, the voltage on the wiring C could reach 15 V, as shown by the dashed VC waveform in Figure 5. If the insulation film breakdown voltage of the anti-fuse element Ca is 10 V, the anti-fuse element Ca will be written.

[0031] On the other hand, when the noise suppression circuit of this embodiment is present, the noise detection capacitor Cn1 in the noise detection circuit 102 blocks the power supply voltage VDD but transmits the high-frequency components of the noise voltage. As a result, the noise detection signal Vgn2 supplied to the gate of the transistor MND2, which functions as a noise discharge switch, rises as shown by the Vgn2 waveform in FIG. 5. In other words, the gate voltage of the transistor MND2 rises. Here, during the MND2-on period when the noise detection signal Vgn2 exceeds the on-threshold voltage (Vth) of the noise discharge switch MND2, the noise discharge switch MND2 is turned on. This allows the surge current flowing into the wiring C to be discharged to ground GND via the noise discharge switch MND2.

[0032] Therefore, by suppressing the voltage rise on wiring C, as shown by the solid VC waveform in Figure 5, the voltage on wiring C can be kept below 10V, the insulation film breakdown voltage of the anti-fuse element Ca. This prevents erroneous writing to the anti-fuse element Ca due to noise voltages entering through the VH terminal. The noise detection capacitor Cn1 and the noise discharge switch MND2 must be configured with high-voltage capacitors and high-voltage transistors to prevent element breakdown even when high voltages (e.g., 32V) or noise voltages are applied during normal operation. The noise detection circuit 102 also includes a pull-down resistor Rn1 to prevent the noise discharge switch MND2 from turning on when noise is not entering, i.e., in a steady state where the voltage on the VH terminal is stable. Although not shown, it is preferable to connect a protective diode, commonly used as a protective element, between the VH terminal and GND to prevent element breakdown due to noise voltages. The noise detection circuit 102, comprised of the noise detection capacitor Cn1 and pull-down resistor Rn1, can also be considered a high-pass filter that blocks the DC power supply voltage supplied from the VH terminal and allows noise to pass through.

[0033] Here, it is preferable to connect a resistor Rp in parallel to the anti-fuse element Ca, as shown in Fig. 3. Without the resistor Rp, when a write voltage is applied to the wiring D, even though the write control switch MND1 is in the off state, a high voltage may be applied across the anti-fuse element Ca, and writing may occur to the anti-fuse element Ca. This can be prevented by connecting the resistor Rp in parallel to the anti-fuse element Ca.

[0034] Next, a specific example of the cross-sectional structure of the anti-fuse element Ca, resistor Rp, and transistor MND1 shown in FIG. 3 is shown in FIG. 6. In a semiconductor substrate 610, a P-well region 601 and N-well regions 602a, 602b, and 602c are formed on a P-type silicon substrate 600. The P-well region 601 can be formed in the same process as the P-well of an NMOS transistor that constitutes a logic circuit. Furthermore, the N-well regions 602a, 602b, and 602c can be formed in the same process as the N-well of a PMOS transistor that constitutes a logic circuit.

[0035] The impurity concentration of the N-well region relative to the P-type silicon substrate 600 is set so that the breakdown voltage between the N-well regions 602a, 602b, and 602c and the P-type silicon substrate 600 becomes higher than the voltage of the VID terminal when a high voltage is applied. Also, the impurity concentrations of the P-well region 601 and the N-well regions 602a, 602b, and 602c are set so that the breakdown voltage between the P-well region 601 and the N-well regions 602a and 602b becomes higher than the voltage of the VID terminal when a high voltage is applied.

[0036] A field oxide film 603, heavily doped N-type diffusion regions 606a to 606e, and a heavily doped P-type diffusion region 607 are formed in a P-well region 601 and N-well regions 602a, 602b, and 602c. The field oxide film 603 can be formed by, for example, the LOCOS (Local Oxidation of Silicon) method.

[0037] The structure of transistor MND1, which is a high-voltage NMOS transistor, will be described. A gate electrode 605a is disposed on adjacent P-well region 601 and N-well region 602a via a gate insulating film 604. The region where the P-well region 601 and gate electrode 605a overlap becomes a channel formation region.

[0038] The heavily doped N-type diffusion region 606a is the source of the transistor MND1, and the heavily doped P-type diffusion region 607 is the back gate electrode. The N-well region 602a has a portion that extends to the bottom of the gate electrode 605a as a drain electric field relaxation region. The heavily doped N-type diffusion region 606b formed in the N-well region 602a becomes the drain electrode of the transistor MND1.

[0039] Furthermore, the drain side of the gate electrode 605a has a so-called LOCOS offset structure, which is a structure in which the gate electrode 605a rides on the field oxide film 603 formed in the N-well region 602. This ensures a gate-drain breakdown voltage even when the transistor MND1 is in the off state, that is, when the gate electrode voltage is at the GND potential and the drain electrode voltage rises to the voltage of the VID terminal when it becomes a high voltage.

[0040] Next, the structure of the antifuse element Ca will be described. The antifuse element Ca has an upper electrode, a lower electrode, and an insulating layer therebetween. For example, an electrode 605b provided on an N-well region 602b via a gate insulating film 604 functions as the upper electrode of the antifuse element Ca. In addition, in the N-well region 602b, a portion that is connected to a high-concentration N-type diffusion region 606c and overlaps with the upper electrode in a planar view relative to the surface of the semiconductor substrate 610 on which elements such as the transistor MND1 are arranged functions as a lower electrode. Note that the planar view relative to the surface on which elements such as the transistor MND1, the antifuse element Ca, and the resistor Rp are arranged refers to, for example, a planar view relative to the surface of the channel formation region of the transistor MND1.

[0041] 6, the heavily doped N-type diffusion region 606c is formed only in the region of the N-well region 602b that does not overlap with the upper electrode in a plan view, but the heavily doped N-type diffusion region 606c is not limited to this. For example, the heavily doped N-type diffusion region 606c may be formed in a part of the region that overlaps with the upper electrode or in the entire overlapping region. If the heavily doped N-type diffusion region 606c is also formed in the region that overlaps with the upper electrode in a plan view, the overlapping portion of the heavily doped N-type diffusion region 606c also functions as the lower electrode of the anti-fuse element Ca.

[0042] Furthermore, in Figure 6, the lower electrode of the anti-fuse element Ca is connected to the drain of the transistor MND1, but the upper electrode may be connected to the drain of the third transistor MND1, and the lower electrode may be connected to a high voltage (the first terminal AA shown in Figure 1).

[0043] The gate insulating film 604 can be formed in the same process as the gate insulating films of the transistors MP1 and MN1 that constitute the logic circuit, and can be formed of, for example, an oxide film. The electrodes 605a and 605b can be formed of, for example, a polysilicon layer. The polysilicon layer, heavily doped N-type diffusion regions 606a-606c, and heavily doped P-type diffusion region 607 can be formed in the same process as the formation of the respective elements of the transistors MP1 and MN1 that constitute the low-voltage logic circuit.

[0044] In this way, the anti-fuse element Ca is a capacitance element having a MOS structure, and the transistor that controls writing to the anti-fuse element Ca is a MOS transistor. Therefore, the anti-fuse element Ca and the transistor can be formed in the same process, making it possible to form a semiconductor device inexpensively with a small number of processes.

[0045] An insulating film having a plurality of contact portions 608 is provided on the high-concentration P-type diffusion region 607, the N-type diffusion regions 606a-606e, and the field oxide film 603, and conductive layers 609a-609e are provided on the insulating film. The conductive layers 609a-609e can be made of a metal such as aluminum. The manufacturing method, materials, and structure of the conductive layers 609a-609e are not limited as long as they are electrically connected to the electrodes and wiring.

[0046] 6 shows an example of a capacitance element in which the lower electrode and the upper electrode are formed of an N-well region and polysilicon as the anti-fuse element Ca, but the anti-fuse element Ca is not limited to this structure and may be a capacitance element using, for example, a PMOS transistor. One of the lower electrode and the upper electrode of the anti-fuse element Ca functions as one terminal, and the other functions as the other terminal.

[0047] The resistor element Rp is a diffused resistor, and has an N-well region 602c, which is a semiconductor region in a semiconductor substrate 610, and is connected to conductive layers 609d and 609e via heavily doped N-type diffusion regions 606d and 606e, respectively. The resistor element Rp is not limited to this structure. For example, a resistor made of a conductive layer or a resistor made of polysilicon may be used as the resistor element Rp.

[0048] The insulating film is an insulator layer formed on the semiconductor substrate 610 so as to cover the transistor MND1, the resistor element Rp, etc., and is made of, for example, silicon oxide. The insulator layer is not limited to this, and may be made of silicon nitride or silicon carbide, or may be a laminate or mixture layer of these.

[0049] The conductive layer 609a is connected to the source and back gate of the transistor MND1 via a contact portion 608, and is supplied with a ground potential. The conductive layer 609b is connected to the drain electrode of the transistor MND1 and the lower electrode of the anti-fuse element Ca via the contact portion 608. The conductive layer 609c is connected to the upper electrode of the anti-fuse element Ca via the contact portion 608, and is connected to the first terminal AA shown in FIG. 1 at a portion not shown. A high voltage (e.g., 32 V) is applied to the conductive layer 609c via the first terminal AA during writing. The conductive layer 609d is connected to the conductive layer 609c (not shown), and the conductive layer 609e is connected to the conductive layer 609b (not shown).

[0050] Second Embodiment In this embodiment, a noise detection circuit 302 is shown in Figure 3, which efficiently discharges noise current to ground GND by driving a noise discharge switch more stably. The noise detection circuit 302 receives a signal from a noise detection capacitor Cn2 via a transistor MN2. In this embodiment, the logic power supply voltage VDD is divided by a pull-up resistor Rn3 and a transistor MN2, and the resulting signal Vgn4 is inverted by a logic inverter INV1 to generate a signal Vgn5, which drives the noise discharge switch MND4. Detailed voltage waveforms are shown in Figure 7. The VH waveform is a waveform in which a noise voltage is superimposed on a high voltage (32 V). When noise occurs, a voltage with this waveform is supplied to the VH terminal. During information read, the high-voltage transistor MPD1 of the voltage generation circuit 101 is off, so the voltage value of the line D is equal to the power supply voltage VDD or the read voltage value of the anti-fuse element Ca. If a noise voltage of several tens of MHz and a peak of 60 V is applied to the VH terminal in addition to a high voltage, the high-frequency components of the noise voltage are transmitted to the line D via the parasitic capacitance Cp. Without the noise countermeasure circuit of this embodiment (the noise detection circuit 302 and the noise discharge switch MND4), the voltage on the line D could reach 15V, as shown by the dashed VD waveform in FIG. 7. On the other hand, with the noise countermeasure circuit of this embodiment, the noise detection capacitor Cn2 in the noise detection circuit 302 blocks the power supply voltage VDD but transmits the high-frequency components of the noise voltage. As a result, the noise detection signal Vgn3 supplied to the gate of the transistor MN2 rises, as shown by the Vgn3 waveform in FIG. 7. In other words, the gate voltage of the transistor MN2 rises. During the transistor MN2 on-period, when the voltage of the noise detection signal Vgn3 exceeds the on-threshold voltage (Vth) of the transistor MN2, the transistor MN2 turns on. When the transistor MN2 turns on, the signal Vgn4 at the input terminal of the logic inversion element INV1 becomes 0V. Therefore, the voltage of the signal Vgn5, which is the output signal of the logic inversion element INV1, i.e., the gate voltage of the noise discharge switch MND4, becomes the on-voltage (= power supply voltage VDD). This allows the noise current that has flowed into the wiring D to be discharged to the ground GND via the noise discharge switch MND4.

[0051] The noise voltage peaks and then falls. Accordingly, the noise detection signal Vgn3 also falls, causing transistor MN2 to switch from on to off. However, a low-pass filter with a time constant τ = Rn3 × Cinv is formed at the input terminal of the inverter INV1. This is determined by the pull-up resistor Rn3 and the capacitance Cinv added to the gate of the inverter INV1. Therefore, it takes a time proportional to the time constant τ for the voltage of the input signal Vgn4 to the inverter INV1 to transition from 0V to the power supply voltage VDD. For the inverter INV1 to logically invert the output signal Vgn5, the voltage of the input signal Vgn4 to the inverter INV1 must exceed a threshold voltage (approximately half the power supply voltage VDD). Therefore, the noise discharge switch MND4 remains on during the period when the voltage of the signal Vng4 does not exceed the threshold voltage (the MND4 on period), allowing the noise current to continue flowing to ground GND.

[0052] For example, if Rn3 = 100 kΩ and Cinv = 1 pF, the time constant τ = 1 μsec, and it takes approximately 0.7 μsec for the voltage of signal Vgn4 to rise from 0 V to the threshold voltage. Therefore, the noise discharge switch MND4 can continue to discharge the noise current for 0.7 μsec after the voltage of signal Vgn4 starts to rise.

[0053] Therefore, transistor MN2, pull-up resistor Rn3, and capacitor Cinv function as a waveform shaping unit that extends the period during which noise maintains a voltage near its peak value. Also, referring to Figure 7, while the level of the input signal Vng4 to logic inverter INV1 is below the inversion threshold (VDD × 1 / 2), the output of logic inverter INV1 has a HIGH logic level. The voltage corresponding to the HIGH logic level is the voltage that turns on transistor MND4. Therefore, transistor MN2, pull-up resistor Rn3, capacitor Cinv, and logic inverter INV1 collectively function as a waveform shaping unit or monostable multivibrator that extends the period during which noise maintains its peak value. In particular, if the noise continues to maintain a peak value, this waveform shaping unit updates the period during which the noise maintains its peak value each time a peak value is reached. Therefore, the transistor MN2, pull-up resistor Rn3, capacitor Cinv, and logic inverting element INV1, taken as a whole, can be said to function as a retriggerable monostable multivibrator that is triggered by the noise peak pulse. Alternatively, the transistor MN2, pull-up resistor Rn3, capacitor Cinv, and logic inverting element INV1, taken as a whole, can be said to function as a pulse width expansion circuit that widens the noise pulse width. Furthermore, because the noise pulse width is widened every time the noise reaches a peak value, it can also be said to function as a retriggerable pulse width expansion circuit. The noise discharge switch MND4 enables the noise current to be discharged from the wiring during the period when the pulse width is widened by the pulse width expansion circuit, which is the period when the noise detection circuit 302 is detecting noise.

[0054] Furthermore, in this circuit configuration, the voltage of signal Vgn5 can be maintained at the power supply voltage VDD while the noise discharge switch MND4 is driven, thereby maintaining a higher current driving capability of the transistor compared to the noise detection circuit 102 of the first embodiment. In other words, as shown in FIG. 7, when the noise voltage has multiple peaks in a short period of time, it is possible to prevent the discharge from pausing between the peaks. This allows the noise current to flow more efficiently to ground GND. This suppresses the voltage rise on line D, as shown by the solid VD waveform in FIG. 7. Therefore, it is possible to maintain the voltage on line D at or below 10 V, the insulation film breakdown voltage of the anti-fuse element Ca, and it is possible to prevent erroneous writing to the anti-fuse element Ca due to noise voltage entering from the VH terminal.

[0055] Furthermore, between the time when the noise detection circuit 302 detects noise and the time when the noise discharge switch MND4 is turned on, there is a possibility that the noise voltage will pass through the voltage generation circuit 101 and reach the wiring D. To avoid this, in this embodiment, as shown in FIG. 3, a noise delay resistor Rd is inserted between the output terminal of the voltage generation circuit 101 and the intermediate node CC. Here, the intermediate node CC is located on the wiring D between the output terminal of the voltage generation circuit 101 and the terminal AA. The noise discharge switch MND4 has a first connection terminal connected to the intermediate node CC and a second connection terminal connected to ground GND. With this configuration, as shown in the VD waveform in FIG. 7, noise entering the wiring D is delayed, and the noise discharge switch MND4 can be turned on before the voltage of VD rises. To avoid a voltage drop due to the noise delay resistor Rd or the write current being limited by the noise delay resistor Rd when writing to the antifuse element Ca, the resistance value of the noise delay resistor Rd is set small, for example, to approximately several tens of ohms. For this purpose, for example, the noise delay resistive element Rd may be formed in a polysilicon layer with a small resistance value, or may be formed by high concentration N-type diffusion.

[0056] FIG. 8 shows the circuit configuration of an inkjet recording element substrate equipped with a noise suppression circuit according to this embodiment. The inkjet recording element substrate includes multiple recording element modules 801 and multiple memory modules 802. Each recording element module 801 includes a recording element Rh and a transistor MND80 connected in series between a power supply Vheat and a ground GND. Each memory module 802 includes a memory unit 303. The recording element Rh may be a heater for heating ink in a pressure chamber provided in the inkjet printhead, or a piezoelectric element for driving ink in the pressure chamber. The inkjet recording element substrate is provided with multiple anti-fuse elements Ca, and information associated with the inkjet recording element substrate is written into the multiple anti-fuse elements, for example.

[0057] The selection circuit 803 supplies a function selection signal 805 for selecting either the recording element Rh or the anti-fuse element Ca to the selection logic elements in each recording element module 801 and each memory module 802. The selection circuit 803 also supplies a bit selection signal 804 for switching between selection and non-selection of each bit to the selection logic elements in each recording element module 801 and each memory module 802.

[0058] 8, the noise detection circuit 102 is disposed closer to the VH terminal, which is an external connection terminal, than the voltage generation circuit 101. The noise detection circuit 102 is also disposed closer to the VH terminal, which is an external connection terminal, than the anti-fuse element Ca. When the noise detection circuit 102 detects noise, the noise discharge switch MND4 is turned on before the noise reaches the intermediate node CC via the voltage generation circuit 101 and the noise delay resistor Rd. This prevents noise from entering the recording element module 801 and the memory module 802.

[0059] FIG. 9 shows an example of the noise suppression circuit of this embodiment arranged on an inkjet recording element substrate 901. The memory modules 802 are arranged in parallel in the direction in which the recording element modules 801 are arranged, with the external connection terminal arrays 903a and 903b arranged at both ends of the array. The noise detection circuit 102, noise discharge switch MND4, and voltage generation circuit 101 are arranged in the area between the external connection terminal arrays 903a and the recording element module 801 array. The noise detection circuit 102 is preferably arranged adjacent to the VH terminal so that it can detect noise voltage with high sensitivity and good responsiveness. The selection circuit 803 is also arranged in the area between the external connection terminal arrays 903b and the recording element module 801 array. Arranging the circuits according to FIG. 9 maintains symmetry with the outer shape of the inkjet recording element substrate and the ink supply ports 902 as much as possible, while minimizing the wiring connection area within the substrate.

[0060] <Third embodiment> This embodiment illustrates an example in which multiple voltage generating circuits, as described in the above embodiments, are arranged. Figure 10 shows the circuit configuration of a semiconductor device according to this embodiment. The semiconductor device includes multiple memory units 303, each of which includes an anti-fuse element Ca, a parallel resistor Rp, a transistor MND1, and logic inverters MP1 and MN1. The wiring E and wiring F are electrically isolated from each other, and each wiring includes a voltage generating circuit 101A, 101B, a noise discharge switch MND41, a noise discharge switch MND42, and a connection switch MND31, MND32 with the readout circuit 204. Therefore, multiple memory units 303 are provided for the combination of the voltage generating circuit 101A and the noise discharge switch MND41, and multiple memory units 303 are also provided for the combination of the voltage generating circuit 101A, 101B, and the noise discharge switch MND42.

[0061] Furthermore, one noise detection circuit 102 is provided with a set of a voltage generation circuit 101A and a noise discharge switch MND41, and a set of voltage generation circuits 101A, 101B and a noise discharge switch MND42. A noise detection signal Vgn5, which is an output signal from the noise detection circuit 102, is connected to the gates of the noise discharge switches MND41 and MND42. When noise is detected, the noise voltage that has entered each of the wirings E and F is discharged as a noise current to ground GND by turning on the noise discharge switches MND41 and MND42 that have received the noise detection signal Vgn5.

[0062] For the sake of explanation, this embodiment shows an example in which the semiconductor device has two voltage generation circuits. However, if it is desired to further increase the number of bits written to the antifuse element Ca in a single period, more voltage generation circuits may be provided. Similarly, if it is desired to further increase the number of bits read from the antifuse element Ca in a single period, multiple read circuits may be provided. The configuration of this embodiment makes it possible to prevent erroneous writing to the antifuse element Ca from noise voltage entering from the VH terminal.

[0063] <Other embodiments> The anti-fuse element Ca and the transistor MND1 may be interchanged. In this case, a circuit may be provided that switches the transistor MND1 on and off by controlling the source-drain voltage of the transistor MND1 according to the logic level of the first write control signal Sig1.

[0064] In the above embodiment, the second terminal BB, the source of the transistor MND2, and the source of the transistor MN1 are connected to the ground GND, but they may also be connected to a power supply having a constant potential.

[0065] The noise delay resistive element Rd in the above embodiment may be replaced with another delay element.

[0066] In the above embodiment, the second terminal BB is connected to ground GND, but it may be modified so that it is not connected to ground GND. For example, some kind of circuit may be inserted between ground GND and the second terminal BB. In conjunction with this modification, the logic inverting circuit formed by transistors NP1 and MN1 may be modified as necessary.

[0067] In the above embodiments, an antifuse element has been described as an example of a characteristic variable element, but the present disclosure is not limited to this. The present disclosure also includes characteristic variable elements whose electrical characteristics change upon programming compared to before programming. For example, the present disclosure also includes elements whose resistance value becomes higher upon programming than before programming, and characteristic variable elements whose electrical impedance changes upon programming.

[0068] In the above embodiment, a configuration has been described in which the noise reduction circuit is used to protect the anti-fuse element from noise voltages such as surge voltages. However, the present disclosure is not limited to this and also includes a configuration in which the noise reduction circuit protects other elements or circuits from noise voltages such as surge voltages.

[0069] <Technical Features of the Present Disclosure> The present disclosure includes the following configurations.

[0070] [Configuration 1] a characteristic variable element whose electrical characteristics change when a voltage equal to or higher than a predetermined voltage is applied; a write control switch that switches between a conductive state and a non-conductive state based on a first write control signal for controlling writing to the characteristic variable element; a voltage generating circuit that outputs a write voltage from an output terminal based on a second write control signal for controlling a power supply and writing to the characteristic variable element; Equipped with a semiconductor device in which, when the write voltage is output from the output terminal of the voltage generating circuit and the write control switch is in a conductive state, a voltage equal to or higher than the predetermined voltage is applied to the characteristic variable element, thereby changing the electrical characteristics of the characteristic variable element; a wiring used to apply a voltage equal to or higher than the predetermined voltage to the characteristic variable element; a noise detection circuit that detects noise in the power supply; a noise discharge switch that enables the noise current to be discharged from the wiring when the noise detection circuit detects noise in the power supply; The semiconductor device further comprises:

[0071] [Configuration 2] the characteristic variable element and the write control switch are arranged in series between a first terminal and a second terminal; the output terminal and the first terminal of the voltage generating circuit are connected to each other via the wiring; the potential of the second terminal is a potential at which a voltage equal to or greater than the predetermined voltage is applied to the characteristic variable element when the write voltage is output from the output terminal of the voltage generating circuit and the write control switch is in a conductive state; The semiconductor device according to configuration 1.

[0072] [Configuration 3] The second terminal is grounded. 3. The semiconductor device according to configuration 2.

[0073] [Configuration 4] the noise discharge switch is arranged to enable a noise current to be discharged from an intermediate node in the wiring between the output terminal of the voltage generating circuit and the first terminal when the noise detection circuit detects noise in the power supply; a delay element disposed between the output terminal of the voltage generating circuit and the intermediate node, the delay element delaying noise; The semiconductor device according to configuration 2 or 3.

[0074] [Configuration 5] The delay element is a resistive element. 5. The semiconductor device according to configuration 4.

[0075] [Configuration 6] the noise discharge switch grounds the wiring when the noise detection circuit detects noise in the power supply; 6. The semiconductor device according to any one of configurations 1 to 5.

[0076] [Configuration 7] further comprising a resistive element connected in parallel to the characteristic variable element; 7. The semiconductor device according to any one of configurations 1 to 6.

[0077] [Configuration 8] The resistive element is a diffused resistor. 8. The semiconductor device according to configuration 7.

[0078] [Configuration 9] further comprising a read circuit for reading out the electrical characteristics of the characteristic variable element; 9. The semiconductor device according to any one of configurations 1 to 8.

[0079] [Configuration 10] The readout circuit includes: a current source that generates a current; A comparator; Equipped with the voltage of the wiring when the current is passed through the characteristic variable element is compared with a reference voltage by the comparator; 10. The semiconductor device according to configuration 9.

[0080] [Configuration 11] the voltage generating circuit and the readout circuit are exclusively electrically connected to the wiring; The semiconductor device according to configuration 9 or 10.

[0081] [Configuration 12] the characteristic variable element is an anti-fuse element whose resistance value changes when a voltage equal to or higher than the predetermined voltage is applied; 12. The semiconductor device according to claim 1.

[0082] [Configuration 13] the noise detection circuit includes a high-pass filter that blocks the DC voltage of the power supply and transmits noise; 13. The semiconductor device according to any one of configurations 1 to 12.

[0083] [Configuration 14] the noise detection circuit includes a pulse width expansion circuit that expands the pulse width of the noise; the noise discharge switch enables the discharge of noise current from the wiring during a period in which the pulse width is widened by the pulse width widening circuit, as a period in which the noise detection circuit detects noise; 14. The semiconductor device according to claim 1.

[0084] [Configuration 15] The voltage generating circuit is composed of a P-type high-voltage transistor. 15. The semiconductor device according to any one of configurations 1 to 14.

[0085] [Configuration 16] The power supply is supplied from an external connection terminal, the noise detection circuit is disposed at a position closer to the external connection terminal than both a position where the voltage generation circuit is disposed and a position where the characteristic variable element is disposed; 16. The semiconductor device according to any one of configurations 1 to 15.

[0086] [Configuration 17] a plurality of sets of the characteristic variable element and the write control switch are provided for one set of the voltage generating circuit, the noise detecting circuit, and the noise discharging switch; 17. The semiconductor device according to any one of configurations 1 to 16.

[0087] [Configuration 18] a plurality of pairs of the voltage generating circuit and the noise discharge switch are provided for one noise detection circuit; a plurality of pairs of the characteristic variable element and the write control switch are provided for each pair of the voltage generating circuit and the noise discharge switch; 17. The semiconductor device according to any one of configurations 1 to 16.

[0088] [Configuration 19] 19. An ink jet recording element substrate having the semiconductor device according to any one of configurations 1 to 18. [Explanation of symbols]

[0089] 101 Voltage generation circuit 102 Noise detection circuit 901 Inkjet recording element substrate MND2, MND4 noise discharge switches Ca antifuse element MND1 Write control switch

Claims

1. a characteristic variable element whose electrical characteristics change when a voltage equal to or higher than a predetermined voltage is applied; A conductive state is established based on a first write control signal for controlling writing to the characteristic variable element. a write control switch that switches between a conducting state and a non-conducting state; based on a second write control signal for controlling a power supply and writing to the characteristic variable element; a voltage generating circuit that outputs a write voltage from an output terminal; Equipped with The write voltage is output from the output terminal of the voltage generating circuit, and the write control switch When the switch is in a conductive state, a voltage equal to or higher than the predetermined voltage is applied to the characteristic variable element. a semiconductor device in which the electrical characteristics of the characteristic variable element are changed by a wiring used to apply a voltage equal to or higher than the predetermined voltage to the characteristic variable element; a noise detection circuit that detects noise in the power supply; When the noise detection circuit detects noise in the power supply, it discharges noise current from the wiring. a noise discharge switch that enables a read circuit for reading out the electrical characteristics of the characteristic variable element; Further provided with The voltage generating circuit and the readout circuit are electrically connected exclusively to the wiring.

2. a characteristic variable element whose electrical characteristics change when a voltage equal to or higher than a predetermined voltage is applied; A conductive state is established based on a first write control signal for controlling writing to the characteristic variable element. a write control switch that switches between a conducting state and a non-conducting state; based on a second write control signal for controlling a power supply and writing to the characteristic variable element; a voltage generating circuit that outputs a write voltage from an output terminal; Equipped with The write voltage is output from the output terminal of the voltage generating circuit, and the write control switch When the switch is in a conductive state, a voltage equal to or higher than the predetermined voltage is applied to the characteristic variable element. a semiconductor device in which the electrical characteristics of the characteristic variable element are changed by a wiring used to apply a voltage equal to or higher than the predetermined voltage to the characteristic variable element; a noise detection circuit that detects noise in the power supply; When the noise detection circuit detects noise in the power supply, it discharges noise current from the wiring. a noise discharge switch that enables Further provided with The power supply is supplied from an external connection terminal, The semiconductor device wherein the noise detection circuit is disposed at a position closer to the external connection terminal than the characteristic variable element and the voltage generation circuit are disposed.

3. The characteristic variable element and the write control switch are connected between a first terminal and a second terminal. Arranged in series, The output terminal and the first terminal of the voltage generating circuit are connected to each other via the wiring. 、 The potential of the second terminal is the potential at which the write voltage is output from the output terminal of the voltage generating circuit. When the write control switch is in a conductive state, the characteristic variable element is A potential at which a voltage equal to or greater than the applied voltage is applied. The semiconductor device according to claim 1 .

4. The second terminal is grounded. The semiconductor device according to claim 3 .

5. The noise discharge switch is configured to turn on when the noise detection circuit detects noise from the power supply. The wiring is connected to an intermediate node between the output terminal of the voltage generating circuit and the first terminal. arranged to allow noise currents to discharge from a noise delay circuit disposed between the output terminal of the voltage generating circuit and the intermediate node; further comprising a delay element; The semiconductor device according to claim 3 .

6. The delay element is a resistive element. The semiconductor device according to claim 5 .

7. The noise discharge switch is connected to the front end when the noise detection circuit detects noise on the power supply. Ground the wiring. The semiconductor device according to claim 1 .

8. further comprising a resistive element connected in parallel to the characteristic variable element; The semiconductor device according to claim 1 .

9. The resistive element is a diffused resistor. The semiconductor device according to claim 8 .

10. The readout circuit includes: a current source that generates a current; A comparator; Equipped with The voltage of the wiring when the current flows through the characteristic variable element is compared with a reference voltage by the comparator. Compared to pressure, The semiconductor device according to claim 1 .

11. The characteristic variable element is an amplifier whose resistance value changes when a voltage equal to or higher than the predetermined voltage is applied. a fuse element, The semiconductor device according to claim 1 .

12. The noise detection circuit includes a high-pass filter that blocks the DC voltage of the power supply and transmits noise. Equipped with a filter, The semiconductor device according to claim 1 .

13. the noise detection circuit includes a pulse width expansion circuit that expands the pulse width of the noise; The noise discharge switch operates while the pulse width is being expanded by the pulse width expansion circuit. The noise detection circuit detects noise during this period and releases noise current from the wiring. Enabling electricity The semiconductor device according to claim 1 .

14. the voltage generating circuit is composed of a P-type high-voltage transistor; The semiconductor device according to claim 1 .

15. For one set of the voltage generating circuit, the noise detecting circuit, and the noise discharging switch , a plurality of pairs of the characteristic variable element and the write control switch are provided; The semiconductor device according to claim 1 .

16. For one noise detection circuit, the voltage generation circuit and the noise discharge switch There are multiple sets, For each set of the voltage generating circuit and the noise discharge switch, A plurality of sets of write control switches are provided. The semiconductor device according to claim 1 .

17. An ink jet recording element substrate having the semiconductor device according to any one of claims 1 to 16. Board.

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