electronic machinery

Abstract

To provide an electronic instrument mounted with a laminated ceramic electronic component which can be mounted in a saved space and whose function can be enhanced.SOLUTION: An electronic instrument is provided with: first and second circuit boards; a laminated ceramic electronic component; a component connection part composed of solder, which connects first and second external electrodes of the component to a mounting surface of the first circuit board so that a first main surface of a raw body and the mounting surface of the first circuit board face each other; and a board connection part composed of solder, whose dimension in a first axis-direction is larger than a dimension of the laminated ceramic electronic component, which connects the first circuit board to the second circuit board. The first and second external electrodes have first regions extending from a first or second end face up to the first main surface, and second regions arranged in the first axis-direction adjacently to the first regions, on the first or second end face. The first region includes a first outermost layer as a principal component that reacts with the solder of the component connection part more readily than the second region, and a dimension of the component connection part in the first-axis direction is smaller than a dimension of the laminated ceramic electronic component.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to an electronic device in which a multilayer ceramic electronic component such as a multilayer ceramic capacitor is mounted. [Background technology]

[0002] As electronic devices become smaller, there is a demand for lower-profile multilayer ceramic electronic components. Patent Document 1 discloses a low-profile multilayer ceramic capacitor including a ceramic body, a plurality of first and second internal electrodes arranged on the ceramic body, and first and second external electrodes electrically connected to the first and second internal electrodes, respectively. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-130999 Summary of the Invention [Problem to be solved by the invention]

[0004] Multilayer ceramic capacitors are mounted on a substrate, for example, by soldering the external electrodes to the substrate. During this process, the solder may wet up the height of the external electrodes and reach the peripheral edges of the external electrodes. This can result in the height, including the solder, being larger than the height of the multilayer ceramic electronic component, resulting in increased mounting space. Furthermore, restrictions on the height of the ceramic body (ceramic element body) and the number of layers of the internal electrodes have hindered efforts to achieve higher capacitance and other advanced functionality.

[0005] In view of the above circumstances, an object of the present invention is to provide an electronic device equipped with a multilayer ceramic electronic component that can be mounted in a space-saving manner and can be made highly functional. [Means for solving the problem]

[0006] In order to achieve the above object, an electronic device according to an embodiment of the present invention includes a first circuit board and a second circuit board whose mounting surfaces face each other, and a first axial direction in which the mounting surfaces face each other. Ceramic layer sandwiched First internal electrode and second internal electrode an intermediate ceramic layer that is thicker than the ceramic layers and is sandwiched between the first capacitance forming region and the second capacitance forming region in the first axial direction; a first main surface and a second main surface facing the first axis direction, and a first end surface facing a second axis direction perpendicular to the first axis and from which the first internal electrode is drawn; 、 a second end surface facing the second axial direction and from which the second internal electrode is drawn; a side surface facing a third axis direction perpendicular to the first axis and the second axis; a ceramic body having a first end surface covering the first main surface; and the above aspect a first external electrode extending to cover the second end surface and the first main surface; and the above aspect a component connection portion made of solder that connects the first external electrodes and the second external electrodes to the mounting surface of the first circuit board so that the first main surface faces the mounting surface of the first circuit board; and a substrate connection portion made of solder that has a dimension in the first axis direction larger than a dimension of the multilayer ceramic electronic component and connects the mounting surface of the first circuit board to the mounting surface of the second circuit board, Each of the first external electrode and the second external electrode is From the first end surface or the second end surface to the first main surface and the above aspect Extended until and electrically connected to the first internal electrode or the second internal electrode of each of the first capacitance forming region and the second capacitance forming region. A first region; exposing the intermediate ceramic layer in the first end face or the second end face of the ceramic body so as to divide the first region on the first end face or the second end face along the third axis direction into a portion covering the first capacitance formation region and a portion covering the second capacitance formation region; a second region disposed adjacent to the first region in the first axial direction on the first end surface or the second end surface, The first region has a main component that reacts more easily with the solder of the component connection portion than the second region. The best The component connection portion includes an outer layer, and the dimension in the first axial direction is smaller than the dimension of the multilayer ceramic electronic component, and a gap is provided between the first external electrode and the second external electrode and the mounting surface of the second circuit board.

[0007] In the above configuration, the first region includes a first outermost layer made of a main component that readily reacts with solder and is disposed so as to extend from the first end face or the second end face to the first main surface. This allows the first main surface and the mounting substrate to face each other during mounting, thereby allowing the solder to sufficiently react with the first outermost layer near the first main surface and reliably bond the solder to the first and second external electrodes. Furthermore, in the above configuration, the second region is disposed adjacent to the first region in the first axial direction. This prevents the solder from wetting up along the first axial direction in the second region and preventing the solder from reaching the second main surface. Therefore, after mounting, the height dimension in the first axial direction of the multilayer ceramic electronic component including the solder can be restricted, allowing the multilayer ceramic electronic component to be mounted in a space-saving manner. Furthermore, the height dimension in the first axial direction of the ceramic body can be sufficiently secured relative to the mounting space, allowing the mounting space to be fully utilized and achieving high performance of the multilayer ceramic electronic component.

[0012] For example, the second region is on the first end surface or the second end surface. the above It may extend along the third axis direction. This allows the second region to come into contact with the solder that wets up in the first axial direction over a wide area, making it possible to effectively suppress the wet-up of the solder.

[0013] the first external electrode covers the first end face and extends to the first main surface and the second main surface; the second external electrode covers the second end surface and extends to the first main surface and the second main surface; The second region is a region in the first axis direction of each of the first external electrode and the second external electrode. It is located in the center of The first region is the first end surface and It may extend from the second end surface to the first main surface and the second main surface. This allows the second region to suppress solder wetting whether the multilayer ceramic electronic component is mounted with the first main surface facing the circuit board or the second main surface facing the circuit board, thereby increasing the degree of freedom in the mounting orientation of the multilayer ceramic electronic component. [Effects of the Invention]

[0015] As described above, according to the present invention, it is possible to provide an electronic device incorporating a multilayer ceramic electronic component that can be mounted in a space-saving manner and has high functionality. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a perspective view schematically showing a multilayer ceramic electronic component according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA' of the multilayer ceramic electronic component. [Figure 3] FIG. 2 is a cross-sectional view of the multilayer ceramic electronic component taken along line BB'. [Figure 4] FIG. 3 is an enlarged view showing a part of FIG. 2. [Figure 5] 4 is a flowchart showing a method for manufacturing the multilayer ceramic electronic component. [Figure 6] 3A to 3C are perspective views illustrating a manufacturing process of the multilayer ceramic electronic component. [Figure 7] FIG. 2 is a schematic cross-sectional view showing a circuit board on which the multilayer ceramic electronic component is mounted. [Figure 8] FIG. 4 is a schematic cross-sectional view showing a circuit board on which a multilayer ceramic electronic component according to a comparative example of the first embodiment is mounted. [Figure 9] FIG. 9 is an enlarged view showing a part of FIG. 8. [Figure 10] FIG. 8 is an enlarged view showing a part of FIG. [Figure 11] FIG. 8 is an enlarged cross-sectional view corresponding to FIG. 7, showing a modified example of the multilayer ceramic electronic component. [Figure 12]FIG. 4 is a perspective view showing a multilayer ceramic electronic component according to a second embodiment of the present invention. [Figure 13] FIG. 13 is a cross-sectional view taken along line CC' in FIG. [Figure 14] FIG. 14 is an enlarged view showing a part of FIG. [Figure 15] FIG. 2 is a schematic cross-sectional view showing a circuit board on which the multilayer ceramic electronic component is mounted. [Figure 16] FIG. 10 is a perspective view showing a multilayer ceramic electronic component according to a third embodiment of the present invention. [Figure 17] FIG. 17 is a cross-sectional view taken along the line DD' in FIG. [Figure 18] FIG. 18 is an enlarged view showing a part of FIG. [Figure 19] 4 is a flowchart showing an example of a method for manufacturing the multilayer ceramic electronic component. [Figure 20] 3A to 3C are perspective views illustrating a manufacturing process of the multilayer ceramic electronic component. [Figure 21] FIG. 2 is a schematic cross-sectional view showing a circuit board on which the multilayer ceramic electronic component is mounted. [Figure 22] FIG. 10 is a perspective view showing a multilayer ceramic electronic component according to a fourth embodiment of the present invention. [Figure 23] FIG. 23 is a cross-sectional view taken along line EE' in FIG. 22. [Figure 24] FIG. 24 is an enlarged view showing a part of FIG. 23. [Figure 25] FIG. 2 is a schematic cross-sectional view showing a circuit board on which the multilayer ceramic electronic component is mounted. [Figure 26] FIG. 10 is a side view showing a multilayer ceramic electronic component according to a fifth embodiment of the present invention. [Figure 27] FIG. 10 is a cross-sectional view showing a circuit board according to a sixth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, X-axis, Y-axis, and Z-axis, which are mutually orthogonal, are shown as appropriate. The X and Z axes are common to all figures.

[0018] First Embodiment [Overall structure of a multilayer ceramic capacitor] 1 to 3 are diagrams showing a multilayer ceramic capacitor 10 according to a first embodiment of the present invention. Fig. 1 is a perspective view of the multilayer ceramic capacitor 10. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line A-A' in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line B-B' in Fig. 1.

[0019] The multilayer ceramic capacitor 10 includes a ceramic body 11, a first external electrode 14, and a second external electrode 15. The external electrodes 14, 15 are each formed on the surface of the ceramic body 11.

[0020] The ceramic body 11 has a substantially rectangular parallelepiped shape. That is, the ceramic body 11 includes a pair of end faces 11a and 11b facing the X-axis direction, a pair of side faces 11c and 11d facing the Y-axis direction, and a pair of main faces 11e and 11f facing the Z-axis direction. The end faces 11a and 11b extend along the Y-axis direction and the Z-axis direction. The side faces 11c and 11d extend along the Z-axis direction and the X-axis direction. The main faces 11e and 11f extend along the X-axis direction and the Y-axis direction.

[0021] The end faces 11a and 11b, the side faces 11c and 11d, and the main faces 11e and 11f of the ceramic body 11 are all flat surfaces. The flat surfaces according to this embodiment do not necessarily have to be strictly planar as long as they are recognized as flat when viewed overall, and include, for example, surfaces with minute irregularities or gently curved shapes within a predetermined range.

[0022] The ceramic body 11 includes, for example, ridges connecting the respective surfaces. The ridge connecting the first main surface 11e to the first end surface 11a or the second end surface 11b is referred to as a first ridge 11g. The ridge connecting the second main surface 11f to the first end surface 11a or the second end surface 11b is referred to as a second ridge 11h. Each ridge may be chamfered, for example.

[0023] The size of the multilayer ceramic capacitor 10 is, for example, 0.2 mm to 2.0 mm in the X-axis direction and 0.2 mm to 2.0 mm in the Y-axis direction. The multilayer ceramic capacitor 10 may have its longer side in either the X-axis direction or the Y-axis direction, and in the example shown in FIGS. 1 to 3, its longer side is in the Y-axis direction. The dimension of the multilayer ceramic capacitor 10 in the Z-axis direction is, for example, 100 μm or less, and the multilayer ceramic capacitor 10 is configured to have a low profile. Note that each dimension of the multilayer ceramic capacitor 10 is the dimension of the largest part in each direction.

[0024] The ceramic body 11 has a capacitance forming portion 111, a cover portion 112, and a side margin portion 113. The capacitance forming portion 111 is disposed in the center of the ceramic body 11 in the Y-axis and Z-axis directions. The cover portion 112 covers the capacitance forming portion 111 from the Z-axis direction, and the side margin portion 113 covers the capacitance forming portion 111 from the Y-axis direction.

[0025] More specifically, the cover portions 112 are arranged on both sides of the capacitance forming portion 111 in the Z-axis direction. The side margin portions 113 are arranged on both sides of the capacitance forming portion 111 in the Y-axis direction. The cover portions 112 and the side margin portions 113 mainly have the function of protecting the capacitance forming portion 111 and ensuring insulation around the capacitance forming portion 111.

[0026] The capacitance forming portion 111 is formed by alternately stacking a plurality of first internal electrodes 12 and a plurality of second internal electrodes 13 in the Z-axis direction with ceramic layers 16 (see FIG. 3) interposed therebetween. The internal electrodes 12, 13 are both sheet-shaped extending along the X-axis direction and the Y-axis direction, and are alternately arranged along the Z-axis direction.

[0027] The internal electrodes 12 and 13 are each made of a good electrical conductor. Examples of the good electrical conductor that forms the internal electrodes 12 and 13 include metals and alloys containing nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), and gold (Au) as the main component. The term "main component" refers to a component that accounts for 50% or more of the composition.

[0028] 2, the first internal electrode 12 is extended to a first end face 11a of the ceramic body 11 and connected to a first external electrode 14. The second internal electrode 13 is extended to a second end face 11b of the ceramic body 11 and connected to a second external electrode 15. This allows the internal electrodes 12, 13 to be electrically connected to different external electrodes 14, 15, respectively.

[0029] The ceramic layers 16 are made of dielectric ceramics. In the multilayer ceramic capacitor 10, a dielectric ceramic with a high dielectric constant is used to increase the capacitance of each ceramic layer 16 between the internal electrodes 12 and 13. Examples of dielectric ceramics with a high dielectric constant include perovskite-structured materials containing barium (Ba) and titanium (Ti), such as barium titanate (BaTiO).

[0030] In addition to barium titanate-based materials, the dielectric ceramics may also be strontium titanate (SrTiO3)-based, calcium titanate (CaTiO3)-based, magnesium titanate (MgTiO3)-based, calcium zirconate (CaZrO3)-based, calcium titanate zirconate (Ca(Zr,Ti)O3)-based, barium zirconate (BaZrO3)-based, titanium oxide (TiO2)-based, etc.

[0031] The cover portion 112 and the side margin portion 113 are also made of dielectric ceramics. The material for forming the cover portion 112 and the side margin portion 113 may be any insulating ceramic, but using a material with the same composition as the capacitance forming portion 111 improves manufacturing efficiency and suppresses internal stress in the ceramic body 11.

[0032] With the above configuration, when a voltage is applied between the external electrodes 14, 15 in the multilayer ceramic capacitor 10, the voltage is applied to the plurality of ceramic layers 16 between the internal electrodes 12, 13 in the capacitance forming portion 111. As a result, a charge corresponding to the voltage between the external electrodes 14, 15 is stored in the multilayer ceramic capacitor 10.

[0033] [External electrode configuration] 2, the first external electrode 14 covers the first end face 11a and extends to at least the first main face 11e. In this embodiment, the first external electrode 14 covers the first end face 11a and extends to both main faces 11e and 11f and both side faces 11c and 11d. The second external electrode 15 covers the second end face 11b and extends to at least the first main face 11e. In this embodiment, the second external electrode 15 covers the second end face 11b and extends to both main faces 11e and 11f and both side faces 11c and 11d.

[0034] Each of the external electrodes 14, 15 has a first region 17 extending from the first end face 11a or the second end face 11b to the first main face 11e, and a second region 18 arranged adjacent to the first region 17 in the Z-axis direction on the end faces 11a, 11b. The phrase "the second region 18 is adjacent to the first region 17" also includes a case where the periphery of the second region 18 is surrounded by the first region 17, as shown in an example described later.

[0035] In this embodiment, the second region 18 is disposed in the center of the external electrodes 14, 15 in the Z-axis direction. "The center of the external electrodes 14, 15 in the Z-axis direction" refers to the center region when the external electrodes 14, 15 are divided into thirds in the Z-axis direction. The second region 18 is configured in a strip shape (groove shape) extending along the Y-axis direction. The second region 18 only needs to be formed in the region on at least the end faces 11a, 11b, and in this embodiment, it extends from the region on the end faces 11a, 11b to the regions on both side faces 11c, 11d.

[0036] In this embodiment, each of the external electrodes 14, 15 has two first regions 17 arranged side by side in the Z-axis direction with a second region 18 sandwiched between them. The two first regions 17 are, for example, completely separated by the second region 18.

[0037] In this embodiment, these first regions 17 extend from the first end face 11a or the second end face 11b to the first main surface 11e and the second main surface 11f. More specifically, one first region 17 extends from the center of the external electrodes 14, 15 in the Z-axis direction, through the first ridge portion 11g, to the first main surface 11e. The other first region 17 extends from the center of the external electrodes 14, 15 in the Z-axis direction, through the second ridge portion 11h, to the second main surface 11f.

[0038] In this embodiment, the second region 18 is formed thinner than the first region 17 and is recessed from the first region 17. As will be described later, the second region 18 is configured as a region that regulates wetting and rising of the solder.

[0039] Fig. 4 is an enlarged view showing a part of Fig. 2. Since the external electrodes 14 and 15 have the same configuration, the second external electrode 15 is not shown in Fig. 4.

[0040] In this embodiment, the first region 17 includes a first inner layer 171 and a first outermost layer 172. The first inner layer 171 is disposed on the ceramic body 11. The first outermost layer 172 is mainly composed of tin and is disposed on the first inner layer 171.

[0041] The first inner layer 171 includes one or more layers, and in this embodiment, includes multiple layers. The first inner layer 171 includes, for example, a first layer 171a disposed on the ceramic body 11 and a second layer 171b disposed on the first layer 171a. The first layer 171a includes one or more layers, for example, a plating base film and a plating film. The second layer 171b constitutes the outermost layer of the first inner layer 171 and is formed of, for example, a plating film.

[0042] The plating base film of the first layer 171a is formed by applying a conductive paste by, for example, a dipping method, a printing method, etc., and then baking it. The plating base film can be mainly composed of copper, nickel, palladium, platinum, silver, gold, etc.

[0043] The plating film of the first layer 171a may be mainly composed of, for example, copper, nickel, platinum, palladium, silver, gold, etc., other than tin. The plating film of the first layer 171a may be omitted.

[0044] The second layer 171b is a plating film whose main component is, for example, copper, nickel, platinum, palladium, silver, gold, etc., other than tin. As an example, the second layer 171b is a nickel plating film whose main component is nickel.

[0045] In this embodiment, the first outermost layer 172 is configured as a tin-plated film containing tin as a main component. The first outermost layer 172 is divided into upper and lower parts at the center of the external electrode 14 in the Z-axis direction.

[0046] In this embodiment, the second region 18 includes a second inner layer 181 disposed on the ceramic body 11 and a second outermost layer 182 disposed on the second inner layer 181. The second region 18 in this embodiment has a layer structure common to the first inner layer 171 of the first region 17.

[0047] The second inner layer 181 has, for example, a layer structure common to the first layer 171a of the first region 17. That is, the second inner layer 181 includes one or more layers, for example, a plating base film disposed on the ceramic body 11 and a plating film disposed on the plating base film. The plating base film forms a layer continuous with the plating base film of the first layer 171a. The plating film forms a layer continuous with the plating film of the first layer 171a. The plating film of the second inner layer 181 may be omitted.

[0048] The second outermost layer 182 does not contain tin as a main component. Note that "a layer does not contain tin as a main component" means that the composition ratio of tin in the layer is 5% or less. The second outermost layer 182 may contain, for example, copper, nickel, platinum, palladium, silver, or gold as a main component other than tin. As an example, the second outermost layer 182 is a nickel plating film containing nickel as a main component. In this embodiment, the second outermost layer 182 is formed continuously with at least a portion of the first inner layer 171, and more specifically, is formed continuously with the second layer 171b of the first inner layer 171. In other words, the second outermost layer 182 forms a single layer that is continuous with the second layer 171b.

[0049] A method for manufacturing the multilayer ceramic capacitor 10 having the above configuration will now be described.

[0050] [Method of manufacturing the multilayer ceramic capacitor 10] Fig. 5 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 10. Fig. 6 is a diagram showing the manufacturing process of the multilayer ceramic capacitor 10. The method for manufacturing the multilayer ceramic capacitor 10 will be described below along Fig. 5, with reference to Fig. 6 as needed.

[0051] (Step S11: Fabricating a ceramic body) In step S11, a first ceramic sheet S1 and a second ceramic sheet S2 for forming the capacitance forming portion 111 and a third ceramic sheet S3 for forming the cover portion 112 are prepared. Then, as shown in Fig. 6, these ceramic sheets S1, S2, and S3 are stacked and fired to produce the ceramic body 11.

[0052] The ceramic sheets S1, S2, and S3 are formed as unfired dielectric green sheets whose main component is dielectric ceramics. An unsintered first internal electrode 12u corresponding to the first internal electrode 12 is formed on the first ceramic sheet S1, and an unsintered second internal electrode 13u corresponding to the second internal electrode 13 is formed on the second ceramic sheet S2. On the ceramic sheets S1 and S2, an area corresponding to a side margin portion 113 where no internal electrodes 12u and 13u are formed is provided on the periphery in the Y-axis direction of the internal electrodes 12u and 13u. No internal electrodes are formed on the third ceramic sheet S3.

[0053] 6, the green ceramic body 11u is formed by alternately stacking ceramic sheets S1 and S2, and stacking a third ceramic sheet S3 corresponding to the cover portion 112 on the top and bottom surfaces in the Z-axis direction. The green ceramic body 11u is integrated by pressure-bonding the ceramic sheets S1, S2, and S3. The number of ceramic sheets S1, S2, and S3 is not limited to the example shown in FIG.

[0054] Although the above has described an unfired ceramic body 11u corresponding to one ceramic body 11, in reality, a laminated sheet is formed as a large, undivided sheet, and then the laminated sheet is divided into individual ceramic bodies 11u.

[0055] The ceramic body 11 shown in FIGS. 1 to 3 is produced by sintering the unsintered ceramic body 11u. The firing temperature can be determined based on the sintering temperature of the ceramic body 11u. For example, when a barium titanate-based material is used as the dielectric ceramic, the firing temperature can be set to approximately 1000 to 1300°C. Furthermore, firing can be performed, for example, in a reducing atmosphere or a low-oxygen partial pressure atmosphere.

[0056] (Step S12: Forming external electrodes) In step S12, the external electrodes 14, 15 are formed, each having a first region 17 and a second region 18. In the external electrodes 14, 15 of this embodiment, a layer common to the first region 17 and the second region 18 is formed, and then a first outermost layer 172 of the first region 17 is formed.

[0057] First, a plating base film is formed on the end faces 11a and 11b, which is common to the first layer 171a of the first region 17 and the second inner layer 181 of the second region. The plating base film is provided so as to extend, for example, from the first end face 11a or the second end face 11b to both main faces 11e and 11f and both side faces 11c and 11d. The plating base film is formed by applying a conductive paste by, for example, a dipping method or a printing method, followed by baking.

[0058] Next, one or more plating films are formed over the entire plating base film. Each plating film is mainly composed of copper, nickel, platinum, palladium, silver, gold, or the like, other than tin, and is formed by, for example, electrolytic plating. The outermost layer of the plating film constitutes the second layer 171b of the first inner layer 171 of the first region 17 and the second outermost layer 182 of the second region 18, and is formed of, for example, a nickel plating film.

[0059] Then, a tin-plated film containing tin as a main component is formed on the second layer 171b of the first region 17. This tin-plated film constitutes the first outermost layer 172. The tin-plated film is formed by, for example, electrolytic plating. Before forming the tin-plated film, for example, a process is performed to prevent the formation of the tin-plated film on the second outermost layer 182 of the second region 18. As a result, the tin-plated film is formed only on the second layer 171b of the first region 17.

[0060] As a treatment that does not form a tin plating film, for example, a mask may be formed on the second layer 171b of the first region 17, and an oxidation treatment may be performed to oxidize the second outermost layer 182 of the second region 18. The oxidation treatment may be natural oxidation or plasma treatment in an oxygen atmosphere. A tin plating film is not formed on the oxidized second outermost layer 182. Therefore, by removing the mask after the oxidation treatment and performing a tin plating treatment, a tin plating film is formed only on the second layer 171b of the first region 17.

[0061] Alternatively, as a process to prevent the formation of a tin-plated film, a mask may be formed on the second outermost layer 182 of the second region 18. The tin-plated film is not formed in the region where the mask is formed. Therefore, by performing a tin-plating process after forming the mask, the tin-plated film is formed only in the region corresponding to the first region 17. The mask can be removed after the tin-plated film is formed.

[0062] Through the above steps, the multilayer ceramic capacitor 10 shown in FIGS. 1 to 3 is manufactured. Furthermore, the multilayer ceramic capacitor 10 is mounted on a substrate by soldering the external electrodes 14 and 15.

[0063] [Circuit board configuration] FIG. 7 is a cross-sectional view showing the circuit board 100 of this embodiment, corresponding to FIG.

[0064] 7, the circuit board 100 includes a first substrate (mounting substrate) 101, a multilayer ceramic capacitor 10, and solder H (component connecting portion) that connects the external electrodes 14, 15 to the first substrate 101. The circuit board 100 shown in FIG. 7 further includes a second substrate 102 and a connecting member C (substrate connecting portion) that connects the first substrate 101 and the second substrate 102.

[0065] The first substrate 101 is configured as a mounting substrate for mounting the multilayer ceramic capacitor 10. The first substrate 101 includes a substrate body 103 including a mounting surface 103a, and a The substrate body 103 includes component mounting lands 104 arranged on the mounting surface 103a, board connection lands 105 arranged on the mounting surface 103a, and solder resist 106 arranged around the lands 104, 105 on the mounting surface 103a. A circuit (not shown) is formed on the board body 103. In this embodiment, the mounting surface 103a is arranged perpendicular to the Z-axis direction. The lands 104, 105 are configured as connection terminals on the mounting surface 103a. The solder resist 106 is configured as an insulating resin film.

[0066] The second substrate 102 is used as a substrate disposed opposite the first substrate 101 in the Z-axis direction. The second substrate 102 includes a substrate main body 107 including an opposing surface 107a facing the mounting surface 103a, substrate connection lands 108 disposed on the opposing surface 107a, and solder resist 109 disposed around the substrate connection lands 108 on the opposing surface 107a. A circuit (not shown) is formed on the substrate main body 107. In this embodiment, the opposing surface 107a faces the mounting surface 103a in the Z-axis direction and is disposed, for example, perpendicular to the Z-axis direction. The substrate connection lands 108 are configured as connection terminals on the opposing surface 107a. The solder resist 109 is configured as an insulating resin film.

[0067] In this embodiment, the connection member C is configured as a ball-shaped solder. The connection member C connects the substrate connection land 105 of the first substrate 101 and the substrate connection land 108 of the second substrate 102, and forms a gap in the Z-axis direction between the mounting surface 103 a and the opposing surface 107 a.

[0068] The circuit board 100 is manufactured as follows. First, solder paste is applied to the component mounting lands 104 on the first substrate 101, and the multilayer ceramic capacitor 10 is placed on the solder paste. This brings the surfaces of the external electrodes 14, 15 on the main surface 11e into contact with the solder paste. Typically, the first substrate 101 is placed so that the mounting surface 103a faces vertically upward during soldering.

[0069] Next, solder paste is applied to the board connection lands 105. Then, the second board 102 is placed so that the solder paste on the board connection lands 105 comes into contact with the board connection lands 108 of the second board 102. As a result, the second board 102 is placed opposite the first board 101. In this state, the second board 102 is heated in a reflow furnace, and the solder paste on the lands 104 and 105 is heated and melted.

[0070] As the solder paste melts, the multilayer ceramic capacitor 10 sinks toward the component mounting lands 104. As a result, the solder paste on the component mounting lands 104 wets and rises from the first main surfaces 11e of the external electrodes 14, 15 to the end surfaces 11a, 11b. The solder paste then cools and solidifies, forming solder H that connects the external electrodes 14, 15 to the first substrate 101. Similarly, the solder paste on the substrate connection lands 105 melts and then solidifies, forming a connection member C that connects the substrate connection lands 105, 108 of the first substrate 101 and the second substrate 102.

[0071] [Effects of this embodiment] In this embodiment, as shown in FIG. 4, the first region 17 arranged to cover the first edge portion 11g includes a first outermost layer 172 primarily composed of tin. During mounting, the solder paste wets and rises up the first outermost layer 172 from the first edge portion 11g toward the second edge portion 11h. Because the first outermost layer 172 is primarily composed of tin, it reacts with the solder paste and melts, and is sufficiently bonded to the solder H when the solder H solidifies. Therefore, the first region 17 including the first outermost layer 172 can sufficiently ensure the reliability of the bond with the solder H.

[0072] On the other hand, the external electrodes 14, 15 of this embodiment have second regions 18 arranged adjacent to the first region 17 in the Z-axis direction on the end faces 11a, 11b. The second region 18 does not include an outermost layer mainly composed of tin, and is therefore less likely to react with the solder H. This makes it possible to suppress wetting of the solder paste in the second region 18 and to prevent the solder paste from reaching the second edge portion 11h. Therefore, after mounting, it is possible to prevent the solder H from being formed in the region on the second main surface 11f of the external electrodes 14, 15.

[0073] FIG. 8 is a schematic cross-sectional view showing a circuit board 200 on which a multilayer ceramic capacitor 20 according to a comparative example of this embodiment is mounted. 8, the multilayer ceramic capacitor 20 includes external electrodes 24, 25 that do not have a second region. That is, the entire external electrodes 24, 25 are configured similarly to the first region 17 of the present embodiment, and include a first outermost layer 272 containing tin as a main component, and a first inner layer 271.

[0074] FIG. 9 is an enlarged view showing a part of FIG. In the multilayer ceramic capacitor 20, during mounting, the solder paste wets and rises from the first edge portion 11g toward the second edge portion 11h, and the solder paste can reach the surfaces on the second main surface 11f of the external electrodes 24, 25. In particular, when the multilayer ceramic capacitor 20 is low-profile, the height dimension in the Z-axis direction is small, so the solder paste can easily reach the surfaces on the second main surface 11f.

[0075] As shown in FIG. 9, the height dimension of the multilayer ceramic capacitor 20 in the Z-axis direction is defined as component height dimension t'1. The height dimension of the solder H in the Z-axis direction is defined as solder height dimension t'2. In this example, since the solder H is formed on the surface on the second main surface 11f of the external electrodes 24, 25, the solder height dimension t'2 is larger than the component height dimension t'1 in the Z-axis direction by a thickness t'3. Therefore, the effective height dimension of the multilayer ceramic capacitor 20 mounted with the solder H is the solder height dimension t'2, which is larger than the actual component height dimension t'1 by a thickness t'3.

[0076] For this reason, in circuit board 200, it is necessary to set the opposing distance between first substrate 101 and second substrate 102 in consideration of solder height dimension t'2, which is larger than component height dimension t'1. This makes it difficult to reduce the overall thickness of circuit board 200, which may hinder miniaturization of electronic devices in which circuit board 200 is mounted.

[0077] Furthermore, the solder H on the surfaces of the external electrodes 24, 25 on the second main surface 11f is likely to come into contact with structures such as the solder resist 109 of the second substrate 102. This may result in an external impact being applied to the multilayer ceramic capacitor 20, which may cause damage such as cracks.

[0078] Furthermore, if the facing distance between the first substrate 101 and the second substrate 102 is specified, the solder height dimension t'2 of the multilayer ceramic capacitor 20 must be set to be equal to or less than this facing distance. Therefore, the component height dimension t'1 must be set smaller by the thickness t'3 of the solder H. This inevitably limits the height dimension of the ceramic body 11, restricts the number of layers of the internal electrodes 12, 13 of the multilayer ceramic capacitor 20, and makes it difficult to achieve high capacitance. This also narrows the thickness of each ceramic layer 16, potentially resulting in problems such as reduced bias characteristics and reduced reliability.

[0079] On the other hand, in the multilayer ceramic capacitor 10 of this embodiment, the external electrodes 14, 15 have second regions 18 that restrict wetting up of the solder H. This makes it possible to prevent the solder H from reaching the surfaces on the second main surfaces 11f of the external electrodes 14, 15.

[0080] FIG. 10 is an enlarged view showing a part of FIG. As shown in FIG. 10, the height dimension of the multilayer ceramic capacitor 10 in the Z-axis direction is defined as component height dimension t1. The height dimension of the solder H in the Z-axis direction is defined as solder height dimension t2. In this embodiment, the second region 18 acts to suppress solder wetting, preventing the solder H from reaching the surface on the second main surface 11f. Therefore, the solder height dimension t2 is smaller than the component height dimension t1. In other words, even when mounted using the solder H, the substantial height dimension of the multilayer ceramic capacitor 10 coincides with the actual component height dimension t1.

[0081] Therefore, in circuit board 100, the opposing distance between first substrate 101 and second substrate 102 can be set taking into consideration only component height dimension t1. This allows the thickness of circuit board 100 in the Z-axis direction to be reduced, which can contribute to the miniaturization of electronic devices in which circuit board 100 is mounted.

[0082] Furthermore, the circuit board 100 does not have solder H that would increase the substantial height of the multilayer ceramic capacitor 10. Therefore, even if the opposing distance between the first substrate 101 and the second substrate 102 becomes narrow, the multilayer ceramic capacitor 10 can be prevented from coming into contact with the structure of the second substrate 102, and damage to the multilayer ceramic capacitor 10 can be prevented.

[0083] Furthermore, even when the facing distance between the first substrate 101 and the second substrate 102 is specified, the component height dimension t1 of the multilayer ceramic capacitor 10 can be sufficiently ensured according to the facing distance, without considering the thickness t'3 of the solder H. This allows the height dimension of the ceramic body 11 of the multilayer ceramic capacitor 10 to be sufficiently ensured. Therefore, the number of layers of the internal electrodes 12, 13 can be increased, thereby achieving high capacitance. In addition, deterioration of bias characteristics and deterioration of reliability due to narrowing of the thickness of the ceramic layers 16 can be suppressed.

[0084] Furthermore, since the component height dimension t1 of the multilayer ceramic capacitor 10 can be sufficiently ensured, the multilayer ceramic capacitor 10 can have sufficient flexural strength. The flexural strength of a multilayer ceramic capacitor is measured by supporting both ends of the multilayer ceramic capacitor in the Z-axis direction using a stand or the like and pressing the center of the multilayer ceramic capacitor 10 in the XY plane downward in the Z-axis direction with a presser. The value of the flexural strength can be the magnitude of the load applied to the presser when damage occurs to the multilayer ceramic capacitor. In fact, when the opposing distance between the first substrate 101 and the second substrate 102 in the circuit boards 100 and 200 is set to the same, the flexural strength of the multilayer ceramic capacitor 10 of this embodiment is approximately 1.4 times that of the multilayer ceramic capacitor 20 of the comparative example.

[0085] That is, the multilayer ceramic capacitor 10 can have high mechanical strength even though it is low-profile, and therefore can have a highly reliable configuration that can withstand bending of the board after mounting and external impacts.

[0086] In this embodiment, the second region 18 is configured to extend in the Y-axis direction. This allows the second region 18 to come into contact with the solder that wets up in the Z-axis direction over a wide area of ​​the region on the end faces 11a, 11b of the external electrodes 14, 15, making it possible to more effectively suppress the wetting up of the solder. Furthermore, since the first region 17 is completely separated by the second region 18, it is possible to more reliably suppress the wetting up of the solder in the Z-axis direction.

[0087] Additionally, in this embodiment, the second region 18 is disposed in the center of the external electrodes 14, 15 in the Z-axis direction, and the first region 17 extends from the first end face 11a or the second end face 11b to both main faces 11e, 11f. This allows the above-described effects to be obtained in both cases where the multilayer ceramic capacitor 10 is mounted with the first main face 11e facing the first substrate 101 and where the second main face 11f faces the first substrate 101. This increases the degree of freedom in the mounting orientation of the multilayer ceramic capacitor 10, and improves handling during mounting.

[0088] [Variations] Each layer of the first region 17 and the second region 18 may have various configurations other than the above examples.

[0089] For example, the second inner layer 181 of the second region 18 may be composed of a layer continuous with the plating base film included in the first layer 171a of the first region 17, and the second outermost layer 182 may be composed of a layer continuous with the plating film included in the first layer 171a of the first region 17.

[0090] 11, the second region 18 may have a second outermost layer 182 but may not have a second inner layer. For example, the second outermost layer 182 may be a baked film of a conductive paste configured as a plating base film, and may be formed continuously with the plating base film of the first layer 171a of the first region 17. In this case, in the first region 17, the first layer 171a of the first inner layer 171 may be configured as a plating base film, and the second layer 171b may be configured as one or more plating films that do not contain tin as a main component.

[0091] Second Embodiment [Structure of multilayer ceramic capacitors] Fig. 12 is a perspective view showing a multilayer ceramic capacitor 30 in accordance with a second embodiment of the present invention. Fig. 13 is a cross-sectional view taken along line CC' in Fig. 12. Note that the cross section parallel to the YZ plane corresponding to Fig. 3 is the same as that in the first embodiment, and is therefore not shown. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals and the description thereof will be omitted.

[0092] The multilayer ceramic capacitor 30 includes a ceramic body 11, a first external electrode 34, and a second external electrode 35. In this embodiment, the first external electrode 34 covers the first end face 11a and extends to both principal faces 11e, 11f and both side faces 11c, 11d. In this embodiment, the second external electrode 35 covers the second end face 11b and extends to both principal faces 11e, 11f and both side faces 11c, 11d.

[0093] Each of the external electrodes 34, 35 has a first region 37 that covers the first edge portion 11g and the second edge portion 11h, and a second region 38 that is disposed adjacent to the first region 37 in the Z-axis direction.

[0094] In this embodiment, the second region 38 is disposed in the center of the external electrodes 34, 35 in the Z-axis direction. The second region 38 is configured in a strip shape extending along the Y-axis direction. The second region 38 is formed, for example, in a region on the end faces 11a, 11b. In this embodiment, the second region 38 is configured to protrude from the first region 37.

[0095] The first region 37 extends from the end faces 11a, 11b to the regions on both main faces 11e, 11f and both side faces 11c, 11d. In this embodiment, the first region 37 is divided vertically in the Z-axis direction only in the regions on the end faces 11a, 11b by the second region 38. The first region 37 covers both the first ridge portion 11g and the second ridge portion 11h.

[0096] Fig. 14 is an enlarged view showing a part of Fig. 13. Since the external electrodes 34 and 35 have the same configuration, the second external electrode 35 is not shown in Fig. 14.

[0097] In this embodiment, the first region 37 includes a first inner layer 371 and a first outermost layer 372 containing tin as a main component.

[0098] The first inner layer 371 is disposed on the ceramic body 11. The first inner layer 371 includes one or more layers, and in this embodiment, includes multiple layers. Similar to the first inner layer 171 of the first embodiment, the first inner layer 371 includes a plating base film and one or more plating films.

[0099] The first outermost layer 372 is disposed on the first inner layer 371. The first outermost layer 372 is configured as a tin-plated film containing tin as a main component, similar to the first outermost layer 172 of the first embodiment.

[0100] In this embodiment, the second region 38 includes a second inner layer 381, a tin-containing layer 382, ​​and a second outermost layer 383 that does not contain tin as a main component.

[0101] The second inner layer 381 is disposed on the ceramic body 11 and has a layer structure common to the first inner layer 371 of the first region 37. That is, the second inner layer 381 includes one or more layers, such as a plating base film and one or more plating films.

[0102] The tin-containing layer 382 is mainly composed of tin and is disposed on the second inner layer 381. The tin-containing layer 382 is formed continuously with the first outermost layer 372 and is configured as a tin-plated film mainly composed of tin.

[0103] The second outermost layer 383 does not contain tin, which is highly reactive with solder, as its main component. Therefore, the second region 38 is configured as a region that restricts the wetting and rising of solder. The composition of the second outermost layer 383 is not particularly limited as long as it contains a main component other than tin, and can be, for example, a metal other than tin, such as gold or platinum, a metal oxide such as copper oxide, ceramics, diamond-like carbon, or the like.

[0104] The method for forming the second outermost layer 383 is not particularly limited, and a method such as sputtering, vapor deposition, or printing may be appropriately selected depending on the composition. The second outermost layer 383 is formed by the above method, for example, after a mask is formed on the first outermost layer 372 of the first region 37. The mask is removed, for example, after the second outermost layer 383 is formed.

[0105] [Circuit board configuration] FIG. 15 is a diagram showing a circuit board 300 of this embodiment, and is a cross-sectional view corresponding to FIG.

[0106] 15, the circuit board 300 includes a first substrate (mounting substrate) 101, a multilayer ceramic capacitor 30, and solder H (component connecting portion) that connects the external electrodes 34, 35 to the first substrate 101. The circuit board 300 shown in FIG. 15 further includes a second substrate 102 and a connecting member C (substrate connecting portion) that connects the first substrate 101 and the second substrate 102. The solder H is formed from the first region 37 to the second region 38 of the external electrodes 34, 35 of the multilayer ceramic capacitor 30.

[0107] [Effects of this embodiment] In this embodiment, the external electrodes 34, 35 also have the second regions 38, which restricts the wetting of the solder on the external electrodes 34, 35. This reduces the solder height and restricts the effective height of the multilayer ceramic capacitor 30 on the circuit board 300. This reduces the mounting space for the multilayer ceramic capacitor 30 and contributes to the miniaturization of the circuit board 300 and the electronic device on which it is mounted. Furthermore, restricting the effective height of each multilayer ceramic capacitor 30 reduces contact between the multilayer ceramic capacitor 30 and other structures on the circuit board 300, preventing damage to the multilayer ceramic capacitor 30. Furthermore, ensuring a sufficient height of the ceramic body 11 contributes to increasing the capacitance and improving the bias characteristics of the multilayer ceramic capacitor 30, and also ensures sufficient mechanical strength of the multilayer ceramic capacitor 30.

[0108] In addition, by configuring the second region 38 to extend in the Y-axis direction, it is possible to effectively suppress the solder from wetting up in the Z-axis direction. Also, by arranging the second region 38 in the center of the external electrodes 34, 35 in the Z-axis direction and by having the first region 37 extend to both main surfaces 11e, 11f, it is possible to increase the degree of freedom in the mounting posture of the multilayer ceramic capacitor 30.

[0109] <Third embodiment> [Structure of multilayer ceramic capacitors] 16 is a perspective view showing a multilayer ceramic capacitor 40 in accordance with a third embodiment of the present invention, and FIG. 17 is a cross-sectional view taken along line DD' in FIG.

[0110] The multilayer ceramic capacitor 40 includes a ceramic body 41, a first external electrode 44, and a second external electrode 45. In this embodiment, the first external electrode 44 covers the first end face 41a and extends to both principal faces 41e, 41f and both side faces 41c, 41d. In this embodiment, the second external electrode 45 covers the second end face 41b and extends to both principal faces 41e, 41f and both side faces 41c, 41d.

[0111] The ceramic body 41 has a capacitance forming portion 411, a cover portion 412, and side margin portions (not shown). The cover portions 412 are arranged on both sides of the capacitance forming portion 411 in the Z-axis direction. The side margin portions are arranged on both sides of the capacitance forming portion 411 in the Y-axis direction.

[0112] The capacitance forming portion 411 includes a first capacitance forming region 411a, a second capacitance forming region 411b, and an intermediate ceramic layer 46c. The first capacitance forming region 411a includes first internal electrodes 12 and second internal electrodes 13 that are alternately stacked in the Z-axis direction with the first ceramic layer 46a interposed therebetween. The second capacitance forming region 411b includes first internal electrodes 12 and second internal electrodes 13 that are alternately stacked in the Z-axis direction with the second ceramic layer 46b interposed therebetween. The second capacitance forming region 411b is connected to the first capacitance forming region 411a in the Z-axis direction with the intermediate ceramic layer 46c interposed therebetween. The intermediate ceramic layer 46c is configured to have a thickness dimension in the Z-axis direction that is thicker than the first ceramic layer 46a and the second ceramic layer 46b.

[0113] Each of the external electrodes 44, 45 has a first region 47 that covers the ridges 41g, 41h, and a second region 48 that is disposed adjacent to the first region 47 in the Z-axis direction. In this embodiment, the second region 48 does not have a conductive layer that constitutes an electrode.

[0114] In this embodiment, the second region 48 is disposed at the center of the external electrodes 44, 45 in the Z-axis direction, for example, on the periphery of the intermediate ceramic layer 46c. The second region 48 is configured in a strip shape (groove shape) extending along the Y-axis direction. The second region 48 is formed in a region on the end faces 41a, 41b, for example.

[0115] The first region 47 extends from the region on the end faces 41a, 41b to the regions on both main faces 41e, 41f and both side faces 41c, 41d. In this embodiment, the first region 47 is divided vertically in the Z-axis direction by the second region 48 only in the region on the end faces 41a, 41b.

[0116] Fig. 18 is an enlarged view showing a part of Fig. 17. Since the external electrodes 44 and 45 have the same configuration, the second external electrode 45 is not shown in Fig. 18.

[0117] In this embodiment, the first region 47 includes a first inner layer 471 and a first outermost layer 472 .

[0118] The first inner layer 471 is disposed on the ceramic body 41. The first inner layer 471 includes one or more layers. In this embodiment, the first inner layer 471 includes a plating base film and one or more plating films, similar to the first inner layer 171 of the first embodiment.

[0119] The first outermost layer 472 is mainly composed of tin and is disposed on the first inner layer 471. The first outermost layer 472 is configured as a tin-plated film mainly composed of tin, similar to the first outermost layer 172 of the first embodiment.

[0120] The second region 48 does not include an outermost layer primarily composed of tin, and in this embodiment, does not include an electrode layer. That is, in this embodiment, the end faces 41a and 41b of the ceramic body 41 are exposed from the second region 48. Therefore, the second region 48 has low reactivity with solder and is configured as a region that restricts wetting of the solder.

[0121] [Manufacturing method for multilayer ceramic capacitors] Fig. 19 is a flowchart showing an example of a method for manufacturing the multilayer ceramic capacitor 40. Fig. 20 is a diagram showing the manufacturing process of the multilayer ceramic capacitor 40. The method for manufacturing the multilayer ceramic capacitor 40 will be described below along Fig. 19 with appropriate reference to Fig. 20.

[0122] (Step S31: Fabricating a first ceramic body) In step S31, a first ceramic sheet S1 and a second ceramic sheet S2 for forming the first capacitance forming region 411a, and a third ceramic sheet S3 for forming the cover portion 412 and part of the intermediate ceramic layer 46c are prepared. Then, as shown in FIG. 20A, these ceramic sheets S1, S2, and S3 are stacked to produce an unsintered first ceramic body 41ua. Each of the ceramic sheets S1, S2, and S3 has the same configuration as in the first embodiment. The number of ceramic sheets S1, S2, and S3 is not limited to the example shown in FIG. 20A.

[0123] 20A, the unsintered first ceramic body 41ua is formed by alternately stacking ceramic sheets S1 and S2, and a third ceramic sheet S3 corresponding to the cover portion 412 on the first main surface 41e side is stacked on the upper surface in the Z axis direction of the unsintered first ceramic body 41ua. The third ceramic sheet S3 constituting part of the intermediate ceramic layer 46c is arranged on the lower surface in the Z axis direction of the unsintered first ceramic body 41ua. The ceramic sheets S1, S2, and S3 are pressure-bonded together to form an integrated body.

[0124] (Step S32: Fabricating a second ceramic body) In step S32, a first ceramic sheet S1 and a second ceramic sheet S2 for forming the second capacitance forming region 411b, and a third ceramic sheet S3 for forming the cover portion 412 and part of the intermediate ceramic layer 46c are prepared. Then, as shown in FIG. 20B, these ceramic sheets S1, S2, and S3 are stacked to produce an unsintered second ceramic body 41ub. Each of the ceramic sheets S1, S2, and S3 has the same configuration as in the first embodiment. The number of ceramic sheets S1, S2, and S3 is not limited to the example shown in FIG. 20B.

[0125] 20B, the unsintered second ceramic body 41ub is formed by alternately stacking ceramic sheets S1 and S2 to form a laminate, and a third ceramic sheet S3 corresponding to the cover portion 412 on the second main surface 41f side is stacked on the lower surface in the Z axis direction of the laminate. The third ceramic sheet S3 constituting part of the intermediate ceramic layer 46c is arranged on the upper surface in the Z axis direction of the laminate. The unsintered second ceramic body 41ub is integrated by pressure-bonding the ceramic sheets S1, S2, and S3.

[0126] Although the above has described the unsintered ceramic bodies 41ua and 41ub corresponding to one ceramic body 41, in reality, a laminated sheet is formed as a large, undivided sheet, and then the laminated sheet is diced into individual unsintered ceramic bodies 41ua and 41ub.

[0127] (Step S33: Applying conductive paste) In step S33, a conductive paste to serve as a plating base film is applied to cover the end faces of the unsintered first ceramic body 41ua in the X-axis direction and extend to the upper surface in the Z-axis direction and both side surfaces in the Y-axis direction. Similarly, a conductive paste to serve as a plating base film is applied to cover the end faces of the unsintered second ceramic body 41ub in the X-axis direction and extend to the lower surface in the Z-axis direction and both side surfaces in the Y-axis direction. At this time, the conductive paste is not applied to the lower surface in the Z-axis direction of the unsintered first ceramic body 41ua or the upper surface in the Z-axis direction of the unsintered second ceramic body 41ub.

[0128] (Step S34: Bonding) In step S34, the unsintered first ceramic body 41ua and the unsintered second ceramic body 41ub are bonded in the Z axis direction. For example, ceramic paste is applied to the lower surface of the unsintered first ceramic body 41ua in the Z axis direction, and the ceramic paste is brought into contact with the upper surface of the unsintered second ceramic body 41ub in the Z axis direction. This bonds the lower surface of the first ceramic body 41ua in the Z axis direction to the upper surface of the unsintered second ceramic body 41ub in the Z axis direction via the ceramic paste.

[0129] (Step S35: Firing) In step S35, the bonded unsintered first ceramic body 41ua and unsintered second ceramic body 41ub are fired to produce the ceramic body 41. As a result, a first capacitance formation region 411a is formed in the region corresponding to the first ceramic body 41ua. A second capacitance formation region 411b is formed in the region corresponding to the second ceramic body 41ub. The conductive paste is also fired to form a plating base film.

[0130] Here, an intermediate ceramic layer 46c made of a third ceramic sheet S3 and a ceramic material for bonding is formed in the center in the Z-axis direction of the ceramic body 41. A region where the plating base film is interrupted is formed along the periphery of the intermediate ceramic layer 46c in the ceramic body 41.

[0131] (Step S36: Forming external electrodes) In step S36, one or more plating films are formed on the plating base film to form the external electrodes 44, 45. Each plating film is mainly composed of copper, nickel, platinum, palladium, silver, gold, or the like, other than tin, and is formed by, for example, electrolytic plating. The plating base film and one or more plating films form the first inner layer 471. Next, a tin plating film, mainly composed of tin, is formed on the one or more plating films. This tin plating film forms the first outermost layer 472.

[0132] In this embodiment, an area where the plating base film is discontinued is formed around the periphery of the intermediate ceramic layer 46c. Therefore, the plating film formed using the plating base film as a base is not formed in the discontinued area of ​​the plating base film. This forms a second area 48 that does not include any electrode layer, such as a plating base film or a plating film.

[0133] Before step S36, the plating underlayer film on the upper side in the Z-axis direction and the plating underlayer film on the lower side in the Z-axis direction are electrically separated. Therefore, to connect these separated plating underlayer films before forming the plating film, a conductive thin film is formed, for example, in the interrupted areas of the plating underlayer film on the side surfaces 41c and 41d. The conductive thin film is formed, for example, by a sputtering method, a vapor deposition method, or the like. Since this conductive thin film also functions as a plating underlayer film, each plating film can be formed on this conductive thin film. As a result, as shown in FIG. 16, a first region 47 that is continuous along the Z-axis direction can be formed on the side surfaces 41c and 41d. The main component of the conductive thin film is not limited, but the same material as the conductive paste can be used, for example.

[0134] [Circuit board configuration] FIG. 21 is a diagram showing a circuit board 400 of this embodiment, and is a cross-sectional view corresponding to FIG.

[0135] 21, the circuit board 400 includes a first substrate (mounting substrate) 101, a multilayer ceramic capacitor 40, and solder H (component connecting portion) that connects external electrodes 44, 45 to the first substrate 101. The circuit board 100 shown in FIG. 21 further includes a second substrate 102 and a connecting member C (substrate connecting portion) that connects the first substrate 101 and the second substrate 102. The solder H is formed from the first region 47 to the second region 48 of the external electrodes 44 and 45 of the multilayer ceramic capacitor 40 .

[0136] [Effects of this embodiment] As shown in FIGS. 17 and 21 , in the multilayer ceramic capacitor 40, the second regions 48 of the external electrodes 44, 45 do not include an electrode layer. This more reliably suppresses solder wetting in the second regions 48. As a result, the solder height can be reduced, and the effective height of the multilayer ceramic capacitor 40 on the circuit board 400 can be controlled. This reduces the mounting space for the multilayer ceramic capacitor 40 and contributes to miniaturization of the circuit board 400 and the electronic device on which it is mounted. Furthermore, since the effective height of each multilayer ceramic capacitor 40 can be controlled, contact between the multilayer ceramic capacitor 40 and other structures on the circuit board 400 can be suppressed, preventing damage to the multilayer ceramic capacitor 40. Furthermore, since the height of the ceramic body 41 can be sufficiently ensured, this contributes to increasing the capacitance and improving the bias characteristics of the multilayer ceramic capacitor 40, and also ensures sufficient mechanical strength of the multilayer ceramic capacitor 40.

[0137] In addition, by configuring the second region 48 to extend in the Y-axis direction, it is possible to more effectively suppress the solder from wetting up in the Z-axis direction. Also, by arranging the second region 48 in the center of the external electrodes 44, 45 in the Z-axis direction and by having the first region 47 extend to both main surfaces 41e, 41f, it is possible to increase the degree of freedom in the mounting posture of the multilayer ceramic capacitor 40.

[0138] <Fourth embodiment> Fig. 22 is a perspective view showing a multilayer ceramic capacitor 50 in accordance with a fourth embodiment of the present invention, and Fig. 23 is a cross-sectional view taken along line EE' in Fig. 22.

[0139] The multilayer ceramic capacitor 50 includes a ceramic body 11, a first external electrode 54, and a second external electrode 55. In this embodiment, the first external electrode 54 covers the first end face 11a and extends to both principal faces 11e, 11f and both side faces 11c, 11d. In this embodiment, the second external electrode 55 covers the second end face 11b and extends to both principal faces 11e, 11f and both side faces 11c, 11d.

[0140] Fig. 24 is an enlarged view showing a part of Fig. 23. Since the external electrodes 54 and 55 have the same configuration, the second external electrode 55 is not shown in Fig. 24. Each of the external electrodes 54, 55 has a first region 57 that covers the first edge portion 11g and a second region 58 that is disposed adjacent to the first region 57 in the Z-axis direction. In this embodiment, the second region 58 is configured to be thinner than the first region 57.

[0141] In this embodiment, the second region 58 extends from the first end face 11a or the second end face 11b to the second main surface 11f. The second region 58 is disposed, for example, from the center in the Z-axis direction of the external electrodes 54, 55 to the entire lower side. On the other hand, the first region 57 extends from the first end face 11a or the second end face 11b to the first main surface 11e, and is disposed from the center in the Z-axis direction of the external electrodes 54, 55 to the entire upper side.

[0142] The first region 57 has the same layer structure as the first region 17 of the first embodiment. That is, the first region 57 includes a first inner layer 571 and a first outermost layer 572.

[0143] The first inner layer 571 is disposed on the ceramic body 11. The first inner layer 571 includes, for example, a first layer 571a disposed on the ceramic body 11 and a second layer 571b disposed on the first layer 571a. The first layer 571a includes one or more layers, for example, a plating base film and a plating film. The second layer 571b constitutes the outermost layer of the first inner layer 571 and is configured, for example, as a nickel plating film containing nickel as a main component.

[0144] The first outermost layer 572 is configured as a tin-plated film containing tin as a main component, and is disposed on the first inner layer 571 .

[0145] The second region 58 also has a layer structure similar to that of the second region 18 of the first embodiment. That is, the second region 58 includes a second inner layer 581 disposed on the ceramic body 11 and a second outermost layer 582 disposed on the second inner layer 581.

[0146] The second inner layer 581 has, for example, a layer structure similar to that of the first layer 571a of the first region 57. That is, the second inner layer 581 includes one or more layers, and in this embodiment, includes a plating base film disposed on the ceramic body 11 and a plating film disposed on the plating base film.

[0147] Second outermost layer 582 is configured as a plating film not containing tin as a main component, and is formed continuously with second layer 571b of first inner layer 571. Second outermost layer 582 is configured as a nickel plating film containing nickel as a main component, for example.

[0148] The external electrodes 54, 55 are formed, for example, as follows. First, a plating underlayer and a plating film are formed to cover the end faces 11a, 11b and extend to both main faces 11e, 11f and both side faces 11c, 11d. The plating underlayer and plating film constitute a first inner layer 571 of the first region 57, and a second inner layer 581 and a second outermost layer 582 of the second region 58. Then, a process is performed to prevent the formation of a tin plating film on the second outermost layer 582 of the plating film. Then, a tin plating film corresponding to the first outermost layer 572 of the first region 57 is formed on the first inner layer 571. This completes the first outermost layer 572 of the first region 57.

[0149] FIG. 25 is a diagram showing a circuit board 500 of this embodiment, and is a cross-sectional view corresponding to FIG.

[0150] 25, the circuit board 500 includes a first substrate (mounting substrate) 101, a multilayer ceramic capacitor 50, and solder H (component connecting portion) that connects the external electrodes 54, 55 to the first substrate 101. The circuit board 500 shown in FIG. 25 further includes a second substrate 102 and a connecting member C (substrate connecting portion) that connects the first substrate 101 and the second substrate 102. The solder H is formed from a first region 57 to a second region 58 of the external electrodes 54, 55 of the multilayer ceramic capacitor 50.

[0151] [Effects of this embodiment] As shown in FIG. 25 , the external electrodes 54, 55 have the second regions 58, which restricts the wetting of the solder on the external electrodes 54, 55. This reduces the solder height and restricts the substantial height of the multilayer ceramic capacitor 50 on the circuit board 500. This reduces the mounting space for the multilayer ceramic capacitor 50 and contributes to the miniaturization of the circuit board 500 and the electronic device on which it is mounted. Furthermore, restricting the substantial height of each multilayer ceramic capacitor 50 reduces contact between the multilayer ceramic capacitor 50 and other structures on the circuit board 500, preventing damage to the multilayer ceramic capacitor 50. Furthermore, since the height of the ceramic body 11 can be sufficiently secured, this contributes to increasing the capacitance and improving the bias characteristics of the multilayer ceramic capacitor 50 and also ensures sufficient mechanical strength of the multilayer ceramic capacitor 50.

[0152] Additionally, in this embodiment, the second region 58 extends from the first end face 11a or the second end face 11b to the second main surface 11f. This more reliably prevents the solder from reaching the region on the second main surface 11f. This more reliably prevents the solder height from becoming larger than the component height.

[0153] Fifth Embodiment 26 is a side view of the multilayer ceramic capacitor 60 in accordance with the fifth embodiment of the present invention as viewed from the X-axis direction. In this embodiment, an example of the arrangement of the second regions will be described.

[0154] The multilayer ceramic capacitor 60 includes a ceramic body 11, a first external electrode 64, and a second external electrode 65 configured similarly to the first external electrode 64. The external electrodes 64, 65 of this embodiment have a first region 67 that covers the first ridge portion 11g, and a second region 68 that is disposed adjacent to the first region 67 in the Z-axis direction. Note that the second region 68 in FIG. 26 is shown with diagonal hatching for ease of explanation.

[0155] As shown in FIG. 26A, the second region 68 may extend over a portion of the external electrodes 64, 65 in the Y-axis direction, for example. 26B and 26C, a plurality of second regions 68 may be arranged spaced apart in the Y-axis direction. In this case, the second regions 68 may be configured in a strip shape extending in the Y-axis direction as shown in Fig. 26B, or may have a planar shape such as a dot shape as shown in Fig. 26C.

[0156] The multilayer ceramic capacitor 60 can also be mounted on a circuit board similar to that of the first embodiment, for example.

[0157] These second regions 68 also restrict the wetting up of the solder on the external electrodes 64, 65. This reduces the solder height, and restricts the effective height of the multilayer ceramic capacitor 60 on the circuit board. This reduces the mounting space for the multilayer ceramic capacitor 60 and contributes to the miniaturization of the circuit board and the electronic device in which it is mounted. It also prevents the multilayer ceramic capacitor 60 from being damaged by the structure of the circuit board. Furthermore, since the height of the ceramic body 11 can be sufficiently secured, this contributes to the increase in capacitance and improvement of the bias characteristics of the multilayer ceramic capacitor 60, and also ensures sufficient mechanical strength of the multilayer ceramic capacitor 60.

[0158] Sixth Embodiment [Circuit board configuration] 27 is a cross-sectional view showing a circuit board 700 according to a sixth embodiment of the present invention. The circuit board 700 of this embodiment further includes a frame-shaped core substrate between the first substrate 101 and the second substrate 702.

[0159] 27, the circuit board 700 includes a first substrate (first mounting substrate) 101, two multilayer ceramic capacitors 10, and solder H (component connection portion) that connects the external electrodes 14, 15 to the first substrate 101. The circuit board 700 shown in FIG. 27 further includes a second substrate (second mounting substrate) 702, a third substrate 703, and connection members D (substrate connection portions) that respectively connect the first substrate 101 and the third substrate 703, and the second substrate 702 and the third substrate 703.

[0160] One of the multilayer ceramic capacitors 10 is mounted on the first substrate 101. The first substrate 101 includes a substrate body 103 including a first mounting surface 103a facing the Z-axis direction, component mounting lands 104 arranged on the mounting surface 103a, substrate connection lands 105 arranged on the mounting surface 103a, and a solder resist 106 arranged around the lands 104 and 105 on the mounting surface 103a. A circuit (not shown) is formed on the substrate body 103.

[0161] The second substrate 702 mounts the other multilayer ceramic capacitor 10. The second substrate 702 includes a substrate main body 707 including a second mounting surface 707a facing the first mounting surface 103a in the Z-axis direction, component mounting lands 708 arranged on the second mounting surface 707a, substrate connection lands 709 arranged on the second mounting surface 707a, and a solder resist 710 arranged around these lands 708 and 709 on the second mounting surface 707a. A circuit (not shown) is formed on the substrate main body 707.

[0162] The third substrate 703 is disposed between the first substrate 101 and the second substrate 702, and is configured as a core substrate having a space for accommodating components. The third substrate 703 includes a frame-shaped substrate main body 711 and through-holes 712 formed to penetrate the substrate main body 711 in the Z-axis direction. A conductive material such as copper is embedded in the through-holes 712. A plurality of through-holes 712 are disposed, for example, along the sidewall of the substrate main body 711.

[0163] The connection member D connects the through-hole 712 of the third substrate 703 to the substrate connection land 105 of the first substrate 101 and the substrate connection land 709 of the second substrate 702. The connection member D is formed of, for example, solder.

[0164] Of the two multilayer ceramic capacitors 10, one multilayer ceramic capacitor 10 is mounted on a component mounting land 104 of the first substrate 101 via solder H. The other multilayer ceramic capacitor 10 is mounted on a component mounting land 708 of the second substrate 702 via solder H.

[0165] During the manufacture of such a circuit board 700, solder paste is applied to the component mounting lands 104 of the first substrate 101 and the component mounting lands 708 of the second substrate 702, and the multilayer ceramic capacitor 10 is placed on the solder paste. The solder paste is then heated and melted. At this time, the solder paste wets and rises on the external electrodes 14, 15 in the Z-axis direction, forming solder H. The solder H is formed from the first region 17 to the second region 18 of the external electrodes 14, 15 of the multilayer ceramic capacitor 10.

[0166] [Effects of this embodiment] In this embodiment, the external electrodes 14, 15 also have the second regions 18, which limits the wetting of the solder on the external electrodes 14, 15. This reduces the solder height and limits the effective height of the multilayer ceramic capacitor 10 on the circuit board 700. This reduces the mounting space for the multilayer ceramic capacitor 10 and contributes to the miniaturization of the circuit board 700 and the electronic device on which it is mounted. Furthermore, limiting the effective height of each multilayer ceramic capacitor 10 prevents contact between the two multilayer ceramic capacitors 10 and between them and other structures, thereby preventing damage to the multilayer ceramic capacitors 10. Furthermore, ensuring a sufficient height of the ceramic body 11 contributes to increasing the capacitance and improving the bias characteristics of the multilayer ceramic capacitor 10 and ensuring sufficient mechanical strength of the multilayer ceramic capacitor 10.

[0167] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention can be implemented as an embodiment in which the various embodiments are combined.

[0168] The layers of the first and second regions are not limited to the above examples. For example, the first region may include a first outermost layer primarily made of tin, and may include one or more optional conductive layers below the first outermost layer. The second region may not include an outermost layer primarily made of tin, and if the second region includes a conductive layer, it may include one or more optional conductive layers.

[0169] The arrangement of the second region is not limited to the aspects described in the above embodiments as long as it is adjacent to the first region in the Z-axis direction on the end surface. For example, the second region does not have to be arranged in the center of the external electrode in the Z-axis direction, but may be arranged near the first edge or the second edge.

[0170] Furthermore, the external electrodes only need to extend from the end faces to at least the first main surface, and may not extend to the second main surface.

[0171] The multilayer ceramic capacitor 10 does not have to be low-profile, and the shape and size of the multilayer ceramic capacitor 10 are not limited to the above-mentioned examples.

[0172] Although the above embodiment has described a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component, the present invention is applicable to any multilayer ceramic electronic component having a pair of external electrodes, such as a chip varistor, a chip thermistor, or a multilayer inductor. [Explanation of symbols]

[0173] 10, 30, 40, 50, 60... Multilayer ceramic capacitors (multilayer ceramic electronic components) 11,41...Ceramic body 11a, 41a...first end surface 11b, 41b…Second end surface 11e, 41e...First principal surface 11f, 41f...Second main surface 12...First internal electrode 13…Second internal electrode 14,34,44,54,64...1st external electrode 15,35,45,55,65…Second external electrode 17,37,47,57,67…1st area 172,372,472,572…First outermost layer 18,38,48,58,68…Second area 182,383,582…Second outermost layer 100, 300, 400, 500, 700... Circuit board

Claims

1. a first circuit board and a second circuit board whose mounting surfaces face each other; a ceramic body having first and second main surfaces facing the first axial direction, a first end surface facing a second axial direction orthogonal to the first axis, and from which the first internal electrodes are extended, a second end surface facing the second axial direction, and from which the second internal electrodes are extended, and a side surface facing a third axial direction orthogonal to the first axis and the second axis; a first external electrode covering the first end surface and extending to the first main surface and the side surface; and a second external electrode covering the second end surface and extending to the first main surface and the side surface. a component connection portion formed of solder, which connects the first external electrode and the second external electrode to the mounting surface of the first circuit board so that the first main surface faces the mounting surface of the first circuit board; a substrate connection portion configured by solder and having a dimension in the first axis direction larger than a dimension of the multilayer ceramic electronic component, connecting the mounting surface of the first circuit board and the mounting surface of the second circuit board; Equipped with Each of the first external electrode and the second external electrode is a first region extending from the first end face or the second end face to the first main surface and the side surface and electrically connected to the first internal electrode or the second internal electrode of the first capacitance formation region and the second capacitance formation region, respectively; the intermediate ceramic layer in the first end face or the second end face of the ceramic body is exposed so as to divide the first region on the first end face or the second end face along the third axis direction into a portion covering the first capacitance formation region and a portion covering the second capacitance formation region, and a second region is disposed on the first end face or the second end face adjacent to the first region in the first axial direction, the first region includes an outermost layer having a main component that reacts more easily with the solder of the component connection portion than the second region; a dimension of the component connection portion in the first axis direction is smaller than a dimension of the multilayer ceramic electronic component; a gap is provided between the first external electrode and the second external electrode and the mounting surface of the second circuit board; electronic equipment.

2. 10. The electronic device according to claim 1, The component connection portion in the first axial direction covers the first region and does not cover the second region. electronic equipment.

3. 3. The electronic device according to claim 1, a dimension of the component connection portion in the first axial direction substantially equal to a dimension of the first region; electronic equipment.

4. 4. The electronic device according to claim 1, The second region extends along the third axis direction on the first end surface or the second end surface. electronic equipment.

5. 5. The electronic device according to claim 1, the first external electrode covers the first end surface and extends to the first main surface and the second main surface; the second external electrode covers the second end surface and extends to the first main surface and the second main surface; the second region is disposed at a central portion of each of the first external electrode and the second external electrode in the first axis direction, The first region extends from the first end surface and the second end surface to the first main surface and the second main surface. electronic equipment.

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