Method for measuring temperature or thermal resistance and monitoring thermal resistance

Abstract

A method for measuring a temperature in a power electronic system comprising at least one power unit PU comprising at least one semiconductor switch S having a die connected to a heat sink HS 5 via a stack of m material layers Mi, i=1, 2, ..., m, said at least one semiconductor switch being thermally connected in parallel to a heat source 10 via a connection layer Mj of the material layers Mi of the stack, the method comprising providing a limited current to said at least one semiconductor switch S when said at least one semiconductor switch is in an open state such that it does not dissipate heat, said limited current being adapted to measure a first temperature T1 of said at least one semiconductor switch using a thermal sensitive parameter of said at least one semiconductor switch in said open state, and measuring a temperature T1 of said connection layer Mj as equal to said first temperature T1. Mj and calculating

Description

[Technical Field]

[0001] The present disclosure relates to the field of power electronic systems having power semiconductors, more precisely power switching semiconductors, and to a method for monitoring thermal resistance in such power electronic systems. [Background technology]

[0002] To achieve higher current densities in power modules, instead of increasing the die area of ​​such modules, multi-die power module architectures are increasingly being adopted, in which multiple semiconductor dies are electrically connected in parallel to perform the same function as a single switch. In conventional technology, the lifetime of power modules is limited by semiconductor junction temperature swings during mission profiles. Traditional wear mechanisms arise from a combination of thermal cycling and mismatched coefficients of thermal expansion (CTE), which create mechanical stresses between different layers of the power module. These mechanical deformations and excessive strains at the interfaces of different materials can lead to degradation or even failure of the power module due to crack and / or void formation. Additionally, degradation of layers between the semiconductor and the cooling system, such as a heat sink, can increase thermal resistance, thereby increasing the amplitude of temperature swings under a given load condition. The most significant failure mechanism is associated with the electrical interconnection package closest to the semiconductor die, specifically bond wire lift-off and die-attach degradation due to delamination between layers of Sn-based solder or Ag-based sintered layers. References discussing such issues include, for example, Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3.

[0003] In this context, there is a high level of technological interest in monitoring the health status of these layers and assessing the remaining lifespan of power modules before actual module failure occurs. In particular, online condition monitoring of the die attach layer is an important technology for monitoring the degradation level, avoiding failures, planning maintenance, and developing strategies to extend the lifespan of power modules based on this monitoring.

[0004] There are several test methods, such as Patent Document 1 which discloses a junction-case thermal resistance test method, Patent Document 2 which relates to a method for measuring the thermal resistance of a semiconductor device, Patent Document 3 which relates to a method and apparatus for evaluating the thermal impedance of a packaged semiconductor component, Patent Document 4 which relates to a method and apparatus for predicting junction temperature for use in a power conversion module, and Patent Document 5 which provides a method and system for calculating the transient state junction temperature of an IGBT module.

[0005] The thermal impedance is Zth j-ref =(T(t)-T ref ) / Pdiss, where Pdiss is the change in dissipated power, T(t) is the temperature response of the device to this power change, and Tref is a reference temperature, e.g., the heat sink temperature THS, or the cooling fluid temperature TCF, or the cooling means temperature TCM. The thermal resistance is Rth j-ref =lim(Zth)(t->∞).

[0006] In the prior art, the degradation level of the packaging layers is measured and monitored using various techniques based on thermal impedance measurements: Thermistors are calibrated temperature-sensitive electrical resistors typically built into conventional power modules, thermally connected to the ceramic insulating plate of the semiconductor die and electrically connected to the terminals of the power module. These devices allow the temperature of the ceramic plate to be monitored over the life of the module. By monitoring the temperature transition at the device's location, the change in thermal impedance between the heat sink and the module can be monitored. The temperature of the semiconductor die is measured during operation of such semiconductors using multiple thermal sensitive electrical parameters (TSEPs). TSEPs are electrical parameters of the semiconductor that are temperature sensitive, can be calibrated, and can provide information about the temperature of the semiconductor. Therefore, if the power dissipated in the semiconductor, Pdiss, is known, the thermal resistance information between the semiconductor and the heat sink can be extracted over the lifetime of the module. Thermal impedance measurement, a transient thermal response technique, can provide information about the degradation of different interfaces in a power module. This thermal impedance measurement technique typically consists of: First, a semiconductor switch is used as the active device to apply a starting steady-state thermal condition to the power module, which can be either a zero power condition or a condition where a recorded constant power is dissipated in the semiconductor. Second, a controlled power step increase (if the starting condition is a zero power condition) or power step decrease (if the starting condition is a constant power condition) is applied and the power change is recorded, followed by the semiconductor temperature progression until a new steady state thermal condition is reached. Finally, the recorded temperature transient behavior is represented by using an equivalent Foster or Cauer network that represents the thermal structure of the power module with multiple RC elements. By fitting the temperature transient using the Foster equation, the resistance and capacitance of different parts of the power module can be extracted, providing information on the evolution of the thermal resistance and capacitance.

[0007] These techniques are particularly sensitive to solder adhesion and degradation of the different layers that make up the power module.Typically, thermal impedance measurements are primarily performed in offline conditions by mounting the device on a measurement test bench, controlling the load, measuring the power dissipated in the device, and measuring the temperature transients with dedicated sensors.

[0008] Several experiments have been reported in the literature demonstrating a clear correlation of solder layer degradation with the evolution of thermal transient behavior after power cycling of power modules.

[0009] Available transient thermal techniques (e.g., thermal impedance, ZTH) are difficult to implement in the online operation of power modules because it remains difficult to measure the cooling / heating transient temperature during the operation of power devices with sufficiently high data acquisition rates, especially for multi-chip power modules where current is shared between different parallel-interconnected dies, and because measuring the thermal impedance requires controlled knowledge of the dissipated power of each device.

[0010] Available online TSEP monitoring technology allows for real-time monitoring of the semiconductor die temperature, and if similar power dissipation conditions can be reproduced during the measurement, the semiconductor and heat sink Rth j-HS However, an increase in the thermal resistance between Rth j-HS Knowing the σ cannot distinguish which layer or interface is most degraded in the package stack.

[0011] The thermistor is typically thermally connected to an intermediate layer of the power module package stack, typically a ceramic insulating plate, and can monitor its evolution along with that of the semiconductor die thermally connected to the same ceramic insulating plate, i.e., along with that of the direct bonded copper (DBC) ceramic substrate, which corresponds to the direct mating of copper and ceramic, in principle to determine the thermal resistance Rth of the junction. j-DBC is the most deteriorated, or the thermal resistance Rth between the junction and the heat sink DBC-HSHowever, integrating a thermistor implies additional manufacturing costs, requires additional external leads, and requires additional ceramic insulating plate area, which generally increases the cost, volume, and weight of the power module. Therefore, typically, only one thermistor is integrated on a power module, and the temperature measured by it represents only the temperature of the nearest semiconductor chip. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] China Patent Publication No. 103175861 [Patent Document 2] China Patent Publication No. 103792476 [Patent Document 3] European Patent No. 0708327 [Patent Document 4] U.S. Patent No. 7,356,441 [Patent Document 5] China Patent Publication No. 107219016 [Non-patent literature]

[0013] [Non-Patent Document 1] N. Degrenne, J. Ewanchuk, E. David, R. Boldyrjew and S. Mollov, “A Review of Prognostics and Health Management for Power,” Annual Conference of the Prognostics and Health Management Society, (2015) 1-11 [Non-patent document 2] Mauro Ciappa, “Selected failure mechanisms of modern power modules,” Microelectronics Reliability, 42 (2002) 653-667 [Non-patent document 3] PY. Pichon and J. Brandelero, “Relative importance of solder and wire bond defects on the maxi-mum junction temperature of IGBT devices,” Microelectronics Reliability, 126 (2021) 114250 Summary of the Invention [Problem to be solved by the invention]

[0014] In view of this prior art, the present disclosure proposes using individual control of semiconductor switches in a power module to provide an open state configuration for such switches where TSEP measurements are performed to obtain temperature measurements. This is done for modules having one or more semiconductor switches and each die in a multi-chip power module to detect degraded portions of the power module. This allows for determining which portions of equipment using such modules are in a degraded state and for better maintenance planning. [Means for solving the problem]

[0015] More precisely, the present disclosure relates to a method for measuring a temperature or a thermal resistance in a power electronic system comprising at least a first power unit and a heat source thermally connected to a cooling means via a connection layer, the method comprising providing a limited current to the first power unit while the first power unit is in an open state such that it does not dissipate heat, the limited current not allowing the first power unit to be in a power conducting state, measuring a temperature T1 of the first power unit using a thermal sensitive electrical parameter TSEP of the first power unit, and determining a temperature T1 of the connection layer since the first power unit in an open state does not generate heat. CL as equal to such first temperature T1.

[0016] This method provides a simple way to obtain a measurement of the connecting layer temperature without the need for a thermistor.

[0017] The heat source can be a second power unit or any heating element.

[0018] The method is carried out by determining the temperature T CM and measuring the temperature difference T1-T between the connection layer and the cooling means. CM and calculating:

[0019] This makes it possible to obtain information about the thermal resistance between the connection layer and the cooling means.

[0020] If the heat source is a second power unit, the method includes measuring a temperature T2 of the second power unit using a TSEP of the second power unit; Difference T1-T CM The difference T2-T CM Compare with The thermal resistance R between the second power unit and the connection layer 2-CL The thermal resistance R between the connection layer and the cooling means can be calculated as follows: CL-CM To compare with T1=T CLTherefore, R 2-CL / R CL-CM =(T CL -T CM ) / (T2-T CL )=(T1-T CM ) / (T2-T1), such calculation being independent of Q, where Q is the heat flow value applied between the second power unit and the connection layer; It may further include:

[0021] This provides information on the thermal resistance of the layer without the need for any other sensors than those on the cooling means.

[0022] The first power unit and the second power unit may be semiconductor switches thermally connected to the connection layer via a first stack of material layers, and the cooling means may be a heat sink, and the connection layer is thermally connected to the heat sink via a second stack of material layers.

[0023] The first power unit and the second power unit may be semiconductor switches, and the connection layer is a ceramic layer, such as a direct-bonded copper ceramic layer or an active metal brazing layer, attached directly to the heat sink or attached to the heat sink via a base plate BP.

[0024] The first power unit may be a first half-bridge power unit including a first upper switch and a first lower switch, the first upper switch and the first lower switch having dies attached to a first ceramic layer, such as a direct bonded copper ceramic layer or an active metal braze layer, via a first die attach layer; the second electronic unit may be a second half-bridge power unit including a second upper switch and a second lower switch, the upper switch and the lower switch having dies attached to a second direct bonded copper ceramic layer via a second die attach layer, the first direct bonded copper ceramic layer and the second direct bonded copper ceramic layer being attached to a common heat sink via a solder layer and a baseplate layer; and the method includes turning off both the first upper switch and the first lower switch of the first half-bridge power unit while the second upper switch and the second lower switch of the second half-bridge power unit are active; measuring a temperature T2 of a second upper switch by a TSEP of the second upper switch; and measuring a temperature T1 of a first upper switch or a first lower switch by a TSEP of the first upper switch or the first lower switch by providing a limited current to the first upper switch or the first lower switch, the limited current not allowing the first upper switch unit to be in a power conducting state; and determining a temperature difference R between the second upper switch and the base plate, assuming that the temperature of the base plate is equal to the temperature T1. 2-BP =T2-T BP =T2-T1 and Heat sink temperature T HS Then, the ratio r2 = (T2 - T BP ) / (T BP -T HS ) and comparing the thermal resistance of the second die attach layer, the second DBC layer, and the solder layer with the thermal resistance between the base plate and the heat sink; Includes.

[0025] Measurements can be completed for all power units with each power unit being turned off in turn while the other power units remain active.

[0026] The power electronics system may include two or more half-bridge power units, one of which may be turned off to provide baseplate temperature measurements while thermal resistance and thermal resistance ratio measurements are made on the other of the half-bridges, each of which is turned off in turn while the other half-bridge is active to provide a complete test of the half-bridges of the power electronics system.

[0027] The power electronics system may include a first power module having a first pair of half bridges, each having an upper switch and a lower switch and a DBC layer connected to a first base plate, and a second power module having a second pair of half bridges, each having an upper switch and a lower switch and a DBC layer connected to a second base plate, the first base plate and the second base plate being attached via a thermal contact material to a heat sink in contact with a cooling fluid, the power electronics system further including an independent gate driver circuit for each of the switches, and the method includes measuring a thermal resistance R between the upper switch or the lower switch of the first power module and the heat sink. PU1-HS and the thermal resistance between the heat sink and the cooling fluid, R HS-CF and measuring the thermal resistance by All devices in the second power module are left open and the TSEP temperature measurements of one or a combination of the switches in the second power module are used to determine the temperature T of the heat sink interface. HS While the switching function of the power electronics system is performed by the switches of the first power module, the temperature T2 of at least one of the devices of the first power module is measured through the TSEP, and the temperature T of the cooling fluid is measured. CFmeasuring Ratio r3=(T2-T HS ) / (T HS -T CF ) to compare the thermal resistance of the first power module, the first base plate, and the first thermal contact material with the thermal resistance between the heat sink contact surface and the cooling fluid, the method further comprising performing the same step with the switch of the first power module in an open state while a switching function of the power electronics system is performed by the switch of the second power module; and comparing by

[0028] By combining switch-level, power unit-level and module-level methods, thermal resistance ratio measurements can be obtained at multiple levels in the stack of modules on heat sinks and cooling fluids.

[0029] The first power unit may be in the open state during temperature or thermal resistance measurements.

[0030] This allows the measurement sequence to be scheduled.

[0031] The present disclosure also relates to a method for monitoring the thermal resistance of an electric power unit of a power electronics system, the method comprising obtaining an initial thermal resistance of such electric power unit by the disclosed method, storing the initial thermal resistance and a ratio between the initial thermal resistance between the electric power unit and a connection layer of such electric power unit and the thermal resistance between the connection layer and a cooling means, repeating the method during the life of the power electronics system to obtain further thermal resistances and further ratios, and comparing the further thermal resistances and the further ratios with the initial thermal resistance and the initial ratio to detect changes in the thermal resistances and ratios.

[0032] The method of monitoring may include comparing the change in thermal resistance to a predetermined threshold and issuing an alarm if the value of the thermal resistance or the ratio exceeds the threshold.

[0033] The method comprises: The temperature Tj of at least one semiconductor device j of a power electronics system, such as a power converter, is measured over a time interval t sampling and storing the data in memory; integration time t averaging is at least a significant portion of the thermal constants of the power converter, over a time interval t eval At least the average temperature T of semiconductor j mean,j and standard deviation σ mean,j periodically calculating At least, condition T mean,j >C1×T HS and σ mean,j <C2×(T mean,j -T HS ) is observed, wherein C1 is a constant greater than 1 and C2 is a constant less than 1; may include: C1 can be in the range of 1.1 to 5. C2 is a constant between 0.2 and 0.05, and the condition σmean,j <C2*(Tmean,j-T HS ) is a condition that detects the steady-state nature of operation by comparing the standard deviation of the temperature samples to the average temperature difference between the semiconductor and the heat sink during the sampling period.

[0034] Time interval t sampling is a multiple of the inverse of the switching frequency of the power converter, i.e., t sampling =n / f PWM It could be.

[0035] temperature T mean,j can be calculated using the arithmetic mean or median of the data samples Tnj,...,Tjm.

[0036] integration time t averaging may be greater than the thermal constants of the power electronics system.

[0037] Time interval t eval is t averaging The time interval may be longer than

[0038] The switches of the power unit PUx may be controlled independently of each other, where x=1 to n, and n is the total number of switches, and the method comprises measuring a coupling impedance between the power unit PUi and the power unit PUj (i≠j), the measurement comprising: 1 / turning off all switches of the power unit PUj and keeping the switches of the power unit PUi active; 2 / Measuring the temperatures Tx of all power units PUx; 3 / Heat sink temperature T HS and measuring 4 / Temperature difference ΔTx=Tx-T HS and 5 / Comparing ΔTi with ΔTx, e.g., to detect changes in thermal coupling resistance; The method may include performing the method by a sequence including:

[0039] The sequence may be repeated multiple times during the life of the product.

[0040] The method may include measuring the power dissipated in a power unit PUi using an electrical model Pi (IL, Vbus, fPWM, Ti, α...) of such power unit, where IL is the measured load power, Ti is the measured temperature of the power unit PUi, Vbus is the known or measured bus voltage of the power unit PUi, fPWM is the switching frequency of such power unit, and α is the duty cycle of such power unit, and calculating a coupling resistance as ΔTx / Pi.

[0041] The present disclosure also relates to software including instructions that, when executed in a controller of the power system, implement the method, and to a computer-readable non-volatile medium having the software recorded thereon.

[0042] A detailed description of exemplary embodiments of the present invention is discussed below with reference to the accompanying drawings. [Brief explanation of the drawings]

[0043] [Figure 1] FIG. 1 is a schematic diagram of one embodiment of a power electronics system having a power unit with one semiconductor die adapted to the process of the present disclosure. [Figure 2] FIG. 1 is a schematic diagram of one embodiment of a power electronics system having one power unit with two semiconductor dies adapted for the process of the present disclosure. [Figure 3] FIG. 1 is a schematic diagram of one embodiment of a power electronics system having two power units, each unit having a pair of semiconductor switch dies on a single DBC substrate, adapted for the processes of the present disclosure. [Figure 4] FIG. 4 is a diagram showing an electrical circuit of the power electronics system of FIG. 3. [Figure 5] FIG. 1 is a schematic diagram of one embodiment of a power electronics system having three power units, each having a pair of semiconductor switch dies on a single DBC substrate, adapted for the processes of the present disclosure. [Figure 6] FIG. 6 is a diagram showing an electrical circuit of the power electronics system of FIG. 5. [Figure 7] FIG. 1 is a schematic diagram of one embodiment of a power electronics system having two power units, each having four semiconductor dies, adapted for the process of the present disclosure. [Figure 8] FIG. 8 is a diagram showing an electrical circuit of the power electronics system of FIG. 7. [Figure 9A] 1 is a flowchart of an example embodiment of method steps. [Figure 9B]1 is a flowchart of an example embodiment of method steps. [Figure 9C] 1 is a flowchart of an example embodiment of method steps. [Figure 9D] 1 is a flowchart of an example embodiment of method steps. [Figure 10] 1 is an exemplary general flow chart. DETAILED DESCRIPTION OF THE INVENTION

[0044] The disclosed method for measuring temperature in a power electronic system allows for multiple measurements depending on the type of system. In Fig. 1, a power unit PU comprises a semiconductor switch having a die 1a connected to a heat sink HS5 via a stack of m material layers Mi (i = 1, 2, ..., m). In this stack, layers M1 to Mj-1 are arranged between the die 1a and a layer Mj, which may be a DBC layer. The semiconductor switch measures the temperature T via such layer Mj-3, which forms the connection layer Mj of the material layer Mi of the stack. SRC The heat source 10 is thermally connected in parallel to the heat source 10.

[0045] Below the layer Mj there is a further stack 4 of layers Mj+1 to Mm, the layer Mm being connected to a heat sink HS 5.

[0046] The method includes providing a limiting current to the at least one semiconductor switch 1a in the open state, the limiting current being adapted to measure a first temperature T1 of the at least one semiconductor switch using a thermal sensitive parameter (TSEP) of the at least one semiconductor switch in the open state.

[0047] In such a situation, the temperature of the semiconductor switch that does not dissipate heat is close to or equal to the temperature of the DBC layer Mj 3. Then, the temperature T Mj can be calculated as being equal to the first temperature T1 obtained by the TSEP measurement.

[0048] The TSEP measurement can use parameters such as gate resistance or other parameters that can be measured using the existing electrical measurement features of the power unit.

[0049] Conventional semiconductor switches typically have a V of about -8V. GE It is blocked by a voltage of approximately +15V. GE They can conduct voltage and drive currents of tens or hundreds of amperes.

[0050] In the present application, the measurement of T1 by the TSEP parameter is performed using a current source to inject a small current, e.g., a pulse of tens of milliamps, e.g., 25 mA, at the gate-emitter junction for a duration of less than tens of microseconds, thereby measuring the gate / emitter resistance of the semiconductor. With such a small current injection, the VGE voltage of the semiconductor does not rise sufficiently to allow the switch to conduct.

[0051] By using the measurement of the internal gate resistance Rg1 of at least one semiconductor of the switch of PU1, any additional external sensor measuring the junction temperature T1 can be avoided. Thus, the temperature of layer Mj can be determined using only the control terminals of the power electronics system PS.

[0052] The temperature T1 of S1 is measured using a calibration curve using the gate resistance Rg1 of S1. For example, the calibration curve relates T1 to the gate resistance of switch S1 as follows: T1=δR1*Rg1+R01

[0053] The semiconductor switches may be semiconductor switches such as silicon, silicon carbide, or GaAs semiconductors in a silicon insulated gate bipolar transistor (IGBT) or MOSFET configuration.

[0054] The general principle of the present disclosure is that the switch of the power unit PU is intentionally left open so that its temperature can be measured and therefore advantageously used as a temperature sensor to measure the temperature of the layer Mj. The semiconductor switch therefore performs the additional function of being a temperature sensor for the layer Mj.

[0055] 1, the heat source 10 can be any system that generates heat losses and has a thermal connection to the layer Mj, such that the temperature of Mj differs from the temperature of the heat sink, even if the power unit PU does not generate losses. For example, the heat source can be a resistance exposed to an electric current, a mechanical system that generates losses through friction, an inductance exposed to a magnetic flux, a thermal radiation source that changes the temperature of Mj, or any source that has a radiative, convective, inductive or conductive thermal connection to the layer Mj.

[0056] To enable such measurement, the method may include maintaining the semiconductor switch 1 a in an open state that does not dissipate heat, or detecting that the semiconductor switch is in the open state. In one example, the power unit may be thermally connected to the motor body, does not transfer energy, and is used to monitor the temperature of the motor body.

[0057] If the measurement is made while the switch is open, the primary electrical function of the semiconductor switch is not affected because the switch is not active and does not transfer energy. The additional function of measuring temperature is only performed when the switch is not delivering power.

[0058] The disclosed method is adapted to power modules in which the material structure above the semiconductor die 1a does not dissipate as much heat as compared to the stack of layers between the semiconductor switch die 1a and the connecting layer Mj 3. Thus, advantageously, even if there is poor thermal contact between the semiconductor switch die 1a and the layer Mj (e.g., due to degraded thermal contact), the temperature T of the material Mj at a location below such die 1a can be reduced. Mjis sufficiently close to the temperature of semiconductor die 1a, so that these temperatures can be approximated as being the same. For example, the thermal resistance between the top of semiconductor die 1a and the heat sink is more than five times, usually more than ten times, and often more than twenty times, the thermal resistance between semiconductor die 1a and Mj. In one example, only a small surface area of ​​the top surface of semiconductor die 1a is connected to the heat sink via metal, e.g., this contact area is less than 10%, or less than 5%, and this area is minimized to provide only sufficient electrical connection of the top surface, e.g., wire connection to a terminal. In another example, a large portion of the top surface area of ​​the semiconductor die 1a, typically 90% to 95%, is covered with a thermally insulating material, such as an epoxy-based potting compound of a silicone gel compound, having a thermal conductivity of less than 2 W / (mK) (most thermally conductive epoxies have a thermal conductivity in the range of 1 W / (mK) to 1.6 W / (mK)], or preferably less than 1 W / (mK), which provides very limited losses in terms of heat transfer between the die and layer Mj.

[0059] In such a case, the temperature T SRC Assuming that a heat source having a temperature of 10 is in contact with the layer Mj, a semiconductor switch can be used as a temperature sensor for the heat source 10. T1=T Mj =T src or T src Close to.

[0060] In Figure 2, the power electronics system is a power unit PU1 comprising two semiconductor switches each having a die 1a, 2a connected to a heat sink HS 5 via a similar stack of m material layers Mi (i = 1, 2, ..., m). The two semiconductor switches are thermally connected in parallel via a connecting layer Mj 3 of the stack.

[0061] In such a case, each of the two semiconductor switches can form a corresponding heat source and can be used alternately to measure temperature using the methods disclosed herein.

[0062] In such a situation, the method shown in FIG. maintaining a first semiconductor switch of the two semiconductor switches, for example, switch S1 on die 1a, in an open state so that it does not dissipate heat, or detecting that the first semiconductor switch of the two semiconductor switches is in the open state while at least a second switch S2 on die 2a is in a conducting state to form the heat source 100, then injecting a gate current into the gate of semiconductor S1 and measuring a first temperature T1 of die 1a of the first switch S1 using a thermal sensitive parameter of the first semiconductor switch (110); Since the first switch S1 does not generate heat, the temperature T CL as equal to such first temperature T1; In step 120, the temperature T of the heat sink of the power electronics system HS and measuring Difference T1-T HS The difference T2-T HS To compare with In such a condition, the method may include measuring the temperature T2 of the die 2a of the second switch S2 in the conducting state, preferably also using the TSEP parameter of the second switch S2 (130); a thermal resistance R between the die of the second semiconductor switch S2 of the at least two semiconductor switches and the layer Mj; S2,Mj is calculated as the thermal resistance R between Mj and the heat sink by the calculation in step 140 below. Mj,HS To compare with R S2,Mj =Q / (T2-T Mj,S2 ) R Mj,HS =Q / (T Mj,S2 -T HS ) R S2,Mj / R Mj,HS =(T Mj,S2 -T HS ) / (T2-T Mj,S2), the calculation being independent of Q, which is the value of the heat flow applied between the second semiconductor of the at least two semiconductors and the connecting layer Mj; Includes.

[0063] This measurement has the following advantages: The semiconductor S1 is at a temperature T Mj’ The temperature T of Mj is close to Mj is positioned on the layer Mj so as to measure T Mj’, S2≒T Mj, For example, the thermal impedance between point Mj' under semiconductor S2 and point Mj under semiconductor S1 is a small fraction of the thermal impedance between Mj and the heat sink HS, for example less than 20%, typically less than 10%.

[0064] Temperature T below semiconductor S1 Mj If is close enough to the temperature of semiconductor S1, then these temperatures are the same and T Mj =T1.

[0065] In this example, T Mj =T Mj’ =T1. The semiconductor S1 is used as a sensor to measure the temperature of Mj at a position below the semiconductor S1, and it can be approximated that the temperature of Mj' below the semiconductor S2 is the same as the temperature of the semiconductor of S1.

[0066] Under these conditions, it follows that the ratio of the thermal resistance between the semiconductor of S2 and the layer Mj to the thermal resistance between the layer Mj and the heat sink HS can be expressed as: r=R S2-Mj / R Mj-HS =(T1-T HS ) / (T2-T1).

[0067] Therefore, the relative thermal resistance R can be advantageously measured without any additional temperature sensors other than the temperature measurement of the semiconductors S1 and S2 and the temperature measurement of HS. S2,Mj and R Mj-HSBy reversing the measurement, i.e. leaving S2 open, the relative thermal resistance R S1,Mj / R Mj-HS can be measured.

[0068] Using the disclosed method, the thermal resistance R between the die of the second semiconductor S2 and the layer Mj can be calculated. S2,Mj is the resistance R between Mj and the heat sink without needing to know the dissipated power in such a semiconductor. Mj,HS can be compared to

[0069] As a result, this method Thermal resistance R Mj,HS Assuming that the thermal resistance R does not change during the life of the power electronics system PS, S2,Mj monitor changes in, or Thermal resistance R S2-Mj Assuming that the thermal resistance R does not change during the life of the power electronics system PS, Mj,HS Changes in the

[0070] Temperatures T1, T2, and T HS The measurements are preferably taken under steady-state or near-steady-state thermal conditions and are repeated by alternating between switches S1 and S2 to monitor possible degradation of one of the resistances of the intermediate layers between S1 and Mj or between S2 and Mj.

[0071] As mentioned above, a similar measurement process can be performed when switch S2 is open and switch S1 is conducting to determine the thermal resistance R between the die of the first semiconductor S1 and layer Mj. S1,Mj and the resistance R between Mj and the heat sink Mj,HS A comparison can be obtained to obtain thermal data for the complete unit.

[0072] Here, the temperatures T1 and T2 of switches S1 and S2 are both measured using the gate resistances of S1 and S2 using respective calibration curves, for example, the calibration curves linearly relating T1 or T2 to Rg1 or Rg2 as follows: T1=δR1*Rg1+R01 T2=δR2*Rg2+R02

[0073] There are two situations in which this method can be used. In the first type of circuit, the semiconductors comprising dies 1a and 2a are not electrically connected in parallel, have separate gate commands, and do not perform the function of a single switch. In cases where each switch has its own gate driver, this method is implemented when one of the switches is in an open state during module operation. In the second type of circuit, the two semiconductor switches are connected in parallel but driven by separate gate driver commands. In such cases, one of the switches is kept open while the other is conducting for a period sufficient to implement this method. This can be done periodically over a limited time, such as several hundred milliseconds to one second, to provide thermal data about the module. This method requires that the gate commands of the switches be separated or include different control lines.

[0074] For an expert in the field of power electronics module design, it is easy to see that the conditions in the example presented here are generally met. For example, in such a module, the layers Mj are direct bonded copper (DBC) ceramic substrates made mainly of alumina (Al2O3) substrates several mm thick with a thermal conductivity of 20 W / (mK) to 30 W / (mK), and the semiconductor chips S1 and S2 are, for example, T Mj,S2 ≒T Mj,S1 The power electronics module is further provided with a low thermal conductivity composite material for encapsulation.

[0075] 3 and 4, the first power unit PU1 includes two semiconductor switches S11 and S12, each having a freewheeling diode and driven by gate drivers 61a and 62a. Switch S11 is the upper switch of a half-bridge, and switch S12 is the lower switch of such a half-bridge. These switches are fabricated from dies 1a and 2a bonded to a single ceramic substrate 3a. The second power unit PU2 includes two semiconductor switches S21 and S22, each having a freewheeling diode and driven by gate drivers 61b and 62b. Switch S21 is the upper switch of a half-bridge, and switch S22 is the lower switch of such a half-bridge. These switches are fabricated from dies 1b and 2b bonded to a single ceramic substrate 3b.

[0076] Each of the power units is connected to a single heat sink 5 via a layer 3' and one or more sub-layers 4' that form a base plate.

[0077] In such designs, the direct-bonded copper ceramic layers 3a and 3b are often the most critical layers and can limit the lifespan of the power module, making it important to measure the temperature of these DBC layers. To obtain information on the die-attach thermal resistance degradation, a method similar to that of Figure 9A includes the following steps: A - Leave open one adjacent semiconductor that shares the same DBC layer of the target die whose gate driver is being used to evaluate thermal resistance or damage metrics. This open semiconductor is electrically connected in parallel with another die as shown in Figure 4, so the power converter can still perform its function, albeit with a reduced maximum current rating. As an example, the semiconductor switch S11 is kept open during the TSEP measurement to avoid heat dissipation. For example, if the semiconductor S11 can be a silicon-based IGBT with a gate voltage maintained at -8V, the other semiconductors electrically connected in parallel with S11 are electrically active and perform the normal operation of the switch. B - target die temperature T die , the temperature T of the DBC layer with the adjacent die deactivated DBC , and the temperature of the heat sink T HS Measure. In one example, leaving switch S11 on die 1a open allows measurements to be made on die 2a, which shares DBC layer Mj1 with die 1a, while the conversion device still has switch S21 on die 1b to carry the current.

[0078] Repeating such steps at regular time intervals over the life of the product, the temperature difference T between the target die and the DBC layer is die -T DBC and the temperature difference T between the DBC layer and the heat sink DBC -T HS The ratio r1 = (T die -T DBC ) / (T DBC -T HS ) we can monitor the change in the thermal resistance of the die attach layer. In our example, if the thermal coupling between the parallel dies is weak, and referring to the previous example, if the thermal coupling between the parallel dies S11 and S21 is negligible, an increase in this ratio means that the thermal resistance of the die attach layer will increase by the same percentage.

[0079] Using this method, it is possible to determine, within a reasonable approximation, that under steady-state thermal conditions, typically after a few seconds of operation at regulated power, that the above ratio r1 corresponds to the thermal resistance R between the die and the DBC layer. die,DBC and the thermal resistance R between the DBC layer and the heat sink. DBC,HS It can be demonstrated that this corresponds to the ratio between

[0080] Therefore, the method is preferably applied during a steady state thermal event of the power converter, where steady state operation is either intentionally generated during a diagnostic procedure of the power converter or detected during operation of the converter.

[0081] However, the ratio r1 = (T die -T DBC) / (T DBC -T HS ) may still be independent of dissipated power under some circumstances, and therefore the method is not limited to steady-state thermal cases, so it is still possible to use the method to generate a damage indicator in thermal transient situations. In that case, the ratio r1 can be interpreted as a damage indicator rather than as a thermal resistance ratio, and its trend can still be monitored to assess the state of health of the power module.

[0082] For example, step B can be performed less than 100 ms after step A, and this sequence can be repeated at regular time intervals over the life of the product to achieve a temperature differential T between the target die and the DBC layer. die -T DBC and the temperature difference T between the DBC layer and the heat sink DBC -T HS The ratio r1 = (T die -T DBC ) / (T DBC -T HS ) is calculated and the change in the damage parameter R of the die attach layer can be monitored.

[0083] Here again, the method starts with measuring the temperature of the switch that is left open by the TSEP method, and the temperature of the heat sink T HS and measure the first temperature T1 and the heat sink temperature T HS The temperature difference between HS to obtain the value of the thermal resistance between the semiconductor switch and the heat sink in the OFF state.

[0084] Using the same principle of leaving one of the switches open while another switch on the same die is functional, measurements can be made for all dies and layers below such dies.

[0085] 5 and 6 show an embodiment in which three half-bridges are connected in parallel to the output terminals.

[0086] The power electronics system comprises three upper switches S11, S21, S31 arranged on dies 1a, 1b, 1c, respectively, and three lower switches S12, S22, S32 arranged on dies 2a, 2b, 2c, respectively.

[0087] Each upper and lower switch has a gate driver circuit 61a for switch S11, a gate driver circuit 61b for switch S21, a gate driver circuit 61c for switch S31, a gate driver circuit 62a for switch S12, a gate driver circuit 62b for switch S22, and a gate driver circuit 62c for switch S32. The three half-bridges 1a, 2a, 1b, 2b, and 1c, 2c have their own DBC layers 3a, 3b, 3c mounted on a common base plate 4', which is in turn mounted on a heat sink 5.

[0088] This embodiment, corresponding to FIG. 9B, is used to disclose another measurement to obtain the thermal resistance between the die and the baseplate.

[0089] When S11 and S12 of the first power unit PU1 are left open in step 200, the thermal resistance between switch S11 and the baseplate keeps the upper switch S11 and the lower switch S12 of the half-bridge open, and since these switches are off, T B Temperature T equals S11 =T S12 The temperature measurements of switches S11 and S12 are used to provide the baseplate temperature T B can be compared with the thermal resistance between the base plate 4′ and the heat sink 5, and the switching function is performed only by the upper switches S21, S31 on the one hand and only by the lower switches S22, S32 on the other hand, while measuring the temperature of at least the upper switch S21 (T2=T in step 220). PU2 ), the temperature of the heat sink is measured in step 225, and then the thermal resistance of the second power unit is calculated as RPU2 =(T S21 -T B ) / (T B -T HS ) or R PU2 =(T S22 -T B ) / (T B -T HS ) to compare the thermal resistance between the die and the baseplate with the thermal resistance between the baseplate and the heat sink. By performing the same measurements on the other switches, all ratios between the die attach layers 3a, 3b, 3c and the baseplate, and between the baseplate and the heat sink, can be perfectly known. In this configuration with three half-bridges, the maximum current carrying capacity of the converter is reduced by approximately one-third.

[0090] Such measurements can be made on the designs of Figures 3 and 4 with two half bridges, but the current capability of the unit in such a case is reduced by 50%, which can limit the conditions of operation of the unit during the measurements.

[0091] To characterize unit degradation, the method includes storing, for each switch, an initial ratio between a first thermal resistance between the die of the switch and a common layer with other switches and a second thermal resistance between the common layer and a common heat sink using the disclosed method, and repeating the method over the life of the power electronics system to store additional ratios between the first and second thermal resistances; monitoring the change in said second thermal resistance over the lifetime of the power electronics system, assuming that the first thermal resistance does not change; or monitoring a change in the first thermal resistance over the lifetime of the power electronics system, assuming that the second thermal resistance does not change; Includes.

[0092] In this disclosure, the temperature of the heat sink T HS is obtained using one or more state-of-the-art temperature sensors such as thermocouples, thermistors, or infrared detectors.

[0093] According to the present disclosure, the thermal resistance between all switches Sx (x=1 to n) and the connection layers, such as DBC layers Mj, that thermally connect them to the heat sink of the module can be measured or at least evaluated initially and over the lifetime of the module, along with the resistance between such connection layers and the heat sink, to monitor the evolution of such thermal resistance and device aging. If a base plate is present to receive multiple connection layers or DBC layers, the resistance between the switches and the base plate can also be monitored.

[0094] The different measurement methods and steps may be realized by software implemented in a processor of a controller of the power electronics system, the processor being further configured to provide a command to the one or more power units to place the at least one semiconductor switch in the open state, and to provide a command to generate the limited current in the at least one semiconductor switch in the open state.

[0095] Such software may be embodied in a computer-readable non-volatile medium, such as a ROM or other medium.

[0096] One technical application of this method, in which semiconductor switches are temporarily deactivated, is to monitor the temperature of a target layer Mj in a power electronics system consisting of one or more power units or modules. The thermal resistance of a particular layer of a power module can be estimated by comparing the temperature difference between the semiconductor die and the target layer Mj with the temperature difference between the layer Mj and a heat sink. This measurement can be performed online during nominal operation of the power electronics module when each gate of the parallel dies is individually controlled by its own gate driver (multi-chip configuration). By periodically repeating such measurements over the life of the power module, the local degradation state of the power module can be monitored. This allows for better knowledge of the degradation state of such modules and, therefore, better maintenance planning. Furthermore, applying the method of the present invention eliminates the need to incorporate thermistors into the power module, since the semiconductor die itself can perform this function. Finally, the present invention also does not require knowledge or measurement of the power dissipated by the semiconductor die, a significant limitation of other thermal impedance approaches.

[0097] Further types of measurements can be performed on the power electronics system PS5 as described in FIGS.

[0098] In this design, the four power units PU1, PU2, PU3, and PU4 include an upper switch S11 on die 1a, an upper switch S21 on die 1b, an upper switch S31 on die 1c, an upper switch S41 on die 1d, a lower switch S12 on die 2a, a lower switch S22 on die 2b, a lower switch S32 on die 2c, and a lower switch S42 on die 2d, where the upper switches are connected in parallel and the lower switches are connected in parallel.

[0099] The upper and lower switch dies of each power unit are attached to a common DBC layer 3a, 3b, 3'a, 3'b, and two power units PU1, PU2 are regrouped into a first power module MO1 on a first base plate 41, while two other power units PU3, PU4 are regrouped into a second power module MO2 on a second base plate 42. Furthermore, the base plates 41, 42 are attached to a heat sink 5 via connecting layers 81, 82, such as thermal paste. The heat sink is in contact with a cooling fluid 7.

[0100] FIG. 8 shows independent gate driver circuits 61a, 62a, 61b, 62b, 61'a, 62'a, 61'b, and 62'b for each device.

[0101] In this configuration, the thermal resistance R between S21 and / or S11 and / or S22 or S12 and the heat sink 5 PU1-HS All devices in the power module MO2, including PU3 and PU4, are left open, and the temperature measurement of one or a combination of the devices in the power module MO2 is used to determine the temperature T of the heat sink interface. HS , and a switching function is performed by the devices of module MO1, and at the same time, the temperature T2 of at least one of the devices of module 1 (for example, temperature T S21 ) and the temperature of the cooling fluid T CF is measured, and then R = (T2 - T HS ) / (T HS -T CF ) and compare the thermal resistance of the module MO1 and its connection layer 41 with the thermal resistance between the heat sink contact surface and the cooling fluid, thereby determining the thermal resistance R between the heat sink 5 and the cooling fluid 7. HS-CF can be compared to

[0102] The same measurements are made with all switches of power module MO1 left open, and the switching function is performed by the devices of module MO2 to compare the thermal resistance of module MO2 and its connection layer 42 with the thermal resistance between the heat sink contact surface and the cooling fluid.

[0103] This configuration therefore makes it possible to monitor the degradation of the material of the connection layers 41, 42 if measurements are taken repeatedly during the life of the power electronic system. Alternatively, the degradation of the mechanical contact between the module MO1 and the heat sink contact surface can be monitored for a loss of contact pressure due to unfastening of the fastening system or due to degradation of the thermal interface material 81, e.g. pumping out of thermal paste.

[0104] FIG. 9D provides a generalized flowchart in which measurements are repeated after an initialization phase in steps 375, 380, and in step 400, the MOi module is turned off, the MOj module is turned off, j≠i, and T HS is measured, and in step 410, T2 of the module MOj is measured, and in step 420, T CF is measured, and in step 430, the ratio r3=(T2-T HS ) / (T HS -T CF ) is measured, and in step 450 the ratio r3 of the module is stored, and the test is repeated until all j modules have been tested, and in step 365 the values ​​of the ratio r3 are compared to detect any differences in such ratios.

[0105] The material of the connection layers 41, 42 can be a thermally conductive paste, a carbon-based foil, or any material disposed between the power module and the heat sink contact surface.

[0106] By combining measurements at the die level, power unit level, and module level, the thermal resistance from the die to the DBC, the DBC to the baseplate, and the baseplate to the heat sink can be monitored.

[0107] Measurements are beneficially taken at steady state operation of the power electronics system, and to detect such steady state operation and then monitor the thermal resistance ratio, the process is The temperature Tj of at least one semiconductor device j of a power electronics system such as a power converter is measured over a time interval t sampling and storing the data in memory; The integration time t is at least a significant portion of the thermal constants of the power converter. averaging Then, using data samples Tnj,...,Tmj, we calculate the time interval t eval At least the temperature T of semiconductor j mean,j and standard deviation σ mean,j periodically calculating At least, condition T mean,j >C1×T HS and σ mean,j <C2×(T mean,j -T HS ) is observed, carry out the measurement process, may include:

[0108] C1 is a constant greater than 1, for example, such that there is a large temperature differential between the heat sink and the semiconductor die of the power converter and acceptable measurement accuracy can be achieved. HS = 30°C, then C1 = 3, so that the measurement is only applicable when Tmean,j > 90°C, ensuring that sufficient thermal gradients exist within the power converter. Alternatively, C1 may have a different value, such as C1 = 1.1, or preferably C1 = 2, or preferably C1 = 5.

[0109] Condition σmean,j <C2*(Tmean,j-T HS ) is a condition that detects the steady-state nature of operation by comparing the standard deviation of the temperature samples with the average temperature difference between the semiconductor and the heat sink during the sampling period. C2 is preferably minimized, and Tmean,jT HSis a constant limited by the measurement error. For example, C2=0.2, preferably C2=0.1, and preferably C2=0.05.

[0110] During near-thermal steady-state operation of the power converter, the ratio (T1-T HS ) / (T2-T1) is The temperature T1 of the element in the off state, i.e., T HS or T CF Temperature T equals CM the thermal resistance between the layer Mj, the connection layer and the cooling means in is the ratio between the thermal resistance of the active semiconductor (at temperature T2) and the thermal resistance of the layer Mj (at temperature T1), Because there are no errors introduced by delays in obtaining thermal balance, measurements can be made online without significantly affecting the performance of the converter or interrupting its operation.

[0111] The advantage of steady state detection is that it is therefore not necessary to subject the converter to an electrical steady state condition in order to achieve a thermal steady state condition, and the method detects the thermal steady state condition during normal operation of the converter, and when detected, the measurement method proceeds.

[0112] Time interval t sampling is a multiple of the inverse of the switching frequency of the power converter, i.e., t sampling =n / f PWM For example, n=100, preferably n=10. For example, f PWM = 10 kHz, and t sampling is 10 μs, preferably 1 μs. In another example, n is the number of active semiconductor dies in the converter, and the temperature of each die is measured in turn every switching period.

[0113] In another example, the temperature T mean,j can be calculated using the arithmetic mean and median of the data samples Tnj,...,Tjm. The definition of standard deviation is an arbitrary definition of standard deviation that is generally accepted in the field of statistical analysis.

[0114] Time interval t averaging is a time that is sufficiently long compared to the thermal constant of the power converter or the area being investigated. It can be chosen a priori by performing thermal impedance measurements, measuring the time to reach a quasi-steady-state thermal condition, and taking a safety margin to account for possible thermal resistance degradation. For example, if the thermal constant of the power converter is 3 minutes, then t averaging t may be 1 minute for layers close to the die, and the time to reach metastable state is faster than the thermal constant of the power converter, about 3 minutes or even 9 minutes for a complete converter measurement. In another example, the thermal constant of the power converter is 30 seconds, and t averaging The heating time can be 15-30 seconds for the inner layer and less than 270 seconds for the complete conversion device.

[0115] Time interval t eval For example, t averaging is a time interval longer than t eval =t averaging , or t eval =1.5*t averaging , or t eval =10*t averaging is.

[0116] In a design in which the switches of the power units PU can be controlled independently of each other, in addition to measuring the thermal impedance between the power units and the heat sink, the coupling impedance between the power units PUi and PUj (i≠j) can be measured by the sequence shown in FIG. 9C, which is: 1 / In step 300, turning off all PUj and keeping PUi active; 2 / In step 310, measuring the temperature Ti of all PUi; 3 / In step 320, the temperature of the heat sink T HS and measuring 4 / At step 330, the temperature difference ΔTi = Ti - T HS and 5 / In step 340, comparing ΔTi between the power units to detect changes in the coupling thermal resistance; Includes.

[0117] Optionally, the power dissipated in PU1 can be estimated.

[0118] This sequence may be repeated multiple times during the life of the product according to step 350 and may be applied successively to multiple PUi out of all PUi of the PS.

[0119] Therefore, advantageously, the change in the thermal impedance of PUi and / or the coupling term with PUj (i≠j) can be measured.

[0120] When a measurement sequence is applied to all PUi successively, the power Pi dissipated in PUi is measured or estimated, and a thermal steady state is obtained before starting the sequence, the data representation is constructed by arranging the temperature measurements in n matrices n × n, where if power is dissipated only in PU1:

number

number

number

[0121] A thermal resistance matrix including coupling terms (off-diagonal terms) is generated. Therefore, by applying this method multiple times during the product's life, the thermal resistance R ii or coupling resistance R ij Changes in (i≠j) can be monitored.

[0122] An example of measuring the power dissipated in a converter PUi is to use an electrical model Pi of the PU(IL, Vbus, fPWM, Ti, α...), where IL is the measured load power, Ti is the measured temperature of PUi, Vbus is the known or measured bus voltage of PUi or the converter, fPWM is the switching frequency, and α is the duty cycle.

[0123] Alternatively, without measuring the dissipated power, the ratio between the thermal resistance of PU1 and the coupling resistance with PUi is measured, and by placing the temperature measurements ΔTi into a vector, the following is given:

number

[0124] Temperature ΔT for ΔT1 i By normalizing , we obtain a state vector D that represents the state of the thermal resistance coupling between PUi at the measurement instant t.

number

[0125] Thus, the disclosed method can provide a simple method for measuring temperature parameters in power electronics systems, where semiconductor switches can be used in an off state to measure the temperature of a connection layer between such semiconductor switch and a heat source, or between such semiconductor switch and other operating semiconductor switches. The method can measure contact degradation between a die and a common connection layer by examining the temperature of the last temperature dissipation layer underneath the opposite side of the die relative to such connection layer. The method is intended for power electronics conversion systems where individual semiconductor devices are independently driven, thereby allowing sequential temperature measurements on each semiconductor with an independently controllable gate, and where multiple dies share a thermal connection via layer Mj. This is typically the case in multi-chip configurations where multiple semiconductors are electrically connected in parallel to perform the function of a single switch and share current.

[0126] FIG. 10 provides a general flow chart of an online measurement method that provides for measurement 500 during the lifetime of the system, storage 510, comparison with previous measurements 530, providing a warning when a value such as thermal resistance or thermal resistance ratio exceeds a threshold 540, and repeating the measurement after a determined time delay 520.

[0127] Such a method allows the temperature of individual switch devices in a multi-chip power module with different configurations to be measured to estimate the thermal resistance of the layer between one cold device and one hot device. Changes in thermal resistance as the power module ages can be correlated with layer degradation.

[0128] The disclosed methods can be used in DC / DC power converters, AC / AC power converters, and DC / AC power inverters, particularly those with parallel current conducting switches with switches having separate gate inputs, such as converters used in wind systems, photovoltaic inverters, electric vehicles, and traction applications.

Claims

1. 1. A method for measuring temperature or thermal resistance in a power electronic system comprising at least a first power unit and a heat source thermally connected to a cooling means via a connection layer, the method comprising: providing a limited current to the first power unit while the first power unit is in an open state such that it does not dissipate heat, the limited current not allowing the first power unit to be in a power conducting state; measuring a temperature T1 of the first power unit using a thermal sensitive electrical parameter TSEP of the first power unit; and since the first power unit in an open state does not generate heat, the temperature T1 of the connection layer is measured. ＣＬ as equal to such first temperature T1.

2. The method of claim 1 , wherein the heat source is a second power unit.

3. The temperature T of the cooling means ＣＭ and measuring the temperature difference T1-T between the connection layer and the cooling means. ＣＭ The method of claim 2 , further comprising:

4. measuring a temperature T2 of the second power unit using TSEP of the second power unit; The temperature difference T1-T ＣＭ The temperature difference T2-T ＣＭ Compare with The thermal resistance R between the second power unit and the connection layer ２－ＣＬ The thermal resistance R between the connection layer and the cooling means is calculated by the following calculation. ＣＬ－ＣＭ To compare with T1 = T ＣＬ Therefore, R ２－ＣＬ / R ＣＬ－ＣＭ = (T ＣＬ -T ＣＭ ) / (T2-T ＣＬ ) = (T1 - T ＣＭ ) / (T2-T1), such calculation being independent of Q, where Q is the heat flow value applied between the second power unit and the connection layer; The method of claim 3 further comprising:

5. The first power unit and the second power unit are semiconductor switches thermally connected to a connection layer Mj through a first stack of material layers M1, . . . , Mj-1, and the cooling means are heat sinks, and the connection layer is a material layer Mj+1.

5. The method of claim 4, wherein the first and second stacks are thermally connected to the heat sink via a second stack of Mn, . . . , Mn.

6. 6. The method according to claim 5, wherein the first power unit and the second power unit are semiconductor switches, and the connection layer is a ceramic layer of a direct-bonded copper ceramic layer or an active metal brazing layer attached directly to the heat sink or attached to the heat sink via a base plate BP.

7. the first power unit is a first half-bridge power unit including a first upper switch and a first lower switch, the first upper switch and the first lower switch having dies attached to a first ceramic layer of a direct-bonded copper ceramic layer or an active metal braze layer DBC1 via a first die attach layer; the second power unit is a second half-bridge power unit including a second upper switch and a second lower switch, the upper switch and the lower switch having dies attached to a second direct-bonded copper ceramic layer DBC2 via a second die attach layer, the first direct-bonded copper ceramic layer DBC1 and the second direct-bonded copper ceramic layer DBC2 being attached to a common heat sink HS via a solder layer and a base plate layer BP; and the method includes turning off both the first upper switch and the first lower switch of the first half-bridge power unit while the second upper switch and the second lower switch of the second half-bridge power unit are active; Measuring a temperature T2 of the second upper switch by a TSEP of the second upper switch; and measuring a temperature T1 of the first upper switch or the first lower switch by a TSEP of the first upper switch or the first lower switch by providing a limited current to the first upper switch or the first lower switch, the limited current not allowing the first upper switch to be in a power conducting state; and determining a temperature difference R between the second upper switch and the base plate, assuming that the temperature of a base plate is equal to the temperature T1. ２－ＢＰ = T2-T ＢＰ = T2 - T1; Heat sink temperature T ＨＳ Then, the ratio r2 = (T2 - T ＢＰ ) / (T ＢＰ -T ＨＳ ) and comparing the thermal resistance of the second die attach layer, the second DBC layer, and the solder layer to the thermal resistance between the base plate and the heat sink; The method of claim 4, comprising:

8. A method according to any one of claims 4 to 6, wherein each power unit is turned off in turn while the other power units are active.

9. 8. The method of claim 7, wherein the power electronics system comprises two or more half-bridge power units, and one of the half-bridges is turned off to provide temperature measurements of the baseplate while thermal resistance and thermal resistance ratio measurements are made on other of the half-bridges, each of the half-bridges being turned off in turn while the other half-bridge is active to provide a complete test of the half-bridge of the power electronics system.

10. The power electronics system includes a first power module having a first pair of half-bridge power units, each having an upper switch and a lower switch and a DBC layer connected to a first base plate, and a second power module having a second pair of half-bridge power units, each having an upper switch and a lower switch and a DBC layer connected to a second base plate, the first base plate and the second base plate being attached via a thermal contact material to a heat sink in contact with a cooling fluid, the power electronics system further including an independent gate driver circuit for each of the switches, and the method further comprising: determining a thermal resistance R between the upper switch or the lower switch of the first power module and the heat sink; ＰＵ１－ＨＳ and the thermal resistance R between the heat sink and the cooling fluid. ＨＳ－ＣＦ and measuring the thermal resistance by All devices of the second power module are left open and the TSEP temperature measurements of one or a combination of the switches of the second power module are used to determine the temperature T of the heat sink interface. ＨＳ , while the switching function of the power electronics system is performed by the switches of the first power module, and at the same time, the temperature T2 of at least one of the devices of the first power module is measured through its TSEP, and the temperature T ＣＦ measuring Ratio r3=(T2-T ＨＳ ) / (T ＨＳ -T ＣＦ ) and comparing the thermal resistance of the first power module, the first base plate, and a first thermal contact material with the thermal resistance between the heat sink contact surface and the cooling fluid, the method further comprising performing the same step with the switch of the first power module in an open state while the switching function of the power electronics system is performed by the switch of the second power module; and comparing by The method of claim 4.

11. The method according to any one of claims 1 to 6, wherein the first power unit is brought into the open state during measurement of the temperature or the thermal resistance.

12. 7. A method for monitoring the thermal resistance of an electric power unit of a power electronics system, comprising: obtaining an initial thermal resistance of such electric power unit by the method of any one of claims 4 to 6; storing said initial thermal resistance and a ratio between an initial thermal resistance between said electric power unit and said connection layer of such electric power unit and said thermal resistance between said connection layer and said cooling means; repeating said method during the lifetime of the power electronics system to obtain further thermal resistances and further ratios; and comparing said further thermal resistances and said further ratios with said initial thermal resistance and initial ratio to detect changes in thermal resistance and ratio.

13. 13. The method of claim 12, comprising comparing the change in thermal resistance to a predetermined threshold and issuing an alert if the value of the thermal resistance or the ratio exceeds the threshold.

14. The temperature Tj of at least one semiconductor device j of the power electronics system is measured over a time interval t ｓａｍｐｌｉｎｇ and storing the temperature Tj in memory; an integration time t that is at least half the thermal constant of the power converter; ａｖｅｒａｇｉｎｇ , Tnj,...,Tmj are used to calculate the time interval t ｅｖａｌ At least the average temperature T of the semiconductor device j ｍｅａｎ，ｊ and standard deviation σ ｍｅａｎ，ｊ periodically calculating At least, condition T ｍｅａｎ，ｊ > C1 x T ＨＳ , and σ ｍｅａｎ，ｊ <C2 × (T ｍｅａｎ，ｊ -T ＨＳ ) is observed, where C1 is a constant greater than 1 and C2 is a constant less than 1, The method according to any one of claims 1 to 6, comprising:

15. 15. The method of claim 14, wherein C1 is a constant in the range of 1.1 to 5.

16. C2 is a constant between 0.2 and 0.05, and the condition σmean,j<C2*(Tmean,j−T ＨＳ 15. The method of claim 14, wherein the steady-state nature of the operation is detected by comparing the standard deviation of the temperature samples to the average temperature difference between the semiconductor and the heat sink during the sampling period.

17. The time interval t ｓａｍｐｌｉｎｇ is a multiple of the inverse of the switching frequency of the power converter, i.e., t ｓａｍｐｌｉｎｇ = n / f ＰＷＭ The method of claim 14, wherein

18. The average temperature T ｍｅａｎ，ｊ 15. The method of claim 14, wherein Tnj,...,Tjm is calculated using the arithmetic mean or median of the data samples Tnj,...,Tjm.

19. The integration time t ａｖｅｒａｇｉｎｇ The method of claim 14 , wherein is greater than a thermal constant of the power electronics system.

20. The time interval t ｅｖａｌ is t ａｖｅｒａｇｉｎｇ 15. The method of claim 14, wherein the time interval is greater than

21. The switches of the power unit PUx are controlled independently of each other, x=1 to n, where n is the total number of switches, and the method comprises measuring a coupling impedance between the power unit PUi and a power unit PUj (i≠j), the measurement comprising: 1 / turning off all the switches of the module PUj and keeping the switches of the module PUi active; 2 / Measuring the temperature Tx of all modules PUx; 3 / the temperature T of the heat sink ＨＳ and measuring 4 / Temperature difference ΔTx=Tx-T ＨＳ and 5 / Comparing ΔTi with ΔTx to detect changes in the combined thermal resistance between modules; [0033] including performing the sequence 11. The method of any one of claims 7, 9 or 10.

22. 22. The method of claim 21, wherein the sequence is repeated multiple times during the life of the product.

23. 22. The method of claim 21, comprising measuring the power dissipated in the power unit PUi using an electrical model Pi (IL, Vbus, fPWM, Ti, α...) of such power unit, where IL is the measured load power, Ti is the measured temperature of PUi, Vbus is the known or measured bus voltage of the power unit PUi, fPWM is the switching frequency of such power unit, and α is the duty cycle of such power unit, and calculating a coupling resistance as ΔTk / Pi.

24. Software comprising instructions which, when executed in a controller of a power system, implement the method of any one of claims 1 to 6.

25. 25. A computer readable non-volatile medium having the software of claim 24 recorded thereon.

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