Excitation current detection circuit, semiconductor device

Abstract

To provide an excitation current detection circuit capable of accurately detecting a transformer excitation current without using an integration circuit that uses a capacitor having a large capacitance.SOLUTION: An excitation current detection circuit includes an input voltage detection unit 11 that detects a positive voltage of an auxiliary winding voltage Vna which is generated in an auxiliary winding na, an output voltage detection unit 12 that detects a negative voltage of the auxiliary winding voltage Vna which is generated in the auxiliary winding na, a first voltage control oscillator 13 that generates a first clock ckup having a frequency proportional to the positive voltage during a period in which the auxiliary winding voltage Vna is positive, a second voltage control oscillator 14 that generates a second clock ckdwn having a frequency proportional to the negative voltage during a period in which the auxiliary winding voltage Vna is negative, and a counter 15 that is incremented in a cycle of the first clock ckup, and outputs, as a detection value of an excitation current ILm, a counter value CNT decremented in a cycle of the second clock ckdwn.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an excitation current detection circuit for detecting an excitation current of a transformer. [Background technology]

[0002] In a flyback converter insulated between the primary and secondary sides, a technique has been proposed in which the excitation current of a transformer during the period in which current is released to the secondary side is detected using the auxiliary winding voltage value generated in the auxiliary winding (see, for example, Patent Document 1).

[0003] Patent Document 1 discloses an integrating circuit that integrates the difference voltage between the input voltage value applied to the primary winding and the auxiliary winding voltage value generated in the auxiliary winding over time, and outputs a voltage value proportional to the current flowing through the primary winding. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4831010 [Patent Document 2] European Patent No. 3726716 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the conventional technology, time integration is performed using an integrator circuit that uses a capacitor, so if the control IC for the flyback converter is configured using a semiconductor integrated circuit, the capacitance of the capacitor used in the integrator cannot be large. Therefore, integrator circuits that use capacitors have low noise resistance and large variations, making it difficult to improve accuracy.

[0006] In an active clamp flyback converter such as that shown in Patent Document 2, a clamp switch is controlled by detecting the excitation current of the transformer, but with conventional technology, it is difficult to achieve the precision required for a control IC of an active clamp flyback converter.

[0007] The present invention has been made in consideration of these problems, and its purpose is to provide an excitation current detection circuit that can accurately detect the excitation current of a transformer without using an integrating circuit that uses a large-capacity capacitor. [Means for solving the problem]

[0008] In order to achieve the above object, the excitation current detection circuit according to the present invention is configured as follows. The excitation current detection circuit of the present invention is an excitation current detection circuit that detects the excitation current of a transformer that has a primary winding and an auxiliary winding on a primary side and a secondary winding on a secondary side, and is characterized by comprising: a first voltage detection unit that detects a positive voltage of the auxiliary winding voltage generated in the auxiliary winding; a second voltage detection unit that detects a negative voltage of the auxiliary winding voltage generated in the auxiliary winding; a first voltage controlled oscillator that generates a first clock having a frequency proportional to the positive voltage during a period in which the auxiliary winding voltage is at the positive voltage; a second voltage controlled oscillator that generates a second clock having a frequency proportional to the negative voltage during a period in which the auxiliary winding voltage is at the negative voltage; and a counter that adds a counter value during one of the cycles of the first clock and the second clock and subtracts a counter value during the cycle of the other of the first clock and the second clock, and outputs the counter value as a detection value of the excitation current. Moreover, an excitation current detection circuit according to the present invention is an excitation current detection circuit that detects an excitation current of a transformer having a primary winding and an auxiliary winding on a primary side and a secondary winding on a secondary side, and is characterized by comprising: a first voltage detection unit that samples and detects an auxiliary winding voltage generated in the auxiliary winding a preset first delay time after a switch element connected in series with the primary winding transitions to an ON state; a second voltage detection unit that samples and detects the auxiliary winding voltage generated in the auxiliary winding a preset second delay time after the switch element transitions to an OFF state; a first voltage controlled oscillator that generates a first clock having a frequency proportional to the auxiliary winding voltage detected by the first voltage detection unit; a second voltage controlled oscillator that generates a second clock having a frequency proportional to the auxiliary winding voltage detected by the second voltage detection unit; and a counter that adds or adds a counter value with a cycle of the first clock when the switch element is in the ON state and subtracts or adds a counter value with a cycle of the second clock when the switch element is in the OFF state, and outputs the counter value as a detection value of the excitation current. [Effects of the Invention]

[0009] The excitation current detection circuit of the present invention can be configured with a logic circuit, and has the effect of being able to accurately detect the excitation current of a transformer without using an integrating circuit that uses a capacitor with a large capacity. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a configuration diagram of a flyback converter equipped with a first embodiment of an excitation current detection circuit according to the present invention; [Figure 2] FIG. 2 is a configuration diagram of the excitation current detection circuit shown in FIG. [Figure 3] 2 is a waveform diagram of each part of the flyback converter shown in FIG. 1. [Figure 4] 3 is a waveform diagram of each part of the excitation current detection circuit shown in FIG. 2. [Figure 5] FIG. 10 is a diagram illustrating another configuration of the counter. [Figure 6]FIG. 1 is a configuration diagram of a flyback converter equipped with a second embodiment of an excitation current detection circuit according to the present invention. [Figure 7] FIG. 7 is a configuration diagram of the excitation current detection circuit shown in FIG. [Figure 8] 7A to 7C are waveform diagrams of the various parts of the excitation current detection circuit shown in FIG. 6. DETAILED DESCRIPTION OF THE INVENTION

[0011] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

[0012] (First embodiment) The excitation current detection circuit 10 of the first embodiment is applicable to a power supply device that sends power from the primary side to the secondary side via a transformer T, and in the example shown in Figure 1, it is provided in the control circuit 3 of the flyback converter 1.

[0013] The flyback converter 1 includes a transformer T, a switch element Q, a diode Ds, an output capacitor Co, and an output voltage detection circuit 2.

[0014] The transformer T includes a primary winding Np and an auxiliary winding Na on the primary side, and a secondary winding Ns on the secondary side. The winding start of the primary winding Np and the winding start of the secondary winding Ns are wound in opposite phases, and an exciting inductance Lm is provided on the primary winding Np side. In FIG. 1, the auxiliary winding Na is in opposite phase to the primary winding Np, but the polarity of the auxiliary winding Na may be reversed. In this case, in the following description, only the polarity of the voltage generated by the auxiliary winding Na is reversed, and the gist of the present invention remains unchanged.

[0015] A series circuit of a primary winding Np of a transformer T and a switch element Q is connected across a DC power supply (input voltage Vin). The switch element Q will be described as a MOSFET, but it may also be an IGBT (insulated gate bipolar transistor) or the like.

[0016] The anode of the diode Ds is connected to one end of the secondary winding Ns of the transformer T, and the cathode is connected via the output capacitor Co to the other end of the secondary winding Ns of the transformer T. In other words, a series circuit of the diode Ds and the output capacitor Co is connected to both ends of the secondary winding Ns of the transformer T as a rectifying and smoothing circuit, and the voltage across the output capacitor Co is output as the output voltage Vo.

[0017] The output voltage detection circuit 2 detects the output voltage Vo and feeds back the detected output voltage Vo to the control circuit 3 as a feedback voltage Vfb via a photocoupler or the like (not shown).

[0018] The control circuit 3 is configured with a semiconductor device such as a switching regulator IC (semiconductor integrated circuit) that drives the switch element Q to turn on and off so that the output voltage Vo becomes a desired value. The control circuit 3 may have the switch element Q built in.

[0019] The control circuit 3 includes a gate signal generation unit 4 and a drive circuit 5. The gate signal generation unit 4 generates a gate signal G that controls the on / off of the switch element Q with a duty corresponding to the feedback voltage Vfb. The drive circuit 5 applies a control voltage to the gate of the switch element Q based on the gate signal G, thereby driving the switch element Q.

[0020] The control circuit 3 includes an excitation current detection circuit 10. The excitation current detection circuit 10 receives the voltage Vna of the auxiliary winding Na as an input, and outputs an excitation current detection value VLM.

[0021] Referring to FIG. 2, the excitation current detection circuit 10 includes an input voltage detection unit 11, an output voltage detection unit 12, a first voltage controlled oscillator (first VCO) 13, a second voltage controlled oscillator (second VCO) 14, and a counter 15.

[0022] The input voltage detector 11 detects a voltage Vsi proportional to the input voltage generated in the auxiliary winding Na. The output voltage detector 12 detects a voltage Vso proportional to the output voltage generated in the auxiliary winding Na.

[0023] The waveform diagram of each part of the excitation current detection circuit 10 shown in FIG. 3 shows, from top to bottom, (a) the gate voltage (gate signal G) of the switch element Q, (b) the drain-source voltage VQ of the switch element Q, (c) the drain current IQ of the switch element Q, (d) the excitation current ILm of the excitation inductance Lm, (e) the voltage VDs between the terminals of the diode Ds, (f) the forward current IDs of the diode Ds, and (g) the auxiliary winding voltage Vna generated in the auxiliary winding Na.

[0024] In Figure 3(a), the period T1 from time t0 to t1 when the gate voltage of switch element Q is at Hi level is the on period of switch element Q, during which excitation current ILm flows and energy is stored in the primary winding Np and secondary winding Ns. During the on period, as shown in Figure 3(e), diode Ds is reverse biased and no current flows on the secondary side. During the on period when switch element Q is on, input voltage Vin is applied, as shown in Figure 3(c), and excitation current ILm increases at Vin / Lm × t.

[0025] In FIG. 3(a), when the gate voltage of the switch element Q transitions to the Lo level at time t1 and the switch element Q is turned off, energy is transferred from the primary side to the secondary side, and the diode Ds is forward biased, causing a current to flow on the secondary side, as shown in FIG. 3(f).

[0026] The period T2, from time t1 to time t2 when the transfer of energy from the primary side to the secondary side ends, is the discharge period. During the period (discharge period) when the switch element Q is turned off and the excitation current is being discharged to the secondary side, the excitation current ILm decreases at a rate of N·Vo / Lm×t, as shown in Figure 3(d). N is the turns ratio (Np / Ns) between the primary winding Np and the secondary winding Ns.

[0027] A period T3 from time t2 to time t3 when the gate voltage of the switching element Q transitions to Hi level and the switching element Q is turned on is an off period in which no energy transfer occurs.

[0028] The waveform diagram of each part of the excitation current detection circuit 10 shown in Figure 4 shows, from top to bottom, (a) the auxiliary winding voltage Vna generated in the auxiliary winding Na, (b) the voltage Vsi proportional to the input voltage Vin, (c) the voltage Vso proportional to the output voltage Vo, (d) the first clock ckup output from the first voltage controlled oscillator 13, (e) the second clock ckdwn output from the second voltage controlled oscillator 14, and (f) the counter value CNT of the counter 15.

[0029] Referring to FIG. 4(a), the auxiliary winding voltage Vna generated in the auxiliary winding Na becomes a voltage Vsi proportional to the input voltage Vin during the negative period (period T1 and part of period T3), and becomes a voltage Vso proportional to the output voltage Vout during the positive period (period T2 and part of period T3).

[0030] Therefore, the input voltage detection unit 11 inverts and amplifies the auxiliary winding voltage Vna and eliminates the negative voltage component by half-wave rectification, and outputs only the positive voltage as voltage Vsi proportional to the input voltage Vin, as shown in Fig. 4(b).Furthermore, the output voltage detection unit 12 non-inverts and amplifies the auxiliary winding voltage Vna with the same amplification factor as the input voltage detection unit 11 and eliminates the negative voltage component by half-wave rectification, and outputs only the positive voltage as voltage Vso proportional to the output voltage Vout, as shown in Fig. 4(c).

[0031] The first voltage controlled oscillator 13 generates a first clock ckup having a frequency proportional to the voltage Vsi output from the input voltage detection unit 11. As shown in FIG. 4(d), the first clock ckup is output during the period when the auxiliary winding voltage Vna generated in the auxiliary winding Na is negative (period T1 and part of period T3).

[0032] The second voltage-controlled oscillator 14 generates a second clock ckdwn having a frequency proportional to the voltage Vso output from the output voltage detector 12. As shown in FIG. 4(e), the second clock ckdwn is output during the period when the auxiliary winding voltage Vna generated in the auxiliary winding Na is positive (period T2 and part of period T3).

[0033] The counter 15 is a two-clock up-down counter that increments the counter at the cycle of a first clock ckup input to a first clock terminal ck1 and decrements the counter at the cycle of a second clock ckdwn input to a second clock terminal ck2. The counter 15 outputs a counter value CNT from an output terminal out as a detection value of the excitation current ILm.

[0034] Since the first clock ckup has a frequency proportional to the input voltage Vin (voltage Vsi), the counter 15 is incremented in proportion to the excitation current ILm during the on period, as shown in Figure 4(f). Since the second clock ckdwn has a frequency proportional to the output voltage Vout (voltage Vso), the counter 15 is decremented in proportion to the excitation current ILm during the discharge period, as shown in Figure 4(f). Therefore, the counter value CNT output from the counter 15 is proportional to the excitation current ILm and is a highly accurate value equivalent to the excitation current ILm.

[0035] As shown in FIG. 5(a), a reset terminal R may be provided to the counter 15, and the counter value CNT may be reset to "0" at times t0 and t3 when energy storage in the transformer T begins. The reset signal input to the reset terminal R may be reset using a gate signal G at the timing of a transition to a Hi level. Furthermore, when detection of the excitation current ILm by the counter value CNT is used to control a clamp switch in an active clamp flyback converter, the reset signal may be generated by the control circuit of the clamp switch.

[0036] (Second embodiment) An excitation current detection circuit 10a of the second embodiment is provided in a control circuit 3a of a flyback converter 1, as shown in FIG.

[0037] The control circuit 3a detects that the gate signal G generated by the gate signal generating unit 4 Excitation current detection circuit 10a The control circuit 3 of the first embodiment differs from the control circuit 3 of the first embodiment in that the signal is input to the

[0038] Referring to FIG. 7, the excitation current detection circuit 10a includes a first pulse generator (first pulse) 16, a second pulse generator (second pulse) 17, an input voltage detection unit 11a, an output voltage detection unit 12a, a first voltage controlled oscillator (first VCO) 13, a second voltage controlled oscillator (second VCO) 14, and a counter 15a.

[0039] FIG. 8 is a waveform diagram of each part of the excitation current detection circuit 10a, showing, from the top, (a) the gate voltage (gate signal G) of the switch element Q, (b) the pulse signal shck1, (c) the pulse signal shck2, (d) the auxiliary winding voltage Vna generated in the auxiliary winding Na, (e) the voltage Vsi proportional to the input voltage Vin, (f) the voltage Vso proportional to the output voltage Vo, (g) the first clock ckup output from the first voltage-controlled oscillator 13, (h) the second clock ckdwn output from the second voltage-controlled oscillator 14, and (i) the counter value CNT of the counter 15.

[0040] The first pulse generator 16 detects the rising edge of the gate signal G of the switch element Q, and generates a pulse signal shck1 that outputs a one-shot pulse P1 after a preset first delay time delay1, as shown in Fig. 8(b), and outputs the pulse signal shck1 to the first voltage-controlled oscillator 13. The first delay time delay1 is set to be equal to or longer than the time required for the auxiliary winding voltage Vna to stabilize after the switch element Q is turned on by the rising edge of the gate signal G.

[0041] The second pulse generator 17 detects the falling edge of the gate signal G of the switch element Q, and generates a pulse signal shck2 that outputs a one-shot pulse P2 after a preset second delay time delay2, as shown in FIG. 8(c), and outputs the pulse signal shck2 to the second voltage-controlled oscillator 14. The second delay time delay2 is set under This is set to be equal to or longer than the time it takes for the auxiliary winding voltage Vna to stabilize after the switching element Q is turned off by a falling edge.

[0042] The input voltage detection unit 11a includes an inverting amplifier 111 and a sample-and-hold circuit 112. It receives the auxiliary winding voltage Vna and the pulse signal shck1 as inputs and outputs a voltage Vsi proportional to the input voltage Vin to the first voltage-controlled oscillator 13. The inverting amplifier 111 inverts and amplifies the auxiliary winding voltage Vna. The sample-and-hold circuit 112 samples and holds the auxiliary winding voltage Vna inverted and amplified by the inverting amplifier 111 at the timing of a one-shot pulse P1 in the pulse signal shck1 indicated by arrow A in FIGS. 8(d) and 8(e), detects the absolute value of the negative voltage of the auxiliary winding voltage Vna, and outputs it as a voltage Vsi proportional to the input voltage Vin.

[0043] As a result, the voltage Vsi output from the input voltage detection unit 11a becomes a value based on the auxiliary winding voltage Vna in a stable state, avoiding the auxiliary winding voltage Vna that is unstable due to ringing or the like immediately after the switch element Q is turned on.

[0044] The output voltage detection unit 12a includes a non-inverting amplifier 121 and a sample-and-hold circuit 122, and receives the auxiliary winding voltage Vna and the pulse signal shck2 as inputs, and outputs a voltage Vso proportional to the output voltage Vout to the second voltage-controlled oscillator 14. The non-inverting amplifier 121 amplifies the auxiliary winding voltage Vna with the same amplification factor as the inverting amplifier 111 of the input voltage detection unit 11a. The sample-and-hold circuit 122 amplifies the one-shot pulse P in the pulse signal shck2, as indicated by the arrow B in FIGS. 8(d) and (f). 2 At this timing, the auxiliary winding voltage Vna amplified by the non-inverting amplifier 121 is sampled and held, the positive voltage of the auxiliary winding voltage Vna is detected, and is output as a voltage Vso proportional to the output voltage Vout.

[0045] As a result, the voltage Vso output from the output voltage detection unit 12a becomes a value based on the auxiliary winding voltage Vna in a stable state, avoiding the auxiliary winding voltage Vna that is unstable due to ringing or the like immediately after the switch element Q is turned off.

[0046] The first voltage controlled oscillator 13 generates a first clock ckup having a frequency proportional to the voltage Vsi output from the input voltage detector 11a. Since the first clock ckup is generated based on the sampled and held auxiliary winding voltage Vna, as shown in FIG. 8(g), the auxiliary winding voltage Vna generated in the auxiliary winding Na is Positive period (period T 2 The auxiliary winding voltage Vna continues to be output during the negative period (period T1 and part of period T3) as well as during the negative period (period T1 and part of period T3).

[0047] The second voltage-controlled oscillator 14 generates a second clock ckdwn having a frequency proportional to the voltage Vso detected by the output voltage detector 12a. Since the second clock ckdwn is generated based on the sampled and held auxiliary winding voltage Vna, as shown in Fig. 8(h), it is output continuously not only during the period when the auxiliary winding voltage Vna generated in the auxiliary winding Na is positive (period T2 and part of period T3) but also during the period when the auxiliary winding voltage Vna generated in the auxiliary winding Na is negative (period T1 and part of period T3).

[0048] The counter 15a is a two-clock up-down counter and has a control terminal cont that controls increment and decrement of the counter according to the state of the gate signal G. As shown in FIG. 8(i), when the gate signal G input to the control terminal cont is at Hi level, the counter 15a increments the counter at the cycle of the first clock ckup input to the first clock terminal ck1. As shown in FIG. 8(i), when the gate signal G input to the control terminal cont is at Lo level, the counter 15a decrements the counter at the cycle of the second clock ckdwn input to the second clock terminal ck2. The counter 15 then outputs the counter value CNT from the output terminal out as the detection value of the excitation current ILm.

[0049] Because the first clock ckup is generated based on the stable auxiliary winding voltage Vna during the negative period, the counter value CNT of the counter 15a is incremented in proportion to the excitation current ILm even during the period when the auxiliary winding voltage Vna is unstable immediately after the switch element Q is turned on. Because the second clock ckdwn is generated based on the stable auxiliary winding voltage Vna during the positive period, the counter value CNT of the counter 15a is decremented in proportion to the excitation current ILm even during the period when the auxiliary winding voltage Vna is unstable immediately after the switch element Q is turned off. Therefore, the counter value CNT output from the counter 15a is proportional to the excitation current ILm and is a more accurate value equivalent to the excitation current ILm.

[0050] As shown in FIG. 5(b), a reset terminal R may be provided to the counter 15a, and the counter value CNT may be reset to "0" at times t0 and t3 when energy storage in the transformer T begins. The reset signal input to the reset terminal R may be reset using a gate signal G at the timing of a transition to a Hi level. Furthermore, when detection of the excitation current ILm by the counter value CNT is used to control a clamp switch in an active clamp flyback converter, the reset signal may be generated by the control circuit of the clamp switch.

[0051] As described above, this embodiment is an excitation current detection circuit 10 that detects the excitation current ILm of a transformer T that has a primary winding Np and an auxiliary winding na on the primary side and a secondary winding Ns on the secondary side, and includes an input voltage detection unit 11 (first voltage detection unit) that detects the positive voltage of the auxiliary winding voltage Vna generated in the auxiliary winding na, an output voltage detection unit 12 (second voltage detection unit) that detects the negative voltage of the auxiliary winding voltage Vna generated in the auxiliary winding na, a first voltage controlled oscillator 13 that generates a first clock ckup having a frequency proportional to the positive voltage during a period in which the auxiliary winding voltage Vna is a positive voltage, a second voltage controlled oscillator 14 that generates a second clock ckdwn having a frequency proportional to the negative voltage during a period in which the auxiliary winding voltage Vna is a negative voltage, and a counter 15 that adds a counter value CNT during one of the periods of the first clock ckup and the second clock ckdwn and subtracts a counter value CNT during the other period of the first clock ckup and the second clock ckdwn, and outputs the counter value CNT as a detection value of the excitation current ILm. This configuration allows the excitation current detection circuit 10 to be configured as a logic circuit, and the excitation current ILm of the transformer T can be accurately detected without using an integrating circuit with a large-capacity capacitor. Furthermore, because the excitation current detection circuit 10 is configured as a logic circuit, it is easy to integrate and can be applied to the control IC of an active clamp flyback converter.

[0052] Furthermore, in this embodiment, the excitation current detection circuit 10a detects the excitation current ILm of the transformer T having a primary winding Np and an auxiliary winding na on the primary side and a secondary winding Ns on the secondary side, and includes an input voltage detection unit 11a (first voltage detection unit) that samples and detects the auxiliary winding voltage Vna generated in the auxiliary winding Na after a preset first delay time delay1 has elapsed since the switch element Q connected in series with the primary winding Np transitions to the ON state, and an output voltage detection unit 11b (second voltage detection unit) that samples and detects the auxiliary winding voltage Vna generated in the auxiliary winding na after a preset second delay time delay2 has elapsed since the switch element Q transitions to the OFF state. a first voltage controlled oscillator 13 that generates a first clock ckup having a frequency proportional to the auxiliary winding voltage Vna detected by the input voltage detection unit 11a; a second voltage controlled oscillator 14 that generates a second clock ckdwn having a frequency proportional to the auxiliary winding voltage detected by the output voltage detection unit 12a; and a counter 15a that adds or subtracts at the cycle of the first clock ckup when the switch element Q is in the on state and subtracts or adds at the cycle of the second clock ckdwn when the switch element Q is in the off state, and outputs the counter value CNT as the detection value of the excitation current ILm. This configuration allows the excitation current detection circuit 10a to be configured with a logic circuit, eliminating the need for an integrator circuit using a large-capacity capacitor. Furthermore, the counter value CNT of the counter 15a is incremented or decremented in proportion to the excitation current ILm even during the period when the auxiliary winding voltage Vna is unstable immediately after the switch element Q is turned on or off, enabling even more accurate detection of the excitation current ILm of the transformer T.

[0053] Furthermore, in this embodiment, the counters 15 and 15a are provided with a reset terminal R, and the counter values ​​CNT of the counters 15 and 15a are reset to start from "0" when the accumulation of energy in the transformer T begins. This configuration makes it possible to eliminate errors in the counter value CNT.

[0054] It is clear that the present invention is not limited to the above-described embodiments, and that each embodiment can be appropriately modified within the scope of the technical concept of the present invention. Furthermore, the number, position, shape, etc. of the above-described components are not limited to the above-described embodiments, and the number, position, shape, etc. can be set to be suitable for implementing the present invention. Note that the same components are denoted by the same reference numerals in each drawing. [Explanation of symbols]

[0055] 1 Flyback Converter 2 Output voltage detection circuit 3, 3a Control circuit 4 Gate signal generation section 5. Drive circuit 10, 10a Excitation current detection circuit 11, 11a Input voltage detection section 12, 12a Output voltage detection section 13 First voltage controlled oscillator (first VCO) 14 Second voltage controlled oscillator (second VCO) 15, 15a counter 16 First pulse generator (first pulse) 17 Second pulse generator (second pulse) 111 Inverting amplifier 112 Sample and hold circuit 121 Non-inverting amplifier 122 Sample and hold circuit

Claims

1. An excitation current detection circuit for detecting an excitation current of a transformer having a primary winding and an auxiliary winding on a primary side and a secondary winding on a secondary side, a first voltage detection unit that detects a positive voltage of an auxiliary winding voltage generated in the auxiliary winding; a second voltage detection unit that detects a negative voltage of the auxiliary winding voltage generated in the auxiliary winding; a first voltage controlled oscillator that generates a first clock having a frequency proportional to the positive voltage during a period when the auxiliary winding voltage is the positive voltage; a second voltage-controlled oscillator that generates a second clock having a frequency proportional to the negative voltage during a period when the auxiliary winding voltage is at the negative voltage; a counter that adds a counter value at the cycle of either the first clock or the second clock and subtracts a counter value at the cycle of the other of the first clock or the second clock, and outputs the counter value as the detection value of the excitation current.

2. An excitation current detection circuit for detecting an excitation current of a transformer having a primary winding and an auxiliary winding on a primary side and a secondary winding on a secondary side, a first voltage detection unit that samples and detects an auxiliary winding voltage generated in the auxiliary winding after a preset first delay time has elapsed since a switch element connected in series with the primary winding transitioned to an on state; a second voltage detection unit that samples and detects the auxiliary winding voltage generated in the auxiliary winding after a second delay time set in advance has elapsed since the switch element transitioned to an off state; a first voltage controlled oscillator that generates a first clock having a frequency proportional to the auxiliary winding voltage detected by the first voltage detection unit; a second voltage controlled oscillator that generates a second clock having a frequency proportional to the auxiliary winding voltage detected by the second voltage detection unit; a counter that adds or subtracts a counter value at the cycle of the first clock when the switch element is in the on state, and that adds or subtracts a counter value at the cycle of the second clock when the switch element is in the off state, and outputs the counter value as the detection value of the excitation current.

3. the counter includes a reset terminal; 3. The excitation current detection circuit according to claim 1, wherein the counter value of the counter is reset to start from "0" when the storage of energy in the transformer starts.

4. 3. A semiconductor device comprising the excitation current detection circuit according to claim 1.

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