Time series training method and apparatus for LVDS interface

Abstract

To provide a method and apparatus for timing training on an LVDS (Low Voltage Differential Signaling) interface.SOLUTION: A method for timing training on an LVDS interface includes the steps of: sampling data by using second parallel data as reference data, and first parallel data as scanning data, and obtaining a first delay stage when a sampling position corresponding to a delay stage is located at a window center of the scanning data; sampling data by using the first parallel data as reference data, and the second parallel data as scanning data, setting an initial delay stage of the second parallel data as the first delay stage, and obtaining a second delay stage when a sampling position corresponding to the delay stage is located at a window center of the scanning data; setting the sum of the first delay stage and half of a difference between the first delay stage and the second delay stage as a delay stage of the first parallel data, and then receiving LDVS differential data by using the second parallel data as scanning data.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to the technical field of mFPGA (Field Programmable Gate Array), and in particular to a time-series training method and apparatus for LVDS interface. [Background technology]

[0002] The LVDS (Low Voltage Differential Signaling) interface of an FPGA (Field Programmable Gate Array) usually adjusts the phase of the sampling clock or serial data by changing the number of delay chain stages to ensure the establishment of a retention relationship between the serial data and the sampling clock. However, switching the number of delay chain stages is likely to cause burrs in the data stream.

[0003] Chips in different areas on the same wafer may have different errors due to changes in external and production conditions. The overall speed of transistors on chips in some areas of the same wafer may be faster or slower. At the same time, different areas on the same chip may have further differences, i.e., on-chip variation (OCV), due to the above factors.

[0004] When an LVDS interface receiver performs time-series training, it typically determines the sampling position by transmitting a fixed-period training data sequence and then compares the fixed training sequence multiple times to determine the center of the data valid window. However, existing time-series training methods cannot address the adverse impact of chip-to-chip OCV differences on window accuracy. For example, if the designed delay value of a delay unit in a delay chain is 10 ps, ​​the actual delay of a different chip using the same circuit may be 9.5 ps or 10.5 ps. After cascading delay chains, the actual delay difference becomes even larger. Temperature, voltage, and process also affect the delay value of the delay unit. Existing time-series training methods cannot avoid the impact of the difference in the rise and fall slopes of the data on the data valid window, i.e., the impact of the asymmetry between the P and N data of an LVDS signal on the data valid window. Figure 1 is a schematic diagram showing the impact of OCV and the rise and fall time symmetry between the P and N data of an LVDS signal on the data window. Summary of the Invention

[0005] Based on this, the present invention provides a time series training method and apparatus for LVDS interface, which solves the problems that burrs are introduced into the data stream due to switching the number of delay chain stages, resulting in error codes, the need to send a training sequence for interface time series training, the adverse effect of chip OCV difference on window accuracy, and the unavoidable effect of asymmetry between LVDS signal P data and N data on the data valid window.

[0006] The present invention provides a time series training method for an LVDS interface, the method comprising: S1: inputting the P end of the LVDS differential data signal into a first delay chain, and converting it into a first parallel data by serial-to-parallel conversion; inputting the N end of the LVDS differential data signal into a second delay chain, and converting it into a second parallel data by serial-to-parallel conversion; S2: Sampling data using the second parallel data as reference data and the first parallel data as scan data; Current delay stage the sampling positions corresponding to the scanning data of Collect the relative position of the window center and Current delay stage If the sampling position corresponding to is located at the window center of the scan data, Current delay stage The first delay Number of steps and recording the S3: Sampling data using the first parallel data as reference data and the second parallel data as scanning data, and Number of steps The first delay Number of steps and the delay Number of steps and the relative position of the scanning data window center corresponding to the sampling position, Number of steps is located at the window center of the scan data, current The first delay Number of steps The second delay Number of steps and recording the S4: The first delay Number of steps and the second delay Number of steps Delay from Number of steps The difference is calculated, and the first delay Number of steps and the delay Number of steps The sum of half the difference is the delay of the first parallel data Number of steps and receiving the LVDS differential data as the second parallel data as scan data.

[0007] Furthermore, the S2 is S21: The second parallel data is used as reference data, and the first parallel data is used to sample the data. Number of steps and setting the initial delay Number of steps and collecting the relative positions corresponding to the initial delay Number of steps is the total delay of the first delay chain Number of steps With smaller steps than S22: The initial delay Number of stepsis on the left side of the window center of the first parallel data, the initial delay Number of steps Decreased initial delay Number of steps The initial delay Number of steps and then collecting the relative position again after updating the The initial delay Number of steps is on the right side of the window center of the first parallel data, the initial delay Number of steps Increased initial delay Number of steps The initial delay Number of steps and collecting the relative positions again after updating the relative positions to S23: The initial delay Number of steps The initial delay when the sampling position corresponding to Number of steps The first delay Number of steps and

[0008] Furthermore, the S3 S31: The first parallel data is used as reference data, and the first delay Number of steps the initial delay of the second parallel data Number of steps and scan the initial delay Number of steps collecting the relative positions corresponding to S32: The initial delay Number of steps is on the left side of the window center of the second parallel data, the initial delay Number of steps Decreased initial delay Number of steps The initial delay Number of steps and then collecting the relative position again after updating the The initial delay Number of steps The sampling position corresponding to 2 If it is on the right side of the center of the parallel data window, the initial delay Number of steps Increased initial delay Number of steps The initial delay Number of steps and collecting the relative positions again after updating the relative positions to S33: The initial delay Number of stepsThe initial delay when the sampling position corresponding to Number of steps The second delay Number of steps and

[0009] Furthermore, the delays in S2 and S3 Number of steps and the relative position of the scan data window center, S51: Selecting one set of data from the first parallel data and the second parallel data as reference data, and collecting the other set of data as scan data, and delaying the scan data Number of steps is the delay corresponding to the scanning data in the first parallel data and the second parallel data. Number of steps and S52: The delay Number of steps gradually decreasing the value of the reference data and the scanned data and monitoring whether the reference data and the scanned data match within a specific time; S53: Match, said delay Number of steps If does not decrease to zero, repeat S52; If not, the delay Number of steps the first sub-delay Number of steps and proceeding to S54; S54: The delay Number of steps reloading the S55: The delay Number of steps stepwise increasing the value of the reference data and the scanned data, and monitoring whether the reference data and the scanned data match within a specific time; S56: Match, said delay Number of steps is delayed Number of steps If the maximum value of has not been reached, repeat S55. If not, the delay Number of steps The second sub-delay Number of steps and recording the S57: The delay Number of steps , the first sub-delay Number of steps and the second sub-delay Number of steps Based on the first sub-delay Number of stepsDifference, Second Sub-Delay Number of steps Obtain the difference between the first sub-delay Number of steps the difference and the second sub-delay Number of steps Comparing the difference and delay Number of steps and obtaining the relative position of the scanning data window center corresponding to the sampling position.

[0010] Furthermore, S57 S571: The delay Number of steps and the first sub-delay Number of steps The difference between the first sub-delay Number of steps the second sub-delay is the difference Number of steps and the delay Number of steps The difference between the second sub-delay Number of steps a step of subtracting S572: The first sub-delay Number of steps The difference is the second sub-delay Number of steps If the delay is greater than Number of steps the sampling position corresponding to is on the left side of the center of the scanning data window in the first parallel data and the second parallel data, The first sub-delay Number of steps The difference is the second sub-delay Number of steps If the delay is less than Number of steps the sampling position corresponding to is on the right side of the scanning data window center in the first parallel data and the second parallel data, The first sub-delay Number of steps The difference is the second sub-delay Number of steps If it is equal to Number of steps the sampling position corresponding to the first parallel data is at the center of a scanning data window in the second parallel data.

[0011] Furthermore, the total delay of the first delay chain and the second delay chain is greater than the width of the serial data window.

[0012] Furthermore, before S1, S0: further comprising the step of scrambling the LVDS differential data and converting it into serial data through parallel-to-serial conversion, and then inputting it into a delay chain; After S4, S6: The method further includes the step of descrambling the received LVDS differential data.

[0013] Furthermore, the initial delay Number of steps is the total delay of the first delay chain Number of steps It is half of that.

[0014] Furthermore, the delay Number of steps The smaller the difference, the greater the delay caused by on-chip errors and asymmetric slopes between the P and N terminals of the LVDS differential data. Number of steps The difference becomes smaller.

[0015] The present invention further provides a time series training device for an LVDS interface, said device comprising: a conversion module for inputting the P end of the LVDS differential data signal into a first delay chain and converting it into first parallel data through serial-to-parallel conversion, and inputting the N end of the LVDS differential data signal into a second delay chain and converting it into second parallel data through serial-to-parallel conversion; The second parallel data is used as reference data, and the first parallel data is used as scanning data, and data is sampled and delayed. Number of steps and the relative position of the scanning data window center corresponding to the sampling position, Number of steps If the sampling position corresponding to is located at the window center of the scan data, the delay Number of steps The first delay Number of steps a first sampling module for recording the sampling data using the first parallel data as reference data and the second parallel data as scanning data; and Number of steps The first delay Number of steps and delay Number of steps and the relative position of the scanning data window center corresponding to the sampling position, Number of stepsWhen the sampling position corresponding to is located at the window center of the scan data, the first delay Number of steps The second delay Number of steps a second sampling module for recording the The first delay Number of steps and the second delay Number of steps Delay from Number of steps The difference is calculated, and the first delay Number of steps and the delay Number of steps The sum of half the difference is the delay of the first parallel data Number of steps and a data output routing module for setting the second parallel data as scan data and receiving the LVDS differential data as scan data.

[0016] The present invention provides a time series training method for an LVDS interface, which comprises inputting the P end and N end of an LVDS differential data signal into a first delay chain and a second delay chain respectively, and then sampling the data using the second parallel data as reference data and the first parallel data as scanning data, and Number of steps If the sampling position corresponding to is located at the window center of the scan data, the first delay Number of steps and sampling data using the first parallel data as reference data and the second parallel data as scanning data, and obtaining an initial delay of the second parallel data. Number of steps The first delay Number of steps and the delay Number of steps If the sampling position corresponding to is located at the center of the window of the scan data, the second delay Number of steps and the first delay Number of steps and the second delay Number of steps Delay from Number of steps The difference is calculated, and finally the first delay Number of steps and the delay Number of steps The sum of half the difference is the delay of the first parallel data Number of stepsand receives the LVDS differential data as the second parallel data as scan data. This can address the impact on the data valid window caused by the asymmetric signal slope between the P terminal and the N terminal of the OCV and LVDS differential data, while avoiding the occurrence of burrs in the data stream when switching the number of delay chain stages, thereby reducing the design requirements for the delay chain. The time series training device for LVDS interface provided by the present invention can achieve the above effects. [Brief explanation of the drawings]

[0017] In order to more clearly describe the technical solutions in the embodiments of the present invention, the following will briefly describe the accompanying drawings that need to be used in the embodiments. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these accompanying drawings without any creative work.

[0018] [Figure 1] 1 is a schematic diagram showing the effect on a data window of the rise and fall time symmetry between P data and N data of an OCV and LVDS signal. [Figure 2] 1 is a schematic diagram of an LVDS transceiver architecture for applying a time series training method for an LVDS interface provided by an embodiment of the present invention; FIG. [Figure 3] 1 is a flow diagram of a time-series training method for an LVDS interface provided by an embodiment of the present invention; [Figure 4] FIG. 10 is a schematic diagram of a flow for acquiring the first number of delay stages. [Figure 5] FIG. 10 is a schematic diagram of a flow for obtaining the second number of delay stages. [Figure 6] FIG. 10 is a schematic diagram of a process for obtaining the relative position of the sampling position corresponding to the number of delay stages and the center of the scan data window. [Figure 7] FIG. 10 is a schematic flow diagram of another time-series training method for an LVDS interface provided by an embodiment of the present invention. [Figure 8]1 is a schematic block diagram of a time series training device for an LVDS interface provided by an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art of this application, and the terms used in the specification of this application are used only for the purpose of describing specific embodiments and are not intended to limit this application, and the terms "comprises," "has," and any variations thereof in the specification and claims of this application and the above-mentioned attached drawings are intended to be non-exclusive inclusive. Terms such as "first," "second," etc. in the specification and claims of this application or the above-mentioned attached drawings are used to distinguish different objects and are not used to specify a particular order.

[0020] References herein to an "embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The occurrence of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive from other embodiments. Those skilled in the art will understand, either explicitly or implicitly, that the embodiments described herein may be combined with other embodiments.

[0021] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application will be described in more detail below in conjunction with the accompanying drawings and examples. It should be noted that the specific examples described herein are only for the purpose of interpreting the present application and are not intended to limit the present application. Based on the examples of the present invention, other examples obtained by those skilled in the art without any creative work are all included in the protection scope of the present invention.

[0022] In the following description, the terms "module," "component," or "unit" used to indicate an element are used only for the purpose of facilitating the description of this application, and do not have any specific meaning in themselves.

[0023] 2 is a schematic diagram of an LVDS transceiver architecture that applies a time-series training method for an LVDS interface provided by an embodiment of the present invention. The architecture includes a transmit side and a receive side of the LVDS transceiver. The transmit side includes a scrambling module and a parallel-to-serial conversion module, while the receive side includes a delay chain 1, a serial-to-parallel conversion module 1, a delay chain 2, a serial-to-parallel conversion module 2, a delay stage selection module, a sampling position scanning module, a time-series training control module, a data path selection module, and a descrambling module. Here, the transmission path consisting of the delay chain 1 and the serial-to-parallel conversion module 1 is referred to as path 1, and the transmission path consisting of the delay chain 2 and the serial-to-parallel conversion module 2 is referred to as path 2. At the transmit side of the LVDS transceiver, the scrambling module scrambles parallel data. The scrambling module then transmits the scrambled parallel data to the parallel-to-serial conversion module, which converts the parallel data to serial data, and then transmits the serial data stream at the LVDS level. The P and N terminals of the LVDS differential data signal input at the receiving side of the LVDS transceiver are input to one of paths 1 and 2, respectively, and then converted into parallel data through serial-to-parallel conversion. The parallel data from the two paths is then compared to determine the sampling position.

[0024] As shown in FIG. 3, a flow diagram of a time-series training method for an LVDS interface provided by an embodiment of the present invention is applied to the receiving side of the LVDS transceiver in FIG. 2. The method includes: S1: inputting the P end of the LVDS differential data signal into a first delay chain, and converting it into a first parallel data by serial-to-parallel conversion; inputting the N end of the LVDS differential data signal into a second delay chain, and converting it into a second parallel data by serial-to-parallel conversion; S2: Sampling data using the second parallel data as reference data and the first parallel data as scan data; Current delay stage the sampling positions corresponding to the scanning data of Collect the relative position of the window center and Current delay stage If the sampling position corresponding to is located at the window center of the scan data, Current delay stage The first delay Number of steps and recording the S3: Sampling data using the first parallel data as reference data and the second parallel data as scanning data, and Number of steps The first delay Number of steps and the delay Number of steps and the relative position of the scanning data window center corresponding to the sampling position, Number of steps When the sampling position corresponding to is located at the window center of the scan data, the first delay Number of steps The second delay Number of steps and recording the S4: The first delay Number of steps and the second delay Number of steps Delay from Number of steps The difference is calculated, and the first delay Number of steps and the delay Number of steps The sum of half the difference is the delay of the first parallel data Number of steps and receiving the LVDS differential data as the second parallel data as scan data.

[0025] Specifically, in this embodiment, the time series training module in FIG. 2 sends a sampling signal to the sampling position scanning module, which monitors the positional relationship between the scanning sampling position and the window center. The sampling position scanning module scans the positional relationship between the sampling position and the window center, and calibrates the sampling position if the data window is offset from the window center. In this embodiment, when the sampling position scanning module receives the sampling signal from the time series training module, the P end of the LVDS differential data signal is input to delay chain 1 in FIG. 2, and the data output from delay chain 1 is input to serial-to-parallel conversion module 1 to be converted into first parallel data. The N end of the LVDS differential data signal is input to delay chain 2 in FIG. 2, and the data output from delay chain 2 is input to serial-to-parallel conversion module 2 to be converted into second parallel data. Time series training is performed using path 2 as the scanning path and path 1 as the reference path. The initial delay of delay chain 1 Number of steps (for example, the total delay of delay chain 1) Number of steps (It may be set to half of the sampling position scanning module.) Number of steps and the relative position of the scanning data window center corresponding to the sampling position, and the initial delay Number of steps If the sampling position corresponding to is at the center of the scan data window, then the initial delay Number of steps The first delay Number of steps Recorded as initial delay Number of steps If the sampling position corresponding to is not located at the center of the scanning data window, the delay is calculated according to the position result obtained by the sampling position scanning module. Number of steps and sends it to the delay stage selection module, which then selects the adjusted delay Number of steps After sending the delay chain 1, the sampling position scanning module continues scanning, and when the sampling position scanning module scans that the sampling position is at the center of the scanning data window, Number of steps The first delay Number of steps Then, time series training is performed using path 1 as the scanning path and path 2 as the reference path. The initial delay of delay chain 2 Number of steps The first delay Number of steps The sampling position scanning module is set as the first delay Number of steps and the relative position of the scanning data window center corresponding to the sampling position, and the first delay Number of steps If the sampling position corresponding to is at the center of the scan data window, the first delay Number of steps The second delay Number of steps Recorded as the first delay Number of steps If the sampling position corresponding to is not located at the center of the scanning data window, the first delay is set according to the position result obtained by the sampling position scanning module. Number of steps and sends it to the delay stage selection module, which then selects the adjusted delay Number of steps After sending the delay chain 2 to the sampling position scanning module, the sampling position scanning module scans the sampling position to be at the center of the scanning data window. Number of steps The second delay Number of steps Then, the first delay Number of steps and the second delay Number of steps Delay of Number of steps Find the difference and calculate the delay of delay chain 1. Number of steps The delay stage selection module selects the first delay Number of steps and the delay Number of steps , and selects path 2 as the scan path to send to the data routing module to receive the LVDS differential data.

[0026] In some embodiments, as shown in FIG. Number of steps is a schematic diagram of a flow for acquiring the above, and S2 S21: The second parallel data is used as reference data, and the first parallel data is used to sample the data. Number of steps and setting the initial delay Number of steps and collecting the relative positions corresponding to the initial delay Number of steps is the total delay of the first delay chain Number of steps With smaller steps than S22: The initial delay Number of stepsis on the left side of the window center of the first parallel data, the initial delay Number of steps Decreased initial delay Number of steps The initial delay Number of steps and then collecting the relative position again after updating the The initial delay Number of steps is on the right side of the window center of the first parallel data, the initial delay Number of steps Increased initial delay Number of steps The initial delay Number of steps and collecting the relative positions again after updating the relative positions to S23: The initial delay Number of steps The initial delay when the sampling position corresponding to Number of steps The first delay Number of steps and

[0027] Specifically, in this embodiment, the selected path 1 is the scan path, the path 2 is the reference path, and the initial delay of the delay chain 1 is Number of steps Set the initial delay Number of steps is the total delay of delay chain 1 Number of steps is smaller than any number of , then the sampling position scanning module will Number of steps and the relative position between the sampling position corresponding to the first parallel data and the window center of the first parallel data, and Number of steps When the sampling position corresponding to the first parallel data is at the window center of the first parallel data, the initial delay Number of steps The first delay Number of steps The initial delay is recorded as Number of steps is on the left side of the window center of the first parallel data, the time series training control module Number of steps Decreased delay Number of steps is sent to the delay stage selection module, and the delay of delay chain 1 is Number of steps Delay after reducing Number of steps and continues from the sampling position to the delay Number of stepsand a relative position between the sampling position corresponding to the delay and the window center of the first parallel data. Number of steps is on the right side of the window center of the first parallel data, the time series training control module Number of steps Increased delay Number of steps is sent to the delay stage selection module, and the delay of delay chain 1 is Number of steps Delay after increasing Number of steps and continues from the sampling position to the delay Number of steps and the relative position between the sampling position corresponding to the first parallel data window center, and the delay of the adjusted delay chain 1 Number of steps When the sampling position corresponding to is at the window center of the first parallel data, the delay of the delay chain 1 Number of steps The first delay Number of steps Record as.

[0028] In some embodiments, preferably, the initial delay Number of steps is the total delay of the first delay chain Number of steps It is half of that.

[0029] In some embodiments, as shown in FIG. 5, a second delay Number of steps 1 is a schematic diagram of a flow for acquiring the above-mentioned S3. S31: The first parallel data is used as reference data, and the first delay Number of steps the initial delay of the second parallel data Number of steps and scan the initial delay Number of steps collecting the relative positions corresponding to S32: The initial delay Number of steps is on the left side of the window center of the second parallel data, the initial delay Number of steps Decreased initial delay Number of steps The initial delay Number of steps and then collecting the relative position again after updating the The initial delay Number of steps The sampling position corresponding to 2If it is on the right side of the center of the parallel data window, the initial delay Number of steps Increased initial delay Number of steps The initial delay Number of steps and collecting the relative positions again after updating the relative positions to S33: The initial delay Number of steps The initial delay when the sampling position corresponding to Number of steps The second delay Number of steps and

[0030] Specifically, in this embodiment, path 2 is selected as the scanning path, path 1 is selected as the reference path, and the initial delay of delay chain 2 is set as Number of steps The first delay Number of steps Then the sampling position scanning module sets the initial delay Number of steps and the relative position between the sampling position corresponding to the first delay and the window center of the second parallel data. Number of steps When the sampling position corresponding to the second parallel data is at the window center of the second parallel data, the first delay Number of steps The second delay Number of steps The first delay is recorded as Number of steps is on the left side of the window center of the second parallel data, the time series training control module Number of steps Decreased delay Number of steps is sent to the delay stage selection module, and the delay of delay chain 2 is Number of steps Delay after reducing Number of steps and continues from the sampling position to the delay Number of steps and the window center of the first parallel data, and if the sampling position corresponding to the first delay stage is on the right side of the window center of the second parallel data, the time series training control module Number of steps Increased delay Number of steps is sent to the delay stage selection module, and the delay of delay chain 2 is Number of steps Delay after increasing Number of stepsand continues from the sampling position to the delay Number of steps and the relative position between the sampling position corresponding to the second parallel data window center, and the delay of the adjusted delay chain 2 Number of steps When the sampling position corresponding to is at the window center of the second parallel data, the delay of the delay chain 2 Number of steps The second delay Number of steps Record as.

[0031] In some embodiments, as shown in FIG. Number of steps 10 is a schematic diagram of the process of obtaining the relative position of the scanning data window center and the sampling position corresponding to S2 and S3; Number of steps and the relative position of the scan data window center, S51: Selecting one set of data from the first parallel data and the second parallel data as reference data, and collecting the other set of data as scan data, and delaying the scan data Number of steps is the delay corresponding to the scanning data in the first parallel data and the second parallel data. Number of steps and S52: The delay Number of steps gradually decreasing the value of the reference data and the scanned data and monitoring whether the reference data and the scanned data match within a specific time; S53: Match, said delay Number of steps If does not decrease to zero, repeat S52; If not, the delay Number of steps the first sub-delay Number of steps and proceeding to S54; S54: The delay Number of steps reloading the S55: The delay Number of steps stepwise increasing the value of the reference data and the scanned data, and monitoring whether the reference data and the scanned data match within a specific time; S56: Match, said delay Number of steps is delayed Number of stepsIf the maximum value of has not been reached, repeat S55. If not, the delay Number of steps The second sub-delay Number of steps and recording the S57: The delay Number of steps , the first sub-delay Number of steps and the second sub-delay Number of steps Based on the first sub-delay Number of steps Difference, Second Sub-Delay Number of steps Obtain the difference between the first sub-delay Number of steps the difference and the second sub-delay Number of steps Comparing the difference and delay Number of steps and obtaining the relative position of the scanning data window center corresponding to the sampling position.

[0032] Specifically, in this embodiment, when the time series training control module sends a sampling signal to the sampling position scanning module, the sampling position scanning module selects the delays corresponding to the scanning paths in the delay chain 1 and delay chain 2 determined by the time series training control module. Number of steps and select one set of data in the delay chain 1 or the delay chain 2 as reference data, and the remaining set as scan data. Number of steps the delays corresponding to the scan paths in delay chain 1 and delay chain 2 determined by the time series training control module. Number of steps Then, the delay Number of steps and monitor whether the reference data and the scanned data match within a specific time. Number of steps If does not decrease to zero, the delay Number of steps If there is no match, the delay Number of steps the first sub-delay Number of steps The delay is recorded as Number of steps and reload the delay Number of steps The delay is increased stepwise, and it is monitored whether the reference data and the scanned data match within a specific time. Number of steps is delayed Number of stepsIf the maximum value of Number of steps If they do not match, the delay Number of steps The second sub-delay Number of steps and then recorded as the delay Number of steps , the first sub-delay Number of steps and the second sub-delay Number of steps said delay based on Number of steps The relative position of the sampling position corresponding to the center of the scan data window is obtained.

[0033] In some embodiments, the delay provided by embodiments of the present invention, as shown in FIG. Number of steps , 1st sub-delay Number of steps and the second sub-delay Number of steps said delay based on Number of steps 10 is a schematic diagram showing the flow of obtaining the relative position of the sampling position and the scanning data window center corresponding to the step S57; S571: The delay Number of steps and the first sub-delay Number of steps The difference between the first sub-delay Number of steps the second sub-delay is the difference Number of steps and the delay Number of steps The difference between the second sub-delay Number of steps a step of subtracting S572: The first sub-delay Number of steps The difference is the second sub-delay Number of steps If the delay is greater than Number of steps the sampling position corresponding to is on the left side of the center of the scanning data window in the first parallel data and the second parallel data, The first sub-delay Number of steps The difference is the second sub-delay Number of steps If the delay is less than Number of steps the sampling position corresponding to is on the right side of the scanning data window center in the first parallel data and the second parallel data, The first sub-delay Number of steps The difference is the second sub-delay Number of steps If it is equal to Number of stepsa step in which the sampling position corresponding thereto is at the center of a scanning data window in the first parallel data and the second parallel data, and the method includes the step. Specifically, in this embodiment, the delay Number of steps is recorded as step0, the first sub-delay Number of steps is recorded as step1, and the second sub-delay Number of steps is recorded as step2. When step0-step1>step2-step0, the sampling position corresponding to step0 is on the left side of the center of the sampling data window in the first parallel data and the second parallel data. When step0-step1<step2-step0, the sampling position corresponding to step0 is on the right side of the center of the sampling data window in the first parallel data and the second parallel data. When step0-step1=step2-step0, the sampling position corresponding to step0 is at the center of the sampling data window in the first parallel data and the second parallel data. In some embodiments, the total delay of the first delay chain and the second delay chain is greater than the width of the serial data window.

[0034] In some embodiments, as shown in FIG. 6, it is a schematic diagram of the flow of another time series training method for an LVDS interface provided by the embodiment of the present invention. Before S1, S0: further includes a step of scrambling the LVDS differential data, converting it into serial data by parallel-to-serial conversion, and then inputting it into a delay chain. After S4, S6: further includes a step of descrambling and restoring the received LVDS differential data.

[0035] Specifically, in existing time series training methods in which the interface supports dynamic calibration of the sampling position, when there is no valid data on the interface, a constant 0 / constant 1 data stream continuously exists, causing window calibration to fail and the sampling position to deviate from the center of the data window. Therefore, in this embodiment, the LVDS differential data at the transmitting side of the LVDS transceiver in FIG. 2 is scrambled by a scrambling module, the parallel data is converted to serial data by a parallel-to-serial converter, and transmitted to the receiving side of the LVDS transceiver. The data output from the data path selection module at the receiving side of the LVDS transceiver is descrambled by a descrambling module. By scrambling and descrambling, the serial data stream becomes constant 0 / constant 1 when there is no valid data transmission on the transmitting side, preventing time series training and window calibration at the receiving side. This avoids the situation where the sampling position cannot be effectively obtained when there is no valid data for a long period of time.

[0036] In some embodiments, the delay Number of steps The smaller the difference, the greater the delay due to on-chip errors and P / N gradient asymmetry. Number of steps The difference becomes smaller.

[0037] Specifically, in this embodiment, the first delay Number of steps step_path1, second delay Number of steps When step_path2 is used, offset = step_path1 - step_path2 characterizes the asymmetry between path1 and path2 data due to the asymmetry of the slew between the P and N ends of the OCV and LVDS differential data. The smaller the offset, the smaller the delay due to the error on the same chip and the asymmetry of the slew between the P and N ends of the LVDS differential data. Number of steps The difference becomes smaller.

[0038] In some embodiments, as shown in FIG. 8, an embodiment of the present invention provides a time series training device for an LVDS interface, the device including: a conversion module 701 for inputting a P end of an LVDS differential data signal into a first delay chain and converting it into a first parallel data through serial-to-parallel conversion, and inputting an N end of the LVDS differential data signal into a second delay chain and converting it into a second parallel data through serial-to-parallel conversion; The second parallel data is used as reference data, and the first parallel data is used as scanning data, and data is sampled and delayed. Number of steps and the relative position of the scanning data window center corresponding to the sampling position, Number of steps If the sampling position corresponding to is located at the window center of the scan data, the delay Number of steps The first delay Number of steps a first sampling module 702 for recording the sampling data using the first parallel data as reference data and the second parallel data as scanning data; and Number of steps The first delay Number of steps and delay Number of steps and the relative position of the scanning data window center corresponding to the sampling position, Number of steps When the sampling position corresponding to is located at the window center of the scan data, the first delay Number of steps The second delay Number of steps a second sampling module 703 for recording the The first delay Number of steps and the second delay Number of steps Delay from Number of steps The difference is calculated, and the first delay Number of steps and the delay Number of steps The sum of half the difference is the delay of the first parallel data Number of steps and a data output routing module 704 for setting the second parallel data as scan data and receiving the LVDS differential data as scan data.

[0039] For specific limitations of the time-series training apparatus for LVDS interfaces, please refer to the limitations of the time-series training method for LVDS interfaces described above, and they will not be repeated here. All or part of the modules in the time-series training apparatus for LVDS interfaces can be realized by software, hardware, or a combination thereof. Each module may be built into a processor in a computer device in the form of hardware, or may be independent of the processor, or may be stored in a memory in a computer device in the form of software and called by the processor to perform operations corresponding to each module.

[0040] The terms used in the examples of the present invention are used only for the purpose of describing specific examples and are not intended to limit the present invention. As used in the examples of the present invention and the appended claims, the singular forms "a kind of," "the," and "the" include the plural forms unless the context clearly dictates otherwise.

[0041] Depending on the context, "if" as used herein shall be interpreted as "when" or "when" or "responsive to determining" or "responsive to detecting." Similarly, depending on the context, "determining" or "detecting (a stated condition or event)" shall be interpreted as "if it is determined" or "responsive to determining" or "detecting (a stated condition or event)" or "responsive to detecting (a stated condition or event)."

[0042] In some embodiments of the present invention, it should be understood that the disclosed devices and methods may be implemented in other forms. For example, the device embodiments described above are merely illustrative, and the division of the units is merely a division of logical functions. In reality, other division forms may be used. For example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not implemented. Furthermore, the illustrated or discussed couplings or direct couplings or communication connections between interfaces, devices or units may be indirect couplings or communication connections, which may be electrical, mechanical, or other types.

[0043] The above description is only a preferred embodiment of the present invention, and does not limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall all be included within the protection scope of the present invention.

Claims

1. S1: inputting the P end of the LVDS differential data signal into a first delay chain and converting it into a first parallel data by serial-to-parallel conversion, and inputting the N end of the LVDS differential data signal into a second delay chain and converting it into a second parallel data by serial-to-parallel conversion; S2: Sampling data using the second parallel data as reference data and the first parallel data as scan data, collecting a relative position between the sampling position corresponding to the current delay stage number and the window center of the scan data, and if the sampling position corresponding to the current delay stage number is located at the window center of the scan data, recording the current delay stage number as a first delay stage number; S3: Sampling data using the first parallel data as reference data and the second parallel data as scan data, setting the initial delay stage number of the second parallel data as the first delay stage number, collecting the relative position of the sampling position corresponding to the current delay stage number and the window center of the scan data, and if the sampling position corresponding to the current delay stage number is located at the window center of the scan data, recording the current first delay stage number as the second delay stage number; S4: calculating a difference in the number of delay stages from the first number of delay stages and the second number of delay stages, setting the sum of the first number of delay stages and half the difference in the number of delay stages as the number of delay stages of the first parallel data, and receiving the LVDS difference data as scan data of the second parallel data.

2. The S2 is S21: using the second parallel data as reference data, setting an initial delay stage number of the first parallel data for data sampling, and collecting the relative position corresponding to the initial delay stage number, wherein the initial delay stage number is smaller than the total delay stage number of the first delay chain; S22: If the sampling position corresponding to the initial delay stage number is on the left side of the window center of the first parallel data, decrease the initial delay stage number, update the decreased initial delay stage number to the initial delay stage number, and then collect the relative position again; If the sampling position corresponding to the initial delay stage is on the right side of the window center of the first parallel data, increasing the initial delay stage, updating the increased initial delay stage to the initial delay stage, and then collecting the relative position again; S23: A step of setting the initial delay number to the first delay number when a sampling position corresponding to the initial delay number is located at the window center of the first parallel data.

3. The S3 is S31: Scanning the first parallel data using the first delay stage number as reference data and setting the first delay stage number as an initial delay stage number of the second parallel data, and simultaneously collecting the relative position corresponding to the initial delay stage number; S32: If the sampling position corresponding to the initial delay stage number is on the left side of the window center of the second parallel data, decrease the initial delay stage number, update the decreased initial delay stage number to the initial delay stage number, and then collect the relative position again; If the sampling position corresponding to the initial delay stage is on the right side of the window center of the second parallel data, increasing the initial delay stage, updating the increased initial delay stage to the initial delay stage, and then collecting the relative position again; S33: A step of setting the initial delay number to the second delay number when a sampling position corresponding to the initial delay number is located at the window center of the second parallel data.

4. The step of collecting the relative positions of the sampling positions corresponding to the delay stages in S2 and S3 and the center of the scan data window includes: S51: A step of selecting one set of data from the first parallel data and the second parallel data as reference data, and collecting the other set of data as scan data, wherein the number of delay stages of the scan data is the number of delay stages corresponding to the scan data in the first parallel data and the second parallel data; S52: Stepwise decreasing the number of delay stages and monitoring whether the reference data and the scanning data match within a specific time; S53: If there is a match and the delay stage number is not reduced to zero, repeat S52; If not, record the delay stage number as a first sub-delay stage number, and proceed to S54; S54: Reloading the number of delay stages; S55: increasing the number of delay stages stepwise and monitoring whether the reference data and the scanning data match within a specific time; S56: If they match and the number of delay stages has not reached the maximum value, repeat S55; otherwise, recording the delay stage as a second sub-delay stage; S57: Obtaining a first sub-delay stage difference and a second sub-delay stage difference based on the delay stage number, the first sub-delay stage number and the second sub-delay stage number, comparing the first sub-delay stage difference with the second sub-delay stage difference, and obtaining a relative position between the sampling position corresponding to the delay stage number and the center of the scanning data window.

5. The step S57 is S571: A step of setting a difference between the number of delay stages and the first sub-delay stage number as the first sub-delay stage difference, and setting a difference between the second sub-delay stage number and the number of delay stages as the second sub-delay stage difference; S572: if the first sub-delay step difference is greater than the second sub-delay step difference, the sampling position corresponding to the delay step is on the left side of the scanning data window center in the first parallel data and the second parallel data; When the first sub-delay step difference is smaller than the second sub-delay step difference, the sampling position corresponding to the delay step is on the right side of the center of a scanning data window in the first parallel data and the second parallel data; 5. The time series training method for an LVDS interface according to claim 4, further comprising: when the first sub-delay stage difference is equal to the second sub-delay stage difference, the sampling position corresponding to the delay stage is at the center of a scanning data window in the first parallel data and the second parallel data.

6. 2. The time series training method for an LVDS interface according to claim 1, wherein a total delay of the first delay chain and the second delay chain is greater than a width of a serial data window.

7. Before S1, S0: further comprising the step of scrambling the LVDS differential data, converting it into serial data by parallel-to-serial conversion, and then inputting it into a delay chain; After S4, 2. The time series training method for an LVDS interface according to claim 1, further comprising the step of: S6: descrambling the received LVDS differential data.

8. 3. The time series training method for an LVDS interface according to claim 2, wherein the initial number of delay stages is half the total number of delay stages of the first delay chain.

9. 2. The time series training method for an LVDS interface according to claim 1, wherein the smaller the difference in the number of delay stages, the smaller the difference in the number of delay stages due to errors on the same chip and gradient asymmetry between the P terminal and the N terminal of the LVDS differential data.

10. a conversion module for inputting a P end of the LVDS differential data signal to a first delay chain and converting it into first parallel data through serial-to-parallel conversion, and inputting an N end of the LVDS differential data signal to a second delay chain and converting it into second parallel data through serial-to-parallel conversion; a first sampling module for sampling data using the second parallel data as reference data and the first parallel data as scan data, collecting a relative position between a sampling position corresponding to a current delay stage number and a window center of the scan data, and recording the current delay stage number as a first delay stage number when the sampling position corresponding to the current delay stage number is located at the window center of the scan data; a second sampling module for sampling data using the first parallel data as reference data and the second parallel data as scan data, setting an initial delay stage number of the second parallel data as the first delay stage number, collecting a relative position between a sampling position corresponding to a current delay stage number and a window center of the scan data, and recording the current first delay stage number as a second delay stage number when the sampling position corresponding to the current delay stage number is located at the window center of the scan data; a data output path determination module for determining a delay stage difference from the first delay stage number and the second delay stage number, setting the sum of the first delay stage number and half the delay stage difference as the delay stage number of the first parallel data, and receiving the LVDS difference data as the second parallel data as scan data.

Images