Cache control device, information processing device, cache control method, program, and recording medium

Abstract

To provide a cache controller capable of dynamically controlling writing onto a cache memory in an information processing device equipped with a nonvolatile memory device.SOLUTION: The cache controller comprises: an access request information acquisition unit for acquiring access request information; a cache memory control unit for controlling writing access-requested data onto a cache memory on the basis of the access request information and an access management table; and an access management table update unit for updating the access management table on the basis of the access request information. The access request information includes information regarding sections on a main memory having been accessed by an arithmetic processing device and information regarding access types. The control object of the cache memory control unit is the cache memory of the information processing device that includes a nonvolatile memory device as the main memory. The access management table includes access frequency information in which the accessed sections and the access types are associated.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a cache control device, an information processing device, a cache control method, a program, and a recording medium. [Background technology]

[0002] Generally, volatile memories such as DRAMs are used as main memories in information processing devices. On the other hand, in recent years, information processing devices have been known that use nonvolatile memory devices as main memories, which do not lose stored information even when the power supply is lost (having nonvolatility) (Patent Documents 1 and 2, etc.). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2021-520021 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-095001 Summary of the Invention [Problem to be solved by the invention]

[0004] As mentioned above, non-volatile memory devices can be used as main memory in the same way as regular RAM such as DRAM, and have the characteristic that the information stored in them does not volatilize even when the power is turned off (non-volatile). However, because cache memory installed in CPUs and other devices is volatile, there is a problem in that information in cache memory that is not written back to the non-volatile memory device (cache flushing) will volatilize when power is lost.

[0005] In response to this, it is known that the non-temporal store command can be used to prevent data from being stored in cache memory. However, since the non-temporal store command cannot be dynamically controlled, it has the problem that it can only be used for data that is known to be accessed infrequently (for example, log dumps).

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a cache control device capable of dynamically controlling writing to a cache memory in an information processing device equipped with a nonvolatile memory device. [Means for solving the problem]

[0007] In order to achieve the above object, a cache control device of an information processing device of the present invention comprises: an access request information acquisition unit, a cache memory control unit, and an access management table update unit; the access request information acquisition unit acquires access request information from a processing unit to a main memory; the access request information includes information about a section in the main memory accessed by the arithmetic processing unit and information about a type of access; a control target of the cache memory control unit is a cache memory of an information processing device that includes a nonvolatile memory device as a main memory, the cache memory control unit controls writing of data requested for access by the arithmetic processing unit to the cache memory based on the access request information and the access management table; the access management table includes access frequency information; the access frequency information is information in which sections accessed by the arithmetic processing device are associated with types of access; The access management table update unit updates the access management table based on the access request information.

[0008] The cache control method for an information processing device of the present invention comprises: The method includes an access request information acquisition step, a cache memory control step, and an access management table update step, the access request information acquisition step acquires access request information to a main memory by an arithmetic processing unit; the access request information includes information about a section in the main memory accessed by the arithmetic processing unit and information about a type of access; a control target of the cache memory control step is a cache memory of an information processing device that includes a nonvolatile memory device as a main memory; the cache memory control step controls writing of data requested for access by the arithmetic processing unit into the cache memory based on the access request information and the access management table; the access management table includes access frequency information; the access frequency information is information in which sections accessed by the arithmetic processing device are associated with types of access; The access management table updating step updates the access management table based on the access request information.

[0009] The program of the present invention is a program for causing a computer to execute an access request information acquisition procedure, a cache memory control procedure, and an access management table update procedure, the step of acquiring access request information includes acquiring access request information to a main memory by an arithmetic processing unit; the access request information includes information about a section in the main memory accessed by the arithmetic processing unit and information about a type of access; a control target of the cache memory control procedure is a cache memory of an information processing device that includes a nonvolatile memory device as a main memory; the cache memory control step controls writing of data requested for access by the arithmetic processing unit to the cache memory based on the access request information and the access management table; the access management table includes access frequency information; the access frequency information is information in which sections accessed by the arithmetic processing device are associated with types of access; The access management table update procedure is a program that updates the access management table based on the access request information. [Effects of the Invention]

[0010] According to the present invention, in an information processing device equipped with a nonvolatile memory device, writing to a cache memory can be dynamically controlled. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an information processing device including a cache control device according to the first embodiment. [Figure 2] FIG. 2 is a block diagram illustrating an example of a hardware configuration of an information processing device including the cache control device of the first embodiment. [Figure 3] FIG. 3 is a flowchart illustrating an example of processing in the cache control device of the first embodiment. [Figure 4] FIG. 4 is a schematic diagram illustrating an example of an interval tree structure. [Figure 5] FIG. 5 is a schematic diagram showing an example of a method for creating an access management table. DETAILED DESCRIPTION OF THE INVENTION

[0012] In the present invention, a non-volatile memory device (also referred to as a non-volatile memory) refers to, for example, a non-volatile storage device that can be used as a main memory. Specific examples of non-volatile memory devices that can be used as the main memory include Intel Optane Persistent Memory from Intel Corporation.

[0013] In the present invention, the cache memory is not particularly limited as long as it is a cache memory provided in a processing unit, and may be a CPU cache memory such as an L1 cache, an L2 cache, or an L3 cache, a GPU cache memory, or even a cache memory provided in other processing units.

[0014] Embodiments of the present invention will be described with reference to the drawings. The present invention is not limited to the following embodiments. In the following drawings, the same parts are denoted by the same reference numerals. Furthermore, the descriptions of the embodiments can be mutually incorporated unless otherwise specified, and the configurations of the embodiments can be combined unless otherwise specified.

[0015] [Embodiment 1] 1 is a block diagram showing an example of the configuration of an information processing device 100 including a cache control device 10 of this embodiment. As shown in FIG. 1, the information processing device 100 includes, for example, a cache control unit (cache control device) 10 and a main memory (not shown in FIG. 1), and the main memory includes the non-volatile memory device. Although not shown, the information processing device 100 may also include, for example, a storage unit. The cache control device 10 includes an access request information acquisition unit 11, a cache memory control 12, and an access management table update unit 13.

[0016] The information processing device 100 is an information processing device that includes a nonvolatile memory device as a main memory. In this embodiment, the cache control device 10 is an integrated device with the information processing device 100, but, for example, the cache control device 10 and the information processing device 100 may be separate devices. In the latter case, the cache control device 10 and the information processing device 100 can be connected, for example, by communication, and the connection method may be wired or wireless.

[0017] The information processing device 100 may be, for example, a single device including the above-described units, or a device in which the units can be connected via a communication network. The information processing device 100 can also be connected to an external device (described later) via the communication network. The communication network is not particularly limited and any known network can be used, for example, a wired or wireless network. Examples of the communication network include the Internet, the World Wide Web (WWW), a telephone line, a Local Area Network (LAN), a Storage Area Network (SAN), a Delay Tolerant Networking (DTN), a Low Power Wide Area Network (LPWA), and a Local 5G (L5G). Examples of wireless communication include Wi-Fi (registered trademark), Bluetooth (registered trademark), Local 5G, and LPWA. Examples of the wireless communication include direct communication between devices (Ad Hoc communication), infrastructure communication, and indirect communication via an access point. The information processing device 100 may be incorporated into a server as a system. Furthermore, the information processing device 100 may be, for example, a personal computer (PC, for example, a desktop or notebook type) on which the program of the present invention is installed, a smartphone, a tablet terminal, etc. The information processing device 100 may be in the form of cloud computing or edge computing, for example, in which at least one of the units is located on a server and the other units are located on a terminal.

[0018] 2 illustrates a block diagram of a hardware configuration of an information processing device 100 including a cache control device 10. The information processing device 100 includes, for example, a CPU 101, a memory 102, a bus 103, a storage device 104, an input device 106, a display (display device) 107, a communication device (communication unit) 108, and a cache control unit 10. The units of the information processing device 100 are connected to each other via the bus 103 and their respective interfaces (I / F).

[0019] The CPU 101 cooperates with other components via, for example, a controller (such as a system controller or an I / O controller) and controls the entire information processing device 100. As shown in FIG. 2, the CPU 101 includes a cache memory 1011. In FIG. 2, the CPU 101 includes one cache memory 1011, but the present invention is not limited to this, and the CPU 101 may include multiple cache memories 1011 (not shown). In the information processing device 100, the CPU 101 executes, for example, the program 105 of the present invention and other programs, and also reads and writes various types of information. Specifically, for example, the CPU 101 reads a target software program and functions as the target software. The information processing device 100 includes a CPU as a computing device, but may also include other computing devices such as a GPU (Graphics Processing Unit) or an APU (Accelerated Processing Unit), or may include a combination of the CPU and these.

[0020] The bus 103 can also be connected to, for example, an external device. Examples of the external device include an external storage device (such as an external database), a printer, an external input device, an external display device, and an external imaging device. The information processing device 100 can be connected to an external network (the communication line network) by, for example, a communication device 107 connected to the bus 103, and can also be connected to other devices via the external network.

[0021] An example of the memory 102 is a main memory (primary storage device). The main memory is, for example, the nonvolatile memory device described above. When the CPU 101 performs processing, the CPU 101 can read programs such as target software stored in the memory 102 and execute the programs. Note that the present invention is not limited to this. For example, when the CPU 101 performs processing, the memory 102 can read various operation programs such as the program 105 of the present invention stored in the storage device 104 described below, and the CPU 101 can receive data from the memory 102 and execute the programs.

[0022] The storage device 104 is also referred to as an auxiliary storage device, for example, in contrast to the main memory (primary storage device). As described above, the storage device 104 stores an operating program including the program of the present invention. The storage device 104 may be, for example, a combination of a recording medium and a drive that reads and writes data from and to the recording medium. The recording medium is not particularly limited and may be, for example, an internal or external type, such as a hard disk (HD), CD-ROM, CD-R, CD-RW, MO, DVD, flash memory, or memory card. The storage device 104 may be, for example, a hard disk drive (HDD) or a solid state drive (SSD) in which the recording medium and drive are integrated.

[0023] In the information processing device 100, the memory 102 and the storage device 104 can also store various information such as log information, information acquired from an external database (not shown) or an external device, information generated by the information processing device 100, and information used when the information processing device 100 executes processing. Note that at least a portion of the information may be stored, for example, in an external server other than the memory 102 and the storage device 104, or may be stored in a distributed manner across multiple terminals using blockchain technology or the like.

[0024] The information processing device 100 further includes, for example, an input device 106 and a display 107. Examples of the input device 106 include pointing devices such as a touch panel, track pad, and mouse; a keyboard; imaging means such as a camera and scanner; card readers such as an IC card reader and a magnetic card reader; and audio input means such as a microphone. Examples of the display 107 include display devices such as an LED display and a liquid crystal display. In the first embodiment, the input device 106 and the display 107 are configured separately, but the input device 106 and the display 107 may be configured as an integrated unit, such as a touch panel display.

[0025] Next, an example of the cache control method of this embodiment will be described with reference to the flowchart of Fig. 3. The cache control method of this embodiment is implemented as follows, for example, using the cache control device 10 of Fig. 1 or 2. Note that the cache control method of this embodiment is not limited to use of the cache control device 10 of Fig. 1 or 2.

[0026] First, prior to processing by the cache control device 10, an access management table is prepared. The access management table includes access frequency information. The access frequency information is information linking an interval in the main memory (memory 102) accessed by the arithmetic processing device (CPU 101) with the type of access. For example, the start and end points of the interval are linked with information on whether the type of access is write access or read access. The access management table can be created using any data structure, such as an interval tree structure, a list structure, a B-tree structure, or a red-black tree structure. Since the access management table is a table that holds data intervals, it is preferable to create it using an interval tree structure that can handle intervals. Furthermore, an interval tree structure is preferable because it allows the cache memory control unit 12, described later, to quickly search for the access frequency of an interval requested by the arithmetic processing device. If the access management table has a list structure, for example, an entry may be updated if the address range existing in the entry partially overlaps with the address range to be newly accessed. By constructing a list structure in this way, it is possible to reduce the cost of searching the access management table, for example.

[0027] The interval tree structure will be described with reference to FIG. 4. For example, the interval tree structure identifies the center point x of the range containing all intervals in the main memory, as indicated by the dashed line x in FIG. 4. This allows all intervals in the main memory to be classified into three types: Center, which is the group of intervals containing the center point x (the group of intervals shown in black in the top node of FIG. 4); Left, which is the group of intervals within a range smaller than the center point x (the group of intervals shown in white on the left side of the top node of FIG. 4); and Right, which is the group of intervals within a range larger than the center point x (the group of intervals shown in white on the right side of the top node of FIG. 4). Next, as shown in the middle and bottom nodes of FIG. 4, the Left and Right group of intervals are similarly divided until all intervals are in the Center. This allows the group of intervals belonging to the Center to be included in two lists linked to each node of the tree, namely, a list in which the group of intervals is sorted by the starting point, and a list in which the group of intervals is sorted by the end point. As a result, each node in the interval tree stores data such as the position of the center point x, a pointer to the left node, a pointer to the right node, a list of intervals (Center) containing the center point x sorted by their starting points, and a list of intervals (Center) containing the center point x sorted by their ending points.

[0028] Next, an example of constructing an access management table with an interval tree structure will be described with reference to FIG. 5. First, from the access frequency information, the start and end points of intervals accessed by the arithmetic processing unit (CPU 101) and information indicating whether the access is write or read are prepared as an array of interval structures (struct interval), and an interval tree is constructed using pointers to the interval structures in the array. By constructing the access management table in this manner, for example, it is possible to manage interval structures for each interval and delete intervals after a predetermined time has passed. Note that the criteria for deleting interval structures are not limited to this. For example, a memory area may be allocated for the interval structure array and interval structures that overflow from the memory area may be deleted, or interval structures may be linked together using an LRU (Least Recently Used) list, and when the number of interval structures linked in the list exceeds a threshold, the oldest interval structure (i.e., the interval that was accessed least recently) may be deleted.

[0029] When the cache control device 10 detects an access request to the main memory 102 from the CPU 101 (processing unit) of the information processing device 100, the cache control device 10 acquires access request information from the CPU 101 (processing unit) of the information processing device 100 to the main memory 102 by the access request information acquisition unit 11 (S1, access request information acquisition step). The access request information includes information on the section in the main memory accessed by the processing unit and information on the type of access. The section information is information that specifies the location in the main memory accessed by the processing unit, and includes, for example, information on the start and end points of the access section. The access type information is, for example, information on whether the access by the CPU 101 is a write access or a read access.

[0030] Next, the cache memory control unit 12 controls writing of the data requested to be accessed by the arithmetic processing unit into the cache memory based on the access request information and the access management table (S2, cache memory control step). As described above, the cache memory control unit 12 controls the cache memory of the information processing unit 100, which has a nonvolatile memory device as its main memory.

[0031] Specifically, for example, the cache memory control unit 12 first determines whether the type of access by the arithmetic processing unit is a write access based on the access request information (S2A). If the access is not a write access (for example, a read access) (S2A, No), the cache memory control unit 12 may, for example, terminate the process or control the arithmetic processing unit to read from the cache memory (S2E). Furthermore, for example, if the target data is not in the cache memory (in the case of a cache miss), the cache memory control unit 12 may further control the arithmetic processing unit to read from the main memory.

[0032] Then, the access management table update unit 13 updates the access management table based on the access request information (S3, access management table update step), and terminates the processing by the cache control device 10 (END). The access management table update unit 13 can update the access management table, for example, by identifying the start and end points of the interval for which an access request has been made from the arithmetic processing device based on the access request information, and further by linking the type of access to the interval information and adding it to the access management table.

[0033] If the type of access is a write access (S2A, Yes), the cache memory control unit 12 refers to the access management table (S2B) and determines whether the access frequency to the section on the main memory where the data is stored is equal to or greater than a threshold (S2C). The cache memory control unit 12 may determine, for example, whether at least one of the read access frequency and the write access frequency to the section is equal to or greater than a threshold, or may determine either one or both. The threshold is not particularly limited and can be set to any value, and different values ​​may be set for write access and read access, or the same value may be set. The threshold can be set to any value appropriate for the workload of the program execution environment, for example. As a specific example, the threshold for write access can be set to 50% of the cache size, and the threshold for read access can be set to 50% of the cache size. If the access frequency is equal to or greater than the threshold (S2C, Yes), the cache memory control unit 12 writes the data to the cache memory (S2D), and if the access frequency is less than the threshold (S2C, No), the cache memory control unit 12 writes the data to the main memory (S2F). Furthermore, if different threshold values ​​are set for read access and write access, the cache memory control unit 12 can determine the access frequency by using, for example, a threshold corresponding to the type of access for which an access request has been made from the arithmetic processing unit.

[0034] S2 will be described in more detail. First, the cache memory control unit 12 identifies an access request section in the main memory that the arithmetic processing unit is attempting to access, for example, based on the access request information. Then, by referring to the access management table, it searches whether a section including the start point or end point of the access request section is recorded as the access frequency information. For example, if a section including the start point or end point of the access request section is recorded as the access frequency information, the cache memory control unit 12 counts the number of accesses for that section, assuming that the section has been accessed in the past. Next, the cache memory control unit 12 searches for a section that completely includes the access request section. For example, the cache memory control unit 12 compares an arbitrary point p within the access request section with the center point x of the access management table. If point p is smaller than the central point x, the cache memory control unit 12 searches for a section whose starting point is smaller than point p, and if point p is larger than the central point x, it searches for a section whose ending point is larger than p. If these sections are recorded as access frequency information, the cache memory control unit 12 counts the number of accesses for these sections as sections that have been accessed in the past. Also, if point p is the same point as the central point x, the cache memory control unit 12 counts the number of accesses for all sections within that node as sections that have been accessed in the past. Then, the cache memory control unit 12 can determine whether the access frequency of the access request section exceeds the threshold by determining whether the total number of accesses exceeds the threshold.

[0035] Next, the access management table update unit 13 updates the access management table based on the access request information (S3, access management table update step), and ends the processing by the cache control device 10 (END). The processing by the access management table update unit 13 is, for example, as described above.

[0036] The access management table update unit 13 may rebuild the access management table after a predetermined time has elapsed. If the access management table has, for example, an interval tree structure, if intervals are continuously added to the tree, the center point x at each node will no longer match the actual situation, so it is desirable to periodically rebuild the tree using the intervals that have already been added.

[0037] According to the cache control device 10 of this embodiment, for example, when a write access request is received from the arithmetic processing unit, the cache memory control unit 12 can dynamically control whether to write to the cache memory or to the main memory based on the access frequency of the relevant section contained in the access management table. Therefore, the cache control device of the present invention can avoid writing infrequently accessed data to the cache memory, thereby achieving effects such as reducing cache flush overhead, preserving cache memory, and avoiding CPU cache memory searches during access.

[0038] [Embodiment 2] The program of this embodiment is a program for causing a computer to execute each step of the cache control method described above. Specifically, the program of this embodiment is a program for causing a computer to execute an access request information acquisition procedure, a cache memory control procedure, and an access management table update procedure.

[0039] the step of acquiring access request information includes acquiring access request information to a main memory by an arithmetic processing unit; the access request information includes information about a section in the main memory accessed by the arithmetic processing unit and information about a type of access; a control target of the cache memory control procedure is a cache memory of an information processing device that includes a nonvolatile memory device as a main memory; the cache memory control step controls writing of data requested for access by the arithmetic processing unit to the cache memory based on the access request information and the access management table; the access management table includes access frequency information; the access frequency information is information in which sections accessed by the arithmetic processing device are associated with types of access; The access management table update procedure updates the access management table based on the access request information.

[0040] The program of this embodiment can also be said to be a program that causes a computer to function as an access request information acquisition procedure, a cache memory control procedure, and an access management table update procedure.

[0041] The program of this embodiment can be implemented by invoking the descriptions of the cache control device and cache control method of the present invention. For each of the steps, for example, "step" can be read as "processing." The program of this embodiment may also be recorded on a computer-readable recording medium. The recording medium is, for example, a non-transitory computer-readable storage medium. The recording medium is not particularly limited, and examples include random access memory (RAM), read-only memory (ROM), hard disk (HD), optical disk, and floppy disk (FD).

[0042] Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

[0043] <Additional Notes> Some or all of the above embodiments can be described as, but not limited to, the following supplementary notes. (Appendix 1) an access request information acquisition unit, a cache memory control unit, and an access management table update unit; the access request information acquisition unit acquires access request information from a processing unit to a main memory; the access request information includes information about a section in the main memory accessed by the arithmetic processing unit and information about a type of access; a control target of the cache memory control unit is a cache memory of an information processing device that includes a nonvolatile memory device as a main memory, the cache memory control unit controls writing of data requested for access by the arithmetic processing unit to the cache memory based on the access request information and the access management table; the access management table includes access frequency information; the access frequency information is information in which sections accessed by the arithmetic processing device are associated with types of access; The access management table update unit updates the access management table based on the access request information. (Appendix 2) the cache memory control unit determines whether the type of access is a write access based on the access request information; If the type of access is a write access, refer to the access management table and determine whether the frequency of access to the section on the main memory in which the data is stored is equal to or greater than a threshold value; If the access frequency is equal to or greater than the threshold, the data is written to a cache memory; 2. The cache control device according to claim 1, wherein the data is written to a main memory if the access frequency is less than the threshold. (Appendix 3) The cache memory control unit 3. The cache control device according to claim 1, wherein if the type of access is a read access, the cache control device controls the processor to read from the cache memory. (Appendix 4) 4. The cache control device according to claim 1, wherein the access management table has an interval tree structure. (Appendix 5) a cache controller and a main memory, the main memory includes a non-volatile memory device; 5. An information processing device, wherein the cache control unit is a cache control device according to any one of Supplementary notes 1 to 4. (Appendix 6) The method includes an access request information acquisition step, a cache memory control step, and an access management table update step, the access request information acquisition step acquires access request information to a main memory by an arithmetic processing unit; the access request information includes information about a section in the main memory accessed by the arithmetic processing unit and information about a type of access; a control target of the cache memory control step is a cache memory of an information processing device that includes a nonvolatile memory device as a main memory; the cache memory control step controls writing of data requested for access by the arithmetic processing unit into the cache memory based on the access request information and the access management table; the access management table includes access frequency information; the access frequency information is information in which sections accessed by the arithmetic processing device are associated with types of access; The access management table updating step updates the access management table based on the access request information. (Appendix 7) The cache memory control step determines whether the type of access is a write access based on the access request information, If the type of access is a write access, refer to the access management table and determine whether the frequency of access to the section on the main memory in which the data is stored is equal to or greater than a threshold value; If the access frequency is equal to or greater than the threshold, the data is written to a cache memory; 7. The cache control method according to claim 6, wherein if the access frequency is less than the threshold, the data is written to a main memory. (Appendix 8) The cache memory control step includes: 8. The cache control method according to claim 6, further comprising controlling a processor to read from a cache memory when the type of access is a read access. (Appendix 9) 8. The cache control method according to claim 6, wherein the access management table has an interval tree structure. (Appendix 10) A program for causing a computer to execute an access request information acquisition procedure, a cache memory control procedure, and an access management table update procedure, the step of acquiring access request information includes acquiring access request information to a main memory by an arithmetic processing unit; the access request information includes information about a section in the main memory accessed by the arithmetic processing unit and information about a type of access; a control target of the cache memory control procedure is a cache memory of an information processing device that includes a nonvolatile memory device as a main memory; the cache memory control step controls writing of data requested for access by the arithmetic processing unit to the cache memory based on the access request information and the access management table; the access management table includes access frequency information; the access frequency information is information in which sections accessed by the arithmetic processing device are associated with types of access; The access management table update procedure updates the access management table based on the access request information. (Appendix 11) The cache memory control procedure determines whether the type of access is a write access based on the access request information; If the type of access is a write access, refer to the access management table and determine whether the frequency of access to the section on the main memory in which the data is stored is equal to or greater than a threshold value; If the access frequency is equal to or greater than the threshold, the data is written to a cache memory; 11. The program of claim 10, wherein if the access frequency is less than the threshold, the data is written to a main memory. (Appendix 12) The cache memory control procedure includes: 12. The program according to claim 10, wherein the program controls a processor to read from a cache memory when the type of access is a read access. (Appendix 13) 13. The program according to any one of appendices 10 to 12, wherein the access management table has an interval tree structure. (Appendix 14) A computer-readable recording medium having recorded thereon a program according to any one of appendices 10 to 13. [Industrial Applicability]

[0044] According to the present invention, in an information processing device having a nonvolatile memory device as a main memory, writing to a cache memory can be dynamically controlled. Therefore, the present invention is useful in, for example, various fields that utilize information processing devices. [Explanation of symbols]

[0045] 100 Information processing device 10 Cache control device (cache control unit) 11. Access request information acquisition unit 12 Access management table creation section 13 Cache memory control unit 101 CPU 102 memory 103 Bus 104 Storage device 105 Programs 106 Input Device 107 Display device 108 Communication Devices

Claims

1. an access request information acquisition unit, a cache memory control unit, and an access management table update unit; the access request information acquisition unit acquires access request information from a processing unit to a main memory; the access request information includes information about a section in the main memory accessed by the arithmetic processing unit and information about a type of access; a control target of the cache memory control unit is a cache memory of an information processing device that includes a nonvolatile memory device as a main memory, the cache memory control unit controls writing of data requested for access by the arithmetic processing unit to the cache memory based on the access request information and the access management table; the access management table includes access frequency information; the access frequency information is information in which sections accessed by the arithmetic processing device are associated with types of access; The access management table update unit updates the access management table based on the access request information.

2. the cache memory control unit determines whether the type of access is a write access based on the access request information; If the type of access is a write access, refer to the access management table and determine whether the frequency of access to the section on the main memory in which the data is stored is equal to or greater than a threshold value; If the access frequency is equal to or greater than the threshold, the data is written to a cache memory; The cache control device according to claim 1 , wherein if the access frequency is less than the threshold, the data is written to the main memory.

3. The cache memory control unit 3. A cache control device according to claim 1, wherein if the type of access is a read access and the target data is in the cache memory, the processor is controlled to read from the cache memory, and if the type of access is a read access and the target data is not in the cache memory, the processor is controlled to read from the main memory.

4. 4. The cache control device according to claim 1, wherein the access management table has an interval tree structure.

5. a cache controller and a main memory, the main memory includes a non-volatile memory device; The information processing device, wherein the cache control unit is a cache control device according to claim 1 .

6. The method includes an access request information acquisition step, a cache memory control step, and an access management table update step, the access request information acquisition step acquires access request information to a main memory by an arithmetic processing unit; the access request information includes information about a section in the main memory accessed by the arithmetic processing unit and information about a type of access; a control target of the cache memory control step is a cache memory of an information processing device that includes a nonvolatile memory device as a main memory; the cache memory control step controls writing of data requested for access by the arithmetic processing unit into the cache memory based on the access request information and the access management table; the access management table includes access frequency information; the access frequency information is information in which sections accessed by the arithmetic processing device are associated with types of access; The access management table updating step updates the access management table based on the access request information.

7. The cache memory control step determines whether the type of access is a write access based on the access request information, If the type of access is a write access, refer to the access management table and determine whether the frequency of access to the section on the main memory in which the data is stored is equal to or greater than a threshold value; If the access frequency is equal to or greater than the threshold, the data is written to a cache memory; The cache control method according to claim 6 , wherein if the access frequency is less than the threshold, the data is written to the main memory.

8. The cache memory control step includes:

8. A cache control method according to claim 6, further comprising: controlling a processor to read from the cache memory when the type of access is a read access and the target data is in the cache memory; and controlling a processor to read from the main memory when the type of access is a read access and the target data is not in the cache memory.

9. A program for causing a computer to execute an access request information acquisition procedure, a cache memory control procedure, and an access management table update procedure, the step of acquiring access request information includes acquiring access request information to a main memory by an arithmetic processing unit; the access request information includes information about a section in the main memory accessed by the arithmetic processing unit and information about a type of access; a control target of the cache memory control procedure is a cache memory of an information processing device that includes a nonvolatile memory device as a main memory; the cache memory control step controls writing of data requested for access by the arithmetic processing unit to the cache memory based on the access request information and the access management table; the access management table includes access frequency information; the access frequency information is information in which sections accessed by the arithmetic processing device are associated with types of access; The access management table update procedure updates the access management table based on the access request information.

10. A computer-readable recording medium on which the program according to claim 9 is recorded.

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