Memory operations using combined memory commands

Abstract

A memory operation using the composite memory command includes a memory module receiving a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in the memory module, generating a plurality of memory commands to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command, and executing the plurality of memory commands.

Description

[Background technology]

[0001] To perform an in-memory operation, a processor needs to send a large number of fine-grained memory commands. The throughput of an in-memory operation depends on the bandwidth available to send such fine-grained commands to the memory. In addition to in-core bottlenecks that limit this command bandwidth, this bandwidth is also affected by the bandwidth utilization of other co-scheduled computations running in parallel on the associated core. [Brief explanation of the drawings]

[0002] [Figure 1] FIG. 1 is a block diagram of an exemplary processor for memory operations using composite memory commands, according to some embodiments. [Figure 2] 1 is a flowchart of an exemplary method for memory operations using composite memory commands, according to some embodiments. [Figure 3] 1 is a flowchart of an exemplary method for memory operations using composite memory commands, according to some embodiments. [Figure 4] 1 is a flowchart of an exemplary method for memory operations using composite memory commands, according to some embodiments. [Figure 5] 1 is a flowchart of an exemplary method for memory operations using composite memory commands, according to some embodiments. [Figure 6] 1 is a flowchart of an exemplary method for memory operations using composite memory commands, according to some embodiments. [Figure 7] 1 is a flowchart of an exemplary method for memory operations using composite memory commands, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0003] In some embodiments, a method of memory operation using a composite memory command includes: a memory module receiving a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory within the memory module; generating a plurality of memory commands to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command; and executing the plurality of memory commands.

[0004] In some embodiments, the composite memory command indicates a starting memory address and a number of columns for the multiple portions of contiguous memory. In some embodiments, the composite memory command indicates a starting address and an ending address for the multiple portions of contiguous memory. In some embodiments, generating the multiple memory commands includes determining one or more required row activation commands and generating the one or more required row activation commands. In some embodiments, determining the one or more required row activation commands includes maintaining a finite state machine and determining the one or more required row activation commands based on the finite state machine, the starting address, and the ending address. In some embodiments, the method further includes the memory controller determining a latency associated with the composite memory command. In some embodiments, the method further includes the memory controller prioritizing the issuance of one or more other commands based on the latency. In some embodiments, the method further includes the memory controller generating multiple other composite memory commands based on the composite memory command in response to the latency exceeding a threshold.

[0005] In some embodiments, an apparatus for memory operations using composite memory commands includes a processor, a memory controller communicatively coupled to the processor, and a memory module communicatively coupled to the memory controller, wherein the memory module performs steps including receiving the composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in the memory module, generating a plurality of memory commands to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command, and executing the plurality of memory commands.

[0006] In some embodiments, the composite memory command indicates a starting memory address and a number of columns for multiple portions of contiguous memory. In some embodiments, the composite memory command indicates a starting address and an ending address for the multiple portions of contiguous memory. In some embodiments, generating the multiple memory commands includes determining one or more required row activation commands and generating the one or more required row activation commands. In some embodiments, determining the one or more required row activation commands includes maintaining a finite state machine and determining the one or more required row activation commands based on the finite state machine, the starting address, and the ending address. In some embodiments, the memory controller determines a latency associated with the composite memory command. In some embodiments, the memory controller prioritizes the issuance of one or more other commands based on the latency. In some embodiments, the memory controller generates multiple other composite memory commands based on the composite memory command in response to the latency exceeding a threshold.

[0007] A memory controller for memory operations using composite memory commands performs steps including receiving a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in a memory module, generating a plurality of memory commands to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command, and executing the plurality of memory commands.

[0008] In some embodiments, the composite memory command indicates a starting memory address and a number of columns for the multiple portions of contiguous memory. In some embodiments, the composite memory command indicates a starting address and an ending address for the multiple portions of contiguous memory. In some embodiments, generating the multiple memory commands includes determining one or more required row activate commands and generating the one or more required row activate commands.

[0009] 1 is a block diagram of a non-limiting exemplary system 100. The exemplary system 100 can be implemented in a variety of computing devices, including a mobile device, a personal computer, a server, a peripheral hardware component, a gaming device, a set-top box, etc. The processing system 100 includes a processor 102. The processor 102 issues instructions or commands to access a memory module 104 by issuing commands to a memory controller 106. The memory controller 106 is circuitry for managing the flow of data to and from the memory module 104. For example, the memory controller 106 manages instructions to read from and / or write to the memory module 104. The memory controller 106 also refreshes the memory module 104. In some embodiments, the memory controller 106 is an integral component of the processor 102. In other embodiments, the memory controller 106 is a separate component from the processor 102.

[0010] The memory modules 104 are memory (e.g., volatile or non-volatile) used to store data. In an exemplary embodiment, the memory modules 104 are volatile memory modules. The memory modules 104 may comprise, for example, dynamic random access memory (DRAM). Each memory module 104 includes one or more banks 108. Each bank 108 includes multiple rows 110, and each row 110 includes multiple columns 112. To access data from a particular row 110, the row 110 is "activated" and stored in a row buffer of the bank 108. The columns 112 of the row 110 in the row buffer can then be read or written. Thus, accessing data in a particular row 110 requires closing the "open" row 110, assuming that the particular row 110 is not an open row 110 in the row buffer, and that the particular row 110 is opened and stored in the row buffer for access.

[0011] Operations such as bulk copy, bulk "zeroing," or in-memory computing (processing-in-memory) commands traditionally require the processor 102 to issue multiple fine-grained commands to the memory controller 106 for issuance to the memory module 104. Using this approach, bandwidth between the processor 102 and the memory controller 106 is consumed by these multiple fine-grained commands, impacting the bandwidth available for other computations running on the processor 102.

[0012] Instead, memory module 104 is configured to receive composite memory commands from processor 102 via memory controller 106. A composite memory command is a single command that applies one or more operations to a contiguous region of memory (e.g., within memory module 104). In some embodiments, the operation is applied to a specific column 112 of memory module 104. Some examples of operations applied by a composite memory command include a read operation of column 112, a write operation of column 112, or moving a column 112 to an adjacent memory register. For example, a composite memory command for bulk zeroing would apply a write operation of column 112 to each column 112 in a contiguous region of memory. As another example, an in-memory computing command to add two arrays (e.g., two contiguous arrays in memory) is expressed as multiple composite memory commands (e.g., a composite memory command to read multiple portions of data from each array, a composite memory command to add multiple portions of the two arrays, and a composite memory command to write the resulting sum to another contiguous region of memory). In some embodiments, the composite memory command is generated by a compiler in response to a determination that one or more operations apply to a contiguous region of memory, while in other embodiments, the composite memory command is generated by a compiler in response to an explicitly declared composite memory command in the program code.

[0013] In response to receiving the composite memory command, the memory module 104 generates multiple memory commands to apply one or more operations to each of multiple portions of contiguous memory. As an example, in response to receiving a composite memory command to bulk zero a contiguous region of memory, the memory module 104 generates multiple column 112 write commands that, when executed, cause zero values ​​to be written to each column 112 in the contiguous region of memory. Using this example, the memory module 104 generates necessary row open commands, if any, and generates multiple write commands to the contiguous region of memory. In this manner, multiple memory commands (e.g., dynamic random access memory commands) are generated from a single composite memory command. Those skilled in the art will understand that in alternative embodiments, multiple memory commands are generated by the memory controller 106 in response to receiving the composite memory command from a memory client (e.g., the processor 102). The memory controller 106 then provides the generated memory commands to the memory module 104 for execution.

[0014] In some embodiments, the composite memory command indicates a starting address for a region of contiguous memory and the number of columns to which the operations indicated in the composite memory command are to be applied. In other embodiments, the composite memory command indicates a starting address and an ending address for the region of contiguous memory. In some embodiments, multiple portions of contiguous memory are contiguous within the same row 110. In other words, one or more operations are applied to portions of memory located within the same row 110 in the memory module 104. In response to such a composite memory command, the memory module 104 generates memory commands that result in the indicated operations for each column in the contiguous region of memory. In some embodiments, the memory module 104 determines whether a row activation command needs to be generated as one of the multiple memory commands (e.g., to store the row 110 in a row buffer). Whether a row activation command is needed is based on whether the particular row 110 is currently activated or whether the row 110 will be activated in response to another memory command.

[0015] In other embodiments, the portions of contiguous memory are contiguous across multiple rows 110. Because the portions of contiguous memory are contiguous across multiple rows 110, at least one row activation command is required. Thus, in some embodiments, memory module 104 maintains a finite state machine. Based on the composite memory command and the one or more memory commands required to operate the finite state machine, memory module 104 then determines the one or more row activation commands required.

[0016] Because a composite memory command results in multiple memory commands occupying a bank 108 for a particular amount of time, in some embodiments, the memory controller 106 implements fairness logic to ensure that the bank 108 is not occupied at the expense of other commands. Accordingly, in some embodiments, the memory controller 106 is configured to calculate a latency associated with the composite memory command. If consecutive regions of memory in the composite memory command are contiguous across the same row 110, the latency is estimated as, for example, a predefined latency timing for issuing the memory command to the columns 112 multiplied by the number of columns 112 associated with the particular composite memory command. In some embodiments, the predefined latency timing is established in the memory module, a firmware setting, or a separately defined configuration setting. In some embodiments, the memory controller 106 uses the latency to deterministically schedule memory commands (e.g., the memory controller 106 knows to wait a number of cycles based on the latency before issuing another command to the same memory region).

[0017] If the contiguous region of memory is contiguous across multiple rows 110, the latency is calculated based on the starting and ending addresses of the contiguous region of memory (e.g., as indicated in the composite memory command or determined based on the starting address within the composite memory command and the number of affected columns indicated in the composite memory command) by determining which banks 108 are associated with the contiguous region of memory, the number of rows 110 associated with the composite memory command, and whether the first row 110 to be accessed in each bank 108 is already open, and therefore does not require a row activation command. The latency is then calculated using these values ​​and one or more memory timing values.

[0018] In some embodiments, memory controller 106 prioritizes issuing other commands (e.g., memory commands) before the composite memory command based on latency. For example, in some embodiments, latency or weighted latency is used as a threshold. Other commands with latency below the threshold are prioritized and issued to memory module 104 before issuing the composite memory command to memory module 104.

[0019] In other embodiments where the latency exceeds a threshold, the memory controller 106 generates multiple other composite memory commands based on the composite memory command. In some embodiments, a composite memory command associated with a contiguous region of memory is generated into multiple composite memory commands corresponding to subdivisions of the contiguous region of memory. For example, a composite memory command associated with a region of memory that is contiguous across multiple rows 110 may be generated into multiple composite memory commands, each corresponding to a row 110 in the region of contiguous memory. As another example, a composite memory command associated with a region of memory that is contiguous across multiple columns 112 within the same row 110 may be generated into multiple composite memory commands, each associated with a subdivision of the column 112. In some embodiments, the latency of the generated composite memory command is recalculated. Based on the recalculated latency, other instructions are prioritized and / or other composite memory commands are generated. In some embodiments, the memory controller 106 breaks the composite memory command into multiple composite memory commands based on other rules or criteria. For example, in some embodiments, the memory controller 106 breaks a multi-row composite memory command into multiple single-row composite memory commands regardless of latency. As another example, in some embodiments, the memory controller 106 breaks a composite memory command into multiple latency-independent composite memory commands based on a threshold number of operations caused by a single composite memory command.

[0020] For further explanation, FIG. 2 sets forth a flowchart illustrating an exemplary method for memory operations using a compound memory command, including receiving 202 (e.g., by memory module 104 from memory controller 106) a compound memory command (CMEM) 204 indicating one or more operations to be applied to each of multiple portions of contiguous memory within memory module 104. In some embodiments, the operations are operations to be applied to specific columns 112 of memory module 104. Examples of operations caused to be applied by the compound memory command 204 include a read operation of column 112, a write operation of column 112, or moving a column 112 to a contiguous memory register. For example, a compound memory command 204 for bulk zeroing would apply a write operation of column 112 to each column 112 in a contiguous area of ​​memory.

[0021] In some embodiments, the composite memory command 204 indicates a starting address for a region of contiguous memory and the number of columns to which the operation indicated in the composite memory command applies. In other embodiments, the composite memory command 204 indicates starting and ending addresses for multiple portions of contiguous memory. In some embodiments, the multiple portions of contiguous memory are contiguous within the same row 110. In other embodiments, the multiple portions of contiguous memory are contiguous across multiple rows 110.

[0022] 2 also includes (e.g., by the memory module 104) generating 206 a plurality of memory commands 210 to apply one or more operations to each of a plurality of portions of the contiguous memory based on the composite memory command 204. Generating 206 a plurality of memory commands 210 includes generating a memory command 210 for each column 112 in the contiguous memory. The memory commands 210 indicate operations in the composite memory command 204. In some embodiments, generating 206 a plurality of memory commands 210 includes generating one or more row activate commands needed to activate rows 110 affected by the memory command 210.

[0023] 2 also includes (e.g., by memory module 104) executing 208 multiple memory commands 210. As such, only a single composite memory command 204 needs to be passed on the bus or connection between processor 102 and memory controller 106, and the bus or connection between memory controller 106 and the memory module, in order for the multiple memory commands 210 to be executed by memory module 104.

[0024] For further explanation, FIG. 3 sets forth a flowchart illustrating an exemplary method for memory operations using a composite memory command, including receiving 202 (e.g., by memory module 104 from memory controller 106) a composite memory command (CMEM) 204 indicating one or more operations to be applied to each of multiple portions of contiguous memory within memory module 104, generating 206 (e.g., by memory module 104) multiple memory commands 210 to apply one or more operations to each of the multiple portions of contiguous memory based on the composite memory command 204, and executing 208 (e.g., by memory module 104) multiple memory commands 210.

[0025] 3 differs from FIG. 2 in that generating 206 a plurality of memory commands 210 (e.g., by the memory module 104) to apply one or more operations to each of a plurality of portions of contiguous memory based on the composite memory command 204 includes determining 302 one or more required row activation commands. In some embodiments, if the contiguous memory is contiguous across the same row 110, determining 302 the one or more required row activation commands includes determining whether the row 110 is activated (e.g., opened and stored in a row buffer). In some embodiments, if the contiguous memory is contiguous across multiple rows 110, determining 302 the one or more row activation commands includes determining whether the first accessed row 110 in each bank 108 of the contiguous memory is open. In other embodiments, if the contiguous memory is contiguous across multiple rows 110, determining 302 the one or more row activation commands is based on a finite state machine.

[0026] Generating 206 the plurality of memory commands 210 (e.g., by the memory module 104) to apply one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command 204 includes generating 304 one or more required row activation commands. Thus, the executed 208 memory command 210 includes one or more required row activation commands.

[0027] For further explanation, FIG. 4 sets forth a flowchart illustrating an exemplary method for memory operations using a composite memory command, including receiving 202 (e.g., by the memory module 104 from the memory controller 106) a composite memory command (CMEM) 204 indicating one or more operations to be applied to each of multiple portions of contiguous memory in the memory module 104; determining 302 and generating 304 one or more required row activation commands; generating 206 (e.g., by the memory module 104) multiple memory commands 210 to apply one or more operations to each of the multiple portions of contiguous memory based on the composite memory command 204; and executing 208 (e.g., by the memory module 104) the multiple memory commands 210.

[0028] The method of Figure 4 differs from Figure 3 in that determining 302 one or more required row activation commands includes maintaining 402 a finite state machine. The finite state machine may indicate which one or more activated rows 110 (e.g., one or more rows 110 stored in the row buffers of each bank 108) were the memory commands 210 to be executed. The finite state machine may be maintained (e.g., updated) by generating multiple memory commands and then updating the finite state machine to determine which rows 110 need to be activated and in what sequence the rows 110 should be activated to execute the particular memory command.

[0029] Determining 302 the one or more required row activation commands includes determining 404 the one or more row activation commands based on a finite state machine. For example, the row activation commands are generated in response to transitions in the finite state machine that indicate a particular row 110 needs to be activated.

[0030] For further explanation, FIG. 5 sets forth a flowchart illustrating an exemplary method for memory operations using a composite memory command, including receiving 202 (e.g., by a memory module 104 from a memory controller 106) a composite memory command (CMEM) 204 indicating one or more operations to be applied to each of multiple portions of contiguous memory within the memory module, generating 206 (e.g., by the memory module 104) multiple memory commands 210 to apply the one or more operations to each of the multiple portions of contiguous memory based on the composite memory command 204, and executing 208 (e.g., by the memory module 104) the multiple memory commands 210.

[0031] 2 in that it includes (e.g., by the memory controller 106) determining 502 a latency associated with the composite memory command 204. If contiguous regions of memory for the composite memory command 204 are contiguous across the same row 110 of the memory module 104, the latency is estimated as a predefined latency timing for issuing the memory command to the columns 112 multiplied by the number of columns 112 associated with the particular composite memory command 204. In some embodiments, the predefined latency timing is established in the memory module 104, a firmware setting, or a separately defined configuration setting.

[0032] If the contiguous region of memory is contiguous across multiple rows 110 of the memory module 104, the latency is calculated by determining which banks 108 are associated with the contiguous region of memory based on the starting and ending addresses indicated in the composite memory command 204, the number of rows 110 associated with the composite memory command 204, and whether the first row 110 to be accessed in each bank 108 is already open and therefore does not require a row activation command. The latency is then calculated using these values ​​and one or more memory timing values.

[0033] For further explanation, FIG. 6 sets forth a flowchart illustrating an exemplary method for memory operations using a composite memory command, including (e.g., by a memory controller) determining 502 a latency associated with the composite memory command 204; receiving 202 (e.g., by a memory module 104 from a memory controller 106) a composite memory command (CMEM) 204 indicating one or more operations to be applied to each of multiple portions of contiguous memory of the memory module 104; (e.g., by the memory module 104) generating 206 multiple memory commands 210 to apply the one or more operations to each of the multiple portions of the contiguous memory based on the composite memory command 204; and (e.g., by the memory module 104) executing 208 the multiple memory commands 210.

[0034] 6 differs from FIG. 5 in that it includes prioritizing 602 the issuance of one or more other commands based on latency. For example, in some embodiments, latency or weighted latency is used as a threshold. Other commands with latency below the threshold are prioritized and issued to the memory module 104 before the composite memory command 204.

[0035] For further explanation, FIG. 7 sets forth a flowchart illustrating an exemplary method for memory operations using a composite memory command, including (e.g., by a memory controller) determining 502 a latency associated with the composite memory command 204; receiving 202 (e.g., by a memory module 104 from a memory controller 106) a composite memory command (CMEM) 204 indicating one or more operations to be applied to each of multiple portions of contiguous memory of the memory module 104; (e.g., by the memory module 104) generating 206 multiple memory commands 210 to apply the one or more operations to each of the multiple portions of the contiguous memory based on the composite memory command 204; and (e.g., by the memory module 104) executing 208 the multiple memory commands 210.

[0036] 5 in that the method of FIG. 7 includes (e.g., by the memory controller 106) generating 206 a plurality of other composite memory commands based on the composite memory command 204 in response to the latency exceeding a threshold. In some embodiments, a composite memory command 204 associated with a contiguous region of memory is generated into a plurality of composite memory commands corresponding to a subdivision of the contiguous region of memory. For example, a composite memory command 204 associated with a region of memory that is contiguous across multiple rows 110 may be generated into a plurality of composite memory commands each corresponding to a row 110 in the region of contiguous memory. As another example, a composite memory command 204 associated with a region of memory that is contiguous across multiple columns 112 within the same row 110 may be generated into a plurality of composite memory commands each associated with a subdivision of the column 112. In some embodiments, the latency of the generated composite memory command is recalculated. Based on the recalculated latency, other instructions are prioritized and / or other composite memory commands are generated. The generated composite memory command is then provided to the memory module 104.

[0037] In view of the above discussion, the reader will appreciate that the advantages of memory operations using composite memory commands are: It will be appreciated that compounding individual memory commands into compound memory commands includes improved performance of the computing system due to improved bandwidth utilization between the processor, memory controller, and memory modules.

[0038] The advantages and features of the present disclosure may be further explained by the following description. 1. A method of memory operation using a composite memory command, the method including: a memory module receiving a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory within the memory module; generating a plurality of memory commands to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command; and executing the plurality of memory commands. 2. The method of claim 1, wherein the composite memory command indicates a starting memory address and a number of columns as multiple portions of contiguous memory. 3. The method according to any one of statements 1 to 2, wherein the compound memory command indicates the start and end addresses of multiple portions of contiguous memory. 4. A method as described in any of statements 1 to 3, wherein generating a plurality of memory commands includes determining one or more activation commands and generating one or more required row activation commands for required rows. 5. A method as described in any of statements 1 to 4, wherein determining the required line or line start command includes maintaining a finite state machine and determining the required line or line start command based on the finite state machine, the start address, and the end address. 6. The method of any of statements 1-5, further comprising the memory controller determining a latency associated with the composite memory command. 7. The method of any of statements 1-6, further comprising the memory controller prioritizing the issuance of one or more other commands to the memory module based on latency. 8. The method of any of statements 1-7, further comprising the memory controller generating a plurality of other composite memory commands based on the composite memory command in response to the latency exceeding a threshold. 9. An apparatus for memory operations using composite memory commands, comprising: a processor; a memory controller communicatively coupled to the processor; and a memory module communicatively coupled to the memory controller, wherein the memory module is configured to perform steps including receiving a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in the memory module; generating a plurality of memory commands to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command; and executing the plurality of memory commands. 10. The apparatus of statement 9, wherein the composite memory command indicates a starting memory address and a number of columns as multiple portions of contiguous memory. 11. The apparatus of any of claims 9-10, wherein the composite memory command indicates the start and end addresses of multiple portions of contiguous memory. 12. The apparatus of any of statements 9-11, wherein generating a plurality of memory commands includes determining one or more required row activation commands and generating the one or more required row activation commands. 13. The apparatus of any of statements 9 to 12, wherein determining one or more required row activation commands includes maintaining a finite state machine and determining one or more required row activation commands based on the finite state machine, a start address, and an end address. 14. The apparatus of any of statements 9-13, wherein the memory controller is configured to determine a latency associated with the composite memory command. 15. The apparatus of any of statements 9-14, wherein the memory controller is configured to prioritize issuance of one or more other commands to the memory module based on latency. 16. The apparatus of any of statements 9-15, wherein the memory controller is configured to generate, based on the composite memory command, a plurality of other composite memory commands in response to the latency exceeding a threshold. 17. A memory module for memory operations using composite memory commands, the memory module configured to perform steps including: receiving a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory within the memory module; generating a plurality of memory commands to apply the one or more operations to each of the plurality of portions of contiguous memory based on the composite memory command; and executing the plurality of memory commands. 18. The memory controller of statement 17, wherein the composite memory command indicates a starting memory address and a number of columns as multiple portions of contiguous memory. 19. The memory controller according to any of claims 17-18, wherein the composite memory command indicates start and end addresses of multiple portions of contiguous memory. 20. A memory controller as described in any of statements 17-19, wherein generating a plurality of memory commands includes determining one or more required row activation commands and generating the one or more required row activation commands. 21. A method of memory operation using a composite memory command, the method including: a memory controller receiving, from a processor, a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory in a memory module; and transmitting the composite memory command to the memory module. 22. The method of statement 21, further comprising the memory controller determining a latency associated with the composite memory command. 23. The method of any of statements 21-22, further comprising the memory controller prioritizing the issuance of one or more other commands to the memory module based on latency. 24. The method of any of statements 21-23, further comprising the memory controller generating, based on the composite memory command, a plurality of other composite memory commands in response to the latency exceeding a threshold.

[0039] Exemplary embodiments of the present disclosure are described primarily in the context of a fully functional computer system for memory operations using compound memory commands. However, readers skilled in the art will recognize that the present disclosure may be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium can be any storage medium for machine-readable information, including magnetic, optical, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact discs for optical drives, magnetic tape, and others as would occur to one skilled in the art. Those skilled in the art will readily recognize that any computer system with suitable programming means is capable of executing the steps of the methods of the present disclosure embodied in a computer program product. Those skilled in the art will also recognize that while some of the exemplary embodiments described herein are directed to software installed and executed on computer hardware, alternative embodiments implemented as firmware or as hardware are nevertheless well within the scope of the present disclosure.

[0040] The present disclosure may be a system, a method, and / or a computer program product, which may include computer-readable storage medium(s) having computer-readable program instructions for causing a processor to perform aspects of the present disclosure.

[0041] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves having instructions recorded thereon, and any suitable combination thereof. As used herein, a computer-readable storage medium should not be construed as being an electromagnetic wave, such as an electric wave or other freely propagating electromagnetic wave, propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or a transitory signal per se, such as an electrical signal transmitted through a wire.

[0042] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or over a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or to an external computer or external storage device. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and transmits the computer-readable program instructions to a computer-readable storage medium within the respective computing / processing device for storage.

[0043] The computer-readable program instructions for carrying out the operations of the present disclosure can be either assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C, and traditional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions can execute completely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer, partially on a remote computer, or completely on a remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to individualize the electronic circuitry to perform aspects of the present disclosure.

[0044] Aspects of the present disclosure are described herein with reference to flowchart and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0045] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, produce a machine that generates means for performing the function(s) / act(s) specified in the flowchart and / or block diagram block(s). These computer-readable program instructions can also be stored on a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other device to function in a particular way, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions that implement aspects of the function(s) / act(s) specified in the flowchart and / or block diagram block(s).

[0046] Also, the computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to create a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device implement the function / act specified in the block(s) of the flowcharts and / or block diagrams.

[0047] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or acts, or a combination of dedicated hardware and computer instructions.

[0048] It will be understood from the foregoing description that modifications and variations can be made in various embodiments of the present disclosure. The description herein is for illustrative purposes only and should not be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.

Claims

1. 1. An apparatus for memory operations using composite memory commands, comprising: a processor; a memory controller communicatively coupled to the processor; a memory module communicatively coupled to the memory controller; The memory module includes: receiving a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory within the memory module; generating a plurality of memory commands for applying the one or more operations to each of a plurality of portions of the contiguous memory based on the composite memory command; executing the plurality of memory commands; configured to: Device.

2. the composite memory command indicates a starting memory address and a number of columns as portions of the contiguous memory; 10. The apparatus of claim 1.

3. the composite memory command indicates starting and ending addresses of multiple portions of the contiguous memory; 10. The apparatus of claim 1.

4. generating the plurality of memory commands determining one or more required row activation commands; generating the one or more required row activation commands.

4. The apparatus of claim 3.

5. Determining the one or more required row activation commands includes: maintaining a finite state machine; determining the one or more required row activation commands based on the finite state machine, the start address, and the end address.

5. The apparatus of claim 4.

6. The memory controller is configured to determine a latency associated with the composite memory command, and the memory controller is configured to prioritize, based on a threshold based on the latency, issuance of one or more other commands to the memory module having a latency below the threshold.

10. The apparatus of claim 1.

7. The memory controller configured to determine a latency associated with the composite memory command, and wherein the memory controller is configured to generate a plurality of other composite memory commands based on the composite memory command in response to the latency exceeding a threshold.

10. The apparatus of claim 1.

8. 1. A memory module for memory operations using composite memory commands, comprising: receiving a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory within the memory module; generating a plurality of memory commands for applying the one or more operations to each of a plurality of portions of the contiguous memory based on the composite memory command; executing the plurality of memory commands; configured to: Memory module.

9. the composite memory command indicates a starting memory address and a number of columns as portions of the contiguous memory; 9. The memory module of claim 8.

10. the composite memory command indicates starting and ending addresses of multiple portions of the contiguous memory; 9. The memory module of claim 8.

11. generating the plurality of memory commands determining one or more required row activation commands; generating the one or more required row activation commands.

9. The memory module of claim 8.

12. 1. A method of memory operation using a composite memory command, comprising: receiving, from the processor, a composite memory command indicating one or more operations to be applied to each of a plurality of portions of contiguous memory within the memory module; transmitting the composite memory command to the memory module; generating, based on the composite memory command, a plurality of memory commands for applying one or more operations to each of a plurality of portions of the contiguous memory; method.

13. The method of claim 12, further comprising: determining a latency associated with the composite memory command; the memory controller prioritizing issuance of one or more other commands to the memory module having a latency below the threshold based on the latency-based threshold.

13. The method of claim 12.

14. The method of claim 13, further comprising: determining a latency associated with the composite memory command; the memory controller generating a plurality of other composite memory commands based on the composite memory command in response to the latency exceeding a threshold.

13. The method of claim 12.

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