Structure and method for semiconductor packaging

Abstract

To provide a structure and a method for a semiconductor packaging.SOLUTION: In a semiconductor packaging structure 100, a die 102 contains: a bond pad 124; and a first metal layer structure arranged on the die (a first metal layer 107 and a seed layer 106), and the first metal layer has a first width 109, and a first metal structure is electrically coupled to the bond pad 124. The semiconductor packaging structure also contains: a sensitive insulation material 104 of the circumference on a side surface of the first metal layer structure; and a second metal layer structure (a second metal layer 114 and a seed layer 112) arranged onto the first metal layer structure and one part of the insulation material 104. The second metal structure is electrically coupled to the first metal layer structure, and has a second width 119 larger than the first width. Also, the semiconductor packaging structure contains a sensitive insulation material 110 in the circumference on a side surface of the second metal layer structure.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application relates to methods and structures for semiconductor packaging. [Background technology]

[0002] As electronics become more prevalent and functional, the size and cost of semiconductor devices, such as transistors and integrated circuits (ICs), are decreasing. As the size of semiconductor devices decreases, power and current density increase, which can lead to high temperatures and premature packaging failure. As the die becomes smaller, the current density within the packaging increases. The reduction in die size can cause problems related to the packaging of the die, such as electromigration and breakage of conductive lines. Summary of the Invention

[0003] At least one exemplary semiconductor packaging structure includes a die including a bond pad and a first metal layer structure disposed on the die, the first metal layer structure having a first width, the first metal layer structure including a first metal layer electrically coupled to the bond pad. The semiconductor packaging structure also includes a first photosensitive material around a side surface of the first metal layer structure and a second metal layer structure disposed on the first metal layer structure and on a portion of the first photosensitive material, the second metal layer structure being electrically coupled to the first metal layer structure and having a second width greater than the first width. The semiconductor packaging structure also includes a second photosensitive material around a side surface of the second metal layer structure.

[0004] At least one exemplary semiconductor packaging structure includes a die including bond pads and a first metal layer structure disposed on the die, the first metal layer structure including a first metal layer, the first metal layer electrically coupled to the bond pads, and the first metal layer having a first width. The semiconductor packaging structure also includes a first insulating material around sides of the first metal layer structure and a second metal layer structure disposed on the first metal layer structure and on at least a portion of the first insulating material, the second metal layer structure electrically coupled to the first metal layer structure, the second metal layer structure having a planarized surface, and the second metal layer structure having a second width, the second width of the second metal layer structure being greater than the first width of the first metal layer structure. The semiconductor packaging structure also includes a second insulating material around sides of the second metal layer structure and a plating layer disposed on the planarized surface of the second metal layer structure, the plating layer extending over a top surface of the second insulating material.

[0005] At least one exemplary semiconductor packaging structure includes a die including a bond pad and a first metal layer structure disposed on the die, the first metal layer structure including a first metal layer, the first metal layer being electrically coupled to the bond pad. The semiconductor packaging structure also includes a first insulating material around a side surface of the first metal layer structure and a second metal layer structure disposed over the first metal layer structure and a portion of the first insulating material, the second metal layer structure being electrically coupled to the first metal layer, the second metal layer structure extending beyond the edge of the die. The semiconductor packaging structure also includes a second insulating material around a side surface of the second metal layer structure.

[0006] At least one exemplary method includes applying a first insulating material to a semiconductor structure including a bond pad and forming an opening in the first insulating material to expose at least a portion of the bond pad. The method also includes depositing a first seed layer over the first insulating material and in the opening, and plating a first metal layer over the first seed layer and in the opening. The method also includes performing chemical mechanical polishing (CMP) on the first metal layer, the first seed layer, and at least a portion of the first insulating material to form a first metal layer structure in the opening, and applying a second insulating material over the first insulating material and on the first metal layer structure. The method also includes forming an opening in the second insulating material to expose at least a portion of the first metal layer structure and at least a portion of the first insulating material, and depositing a second seed layer over the second insulating material and in the opening. The method also includes plating a second metal layer over the second seed layer and in the opening of the second insulating material, and performing CMP on the second metal layer, the second seed layer, and the second insulating material to form a second metal layer structure in the opening of the second insulating material, the second metal layer structure including the second metal layer and the second seed layer.

[0007] At least one exemplary method includes applying a first insulating material to a semiconductor structure including a bond pad and forming an opening in the first insulating material to expose at least a portion of the bond pad. The method also includes applying a second insulating material over the first insulating material and in the opening, and forming an opening in the second insulating material that extends through at least a portion of the opening in the first insulating material to expose at least a portion of the bond pad. The method also includes depositing a seed layer over the second insulating material and in the opening in the second insulating material and the first insulating material, and plating a metal layer over the seed layer in the opening in the second insulating material and the first insulating material. The method also includes performing CMP on at least a portion of the metal layer, on the seed layer, and on the second insulating material to form a first metal layer structure in the opening in the first insulating material and a second metal layer structure in the opening in the second insulating material. [Brief explanation of the drawings]

[0008] [Figure 1] 1 illustrates a cross-sectional view of an exemplary semiconductor packaging structure.

[0009] [Figure 2] 1 illustrates another exemplary semiconductor packaging structure.

[0010] [Figure 3A] 1 illustrates a cross-sectional view of an exemplary first metal layer and an exemplary second metal layer. [Figure 3B] 1 illustrates a cross-sectional view of an exemplary first metal layer and an exemplary second metal layer. [Figure 3C] 1 illustrates a cross-sectional view of an exemplary first metal layer and an exemplary second metal layer. [Figure 3D] 1 illustrates a cross-sectional view of an exemplary first metal layer and an exemplary second metal layer. [Figure 3E] 1 illustrates a cross-sectional view of an exemplary first metal layer and an exemplary second metal layer. [Figure 3F] 1 illustrates a cross-sectional view of an exemplary first metal layer and an exemplary second metal layer. [Figure 3G]1 illustrates a cross-sectional view of an exemplary first metal layer and an exemplary second metal layer. [Figure 3H] 1 illustrates a cross-sectional view of an exemplary first metal layer and an exemplary second metal layer.

[0011] [Figure 4] 1 illustrates a cross-sectional view of another exemplary semiconductor packaging structure.

[0012] [Figure 5] 1 illustrates a cross-sectional view of an additional exemplary semiconductor packaging structure.

[0013] [Figure 6A] 1 illustrates an exemplary method for manufacturing a semiconductor packaging structure. [Figure 6B] 1 illustrates an exemplary method for manufacturing a semiconductor packaging structure. [Figure 6C] 1 illustrates an exemplary method for manufacturing a semiconductor packaging structure. [Figure 6D] 1 illustrates an exemplary method for manufacturing a semiconductor packaging structure. [Figure 6E] 1 illustrates an exemplary method for manufacturing a semiconductor packaging structure. [Figure 6F] 1 illustrates an exemplary method for manufacturing a semiconductor packaging structure. [Figure 6G] 1 illustrates an exemplary method for manufacturing a semiconductor packaging structure. [Figure 6H] 1 illustrates an exemplary method for manufacturing a semiconductor packaging structure. [Figure 6I] 1 illustrates an exemplary method for manufacturing a semiconductor packaging structure. [Figure 6J] 1 illustrates an exemplary method for manufacturing a semiconductor packaging structure. [Figure 6K] 1 illustrates an exemplary method for manufacturing a semiconductor packaging structure. [Figure 6L] 1 illustrates an exemplary method for manufacturing a semiconductor packaging structure.

[0014] [Figure 7A] 1 illustrates another exemplary method for manufacturing a semiconductor packaging structure. [Figure 7B] 1 illustrates another exemplary method for manufacturing a semiconductor packaging structure. [Figure 7C] 1 illustrates another exemplary method for manufacturing a semiconductor packaging structure. [Figure 7D] 1 illustrates another exemplary method for manufacturing a semiconductor packaging structure. [Figure 7E] 1 illustrates another exemplary method for manufacturing a semiconductor packaging structure. [Figure 7F] 1 illustrates another exemplary method for manufacturing a semiconductor packaging structure. [Figure 7G] 1 illustrates another exemplary method for manufacturing a semiconductor packaging structure.

[0015] [Figure 8] 1 illustrates a cross-sectional view of another exemplary semiconductor packaging structure.

[0016] [Figure 9] 1 illustrates a cross-sectional view of an additional semiconductor packaging structure.

[0017] [Figure 10A] An additional method for manufacturing a semiconductor packaging structure is presented. [Figure 10B] An additional method for manufacturing a semiconductor packaging structure is presented. [Figure 10C] An additional method for manufacturing a semiconductor packaging structure is presented. [Figure 10D] An additional method for manufacturing a semiconductor packaging structure is presented. [Figure 10E] An additional method for manufacturing a semiconductor packaging structure is presented. [Figure 10F] An additional method for manufacturing a semiconductor packaging structure is presented. [Figure 10G]An additional method for manufacturing a semiconductor packaging structure is presented. [Figure 10H] An additional method for manufacturing a semiconductor packaging structure is presented. [Figure 10I] An additional method for manufacturing a semiconductor packaging structure is presented. [Figure 10J] An additional method for manufacturing a semiconductor packaging structure is presented. [Figure 10K] An additional method for manufacturing a semiconductor packaging structure is presented. [Figure 10L] An additional method for manufacturing a semiconductor packaging structure is presented. [Figure 10M] An additional method for manufacturing a semiconductor packaging structure is presented. [Figure 10N] An additional method for manufacturing a semiconductor packaging structure is presented. [Figure 10O] An additional method for manufacturing a semiconductor packaging structure is presented.

[0018] [Figure 11A] 1 illustrates another method for manufacturing a semiconductor packaging structure. [Figure 11B] 1 illustrates another method for manufacturing a semiconductor packaging structure. [Figure 11C] 1 illustrates another method for manufacturing a semiconductor packaging structure. [Figure 11D] 1 illustrates another method for manufacturing a semiconductor packaging structure. [Figure 11E] 1 illustrates another method for manufacturing a semiconductor packaging structure. [Figure 11F] 1 illustrates another method for manufacturing a semiconductor packaging structure.

[0019] [Figure 12] 1 shows a flowchart of an exemplary method for manufacturing a semiconductor packaging structure.

[0020] [Figure 13] 1 shows a flowchart of another exemplary method for manufacturing a semiconductor packaging structure.

[0021] [Figure 14] 10 shows a flowchart of an additional exemplary method for manufacturing a semiconductor packaging structure. DETAILED DESCRIPTION OF THE INVENTION

[0022] The size and cost of semiconductor devices, such as transistors and integrated circuits (ICs), are decreasing. As the size of semiconductor devices decreases, power and current density increase, which causes high temperatures and premature packaging failure. As the die becomes smaller, current density within the packaging increases. The shrinking die size can cause problems related to die packaging, such as electromigration and packaging failure.

[0023] As described in detail herein, an embodiment of a semiconductor packaging structure for chip scale packaging does not include solder within the semiconductor packaging structure. The absence of solder within the semiconductor packaging structure may reduce electromigration, reduce high temperature issues, and improve reliability.

[0024] As described in detail herein, the chip-scale packaging of certain embodiments of the semiconductor packaging structure protects the die while providing for a flexible footprint. For example, certain embodiments of the semiconductor packaging structure use multiple metal layers to effectively couple a small area of ​​the die to a large area on the semiconductor packaging structure for bonding to a printed circuit board (PCB). Thus, current on the outer portions of the semiconductor packaging structure is spread over a larger area than current near the die, improving the durability of the semiconductor packaging structure.

[0025] As described in detail herein, in certain embodiments of the semiconductor packaging structure, a barrier metal, such as a seed layer and a plating layer, completely surrounds the copper-containing material. Surrounding the copper-containing material prevents copper migration and improves the reliability of the semiconductor packaging structure.

[0026] As described in detail herein, the semiconductor packaging structure of certain embodiments does not include wire bonds. The absence of wire bonds in the semiconductor packaging structure improves reliability and reduces parasitics.

[0027] As described in detail herein, the semiconductor packaging structure of certain embodiments does not include a molding compound or additional encapsulation. The lack of additional encapsulation reduces the size and cost of the semiconductor packaging structure. The lack of encapsulation also avoids failure modes from additional materials, processing, and weight.

[0028] As described in detail herein, the semiconductor packaging structure of certain embodiments may operate at high temperatures, for example, greater than 200° C., for periods of time, for example, greater than 50 hours.

[0029] In the semiconductor packaging structure of an embodiment, the package size is the same as the die size, which reduces the amount of packaging material and improves efficiency.

[0030] As described in detail herein, the semiconductor packaging structure of certain embodiments transfers large amounts of power from the die to external connections, for example, the semiconductor packaging structure of certain embodiments may transfer between 2 mW and 5 W of power.

[0031] As described in detail herein, the semiconductor packaging structure of certain embodiments does not use a lead frame or other packaging substrate. The absence of a lead frame or other packaging structure reduces the size of the semiconductor packaging structure.

[0032] As described in detail herein, the semiconductor packaging structure of an embodiment includes a die within a molding compound, and the semiconductor packaging structure does not include exposed silicon. Thus, the die is mechanically, optically, and environmentally protected. In multiple metal layers, when subsequent metal layers are larger than the initial layers, this may be known as fan-out routing. In the semiconductor packaging structure of an embodiment, the fan-out routing extends beyond the edge of the die.

[0033] FIG. 1 illustrates a cross-sectional view of a semiconductor packaging structure 100 for chip-scale packaging. In at least one embodiment, the semiconductor packaging structure 100 does not include solder. A semiconductor structure, such as a substrate 102 in the semiconductor packaging structure 100, is a portion of a die or wafer and includes at least one semiconductor device (e.g., at least one transistor) or integrated circuit. Bond pads 124, disposed on one surface of the substrate 102, are electrically coupled to at least one of the semiconductor devices. The bond pads 124 are the top layer of the die or wafer. In some embodiments, there is no semiconductor material above the bond pads 124. In at least one embodiment (not shown), the top surface of the bond pads 424 is slightly below the top surface of the substrate 102. A portion of the bond pads 424 may be coated with polyimide. A backside coating 122, which may be an opaque film, such as a black film, is disposed on the opposite side of the substrate 102 from the bond pads 124. The backside coating 122 has a thickness 126 of from about 10 μm to about 60 μm, such as from about 25 μm to about 35 μm. The substrate 102 has a thickness 103, which can be from about 50 μm to about 500 μm, such as from about 200 μm to about 300 μm.

[0034] An insulating material 104 is disposed on the substrate 102, over the bond pads 124. The insulating material 104 can have low water absorption, a low modulus of elasticity, and high adhesion. In at least one example, the insulating material 104 is a polymer. In certain embodiments, the insulating material 104 is an epoxy-based near-UV (e.g., about 350 nm to about 400 nm) photoresist. In additional embodiments, the insulating material 104 is an acrylate-based photoresist or a novalak-based photoresist. For example, the insulating material 104 can have a modulus of elasticity of about 2 GPa to about 6 GPa. In certain embodiments, the insulating material 104 has a Poisson's ratio of about 0.2 to about 0.25. In certain embodiments, the insulating material 104 has a film stress of 15 MPa to 65 MPa, for example, about 16 MPa to about 19 MPa. In some embodiments, the insulating material 104 has a maximum shear strain of about 0.01. The insulating material 104 may have a coefficient of friction of about 0.2 μm. In some embodiments, the insulating material 104 has a coefficient of thermal expansion of about 20 ppm / K to about 55 ppm / K. The insulating material 104 may be a photosensitive material that can withstand the stresses of manufacturing and operation. The insulating material 104 may be thicker than conventional photoresists. In some examples, the photosensitive material is a permanent photoresist, such as SU-8, Riston™, TMMR-S2000™, or TMMF-S2000™. Some permanent photoresists are photoresists designed to not be easily removed. Some permanent photoresists are robust enough to withstand subsequent processing. In some embodiments, some permanent photoresists are thicker than conventional photoresists, for example, greater than 5 μm or greater than 50 μm. In at least one example, insulating material 104 can be a non-photosensitive material, such as a mold compound. In at least one embodiment, insulating material 104 has a thickness 105 of about 5 μm to about 100 μm, such as about 50 μm to about 80 μm. Thickness 105 of insulating material 104 can be greater than 50 μm, such as about 100 μm.

[0035] A first metal layer structure includes a first metal layer 107 and a seed layer 106. The first metal layer 107 is electrically coupled to the bond pad 124. The first metal layer structure also includes the first metal layer 107, the seed layer 106, and an insulating material 104, and has a planarized top surface. The insulating material 104 is disposed around the sides of the first metal layer structure. The first metal layer 107 and the seed layer 106 are disposed within openings in the insulating material 104. The first metal layer 107 provides standoff thickness and microstress flexibility. In at least one embodiment, the first metal layer 107 includes copper or an alloy of a conductive metal. The seed layer 106 is disposed between the first metal layer 107 and the insulating material 104. The seed layer 106 provides a barrier between the first metal layer 107 and the insulating material 104 to prevent copper creepage into the first metal layer 107 and to protect the first metal layer 107 from moisture. The seed layer 106 includes titanium, a titanium alloy such as TiW, tantalum, or a tantalum alloy such as TaN. The seed layer 103 has a thickness 128 of less than 2 μm. In at least one example, the first metal layer 107 has a width 109 that can be between 20 μm and 200 μm and a thickness 101 that can be between 4 μm and 100 μm. In at least one example, the thickness 101 of the first metal layer 107 and the thickness of the seed layer 106 are approximately equal to the thickness 105 of the insulating material.

[0036] The insulating material 110 is disposed on the planarized surfaces of the insulating material 104, the first metal layer 107, and the seed layer 106. In at least one example, the insulating material 110 is a polymer. The insulating material 110 can be a photosensitive material such as a permanent photoresist, e.g., SU-8, Riston™, AZ-9260™, TMMR-S2000™, or TMMF-S2000™. In some examples, the insulating material 110 is a non-photosensitive material, such as a mold compound. In at least one example, the insulating material 110 is composed of the same material as the insulating material 104. If the insulating material 110 and the insulating material 104 are composed of the same type of material, they can be differentiated by the planarized surface of the insulating material 104. The surface of the insulating material 104 can be planarized by a chemical mechanical polishing (CMP) process performed on the insulating material 104 prior to the formation of the insulating material 110. In another example, insulating material 110 is composed of a different material than insulating material 104. Thickness 111 of insulating material 110 is from about 25 μm to about 300 μm, for example, from about 100 μm to about 200 μm. In at least one example, thickness 111 of insulating material 110 is greater than 250 μm. Thickness 111 of insulating material 110 can be greater than thickness 105 of insulating material 104. In at least one example, thickness 111 of insulating material 110 is the same as thickness 105 of insulating material 104, or thickness 111 of insulating material 110 is less than thickness 105 of insulating material 104.

[0037] A second metal layer structure, including a second metal layer 114 and a seed layer 112, is disposed within the opening in the insulating material 110, at least partially overlying the first metal layer structure. The seed layer 112 may at least partially cover the bottom and / or sidewalls of the opening, and the second metal layer 114 is formed on the seed layer 112. In at least one example, the second metal layer structure completely covers the first metal layer structure. The second metal layer 114 is electrically coupled to the first metal layer 107. The seed layer 112 physically separates the second metal layer 114 from the insulating material 110, providing a barrier. The seed layer 112 may be composed of Ti, TiW, Ta, or TaN, and has a thickness 113 of less than 2 μm. In at least one example, seed layer 106 and seed layer 112 together completely surround first metal layer 107, with seed layer 112 separating second metal layer 114 from first metal layer 107. In other examples, there is no seed layer between first metal layer 107 and second metal layer 114, and first metal layer 107 may be indistinguishable from second metal layer 114. In at least one example, second metal layer 114, seed layer 112, and insulating material 110 have planarized surfaces. Second metal layer 114 is sufficiently thick to spread current and provide good mechanical strength. Spreading current reduces electromigration, reduces current density, and improves reliability. Second metal layer 114 is composed of a metal, such as a copper-containing material, or is an alloy of a conductive metal. The second metal layer 114 has a thickness 115 of between about 25 μm and 300 μm and a width 117 of greater than 150 μm. In at least one example, the width 117 of the second metal layer 114 is greater than the width 109 of the first metal layer 107. In at least one example, the thickness 115 of the second metal layer is greater than the thickness 101 of the first metal layer 107. In at least one example, the second metal layer 114 is composed of the same material as the first metal layer 107. At least one embodiment includes an additional element, such as a passive element or sensor, between the first metal layer 107 and the second metal layer 114.

[0038] A plating layer 118 is disposed on the planarized surfaces of the second metal layer 114 and the seed layer 112. The plating layer 118 extends over the top surface of the insulating material 110. The plating layer 118 may be composed of nickel, tin, or a nickel alloy such as NiAu, NiPd, NiPdAu, NiAg, or NiSn. In at least one example, the plating layer 118 is a solderable metal stack such as electroless nickel immersion gold (ENIG), electroless nickel electroless gold (ENEG), or electroless nickel electroless palladium immersion gold (ENEPIG). In ENIG and ENEPIG, a thin layer of gold protects the nickel from oxidation. In at least one example, the plating layer 118 has a thickness 115 between approximately 2 μm and 8 μm. In at least one example, the plated layer 118 extends a thickness 115 over the planarized surfaces of the second metal layer 114, the seed layer 112, and the insulating material 110. The plated layer 118 has a width 119, for example, between about 25 μm and about 300 μm, providing low resistance. The wide width of the plated layer 118 reduces current density and heat dissipation, improving reliability. The plated layer 118 protects the metal in the second metal layer 114 and the first metal layer 107 while providing a robust, fracture-resistant solder joint. The copper in the second metal layer 114 and the first metal layer 107 is completely surrounded by the seed layers 106 and 112 and the plated layer 118.

[0039] The semiconductor packaging structure 100 may be divided into dies. The plating layer 118 is used to attach the dies to a printed circuit board (PCB) and provides electrical and thermal connections between transistors on the substrate 102 and the PCB. The electrical connection from the plating layer 118, through the second metal layer 114, through the seed layer 112, through the first metal layer 107, and through the seed layer 106 to the bond pad 124 provides a low resistance, for example, between about 2 mΩ and about 5 mΩ. The low resistance reduces heat and electromigration, improving reliability.

[0040] FIG. 2 is a three-dimensional view of a semiconductor packaging structure 130. The semiconductor packaging structure 130 includes a substrate layer 132, a first metal and insulating material layer 134, a second metal and insulating material layer 136, and a plating layer 138. The substrate layer 132 forms a die having at least one semiconductor device. The first metal and insulating material layer 134 on the substrate layer 132 includes an insulating material, such as a permanent photoresist, and a first metal layer structure, which may be composed of copper, surrounded by a seed layer. The second metal and insulating material layer 136 on the first metal and insulating material layer 134 includes another insulating material, such as another permanent photoresist layer, and a second metal layer, which may include copper, at least partially surrounded by a seed layer. The plating layer 138 is composed of a solderable material and extends over the top, planarized surface of the second metal and insulating material layer 136. In at least one example, large pads or strips in plated layer 138 are used for some connections, such as for power pins, while smaller pads in plated layer 138 are used for other connections, such as for signal pins. Plated layer 138 can be soldered to a PCB to connect the semiconductors in substrate layer 132 to the PCB. Plated layer 138 includes four smaller strips 137 arranged in a row and two long strips 139 arranged in parallel. The smaller strips 137 are useful for lower current connections (signal pins) and maintain a low area while keeping the current density sufficiently low, while the long strips 139 are useful for higher current connections (power pins) and reduce the current density. However, plated layers are highly customizable and can include any pattern.

[0041] 3A-3H illustrate exemplary top-down cross-sectional views of horizontal cross sections of first and second metal layer structure configurations. The first metal layer cross-section is taken in the direction of width 109 in the semiconductor packaging structure 100 illustrated by FIG. 1, and the second metal layer cross-section is taken in the direction of width 117 in the semiconductor packaging structure 100 illustrated by FIG. 1. A single semiconductor packaging structure can include first metal layer structures of different sizes and shapes and second metal layer structures of different sizes and shapes. The second metal layer structure has a larger area than the first metal layer structure, and in some cases, a significantly larger area. In at least one example, the second metal layer structure and the first metal layer structure have similar shapes. In other examples, the second metal layer structure and the first metal layer structure have different cross-sectional shapes. In at least one example, multiple first metal layer structures are bonded to a second metal layer structure. In other examples, one first metal layer structure is bonded to a second metal layer structure.

[0042] In FIG. 3A, the second metal layer structure 240 has a rectangular cross-section, and the first metal layer structure 242 has a circular cross-section. In at least one example, the second metal layer structure 240 can have a square cross-section. In FIG. 3B, the second metal layer structure 250 has a circular cross-section, and the first metal layer structure 252 also has a circular cross-section. In FIG. 3C, the second metal layer structure 260 and the first metal layer structure 262 both have elliptical cross-sections. In FIG. 3D, the second metal layer structure 270 has a rectangular cross-section, and the first metal layer structure 272 has a square cross-section. In at least one example, the first metal layer structure 272 has a rectangular, but not square, cross-section. In FIG. 3E, the second metal layer structure 290 has a circular cross-section, and the first metal layer structure 292 has a square cross-section. In other examples, the first metal layer structure and the second metal layer structure may have other shapes, for example, they may be formed as a triangle or another polygon, such as a pentagon, hexagon, or octagon, or an irregular shape.

[0043] 3F, first metal layer structure 284 and first metal layer structure 282 have square cross-sections, and second metal layer structure 280 has a rectangular cross-section. In at least one example, first metal layer structure 282 couples second metal layer structure 280 to a first bond pad, and first metal layer structure 284 couples second metal layer structure 280 to a second bond pad. In at least one example, first metal layer structures 282 and 284 can have various cross-sectional shapes, such as, for example, circular or rectangular. In at least one example, first metal layer structure 282 has a different cross-sectional shape than first metal layer structure 284. For example, first metal layer structure 282 has a square cross-section, and first metal layer structure 284 has a circular cross-section. Although two first metal layer structures 282 and 284 are depicted coupled to second metal layer structure 280, there may be many more first metal layer structures in the second metal layer, for example, 3, 4, 5, 6, 7, or 8. These different first metal layer structures may contact various locations in the underlying integrated circuit.

[0044] In FIG. 3G, first metal layer structure 287 has a hexagonal cross-section, and second metal layer structure 285 has a hexagonal cross-section. In other embodiments, the first metal layer structure and second metal layer structure can be different polygonal shapes, such as a pentagon, a heptagon, an octagon, or a decagon. In some embodiments, the first metal layer structure and second metal layer structure can be different polygonal shapes. In FIG. 3H, first metal layer structure 297 and second metal layer structure 295 are rounded rectangles. In other embodiments, the first metal layer structure and second metal layer structure are different rounded polygonal shapes, such as a rounded pentagon, a rounded hexagon, a rounded heptagon, a rounded octagon, or a rounded decagon.

[0045] Some exemplary semiconductor packaging structures may have more than two insulating material layers with increasingly wider metal features. FIG. 4 illustrates a semiconductor packaging structure 300 with three insulating material layers with metal features. Other semiconductor packaging structures may have more layers of insulating material and metal, such as four, five, or six. In the semiconductor packaging structure 300, the insulating material 302 is located on the planarized surfaces of the insulating material 110, the second metal layer 114, and the seed layer 112. The insulating material 302 may be composed of a photosensitive material such as a permanent resist. In one embodiment, the insulating material 302 is composed of the same material as the insulating material 110 and the insulating material 104. The insulating material 302 may be distinguishable from the insulating material 110 if they are composed of the same material due to the planarized surface of the insulating material 110 formed by CMP performed on the insulating material 110 before the insulating material 302 is formed. In other examples, insulating material 302 is a different material than insulating material 110 and / or insulating material 302 is a different material than insulating material 104. Insulating material 302 can have a thickness 303 that is greater than thickness 111 of insulating material 110, for example, between about 100 μm and about 500 μm.

[0046] A third metal layer structure, including a third metal layer 306 and a seed layer 304, is located within the opening in the insulating material 302, over the second metal layer 114 and a portion of the insulating material 110. The third metal layer 306 may be composed of a copper-containing material. The seed layer 304, such as titanium, tantalum, a titanium alloy, or a tantalum alloy, physically separates the third metal layer 306 from the insulating material 302. As shown, the second metal layer 114 is completely surrounded by the seed layer 112 and the seed layer 304 and is located between the third metal layer 306 and the second metal layer 114. In other examples, the third metal layer 306 directly contacts the second metal layer 114 without an intermediate seed layer. The third metal layer 306 may be significantly wider than the second metal layer 114. For example, the third metal layer may have a width 305 of about 100 μm to about 500 μm.

[0047] A plating layer 308, e.g., nickel, tin, a nickel alloy, ENIG, ENEG, or ENEPIG, overlies the third metal layer 306 and extends over the top surface of the third metal layer 306 and the insulating material 302. In at least one example, the plating layer 308 and the seed layer 304 completely surround the third metal layer 306. A low resistance connection exists from the plating layer 308 through the third metal layer 306, optionally through the seed layer 304, through the second metal layer 114, optionally through the seed layer 112, through the first metal layer 107, through the seed layer 112, to the bond pads 124. The plating layer 308 can be connected to the PCB to electrically couple the PCB to the bond pads 124 and underlying circuitry.

[0048] 5 illustrates a semiconductor packaging structure 350 in which a first metal layer 357 is tapered through an insulating material 354. The bottom of the first metal layer 357 contacts the bond pad 124 through a seed layer 356 and is narrower than the top of the first metal layer 357, which contacts the second metal layer 114. The first metal layer 357 has a top width 355 at the second metal layer 114 and a bottom width 359 at the bond pad 124, where the top width 355 is larger than the bottom width 359. In at least one example, the sides of the second metal layer 114 may also be tapered, narrowing on the die side and widening on the external contact side.

[0049] 6A-6L illustrate an example method for fabricating a semiconductor packaging structure. FIG. 6A illustrates a substrate 102, which may be a silicon substrate including at least one semiconductor device. Bond pads 124 that provide electrical connection to the at least one semiconductor device are disposed on a surface of the substrate 102. In at least one example, polyimide (PI) is applied to the substrate 102 over at least a portion of the bond pads 124. The PI also separates pin locations between the die and the packaging.

[0050] In FIG. 6B , insulating material 140 is formed on the substrate 102 on the same side as bond pad 124. Insulating material 140 is a polymer. In one embodiment, insulating material 140 is a photosensitive material such as a permanent photoresist, e.g., SU-8, Riston™, SPR 220-7, Ordyl P-50100, Diaplate 132, or another permanent photoresist, such as a permanent photoresist manufactured by TOK™, e.g., TMMR-S2000™ or TMMF-S2000™. In another embodiment, insulating material 140 is a molding compound. In at least one example, insulating material 140 is formed by spin-coating a liquid onto substrate 102. In another embodiment, insulating material 140 is formed by depositing a dry film onto substrate 102. In an additional embodiment, insulating material 140 is formed by spray-coating a photoresist. Dry film materials allow for greater thickness and less shrinkage and stress compared to liquids. The liquid or film may then be soft-baked to remove the solvent. In at least one example, for example, if the insulating material has only a small amount of solvent, a soft-baking is not performed. The insulating material 140 is thick, for example, about 5 μm to about 100 μm.

[0051] 6C, an opening 150 is formed in insulating material 140 over bond pad 124 to expose at least a portion of bond pad 124 and retain insulating material 152. In at least one example where the insulating material is permanent photoresist, opening 150 is formed by exposing the permanent photoresist using a photolithography mask. In another embodiment, insulating material 140 is patterned by laser etching or by plasma etching.

[0052] 6D, a seed layer 162 is disposed on the insulating material 152, covering the bottom and sides of the opening 150 over the bond pad 124. The seed layer 106 may be Ti, TiW, TiWCu, Ta, TaN, or another titanium or tantalum alloy. The seed layer 106 may be deposited using evaporation, sputtering, or chemical vapor deposition (CVD).

[0053] 6E, metal 170, such as a copper-containing material, is plated using seed layer 106. Metal 170 fills opening 150 and extends above the top surface of seed layer 162 over insulating material 152. The top surface of metal 170 may have an irregular shape.

[0054] In FIG. 6F, CMP is performed on the top of metal 170 and on the top of seed layer 162 and insulating material 152 to form a planarized surface. The semiconductor structure includes a first metal layer structure including a first metal layer 107 lined with seed layer 106. First metal layer 107 and seed layer 106 are electrically coupled to bond pads 124. Insulating material 104 surrounds first metal layer 107 and seed layer 106. After CMP, an ash clean is performed to remove any copper remaining on the surface. In at least one example, insulating material 104 is replaced with a mold compound. In at least one example, prior to CMP, the semiconductor structure is mounted on a rigid carrier to reduce sintering stress.

[0055] In FIG. 6G, insulating material 180 is applied over the planarized surfaces of insulating material 104, first metal layer 107, and seed layer 106. In one embodiment, insulating material 180 is the same material as insulating material 104 and is applied in the same manner. Due to the planarized surface formed by the CMP process, a boundary exists between insulating material 180 and insulating material 104 even when insulating material 180 and insulating material 104 are composed of the same material. In another example, insulating material 180 is composed of a different material than insulating material 104. In at least one example, insulating material 180 is a polymer material. In at least one example, insulating material 180 is a photosensitive material, for example, a permanent resist such as SU-8. Insulating material 180 is, for example, an insulating material having a thickness of about 25 μm to about 300 μm.

[0056] In FIG. 6H , openings 182 are formed in insulating material 180 to create insulating material 184. The openings 182 at least partially expose the top surface of first metal layer 107. As shown, one of the openings 182 fully exposes the top surface of one portion of first metal layer 107, and one of the openings 182 fully exposes the top surfaces of two portions of first metal layer 107. In at least one example, the openings may expose more portions of the first metal layer, for example, three, four, five, or more portions of the first metal layer. The openings 182 are wider than the first metal layer 107, as shown. In at least one example, the insulating material is permanent photoresist.

[0057] 6I, seed layer 190 is deposited on insulating material 184 to cover the bottom and sides of opening 182. Seed layer 190 may be Ti, TiW, Ta, TaN, or another titanium or tantalum alloy. Seed layer 190 may be deposited using evaporation, sputtering, or CVD. In at least one example, seed layer 190 is less than 2 μm thick.

[0058] 6J, metal 195, for example a copper-containing material, is deposited over seed layer 190. Metal 195 fills opening 182 and extends over insulating material 184 and the top surface of seed layer 190. The top surface of metal 195 may be irregular.

[0059] In Figure 6K, the top surface of metal 195, seed layer 190, and insulating material 184 are CMPed to produce a flat, planarized top surface. After CMP, an ash clean may be performed. In one embodiment, the insulating material is replaced with a mold compound. In one embodiment, both insulating material 110 and insulating material 104 are replaced in a single step.

[0060] 6L, a plating layer 118 is formed on the top, planarized surface of second metal layer 114. In at least one example, plating layer 118 is composed of NiSn, Sn, NiAg, NiPd, NiPdAu, NiAu, or another oxidation-resistant novel surface such as ENIG, ENEG, or ENEPIG. Plating layer 118 protects the copper in second metal layer 114 and provides a robust solder joint with the PCB. Thus, second metal layer 114 and first metal layer 107 are surrounded by plating layer 118, seed layer 112, and seed layer 106.

[0061] To form the semiconductor packaging structure 100 of FIG. 1 from the semiconductor structure illustrated in FIG. 6L, the substrate 102 is thinned and a backside coating 122 is applied to a surface of the substrate 102 opposite the surface containing the bond pads 124. Before applying the backside coating 122, the substrate 102 is thinned to a thickness 103 of, for example, about 50 μm to about 500 μm. In at least one example, the carrier is removed before applying the backside coating 122. The backside coating 122 can be applied using spin coating or film deposition. The backside coating 122 can be between about 10 μm and about 60 μm. In at least one example, the backside coating 122 is an opaque material, such as black. Symbols can also be applied to the semiconductor packaging structure 100 (not shown). The semiconductor packaging structure 100 can also be inspected. The wafer can be singulated to form dies. The plating layers 118 of the dies can be attached to at least one PCB.

[0062] 7A-7G illustrate another exemplary method for fabricating a semiconductor packaging structure. The semiconductor structure illustrated in FIG. 7A is formed from the semiconductor structure illustrated in FIG. 6C. An insulating material 200 is deposited over the insulating material 104 and within the opening 150. The insulating material 200 may be composed of a polymer, which may be a photosensitive material such as SU-8 or another permanent photoresist. The insulating material 200 is applied by spin coating or lamination.

[0063] 7B, a pattern is formed in insulating material 200 to form opening 202 in insulating material 204. Opening 202 extends through insulating material 204 and insulating material 104 to expose at least a portion of bond pad 124. In at least one example where insulating materials 204 and 104 are permanent photoresist, the pattern is formed by photolithography.

[0064] 7C, seed layer 210 is applied to insulating material 204 and insulating material 104, completely covering over bond pad 124 and opening 202. In at least one example, seed layer 210 may be Ti, TiW, Ta, TaN, or another titanium or tantalum alloy and is less than 2 μm thick. Seed layer 210 is deposited by, for example, evaporation, sputtering, or CVD.

[0065] 7D, metal 220, such as a copper-containing material, is plated onto seed layer 210. Metal 220 fills opening 202 and extends above the top of insulating material 204 and seed layer 210. The top surface of metal 220 is irregular.

[0066] 7E, a planarized top surface is formed by performing CMP on the top of metal 220 and on the top of seed layer 210 to form seed layer 230 and metal layer 232. Metal layer 232 includes a second metal layer surrounded by insulating material 110 and a first metal layer surrounded by insulating material 104, with no clear boundary between the metal layers.

[0067] 7F, a plating layer 118, comprised of, for example, NiSn, Sn, NiPd, NiAu, or NiPdAu, is formed on top of metal layer 232. In at least one example, plating layer 118 is about 2 μm to about 8 μm thick. Plated layer 118 may be applied using electroless plating. Plated layer 118 forms a solderable finish that may be used to attach the semiconductor packaging structure to at least one PCB.

[0068] 7G, a backside coating 122, e.g., an opaque film, is formed on the backside of the substrate 102. The backside coating 122 is formed on a surface of the substrate 102 opposite the surface including the bond pads 124. In at least one example, the backside coating 122 is about 10 μm to about 60 μm. The substrate 102 may be thinned before the backside coating 122 is applied. The semiconductor packaging structure in wafer form may be singulated to produce the packaging structures.

[0069] In another embodiment, a die embedded in a molding compound forms a semiconductor packaging structure comprising multiple insulating and metal layers. Figure 8 illustrates a semiconductor packaging structure 400 including a semiconductor structure, such as die 402, embedded in a molding compound 422. In at least one example, the molding compound 422 is an opaque material, such as black. The die 402 is at least one semiconductor device, such as at least one transistor and bond pad 424. The die 402 has a thickness 403 between about 50 μm and about 200 μm, and the molding compound 422 has a thickness 423 between about 100 μm and about 700 μm.

[0070] An insulating material 404 is formed over the die 402 and the mold compound 422. The insulating material 404 can have low water absorption, low elasticity, and high adhesion. The insulating material 404 can also withstand the stresses of manufacturing and operation. In at least one example, the insulating material 110 is a polymer. The insulating material 404 can be a photosensitive material such as a permanent photoresist, such as SU-8, Riston™, or another permanent photoresist, such as a permanent photoresist manufactured by TOK™, such as TMMR-S2000™ or TMMF-S2000™. In at least one example, the insulating material 404 can be a non-photosensitive material, such as a mold compound. In at least one example, the insulating material 404 has a thickness 405 of about 5 μm to about 100 μm.

[0071] A first metal layer structure including a first metal layer 407 and a seed layer 406 is disposed within the opening in the insulating material 404. The first metal layer 407, seed layer 406, and insulating material 404 have planarized top surfaces away from the die 402. The seed layer 406 may be composed of Ti, TiW, TiWCu, Ta, or TaN and may be less than 2 μm thick. The first metal layer 407 may include copper and extend through the insulating material 404 to bond to a bond pad 424 in the die 402 through the bottom of the seed layer 406. In at least one example, the first metal layer 407 has a width 409 of about 25 μm to about 200 μm. The tall and narrow dimensions of the first metal layer 407 provide standoff thickness and flexibility to reduce microstress. In at least one example, different portions of the first metal layer 407 within the semiconductor packaging structure 400 have different widths. In other examples, different portions of the first metal layer 107 in the semiconductor packaging structure 400 have similar or the same width. As shown, the first metal layer structure has straight sidewalls. In at least one example, the first metal layer structure has angled sidewalls, narrowing toward the die 402 and widening away from the die 402. The silicon in the die 402 is completely surrounded by the mold compound 422, the insulating material 404, and the first metal layer structure, including the seed layer 406 and the first metal layer 407.

[0072] The insulating material 410 is disposed on the planarized surfaces of the insulating material 404, the first metal layer 407, and the seed layer 406. The insulating material 410 includes a photosensitive polymer, such as a permanent photoresist. In at least one example, the insulating material 410 is a molding compound. In one embodiment, the insulating material 410 is composed of the same material as the insulating material 404. Due to the planarized surface formed by a CMP process performed on the insulating material 404 before applying the insulating material 410, the insulating material 410 may be distinguishable from the insulating material 404 even if they have the same composition. In at least one example, the insulating material 410 is composed of a different material than the insulating material 404. The insulating material 410 has a thickness 411 of about 25 μm to about 300 μm. In at least one example, the thickness 411 of the insulating material 410 is greater than the thickness 403 of the insulating material 404. In at least one example, thickness 411 is approximately the same thickness as thickness 403 , and thickness 411 is less than thickness 403 .

[0073] The insulating material 410 includes a second metal layer structure including a second metal layer 414 surrounded by a seed layer 412. The seed layer 412 may be composed of Ti, TiW, TiWCu, Ta, and TaN and may be less than 2 μm thick. The second metal layer 414 may include copper and have a thickness 415 greater than 150 μm. The second metal layer 414 extends beyond the edge of the die 402. Therefore, the size of the external contacts may be larger than the size of the die, facilitating current transmission and good contact while maintaining a small die size. This allows for die miniaturization while allowing the die to seamlessly bond to a larger PCB with low current density and low heat density. As shown, the seed layer 412 is located between the second metal layer 414 and the first metal layer 407. However, in at least one example, the second metal layer 414 is disposed directly on the first metal layer 407. As shown, second metal layer 414 has straight sidewalls, but in at least one example, it may have sloped sidewalls that narrow on the die side and widen on the contact side. Second metal layer 414 may provide mechanical and metallurgical strength. Second metal layer 414, seed layer 412, and insulating layer 410 have planarized top surfaces.

[0074] A plating layer 418 is disposed on the planarized surface of the second metal layer 414. The plating layer 418 extends beyond the edge of the die 402. The plating layer 418 is composed of a solderable material such as NiSn, Sn, or a nickel or tin alloy. In at least one example, the plating layer 418 is a solderable metal stack such as ENIG, ENEG, or ENEPIG. The plating layer 418 protects the copper in the second metal layer 414 and the copper in the first metal layer 407, enabling a robust solder joint. The copper in the second metal layer 414 and the first metal layer 407 is completely surrounded by the seed layers 406 and 412 and by the plating layer 418. The plating layer 418 has a thickness of about 2 μm to about 8 μm and extends beyond the top surfaces of the second metal layer 414 and the insulating material 410.

[0075] Although the semiconductor packaging structure 400 is shown with two metal layer structures of increasing width in the insulating material, there may be more metal layer structures than this, for example, 3, 4, or 5 metal layers, with each metal layer having wider features than the lower metal layers. A larger number of layers may facilitate bonding to very large connections.

[0076] At least one example may include an additional layer, such as an additional metal layer, such as COA (copper over anything), or additional polyimide or photoresist, or the like.

[0077] 9 illustrates a semiconductor packaging structure 550 including multiple dies, die 402 and die 552. Die 402 and die 552 are at least partially surrounded by a molding compound 572. In at least one example, molding compound 572 is an epoxy resin. Die 402 includes at least one semiconductor device, such as a transistor, in contact with bond pads 424 and 425. Similarly, die 552 includes at least one semiconductor device, such as at least one transistor, in contact with bond pads 574 and 575.

[0078] An insulating material 554 is disposed over the mold compound 572 and dies 402 and 552 on the side of bond pads 424, 425, 574, and 575. The insulating material 554 can be a polymer, for example, a photosensitive polymer such as a permanent resist. The first metal layer structure includes first metal layers 557, 558, 555, and 559 covered by a seed layer 556. The first metal layers 557, 558, 555, and 559 are made of, for example, a copper-containing material and extend through the insulating material 554 to the bond pads 424, 425, 574, and 575, respectively. Although the first metal layers 557, 558, 559, and 555 are illustrated as being similarly sized, in at least one example, the first metal layers 557 can have different sizes. Seed layer 556 may be composed of Ti, TiW, TiWCu, Ta, TaN, or another titanium or tantalum alloy.

[0079] An insulating material 560 is disposed on insulating material 554. In at least one example, insulating material 560 is composed of the same material as insulating material 554. In other examples, insulating material 560 is composed of a different material than insulating material 560. A second metal layer structure including second metal layer 564 and second metal layer 565 with seed layer 562 on all or a portion of the sides and bottom electrically couples first metal layers 557 and 559 to plated layers 467 and 469, respectively, through insulating material 560. Similarly, second metal layer 566 is on all or a portion of the sides and bottom of second metal layers 564, 566, and 565 by seed layer 570. Second metal layer 566 couples first metal layers 558 and 555 to each other and to plated layer 568. Thus, bond pad 425 on die 402 is electrically coupled to bond pad 574 on die 552.

[0080] In at least one example, there are multiple dies within the semiconductor packaging structure, but the dies are not electrically coupled to one another through the packaging structure, e.g., second metal layer 566 is not present and second metal layer 566 is replaced with two second metal layers that individually couple first metal layers 558 and 555 to individual plating layers, but do not electrically couple first metal layer 558 to first metal layer 555.

[0081] 10A-10O illustrate an exemplary method for manufacturing a semiconductor packaging structure, such as the semiconductor packaging structure 400 illustrated by Fig. 8. In Fig. 10A, a carrier 430 is obtained. The carrier 430 can be a metal such as a steel plate, a wafer such as a silicon wafer, glass, a PCB panel, or an adhesive tape such as polyvinyl chloride (PVC), polyolefin, or polyethylene.

[0082] 10B, dies 402, 442, and 444 are attached to carrier 430. In at least one example, dies 402, 442, and 444 are formed by thinning a wafer and singulating the wafer to produce the dies. In at least one example, dies 402, 442, and 444 are placed directly on carrier 430, for example, when carrier 430 is an adhesive tape. Die 402 is placed with bond pads 424 facing carrier 430, die 442 is placed with bond pads 446 facing carrier 430, and die 444 is placed with bond pads 448 facing carrier 430.

[0083] 10C, mold compound 450 is applied to carrier 430 via a transfer mold to at least partially cover die 402, die 442, and die 444. The system then cures the mold compound, hardening the mold compound. Mold compound 450 can be a plastic material, such as an epoxy resin, that surrounds dies 402, 442, and 444 along with carrier 430.

[0084] 10D, carrier 430 is removed to produce reconstituted wafer 451, which includes mold compound 450 and dies 402, 442, and 444. The active sides of dies 402, 442, and 444, including bond pads 424, 446, and 448, are exposed.

[0085] 10E illustrates a portion of reconstructed wafer 451, inverted for clarity, including mold compound 422 with die 402. Although a single die is shown for clarity, multiple dies, such as dies 442 and 444, or more dies, may be embedded within mold compound 422.

[0086] In at least one example, a layer of polyimide may be applied over die 402 and mold compound 422, for example, over at least some portions of bond pads 424.

[0087] In Figure 10F, insulating material 460 is formed over mold compound 422 and over bond pads 424 on die 402. Insulating material 460 can be a thick polymer layer, for example, about 10 μm to about 100 μm thick. Insulating material 460 can be a photosensitive material such as a permanent photoresist. In another example, insulating material 460 is a mold compound.

[0088] 10G, openings 470 are formed in insulating material 460 over bond pad 424, forming insulating material 472. Openings 470 may be formed by photolithography. In other embodiments, openings 470 are formed by another method, such as laser etching or plasma etching. Although openings 470 are illustrated as being the same size, they may be different sizes. Also, in at least one example, there may be more than two openings, such as three, four, five, six, seven, eight, nine, or more openings. Although openings 470 are illustrated with straight sidewalls, they may have sloped sidewalls that are narrower on one side of the die near bond pad 424 and wider on the other side.

[0089] 10H, seed layer 480 is deposited on top of insulating material 472, covering the bottom and sides of opening 470, including bond pad 424. Seed layer 480 can be Ti, TiW, another titanium alloy, Ta, TaN, or another tantalum alloy. The silicon in die 402 is completely surrounded by mold compound 422, insulating material 472, and seed layer 480. Seed layer 480 acts as a barrier to both die 402 and the first metal layer (which has not yet been fabricated).

[0090] In FIG. 10I, seed layer 480 is plated with a metal 490, such as a copper-containing material.

[0091] 10J, CMP is performed on the top surfaces of metal 490, seed layer 480, and insulating material 472 to form a flat, planarized surface in the semiconductor structure. Seed layer 406 surrounds first metal layer 407 on the bottom and sides, forming a first metal layer structure with an exposed top, planarized surface. In at least one example, insulating material 404 is replaced with a mold compound either before or after CMP.

[0092] 10K, insulating material 492 is formed on the top surfaces of insulating material 404, first metal layer 407, and seed layer 406. Insulating material 492 can be the same material as insulating material 404, or it can be a different material from insulating material 404, such as another polymer material. Due to the planarized surface created by the CMP process, insulating material 492 can be distinguishable from insulating material 404 even if they have the same composition. Insulating material 492 can be very thick, for example, about 50 μm to about 200 μm thick.

[0093] In FIG. 10L, openings 494 are formed in insulating material 492 to form insulating material 483. As shown, openings 494 have relatively straight sidewalls, but they may have angled sidewalls that narrow on the die edge near first metal layer 407 and become wider at the top. First metal layer 407 may have a variety of cross-sections parallel to bond pad 424, including irregular, circular, oval, square, rounded, square, rectangular, or another polygonal shape, such as, for example, a pentagon, hexagon, or octagon. At least one example has more than two openings 494, such as between three and ten openings. Although openings 494 are shown having different sizes, they may have the same or similar sizes.

[0094] 10M, seed layer 496 is deposited on insulating material 483, including over first metal layer 407, and on the bottom and sides of opening 494. Seed layer 496 can be, for example, titanium, tantalum, a titanium alloy, or a tantalum alloy. First metal layer 407 is completely surrounded by seed layer 406 and seed layer 496.

[0095] 10N, metal 498 is plated using seed layer 496. Metal 498 may be a copper-containing material.

[0096] 10O, CMP is performed on the top of metal 498, seed layer 496, and insulating material 483 to form a planar surface in the semiconductor structure comprising second metal layer 414, seed layer 412, and insulating material 483. In this manner, the system forms a second metal layer structure including second metal layer 414 and seed layer 412. Second metal layer 414 extends beyond the edge of die 402. Second metal layer 414 can have a variety of shapes. For example, second metal layer 414 can have relatively straight sidewalls, or they can have sloping sidewalls that narrow due to first metal layer 407 and widen at the top. Second metal layer 414 can have a variety of lateral cross-sections, including irregular, circular, elliptical, square, rounded, square, rectangular, or another polygonal cross-section, such as a pentagonal, hexagonal, or octagonal cross-section. In other examples, the second metal layer 414 has various or irregular shapes.

[0097] To form the semiconductor packaging structure 400 in FIG. 8 from the semiconductor structure illustrated in FIG. 10O, a plating layer 418 is applied to the second metal layer 414 using electroless plating. The plating layer 418 may be composed of NiSn, ENIG, Sn, ENEPIG, ENEG, or another solderable material. The plating layer 418 extends beyond the edges of the die 402. The second metal layer 414 is completely surrounded by the seed layer 412 and the plating layer 418 to prevent silicon migration. After applying the plating layer 418, singulation is performed to form individual semiconductor packaging structures. The semiconductor packaging structure 400 can then be attached to a PCB by the plating layer 418.

[0098] 11A-11F illustrate another exemplary method for fabricating a semiconductor packaging structure including a die. In FIG. 11A, insulating material 500 is formed over insulating material 404 and within opening 470 of the semiconductor structure shown in FIG. 10G. Insulating material 500 may be a polymer, such as a permanent photoresist, having a thickness of about 50 μm to about 250 μm. Insulating material 500 may be the same material as insulating material 404. In other examples, insulating material 500 is a different material from insulating material 404, such as a different polymer material.

[0099] 11B, an opening 510 is formed in insulating material 500 to form insulating material 512. Opening 510 extends through insulating material 512 and insulating material 404 to bond pad 424. If insulating material 500 is a photosensitive material, opening 510 may be formed by exposing insulating material 500 using a photolithography mask, developing insulating material 500, and curing insulating material 500. In other examples, opening 510 is formed by plasma etching or laser etching.

[0100] 11C, a seed layer 520 is formed on insulating material 512, covering opening 510 and contacting bond pad 424. Seed layer 520 is formed by sputtering or evaporation to completely cover insulating material 512. Seed layer 522 provides a barrier and may be composed of, for example, titanium, tantalum, a titanium alloy, or a tantalum alloy. Die 402 is completely surrounded by mold compound 422, insulating material 404, and seed layer 522.

[0101] In FIG. 11D, a metal 530, such as a copper-containing material, is plated using the seed layer 520.

[0102] 11E, CMP is performed to form a flat, planarized top surface by removing metal 530, insulating material 512, and the top of seed layer 520. Thus, metal layer 540 is formed, including the second metal layer and the first metal layer, coated with seed layer 542. Metal layer 540 extends laterally beyond the edge of die 402.

[0103] 11F, a plating layer 418 is formed on the metal layer 540 by electroless plating to form a semiconductor packaging structure 547. The plating layer 418 is a solderable finish composed of, for example, Ni / Sn, ENIG, ENEPPIG, ENEG, or Sn. The plating layer 418 extends laterally beyond the edge of the die 402. The metal layer 540 is completely surrounded by the seed layer 542 and the plating layer 418. The semiconductor packaging structure 547 can be attached to a PCB by the plating layer 418.

[0104] 12 shows a flowchart 600 for an exemplary method of manufacturing a semiconductor packaging structure. Dies are formed in an integrated circuit at block 602. On top of the wafer, a system fabricates bond pads for external connections.

[0105] In block 604, the system fabricates multiple layers of metal structures, each surrounded by insulating material on the wafer fabricated in block 602. FIGS. 6A-6L, 6I, and 7A-7G illustrate some example processes that may be performed in block 604. Two, three, or more insulating materials are fabricated with progressively wider metal structures, with a first metal layer on the first layer contacting the bond pads. The system applies a plating layer to the outermost metal layer. In this manner, the system forms a semiconductor packaging structure.

[0106] In block 606, the system performs backside grinding on the semiconductor packaging structure produced in block 604 to produce a thinned wafer structure having a desired thickness. The system cleans the top surface of the semiconductor packaging structure. The system also applies protective tape on the top surface of the wafer to protect the wafer from mechanical damage and contamination. The system loads the wafer onto a cassette and places the cassette in a cassette holder of a backside grinding machine. The backside grinding machine uses a robotic arm to pick up the backside of the wafer and position it for backside grinding. A grinding wheel performs backside grinding on the wafer. The system may continuously rinse the wafer with deionized water during backside grinding. After backside grinding, the system returns the wafer to the cassette. The system removes the backside grinding tape from the wafer using, for example, a de-tape tool.

[0107] In block 608, the system applies a backside coating to the backside of the thinned wafer structure produced in block 604 to produce a coated wafer structure. The backside coating 122 can be an opaque film. The system applies the film backside coating to the wafer using spin coating or film application.

[0108] In block 610, the system applies a symbol to the coated wafer structure, e.g., the backside coating, to generate a symbol wafer structure. The symbol identifies the die.

[0109] At block 612, the system singulates the wafer to produce individually packaged dies. The system mounts a symbol wafer structure on plastic tape that is attached to a ring using an adhesive film. The system dices the wafer using a metal or resin bond that includes abrasive grits such as natural diamond, synthetic diamond, or borazon. These dies can then be attached to a PCB using a plating layer.

[0110] 13 shows a flowchart 800 for an exemplary method of manufacturing a semiconductor packaging structure. In block 802, a system manufactures semiconductor devices on a wafer. Integrated circuits and related elements are fabricated within the wafer, with bond pads providing external connections.

[0111] In block 804, the system performs backside grinding on the wafer using the semiconductor devices fabricated in block 802 to thin the wafer to a desired thickness and produce a thinned wafer structure. The system cleans the top surface of the wafer. The system also applies protective tape over the top surface of the wafer to protect the wafer from mechanical damage and contamination. A grinding wheel performs backside grinding on the wafer. The system may continuously rinse the wafer with deionized water during backside grinding. The system removes the backside grinding tape from the wafer.

[0112] In block 806, the system singulates the thinned wafer structure to produce dies. The system mounts the wafer on a plastic tape attached to a ring using an adhesive film. The system dices the wafer using, for example, a metal or resin bond containing abrasive grit such as natural diamond, synthetic diamond, or borazon.

[0113] In block 808, the system attaches the die to the carrier with the bond pads facing the carrier. Figure 10B illustrates an example of the process shown in block 808. If an adhesive material, such as adhesive tape, is used, the system attaches the die directly to the adhesive material. If a non-adhesive material, such as a wafer or PCB panel, is used, the system attaches the die to the carrier using glue.

[0114] In block 810, the system performs molding around the die. Figure 10C illustrates an example of the process performed in block 810. In transfer molding, the system liquefies the molding compound and transfers the molding compound into a mold press. The system then cures the molding compound, hardening the molding compound. The mold can be a plastic material such as, for example, an epoxy resin.

[0115] In block 812, the system removes the carrier, leaving a reconstituted wafer with the mold compound holding the die. Figure 10D illustrates an example of the process that occurs in block 812. The active side of the die, including the bond pads, is exposed.

[0116] In block 814, the system forms chip fan-out packaging on the reconstructed wafer. Multiple layers of insulating material with bond pads are fabricated, with the layer closest to the die having the narrowest features (first metal layer) and the layer farthest from the die having the widest bond pads. Figures 10E-10O, 8, and 11A-11F illustrate examples of the process performed in block 814. The bond pads on the top layer may extend beyond the edge of the die. In at least one example, the top metal layer electrically couples multiple dies. The system also forms a plating layer on the outermost metal layer.

[0117] In block 816, the system applies an identification symbol onto the mold compound opposite the metal layer.

[0118] At block 818, the system singulates the wafer by dicing the mold compound between the dies to form the dies. In one embodiment, each die is in an individual packaging structure. In another example, multiple dies are bonded together into a single packaging structure using a mold compound. The dies may be attached to a PCB using a plating layer.

[0119] FIG. 14 shows a flowchart 700 for an example method of manufacturing a semiconductor packaging structure. Flowchart 700 describes a method that may be performed, for example, in block 604 of flowchart 600, block 814 of flowchart 800, and in FIGS. 6A-6L, 1, 7A-7G, 10A-10O, 8, and 11A-11F. In block 702, the system obtains a wafer or die. The wafer or die includes at least one semiconductor device with bond pads. In one embodiment, the wafer is a reconstituted wafer including a die embedded in a molding compound.

[0120] In block 704, the system applies an insulating material to the bond pad side of the wafer or die obtained in block 702. The system may apply the insulating material by spin-coating or laminating the insulating material onto the wafer. The system may bake the wafer to remove solvents from the insulating material. The insulating material may be a polymer such as a permanent photoresist. In one example, the insulating material is a mold compound.

[0121] In block 706, the system forms openings in the insulating material applied in block 704. For example, the system performs photolithography on the insulating material, which is permanent photoresist. The system exposes the permanent photoresist using a photolithography mask. The system then develops the permanent photoresist and bakes the developed photoresist. In another example, the system patterns the insulating material by laser etching or plasma etching the insulating material. In one embodiment, the system proceeds to block 714 and applies a second layer of insulating material. In another embodiment, the system proceeds to block 708 and deposits a seed layer in the insulating material.

[0122] In block 708, the system deposits a seed layer in the opening formed in block 706 and over the insulating material. The seed layer may be composed of, for example, Ti, TiW, TiWCu, Ta, or TaN. The system may deposit the seed material by sputtering, evaporation, or CVD to coat the top of the insulating material and completely cover the opening.

[0123] In block 710, the system plates a metal, such as a copper-containing material, over the seed layer formed in the opening in block 708. The system overplates the metal, extending it over the top of the insulating material.

[0124] In block 712, the system performs CMP on the top of the metal layer, the seed layer, and the insulating material to form a planarized top surface. In this manner, the system produces a semiconductor post structure comprising a semiconductor post lined on the bottom and sides with the seed layer.

[0125] In block 714, the system applies an insulating material over the first insulating material, for example, by spin-coating or depositing the insulating material. In one embodiment, the insulating material is deposited over the first metal layer structure formed in block 712. In another embodiment, the insulating material is deposited in the opening formed in block 706. The second insulating material can be the same material as the first insulating material. In other examples, the second insulating material is a different layer from the first insulating material. The second insulating material can be a photosensitive material, such as a permanent photoresist.

[0126] In block 716, the system forms an opening in the second insulating material. For example, the system performs photolithography to form the opening. The system exposes the permanent photoresist using a photolithography mask. The system then develops the permanent photoresist and bakes the developed photoresist. In another example, the system patterns the insulating material by laser etching or plasma etching the insulating material.

[0127] In block 718, the system deposits a seed layer over the second insulating material, including in the opening formed in block 716. The system may deposit the seed layer by evaporation, sputtering, or CVD.

[0128] At block 720, the system plates a seed layer, for example with a copper-containing material, to fill the opening in the insulating material. The system overplates the metal so that it extends over the top of the second insulating material.

[0129] At block 722, the system performs CMP on the metal layer, the seed layer, and the insulating material to form a planarized surface. In this manner, the system forms a second metal layer structure including a second metal layer at least partially surrounded by the seed layer. In at least one example, the thick metal layer structure extends laterally beyond the edge of the die.

[0130] In at least one example, blocks 714, 716, 718, 720, and 722 are repeated to form additional layers of increasingly wider metal features surrounded by insulating material.

[0131] At block 724, the system performs electroless plating to form a plating layer on the second metal layer. The plating layer can be Ni / Sn, ENIG, ENEPPIG, ENEG, Sn, or another plating layer.

[0132] Modifications are possible in the described embodiments and other embodiments are possible within the scope of the claims.

Claims

1. 1. A semiconductor packaging structure, comprising: a die including bond pads on a surface of the die; a segment of a first metal layer structure disposed on the die, the segment having a first width in a direction parallel to the die surface and a first thickness in a direction perpendicular to the die surface, the segment including a first metal layer and a first seed layer surrounding a bottom and side surfaces of the first metal layer and coupled to the bond pad; a first photosensitive material around the sides of the segments of the first metal layer structure; a second metal layer structure segment disposed on the first metal layer structure segment and on a portion of the first photosensitive material, the second metal layer structure segment having a second width in a direction parallel to the die surface and a second thickness in a direction perpendicular to the die surface, the second width being greater than the first width and the second thickness being greater than the first thickness, the second metal layer segment including: a second metal layer; and a second seed layer surrounding a bottom and side surface of the second metal layer and coupled to the first metal layer and the first seed layer; a second photosensitive material around the sides of the segments of the second metal layer structure; a plating layer disposed on the segments of the second metal layer structure, the plating layer protruding from the second photosensitive material to provide a solder joint; Including, The semiconductor packaging structure, wherein the second metal layer is completely surrounded by the second seed layer and the plating layer.

2. 10. The semiconductor packaging structure of claim 1, A semiconductor packaging structure, wherein the first photosensitive material is a permanent photoresist.

3. 10. The semiconductor packaging structure of claim 1, A semiconductor packaging structure, wherein the first thickness is between 3 μm and 100 μm, and the first width is between 20 μm and 200 μm.

4. 10. The semiconductor packaging structure of claim 1, The semiconductor packaging structure, wherein the second thickness is between 25 μm and 300 μm, and the second width is greater than 150 μm.

5. 10. The semiconductor packaging structure of claim 1, the segments of the first metal layer structure further have a cross section that is rectangular, square, circular, or elliptical; A semiconductor packaging structure, wherein the segment of the second metal layer structure further has a cross section that is rectangular, circular, elliptical, polygonal, or polygonal with rounded corners.

6. 10. The semiconductor packaging structure of claim 1, the bond pad is a first bond pad; A semiconductor packaging structure, wherein a segment of the first metal layer structure electrically couples a segment of the second metal layer structure to a second bond pad of the die.

7. 10. The semiconductor packaging structure of claim 1, A semiconductor packaging structure, wherein the segment of the first metal layer structure has a top width where it abuts the segment of the second metal layer structure and a bottom width where it abuts the bond pad, the top width being greater than the bottom width.

8. 10. The semiconductor packaging structure of claim 1, the bond pad is located on a first side of the die; The semiconductor packaging structure further includes a backside coating disposed on a second side of the die opposite the first side of the die.

9. 9. The semiconductor packaging structure of claim 8, A semiconductor packaging structure, wherein the backside coating is a black film.

10. 10. The semiconductor packaging structure of claim 1, The semiconductor packaging structure does not include solder.

11. 10. The semiconductor packaging structure of claim 1, the segments of the first metal layer structure further comprise copper or an alloy of a conductive metal; A semiconductor packaging structure, wherein the segments of the second metal layer structure further comprise copper or an alloy of a conductive metal.

12. 10. The semiconductor packaging structure of claim 1, the segments of the second metal layer structure have planarized surfaces; a plating layer disposed on the planarized surface of the segment of the second metal layer structure, and at least a portion of the plating layer extending above the top surface of the second photosensitive material;

13. 13. The semiconductor packaging structure of claim 12, A semiconductor packaging structure, wherein the first thickness is between 3 μm and 100 μm, and the first width is between 25 μm and 200 μm.

14. 14. The semiconductor packaging structure of claim 13, The semiconductor packaging structure, wherein the second thickness is between 25 μm and 300 μm, and the second width is greater than 150 μm.

15. 13. The semiconductor packaging structure of claim 12, The semiconductor packaging structure, wherein the plating layer has a thickness of 2 μm to 8 μm.

16. 13. The semiconductor packaging structure of claim 12, The semiconductor packaging structure, wherein the first seed layer, the second seed layer, and the plating layer surround the first metal layer and the second metal layer.

17. 13. The semiconductor packaging structure of claim 12, 1. A semiconductor packaging structure, wherein the plating layer comprises Ni, NiAu, NiPd, NiPdAu, NiAg, Sn, NiSn, electroless nickel immersion gold (ENIG), electroless nickel electroless gold (ENEG), or electroless nickel electroless palladium immersion gold (ENEPIG).

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