Liquid ejection device and temperature calculation device

Abstract

To provide a liquid discharge device that accurately grasp a junction temperature.SOLUTION: A liquid discharge device comprises: a discharge part including a piezoelectric element that changes volume in response to a drive signal to discharge liquid; a drive signal generation part including a class-D amplifier circuit that generates the drive signal; and a temperature calculation part that calculates the temperature of the class-D amplifier circuit. The temperature calculation part includes: a signal acquisition circuit that acquires, at a first timing when an amplified modulation signal satisfies a predetermined condition, first information representing the voltage value of a gate signal and second information representing the voltage value of the amplified modulation signal; and a temperature calculation circuit that outputs a temperature information signal of a first transistor based on the first and second information.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a liquid ejection device and a temperature calculation device. [Background technology]

[0002] BACKGROUND ART Inkjet printers are known that print images or documents on a medium by ejecting ink as a liquid (see, for example, Patent Documents 1 and 2). Among such ink jet printers, those using piezoelectric elements such as piezo elements are known.

[0003] The contents of Patent Document 1 will be described (see, for example, paragraphs 0108 to 0112 of Patent Document 1). For convenience of explanation, the description will be made with reference to FIGS. 3 and 4, which are also referred to in the embodiments. 4, the voltage signal As is a triangular wave, and its oscillation frequency varies depending on the voltage of the first analog base drive signal aA. Specifically, the oscillation frequency is highest when the voltage is at an intermediate value, and decreases as the voltage increases or decreases from the intermediate value.

[0004] Furthermore, the slope of the triangular wave of the voltage signal As is approximately equal when the voltage rises and falls when the voltage is near the intermediate value. Therefore, the duty ratio of the modulation signal Ms obtained by comparing the voltage signal As with the first threshold Vth1 and the second threshold Vth2 of the comparator 514 is approximately 50%. When the voltage of the voltage signal As rises from the intermediate value, the downward slope of the voltage signal As becomes gentler. Therefore, the period during which the modulation signal Ms is at the H level becomes relatively longer, and the duty ratio of the modulation signal Ms becomes larger. On the other hand, when the voltage of the voltage signal As falls from the intermediate value, the upward slope of the voltage signal As becomes gentler. Therefore, the period during which the modulation signal Ms is at the H level becomes relatively shorter, and the duty ratio of the modulation signal Ms becomes smaller.

[0005] The first gate driver 521 controls the first transistor M1 to be on or off based on the modulation signal Ms. That is, the first gate driver 521 controls the first transistor M1 to be on when the modulation signal Ms is at H level, and to be off when the modulation signal Ms is at L level. The second gate driver 522 controls the second transistor M2 to be on or off based on the logically inverted signal of the modulation signal Ms. That is, the second gate driver 522 controls the second transistor M2 to be off when the modulation signal Ms is at H level, and to be on when the modulation signal Ms is at L level.

[0006] Therefore, the voltage value of the first drive signal COMA, which is obtained by smoothing the amplified modulated signal output from the amplifier 550 by the smoothing circuit 560, increases as the duty ratio of the modulated signal Ms increases, and decreases as the duty ratio decreases. In other words, the waveform of the first drive signal COMA is controlled to have a waveform that is an expanded version of the voltage of the first analog base drive signal aA, which is obtained by converting the digital first base drive signal dA into analog.

[0007] Furthermore, because the first drive circuit 50-a uses pulse density modulation, it has the advantage of being able to vary the duty ratio over a wider range than pulse width modulation, which has a fixed modulation frequency. The minimum positive and negative pulse widths that can be used in the first drive circuit 50-a are limited by circuit characteristics. Therefore, in pulse width modulation, which has a fixed frequency, the range of variation in the duty ratio is limited within a predetermined range. In contrast, in pulse density modulation, the oscillation frequency decreases as the voltage of the voltage signal As moves away from the median value, making it possible to increase the duty ratio in high-voltage ranges. Furthermore, it is possible to decrease the duty ratio in low-voltage ranges. Therefore, by adopting self-oscillating pulse density modulation, it is possible to ensure a wider range of variation in the duty ratio.

[0008] The contents of Patent Document 2 will be described (see, for example, paragraphs 0015 and 0034 of Patent Document 2). In the inkjet printer, the control unit uses an arithmetic formula to calculate the calculated fin temperature from the ambient temperature, the power loss of the drive element calculated from the drop volume determination unit and the power loss data table for each drive waveform, the ratio of the number of nozzles by drop volume to the total number of nozzles in the head calculated from the nozzle number counting means by drop volume, the known maximum junction temperature, the thermal resistance from the junction to the cooling fin, and the ambient temperature detected by the ambient temperature detection unit, and if the detected fin temperature detected by the fin temperature detection unit is higher than the calculated fin temperature, it determines that an overheating error has occurred in the drive element.

[0009] Here, the droplet volume determination unit determines dot data for each ink droplet volume from the print data and counts the number of driven nozzles for the determined ink droplet volume.The droplet volume determination unit then calculates the drive duty by dividing the counted number of driven nozzles by the total number of nozzles in the nozzle row.For example, if the number of driven nozzles for large ink droplet volume is 50 and the total number of nozzles in the nozzle row is 100, the drive duty is 0.5 (= 50 / 100 = 0.5). In this way, by using the drive duty of the drive waveform at the time immediately before ink ejection, it is possible to use the drive duty that is closest to the timing at which transistor overheating is detected. Note that the calculation period for the drive duty is not limited to that time, and for example, the drive duty for a period from that time to another time may be used. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Patent Publication No. 2021-30699 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-14096 Summary of the Invention [Problem to be solved by the invention]

[0011] As described in Patent Document 1, an inkjet is known that ejects liquid by driving a piezoelectric element using a highly efficient class D amplifier (see Patent Document 1). In such a class D amplifier circuit, a modulation signal is generated using self-excited pulse density modulation, which makes it possible to ensure a wider range of variation in the duty ratio.

[0012] Inkjet printers also require high-voltage operation because they use piezoelectric elements, whose volume changes in proportion to the voltage applied, to eject droplets. In addition, the current flowing instantaneously is large due to the recent increase in demand for high-speed printing. This means that high voltages and large currents flow through the transistors used in class-D amplifiers, causing them to become extremely hot. If the temperature of a transistor exceeds its allowable limit, it could be damaged. Therefore, to prevent this, it is necessary to monitor the temperature of the heat-generating part.

[0013] Here, methods for indirectly determining junction temperature have been known for some time (see Patent Document 2), but it is difficult to accurately grasp the value of thermal resistance or heat dispersion, and there has been insufficient research from the perspective of accurately measuring the heat generation of a transistor. Furthermore, because switching occurs at several MHz and the temperature is constantly changing, it is not easy to grasp the temperature at the timing when the heat-generating part reaches its maximum temperature. [Means for solving the problem]

[0014] In one aspect to solve the above problem, a liquid ejection device includes an ejection unit including a piezoelectric element that changes in volume in response to a drive signal to eject liquid, a drive signal generation unit including a class D amplifier circuit that generates the drive signal, and a temperature calculation unit that calculates the temperature of the class D amplifier circuit, wherein the class D amplifier circuit includes a DAC that converts a base drive signal into an analog base drive signal, a modulation circuit that pulse density modulates the analog base drive signal and outputs a modulated signal, an amplifier circuit that amplifies the modulated signal and outputs an amplified modulated signal, a demodulation circuit that demodulates the amplified modulated signal and outputs the drive signal, and a feedback circuit that feeds back the drive signal to the modulation circuit. and a feedback circuit, wherein the amplifier circuit includes a gate driver that outputs a gate signal based on the modulation signal, and a half-bridge circuit in which a first transistor and a second transistor are connected at a connection point and the amplified modulation signal is output from the connection point in response to the gate signal, and the temperature calculation unit includes a signal acquisition circuit that acquires first information, which is a voltage value of the gate signal, and second information, which is a voltage value of the amplified modulation signal, at a first timing when the amplified modulation signal satisfies a predetermined condition, and a temperature calculation circuit that outputs a temperature information signal of the first transistor based on the first information and the second information.

[0015] In order to solve the above problem, one aspect is a temperature calculation device that calculates the temperature of a class-D amplifier circuit, wherein the class-D amplifier circuit has a DAC that converts a reference drive signal into an analog reference drive signal, a modulation circuit that pulse density modulates the analog reference drive signal and outputs a modulated signal, an amplifier circuit that amplifies the modulated signal and outputs an amplified modulated signal, a demodulation circuit that demodulates the amplified modulated signal and outputs a drive signal, and a feedback circuit that feeds back the drive signal to the modulation circuit, and the amplifier circuit includes a gate driver that outputs a gate signal based on the modulated signal, and a half-bridge circuit in which a first transistor and a second transistor are connected at a connection point and output the amplified modulated signal from the connection point in response to the gate signal, and the temperature calculation device includes a signal acquisition circuit that acquires first information that is a voltage value of the gate signal and second information that is a voltage value of the amplified modulated signal at a first timing when the amplified modulated signal satisfies a predetermined condition, and a temperature calculation circuit that outputs a temperature information signal of the first transistor based on the first information and the second information. [Brief explanation of the drawings]

[0016] [Figure 1A] 1 is a diagram showing a schematic internal configuration of a liquid ejection device according to an embodiment; [Figure 1B] FIG. 2 is a diagram showing the electrical configuration of the liquid ejection device according to the embodiment. [Figure 2] 3 is a diagram showing an outline of the circuit configuration of a first control circuit of the liquid ejection device according to the embodiment. FIG. [Figure 3] FIG. 2 is a diagram showing a circuit configuration of a drive circuit according to an embodiment. [Figure 4] 3A and 3B are diagrams showing waveforms of a voltage signal and a modulation signal according to an embodiment in relation to the waveform of an analog base drive signal. [Figure 5] 5A and 5B are diagrams for explaining the operation of a selection control circuit and a selection circuit according to the embodiment; [Figure 6] FIG. 2 is a diagram illustrating a circuit configuration of a temperature calculation unit according to the embodiment. [Figure 7]FIG. 10 is a diagram showing an example of the relationship between drain current, gate-source voltage, and junction temperature according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments will be described with reference to the drawings.

[0018] FIG. 1A is a diagram showing a schematic internal configuration of a liquid ejection device 1 according to an embodiment. The liquid ejection device 1 is an inkjet printer that ejects ink as a liquid in accordance with image data supplied from an external host computer to form dots on a medium P such as paper, thereby printing an image in accordance with the supplied image data. Note that part of the configuration of the liquid ejection device 1, such as the housing and cover, is not shown in Figure 1A.

[0019] 1A, the liquid ejection device 1 includes a movement mechanism 3 that moves the head unit 2 in the main scanning direction Qa1. The movement mechanism 3 includes a carriage motor 31 that serves as the drive source for the head unit 2, a carriage guide shaft 32 that is fixed at both ends, and a timing belt 33 that extends substantially parallel to the carriage guide shaft 32 and is driven by the carriage motor 31. The movement mechanism 3 also includes a linear encoder 90 that detects the position of the head unit 2 in the main scanning direction Qa1.

[0020] The carriage 24 of the head unit 2 is configured to be able to mount a predetermined number of ink cartridges 22. The carriage 24 is supported by a carriage guide shaft 32 so that it can move back and forth, and is fixed to a portion of a timing belt 33. Therefore, by causing the carriage motor 31 to move the timing belt 33 forward and backward, the carriage 24 of the head unit 2 is guided by the carriage guide shaft 32 and moves back and forth. In other words, the carriage motor 31 moves the carriage 24 in the main scanning direction Qa1. The head 20 is attached to a portion of the carriage 24 that faces the medium P. The head 20 has a number of nozzles, and ejects a predetermined amount of ink from each nozzle at a predetermined timing. Various control signals are supplied to the head unit 2, which operates as described above, via a flexible flat cable 190.

[0021] The liquid ejection device 1 includes a transport mechanism 4 that transports the medium P in the sub-scanning direction Qa2. The transport mechanism 4 includes a platen 40 that supports the medium P, a transport motor 41 that serves as a drive source, and a transport roller 42 that is rotated by the transport motor 41 and transports the medium P in the sub-scanning direction Qa2. With the medium P supported by the platen 40, ink is ejected from the head 20 onto the medium P in accordance with the timing at which the medium P is transported by the transport mechanism 4, thereby forming a desired image on the surface of the medium P.

[0022] A home position, which serves as the base point for the head unit 2, is set in an end region within the movement range of the carriage 24 included in the head unit 2. A capping member 70 that seals the nozzle formation surface of the head 20 and a wiper member 71 that wipes the nozzle formation surface are disposed at the home position. The liquid ejection device 1 forms an image on the surface of the medium P in both directions: when the carriage 24 moves outward from this home position toward the opposite end, and when the carriage 24 moves back from the opposite end toward the home position.

[0023] A flushing box 72 that collects ink ejected from the head 20 during a flushing operation is disposed at the end of the platen 40 in the main scanning direction Qa1, opposite the home position to which the carriage 24 moves. The flushing operation is an operation that forcibly ejects ink from each nozzle regardless of image data to prevent nozzle clogging due to thickening of ink near the nozzles or air bubbles getting into the nozzles, which could prevent the appropriate amount of ink from being ejected. The flushing box 72 may be provided on both sides of the platen 40 in the main scanning direction Qa1.

[0024] FIG. 1B is a diagram showing the electrical configuration of the liquid ejection device according to the embodiment. 1B, the liquid ejection device 1 has a control unit 10 and a head unit 2. The control unit 10 and the head unit 2 are electrically connected via a flexible flat cable 190.

[0025] The control unit 10 has a control circuit 100, a carriage motor driver 35, and a transport motor driver 45. The control circuit 100 generates control signals according to image data supplied from the host computer, and outputs them to the corresponding components.

[0026] Specifically, the control circuit 100 determines the current scanning position of the head unit 2 based on the detection signal of the linear encoder 90. The control circuit 100 then generates a first control signal CTR1 and a second control signal CTR2 according to the current scanning position of the head unit 2. The first control signal CTR1 is supplied to a carriage motor driver 35. The carriage motor driver 35 drives the carriage motor 31 in accordance with the input first control signal CTR1. The second control signal CTR2 is supplied to a transport motor driver 45. The transport motor driver 45 drives the transport motor 41 in accordance with the input second control signal CTR2. This controls the movement of the carriage 24 in the main scanning direction Qa1 and the transport of the medium P in the sub-scanning direction Qa2.

[0027] In addition, the control circuit 100 generates a clock signal SCK, a print data signal SI, a latch signal LAT, a change signal CH, a first drive signal dA, and a second drive signal dB according to the current scanning position of the head unit 2 based on image data supplied from an external host computer and the detection signal of the linear encoder 90, and outputs them to the head unit 2.

[0028] Furthermore, the control circuit 100 causes the maintenance unit 80 to perform a maintenance process for restoring the ink ejection state of the first ejection section 600-1 to the N-th ejection section 600-N to normal. Here, N is an integer equal to or greater than 2. The first discharge section 600-1 to the Nth discharge section 600-N have the first piezoelectric element 60-1 to the Nth piezoelectric element 60-N, respectively. The first selection circuit 230-1 to the Nth selection circuit 230-N are provided corresponding to the first discharge section 600-1 to the Nth discharge section 600-N, respectively. The maintenance unit 80 has a cleaning mechanism 81 and a wiping mechanism 82. As a maintenance process, the cleaning mechanism 81 performs a pumping process in which a tube pump (not shown) is used to suck out thickened ink or air bubbles that have accumulated inside the first discharge section 600-1 to the Nth discharge section 600-N. As a maintenance process, the wiping mechanism 82 performs a wiping process in which a wiper member 71 is used to wipe away foreign matter such as paper dust that has adhered to the vicinity of the nozzles of the first discharge section 600-1 to the Nth discharge section 600-N. Note that the control circuit 100 may also execute a flushing operation as a maintenance process to restore the ink discharge state of the first discharge section 600-1 to the Nth discharge section 600-N to normal.

[0029] The head unit 2 includes a first drive circuit 50-a, a second drive circuit 50-b, and a head 20.

[0030] A digital first group drive signal dA is input to the first drive circuit 50-a. The first drive circuit 50-a performs digital-to-analog conversion on the input first group drive signal dA and performs class-D amplification on the converted analog signal to generate a first drive signal COMA, which is output to the head 20. Similarly, a digital second group drive signal dB is input to the second drive circuit 50-b. The second drive circuit 50-b performs digital-to-analog conversion on the input second group drive signal dB and performs class-D amplification on the converted analog signal to generate a second drive signal COMB, which is output to the head 20.

[0031] That is, the first drive signal dA determines the waveform of the first drive signal COMA, and the second drive signal dB determines the waveform of the second drive signal COMB. Therefore, the first drive signal dA and the second drive signal dB may be any signal capable of determining the waveforms of the first drive signal COMA and the second drive signal COMB, and may be, for example, analog signals. Furthermore, while the description of FIG. 1B illustrates that the first drive circuit 50-a and the second drive circuit 50-b are included in the head unit 2, each of the first drive circuit 50-a and the second drive circuit 50-b may be included in the control unit 10. In this case, the first drive signal COMA and the second drive signal COMB output by the first drive circuit 50-a and the second drive circuit 50-b, respectively, are supplied to the head 20 of the head unit 2 via a flexible flat cable 190.

[0032] The head 20 includes a selection control circuit 210, a plurality of selection circuits, namely, a first selection circuit 230-1 to an N-th selection circuit 230-N, and a first ejection section 600-1 to an N-th ejection section 600-N corresponding to the first selection circuit 230-1 to the N-th selection circuit 230-N, respectively. The selection control circuit 210 generates a selection signal for selecting or not selecting the waveforms of the first drive signal COMA and the second drive signal COMB based on the clock signal SCK, print data signal SI, latch signal LAT, and change signal CH supplied from the control circuit 100, and outputs the selection signal to each of the first selection circuit 230-1 to the N-th selection circuit 230-N.

[0033] Each of the first selection circuit 230-1 to the Nth selection circuit 230-N receives as input the first drive signal COMA, the second drive signal COMB, and a selection signal output by the selection control circuit 210. The first selection circuit 230-1 to the Nth selection circuit 230-N then selects or deselects the waveforms of the first drive signal COMA and the second drive signal COMB based on the input selection signal, thereby generating a drive signal VOUT based on the first drive signal COMA and the second drive signal COMB, and outputs it to the corresponding first discharge unit 600-1 to the Nth discharge unit 600-N.

[0034] Each of the first ejection sections 600-1 to N-th ejection sections 600-N includes a first piezoelectric element 60-1 to an N-th piezoelectric element 60-N. A drive signal VOUT output from the corresponding first selection circuit 230-1 to N-th selection circuit 230-N is supplied to one end of each of the first piezoelectric elements 60-1 to N-th piezoelectric elements 60-N. A reference voltage signal VBS is applied to the other end of each of the first piezoelectric elements 60-1 to N-th piezoelectric elements 60-N. The first piezoelectric elements 60-1 to N-th piezoelectric elements 60-N included in the first ejection sections 600-1 to N-th ejection sections 600-N are driven in response to the potential difference between the drive signal VOUT supplied to one end and the reference voltage signal VBS supplied to the other end. A volume of ink corresponding to the drive of each of the first piezoelectric elements 60-1 to N-th piezoelectric elements 60-N is ejected from each of the first ejection sections 600-1 to N-th ejection sections 600-N.

[0035] Here, the first drive circuit 50-a that outputs the first drive signal COMA is an example of a drive signal output circuit, and the second drive circuit 50-b that outputs the second drive signal COMB is another example of a drive signal output circuit. Therefore, the first drive signal COMA is an example of a drive signal, and the second drive signal COMB is another example of a drive signal. The drive signal VOUT generated by selecting the waveforms of the first drive signal COMA and the second drive signal COMB is also an example of a drive signal. The first piezoelectric elements 60-1 to the N-th piezoelectric elements 60-N that are driven by the supply of the drive signal VOUT are an example of a drive element. The head 20 that has the first piezoelectric elements 60-1 to the N-th piezoelectric elements 60-N and ejects liquid by driving the first piezoelectric elements 60-1 to the N-th piezoelectric elements 60-N is an example of a liquid ejection head.

[0036] FIG. 2 is a diagram showing an outline of the circuit configuration of the first control circuit 701 of the liquid ejection device 1 according to the embodiment. The first control circuit 701 includes a class D amplifier circuit J1, a temperature calculation unit J2, a determination unit J3, and a piezoelectric element J4. The class D amplifier circuit J1 includes a capacitor 711, a first IC 712 which is an IC, a high-side amplifier 713, a low-side amplifier 714, and an LC filter 715. The temperature calculation unit J2 includes a first voltage detector 731, a second voltage detector 732, and a conversion microcomputer 733 that is a microcomputer that functions as a calculator. The high-side amplifier 713 and the low-side amplifier 714 are each configured using, for example, a field effect transistor (FET). The determination unit J3 includes a system on a chip (SOC) 751.

[0037] The class D amplifier circuit J1 outputs a voltage Vgate, which is a gate voltage corresponding to the first information α, and a voltage Vsw corresponding to the second information β to the temperature calculation unit J2. In the temperature calculation unit J2, a first voltage detector 731 receives the voltage Vgate, and a second voltage detector 732 monitors the voltage Vsw. When the voltage Vsw reaches a desired value, the second voltage detector 732 notifies the first voltage detector 731 of this fact, and at the timing of this notification, the first voltage detector 731 acquires the voltage Vgte and sends a response to the conversion microcomputer 733. This notification may be made, for example, in response to a request from the first voltage detector 731 to the second voltage detector 732, or may be made spontaneously by the second voltage detector 732.

[0038] The conversion microcomputer 733 converts the voltage Vgate input from the first voltage detector 731 into a junction temperature Tj based on pre-stored information, and notifies the determination unit J3 of the junction temperature Tj. In the determination unit J3, the SoC 751 determines whether or not a fault exists based on the junction temperature Tj notified by the conversion microcomputer 733. The SoC 751 may, for example, stop the operation of the class-D amplifier circuit J1 when the junction temperature Tj exceeds a predetermined value, or may temporarily stop the operation of the class-D amplifier circuit J1 when the junction temperature Tj exceeds a predetermined value and stop the operation of the class-D amplifier circuit J1 when this is repeated a predetermined number of times, or may perform other control. The predetermined value may be, for example, 140°C. The predetermined number of times may be two or three times. The SoC 751 may manage the entire circuit of the liquid ejection device 1, for example.

[0039] FIG. 3 is a diagram showing the circuit configuration of a drive circuit according to the embodiment. FIG. 4 is a diagram showing waveforms of a voltage signal and a modulation signal according to the embodiment in relation to the waveform of an analog base drive signal. FIG. 5 is a diagram for explaining the operation of the selection control circuit 210 and the first selection circuit 230-1 to the N-th selection circuit 230-N according to the embodiment.

[0040] Here, the circuit configuration of the drive circuit 50 shown in FIG. 3 is a specific example of the circuit portion of the class D amplifier circuit J1 shown in FIG. The high-side amplifier 713 and the low-side amplifier 714 shown in Fig. 2 correspond to the first transistor M1 and the second transistor M2 shown in Fig. 3. The first transistor M1 and the second transistor M2 form a half-bridge circuit. 3. The LC filter 715 shown in FIG. 2 corresponds to the smoothing circuit 560 shown in FIG. The capacitor 711 and the first IC 712 shown in FIG. 2 are a schematic representation of the control system of the high-side amplifier 713 and the low-side amplifier 714, and the example in FIG. 3 shows an example of a specific circuit configuration.

[0041] First, the operations of the selection control circuit 210 and the first selection circuit 230-1 to the Nth selection circuit 230-N will be described with reference to Fig. 5. In this example, an outline of the operations will be shown. For details of the operations, for example, the same operations as those in Patent Document 1 may be used (for example, see Figs. 3 to 9 of Patent Document 1). The selection control circuit 210 includes a shift register, a latch circuit, and a decoder corresponding to each of the first selection circuit 230-1 to the N-th selection circuit 230-N, but these are not shown in the figure in this example.

[0042] FIG. 5 is a diagram for explaining the operations of the selection control circuit 210 and the first selection circuit 230-1 to the N-th selection circuit 230-N. The print data signal SI is input serially in synchronization with the clock signal SCK and transferred sequentially through shift registers (not shown) corresponding to the first to Nth discharge units 600-1 to 600-N. When the input of the clock signal SCK stops, each shift register holds 2-bit print data [SIH, SIL] corresponding to each of the first to Nth discharge units 600-1 to 600-N. The print data signal SI is input in the order corresponding to the mth, . . . , second, and first stages of the shift register, respectively, of the first to Nth discharge units 600-1 to 600-N.

[0043] When the latch signal LAT rises, each of the latch circuits (not shown) simultaneously latches the 2-bit print data [SIH, SIL] held in the shift register. Note that in Figure 5, LT1, LT2, ..., LTm indicate the 2-bit print data [SIH, SIL] latched by the latch circuits corresponding to the 1st, 2nd, ..., mth stages of the shift register.

[0044] A decoder (not shown) outputs the logic levels of the first selection signal S1 and the second selection signal S2 with predetermined contents during each of the first period T1 and the second period T2, depending on the dot size specified by the latched 2-bit print data [SIH, SIL].

[0045] Specifically, when the print data [SIH,SIL] is [1,1], the decoder sets the first selection signal S1 to H, H level during the first period T1 and the second period T2, and sets the second selection signal S2 to L, L level during the first period T1 and the second period T2. In this case, the first selection circuit 230-1 to the Nth selection circuit 230-N select the trapezoidal waveform Adp1 during the first period T1, and select the trapezoidal waveform Adp2 during the second period T2. As a result, a drive signal VOUT corresponding to a "large dot" is generated.

[0046] Furthermore, when the print data [SIH, SIL] is [1, 0], the decoder sets the first selection signal S1 to H and L levels during the first period T1 and the second period T2, and sets the second selection signal S2 to L and H levels during the first period T1 and the second period T2. In this case, the first selection circuit 230-1 to the Nth selection circuit 230-N select the trapezoidal waveform Adp1 during the first period T1, and select the trapezoidal waveform Bdp2 during the second period T2. As a result, a drive signal VOUT corresponding to a "medium dot" is generated.

[0047] Furthermore, when the print data [SIH, SIL] is [0, 1], the decoder sets the first selection signal S1 to H, L levels during the first period T1 and the second period T2, and sets the second selection signal S2 to L, L levels during the first period T1 and the second period T2. In this case, the first selection circuit 230-1 to the Nth selection circuit 230-N select the trapezoidal waveform Adp1 during the first period T1, and select neither the trapezoidal waveform Adp2 nor the trapezoidal waveform Bdp2 during the second period T2. As a result, a drive signal VOUT corresponding to a "small dot" is generated.

[0048] Furthermore, when the print data [SIH,SIL] is [0,0], the decoder sets the first selection signal S1 to L,L level during the first period T1 and the second period T2, and sets the second selection signal S2 to H,L level during the first period T1 and the second period T2. In this case, the first selection circuit 230-1 to the Nth selection circuit 230-N select the trapezoidal waveform Bdp1 during the first period T1, and select neither the trapezoidal waveform Adp2 nor the trapezoidal waveform Bdp2 during the second period T2. As a result, a drive signal VOUT corresponding to "non-printing" is generated.

[0049] As described above, the selection control circuit 210 and the first selection circuit 230-1 to the Nth selection circuit 230-N select the waveforms of the first drive signal COMA and the second drive signal COMB based on the print data signal SI, the latch signal LAT, the change signal CH, and the clock signal SCK, and output them as the drive signal VOUT to the first ejection section 600-1 to the Nth ejection section 600-N. The start and end voltages of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 are all Vc. That is, the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 each start and end at Vc. The cycle Ta consisting of the first period T1 and the second period T2 corresponds to the printing cycle for forming dots on the medium P. The waveforms of the first drive signal COMA and the second drive signal COMB shown in FIG. 5 are each an example for the purpose of explanation.

[0050] The circuit configuration of the drive circuit will be described with reference to FIG. In this embodiment, the first drive circuit 50-a and the second drive circuit 50-b have the same configuration, except that the signals they input and output are different. Therefore, for the sake of convenience, these will be collectively described as the first driving circuit 50-a in the example of Fig. 3. The same applies to the second driving circuit 50-b.

[0051] The first drive circuit 50-a first converts the first drive signal dA to analog, secondly feeds back the output first drive signal COMA and corrects the deviation between the attenuation signal based on the first drive signal COMA and the target signal using the high-frequency components of the first drive signal COMA, and generates a modulated signal according to the corrected signal, thirdly generates an amplified modulated signal by switching the first transistor M1 and the second transistor M2 according to the modulated signal, fourthly demodulates the amplified modulated signal by smoothing it with a low-pass filter, and outputs the demodulated signal as the first drive signal COMA.

[0052] 3, the first drive circuit 50-a has a modulation circuit J11 that modulates the first drive signal dA input from the control circuit 100 and outputs a modulated signal Ms, an amplifier circuit J12 that amplifies the modulated signal Ms and outputs an amplified modulated signal, and a smoothing circuit 560 that demodulates the amplified modulated signal and outputs a first drive signal COMA that drives the first piezoelectric element 60-1 to the Nth piezoelectric element 60-N. Here, the smoothing circuit 560 is an example of the demodulation circuit J13.

[0053] Specifically, the first drive circuit 50-a has an integrated circuit 500 including a modulation circuit J11, an amplifier circuit J12, a smoothing circuit 560, a first feedback circuit 570, a second feedback circuit 572, and a plurality of other circuit elements.

[0054] The integrated circuit 500 is electrically connected to the outside of the integrated circuit 500 via a plurality of terminals including a first terminal In, a second terminal Bst, a third terminal Hdr, a fourth terminal Sw, a fifth terminal Gvd, a sixth terminal Ldr, a seventh terminal Gnd, and an eighth terminal Vbs. The integrated circuit 500 modulates a first drive signal dA input from the first terminal In, and outputs an amplification control signal that drives each of the first transistor M1 and the second transistor M2 of the amplifier circuit J12.

[0055] As shown in FIG. 3, the integrated circuit 500 includes a digital-to-analog converter (DAC) 511, a modulation circuit J11, a gate drive circuit 520, a reference voltage generation circuit 530, and a power supply circuit 580.

[0056] The power supply circuit 580 generates a first voltage signal DAC_HV and a second voltage signal DAC_LV and supplies them to the DAC 511 .

[0057] The DAC511 converts the digital first base drive signal dA, which defines the waveform of the first drive signal COMA, into a first analog base drive signal aA, which is an analog signal with a voltage value between the first voltage signal DAC_HV and the second voltage signal DAC_LV, and outputs it to the modulation circuit J11. The maximum value of the voltage amplitude of the first analog base drive signal aA is defined by the first voltage signal DAC_HV, and the minimum value is defined by the second voltage signal DAC_LV. That is, the first voltage signal DAC_HV is the high-voltage reference voltage of the DAC511, and the second voltage signal DAC_LV is the low-voltage reference voltage of the DAC511. The first drive signal COMA is obtained by amplifying the first analog base drive signal aA. That is, the first analog base drive signal aA corresponds to a target signal for the first drive signal COMA before amplification. In this embodiment, the voltage amplitude of the first analog base drive signal aA is, for example, 1V to 2V.

[0058] The modulation circuit J11 generates a modulated signal Ms by modulating the first analog base drive signal aA and outputs the modulated signal Ms to the amplifier unit 550 via the gate drive circuit 520. The modulation circuit J11 includes a first adder 512, a second adder 513, a comparator 514, an inverter 515, an integral attenuator 516, and an attenuator 517.

[0059] The integral attenuator 516 attenuates and integrates the voltage at the output terminal Out input via the ninth terminal Vfb, i.e., the first drive signal COMA, and supplies the result to the negative input terminal of the first adder 512. The first analog base drive signal aA is also input to the positive input terminal of the first adder 512. The first adder 512 then subtracts the voltage input to the negative input terminal from the voltage input to the positive input terminal, and supplies the integrated voltage to the positive input terminal of the second adder 513.

[0060] Here, the maximum value of the voltage amplitude of the first analog base drive signal aA is, for example, about 2 V, whereas the maximum value of the voltage of the first drive signal COMA may exceed 40 V. For this reason, the integral attenuator 516 attenuates the voltage of the first drive signal COMA input via the ninth terminal Vfb in order to match the amplitude ranges of both voltages when calculating the deviation.

[0061] The attenuator 517 attenuates the high-frequency components of the first drive signal COMA input via the tenth terminal Ifb and supplies the resulting voltage to the negative input terminal of the second adder 513. The voltage output from the first adder 512 is input to the positive input terminal of the second adder 513. The second adder 513 then outputs to the comparator 514 a voltage signal As obtained by subtracting the voltage input to the negative input terminal from the voltage input to the positive input terminal.

[0062] The voltage signal As output from the second adder 513 is a voltage obtained by subtracting the voltage of the signal supplied to the ninth terminal Vfb from the voltage of the first analog base drive signal aA, and further subtracting the voltage of the signal supplied to the tenth terminal Ifb. Therefore, the voltage of the voltage signal As output from the second adder 513 is a signal obtained by correcting the deviation obtained by subtracting the attenuation voltage of the first drive signal COMA from the target voltage of the first analog base drive signal aA, using the high-frequency component of the first drive signal COMA.

[0063] The comparator 514 outputs a pulse-modulated modulation signal Ms based on the voltage signal As output from the second adder 513. Specifically, the comparator 514 outputs a modulation signal Ms that goes high when the voltage signal As output from the second adder 513 exceeds a predetermined first threshold Vth1 if the voltage signal As is rising, and goes low when the voltage signal As is falling below a predetermined second threshold Vth2 if the voltage signal As is falling. Here, the first threshold Vth1 and the second threshold Vth2 are set such that the first threshold Vth1 is greater than the second threshold Vth2. The frequency and duty ratio of the modulation signal Ms change in accordance with the first base drive signal dA and the first analog base drive signal aA. Therefore, the attenuator 517 adjusts the modulation gain, which corresponds to sensitivity, to adjust the amount of change in the frequency or duty ratio of the modulation signal Ms.

[0064] The modulated signal Ms output from the comparator 514 is supplied to a first gate driver 521 included in a gate drive circuit 520. The modulated signal Ms is also supplied to a second gate driver 522 included in the gate drive circuit 520 after its logical level is inverted by an inverter 515. In other words, the logical levels of the signals supplied to the first gate driver 521 and the second gate driver 522 are mutually exclusive.

[0065] Here, the timing may be controlled so that the logical levels of the signals supplied to the first gate driver 521 and the second gate driver 522 do not become H level at the same time. In other words, strictly speaking, the term "exclusive" here means that the logical levels of the signals supplied to the first gate driver 521 and the second gate driver 522 do not become H level at the same time, and more specifically, this means that the first transistor M1 and the second transistor M2 included in the amplifier circuit J12 are not turned on at the same time.

[0066] Incidentally, the modulated signal is, in the strict sense, the modulated signal Ms, but if one considers it to be pulse-modulated in accordance with the analog first analog unit drive signal aA based on the digital first unit drive signal dA, then the modulated signal also includes a signal with the logical level of the modulated signal Ms inverted. In other words, the modulated signal output from the modulation circuit J11 includes not only the modulated signal Ms input to the first gate driver 521, but also a signal with the logical level of the modulated signal Ms input to the second gate driver 522 inverted, or a signal with timing controlled relative to the modulated signal Ms.

[0067] The gate drive circuit 520 includes a first gate driver 521 and a second gate driver 522 .

[0068] The first gate driver 521 level-shifts the modulation signal Ms output from the comparator 514 and outputs it as a first amplification control signal from the third terminal Hdr. The high-level side of the power supply voltage of the first gate driver 521 is a voltage applied via the second terminal Bst, and the low-level side is a voltage applied via the fourth terminal Sw. The second terminal Bst is connected to one end of the fifth capacitor C5 and the cathode of the first diode D1 for preventing backflow. The fourth terminal Sw is connected to the other end of the fifth capacitor C5. The anode of the first diode D1 is connected to the fifth terminal Gvd. As a result, a voltage Vm, for example, a DC voltage of 7.5 V, supplied from a power supply circuit (not shown) is supplied to the anode of the first diode D1. Therefore, the potential difference between the second terminal Bst and the fourth terminal Sw is approximately equal to the potential difference across the fifth capacitor C5, i.e., the voltage Vm. The first gate driver 521 outputs from the third terminal Hdr a first amplification control signal that is higher in voltage than the fourth terminal Sw by a voltage Vm in accordance with the input modulation signal Ms.

[0069] The second gate driver 522 operates at a lower potential than the first gate driver 521. The second gate driver 522 level-shifts a signal obtained by inverting the logical level of the modulation signal Ms output from the comparator 514 by an inverter 515, and outputs the level-shifted signal as a second amplification control signal from the sixth terminal Ldr. A voltage Vm is applied to the high side of the power supply voltage of the second gate driver 522, and a ground potential GND of, for example, 0 V is supplied to the low side via the seventh terminal Gnd. Then, the second gate driver 522 outputs a second amplification control signal from the sixth terminal Ldr, which is higher by the voltage Vm than the seventh terminal Gnd in accordance with the signal input to the second gate driver 522.

[0070] The reference voltage generating circuit 530 outputs a reference voltage signal VBS, for example, a DC voltage of 6 V, which is supplied to a terminal different from the terminal to which the drive signal VOUT of the first piezoelectric element 60-1 through the Nth piezoelectric element 60-N is supplied. The reference voltage generating circuit 530 is formed, for example, by a constant voltage circuit including a bandgap reference circuit. The reference voltage signal VBS is a signal of a potential that serves as a reference for driving the first piezoelectric element 60-1 through the Nth piezoelectric element 60-N, and may be, for example, a signal of ground potential GND.

[0071] The amplifier unit 550 includes a first transistor M1 accommodated in a first accommodation portion 551 and a second transistor M2 accommodated in a second accommodation portion 552.

[0072] The drain of the first transistor M1 is electrically connected to the first drain terminal Hd of the first accommodation portion 551. A voltage VHV, which is, for example, a DC voltage of 42 V, is supplied to the drain of the first transistor M1 via the first drain terminal Hd. The gate of the first transistor M1 is electrically connected to the first gate terminal Hg of the first accommodation portion 551. The first gate terminal Hg of the first accommodation portion 551 is electrically connected to one end of the first resistor R1, and the other end of the first resistor R1 is electrically connected to the third terminal Hdr of the integrated circuit 500. That is, the first amplification control signal output from the third terminal Hdr of the integrated circuit 500 is supplied to the gate of the first transistor M1. The source of the first transistor M1 is electrically connected to the first source terminal Hs of the first accommodation portion 551. The first source terminal Hs of the first accommodation portion 551 is electrically connected to the fourth terminal Sw of the integrated circuit 500.

[0073] The drain of the second transistor M2 is electrically connected to the second drain terminal Ld of the second accommodation portion 552. The second drain terminal Ld of the second accommodation portion 552 is electrically connected to the fourth terminal Sw of the integrated circuit 500. That is, the drain of the second transistor M2 and the source of the first transistor M1 are electrically connected to each other. The gate of the second transistor M2 is electrically connected to the second gate terminal Lg of the second accommodation portion 552. The second gate terminal Lg of the second accommodation portion 552 is electrically connected to one end of the second resistor R2, and the other end of the second resistor R2 is electrically connected to the sixth terminal Ldr of the integrated circuit 500. That is, the second amplification control signal output from the sixth terminal Ldr of the integrated circuit 500 is supplied to the gate of the second transistor M2. The source of the second transistor M2 is electrically connected to the second source terminal Ls of the second accommodation portion 552. The ground potential GND is supplied to the source of the second transistor M2 via the second source terminal Ls of the second accommodating portion 552.

[0074] In the amplifier unit 550 configured as described above, when the first transistor M1 is controlled to be off and the second transistor M2 is controlled to be on, the voltage of the node to which the fourth terminal Sw is connected becomes the ground potential GND. Therefore, the voltage Vm is supplied to the second terminal Bst. On the other hand, when the first transistor M1 is controlled to be on and the second transistor M2 is controlled to be off, the voltage of the node to which the fourth terminal Sw is connected becomes the voltage VHV. Therefore, a voltage signal with a potential of voltage VHV+Vm is supplied to the second terminal Bst.

[0075] That is, the first gate driver 521 that drives the first transistor M1 uses the fifth capacitor C5 as a floating power supply, and changes the potential of the fourth terminal Sw to 0V or voltage VHV depending on the operation of the first transistor M1 and the second transistor M2, so that the first gate driver 521 supplies a first amplification control signal whose L level is the potential of voltage VHV and whose H level is the potential of voltage VHV+voltage Vm to the gate of the first transistor M1.

[0076] On the other hand, the second gate driver 522 that drives the second transistor M2 supplies a second amplification control signal whose L level is the ground potential GND and whose H level is the potential of the voltage Vm to the gate of the second transistor M2, regardless of the operation of the first transistor M1 and the second transistor M2.

[0077] As described above, the amplifier unit 550 includes a first transistor M1 electrically connected to a first drain terminal Hd to which a voltage VHV is input as a power supply voltage, and a second transistor M2 electrically connected to a second source terminal Ls to which a ground potential GND is input as a reference voltage. The first transistor M1 and the second transistor M2 amplify a modulated signal Ms obtained by modulating the first analog base drive signal aA from the first base drive signal dA, thereby generating an amplified modulated signal at a junction where the source of the first transistor M1 and the drain of the second transistor M2 are commonly connected. The generated amplified modulated signal is input to the smoothing circuit 560. Here, the first drain terminal Hd is an example of a first input terminal of the amplifier unit 550, and the second source terminal Ls is an example of a second input terminal of the amplifier unit 550. Furthermore, the first transistor M1 is an example of a first transistor, and the second transistor M2 is an example of a second transistor. The first accommodating section 551 that accommodates the first transistor M1 is an example of a first accommodating section, and the second accommodating section 552 that accommodates the second transistor M2 is an example of a second accommodating section.

[0078] The smoothing circuit 560 generates a first drive signal COMA by smoothing the amplified modulated signal output from the amplifier 550, and outputs the first drive signal COMA from the first drive circuit 50-a. The smoothing circuit 560 includes a first coil L1 and a first capacitor C1.

[0079] The amplified modulated signal output from the amplifier unit 550 is input to one end of the first coil L1. The other end of the first coil L1 is connected to the output terminal Out, which is the output of the first drive circuit 50-a. That is, the first drive circuit 50-a is connected to each of the first selection circuits 230-1 to the N-th selection circuits 230-N via the output terminal Out. As a result, the first drive signal COMA output from the first drive circuit 50-a is supplied to the first selection circuits 230-1 to the N-th selection circuits 230-N. The other end of the first coil L1 is also connected to one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the ground potential GND. That is, the first coil L1 and the first capacitor C1 smooth and demodulate the amplified modulated signal output from the amplifier unit 550, and output it as the first drive signal COMA.

[0080] The first feedback circuit 570 includes a third resistor R3 and a fourth resistor R4. One end of the third resistor R3 is connected to the output terminal Out, from which the first drive signal COMA is output, and the other end is connected to the ninth terminal Vfb and one end of the fourth resistor R4. The voltage VHV is supplied to the other end of the fourth resistor R4. As a result, the first drive signal COMA that has passed through the first feedback circuit 570 from the output terminal Out is fed back to the ninth terminal Vfb in a pulled-up state.

[0081] The second feedback circuit 572 includes a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth resistor R5, and a sixth resistor R6.

[0082] One end of the second capacitor C2 is connected to the output terminal Out, from which the first drive signal COMA is output, and the other end is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6. A ground potential GND is supplied to the other end of the fifth resistor R5. As a result, the second capacitor C2 and the fifth resistor R5 function as a high-pass filter (HPF). The cutoff frequency of the high-pass filter is set to, for example, approximately 9 MHz. The other end of the sixth resistor R6 is connected to one end of the fourth capacitor C4 and one end of the third capacitor C3. The ground potential GND is supplied to the other end of the third capacitor C3. As a result, the sixth resistor R6 and the third capacitor C3 function as a low-pass filter (LPF). The cutoff frequency of the LPF is set to, for example, approximately 160 MHz. In this way, the second feedback circuit 572 is configured to include a high-pass filter and a low-pass filter, so that the second feedback circuit 572 functions as a band-pass filter (BPF) that passes a predetermined frequency range of the first drive signal COMA.

[0083] The other end of the fourth capacitor C4 is connected to the tenth terminal Ifb of the integrated circuit 500. As a result, a signal from which the DC component has been cut out of the high-frequency components of the first drive signal COMA that has passed through the second feedback circuit 572, which functions as a band-pass filter, is fed back to the tenth terminal Ifb.

[0084] The first drive signal COMA output from the output terminal Out is a signal obtained by smoothing the amplified modulated signal through the smoothing circuit 560. The first drive signal COMA is then integrated and subtracted via the ninth terminal Vfb, and fed back to the first adder 512. Therefore, the first drive circuit 50-a self-oscillates at a frequency determined by the feedback delay and the feedback transfer function.

[0085] However, because the feedback path via the ninth terminal Vfb has a large delay, it may not be possible to raise the self-oscillation frequency enough to ensure the accuracy of the first drive signal COMA using only feedback via the ninth terminal Vfb. Therefore, by providing a path for feeding back the high-frequency components of the first drive signal COMA via the tenth terminal Ifb, in addition to the path via the ninth terminal Vfb, the delay in the entire circuit is reduced. This allows the frequency of the voltage signal As to be raised enough to ensure the accuracy of the first drive signal COMA, compared to when the path via the tenth terminal Ifb is not present.

[0086] FIG. 4 shows the waveforms of the voltage signal As and the modulation signal Ms in relation to the waveform of the analog first analog base drive signal aA. In FIG. 4, the horizontal axis common to all signals represents time t, and the vertical axis of each signal represents the value of that signal. The details of FIG. 4 are the same as those described in the background art section above.

[0087] FIG. 6 is a diagram showing the circuit configuration of the temperature calculation unit J2 according to the embodiment. Here, the circuit configuration shown in FIG. 6 is a specific example of the circuit portion of the temperature calculation unit J2 shown in FIG. 2 are realized by the ADC 841 and the circuits preceding it. Here, the ADC 841 and the circuits preceding it are, for example, an example of a signal acquisition circuit. 2. The functional portion of the conversion microcomputer 733 shown in FIG.

[0088] In the example of FIG. 6, the temperature calculation unit J2 includes a voltage detection circuit J21, a frequency detection circuit J22, an acquisition circuit J23, a delay circuit J24, a conversion circuit J25, a first AND circuit 831 which is an AND circuit, and a second AND circuit 832 which is an AND circuit. The voltage detection circuit J21 includes a first operational amplifier 811 and a second operational amplifier 812. The frequency detection circuit J22 includes a pulse generator 821, a shift register 822, and an XOR circuit, XOR 813. The acquisition circuit J23 includes an analog-to-digital converter, ADC841. The delay circuit J24 includes a first flip-flop 851, a second flip-flop 852, and a third flip-flop 853. In this embodiment, the delay circuit J24 includes three flip-flops connected in series, but any number of flip-flops may be connected in series depending on the required delay time. The conversion circuit J25 includes a calculator 861.

[0089] An example of the operation of the voltage detection circuit J21 will be shown. In the first operational amplifier 811 , the voltage Vef_h is input to the + input terminal, the voltage Vsw is input to the − input terminal, and an output voltage corresponding to these is input to one input terminal of the first AND 831 . In the second operational amplifier 812 , the voltage Vsw is input to the + input terminal, the voltage Vef_l is input to the − input terminal, and an output voltage corresponding to these is input to the other input terminal of the first AND 831 .

[0090] Here, the first operational amplifier 811 determines that the voltage Vref_h is greater than the voltage Vsw. Moreover, the second operational amplifier 812 determines that the voltage Vsw>Vref_l. If both of these are met, that is, if voltage Vref_h>voltage Vsw>Vref_l, the first AND 831 outputs 1, and otherwise outputs 0. The output voltage from the first AND 831 is input to one input terminal of the second AND 832.

[0091] The voltage detection circuit J21 determines whether the voltage Vsw is at an intermediate potential, which is the potential at which the junction temperature Tj is at its maximum. Here, in this embodiment, the case where the junction temperature Tj of the high-side first transistor M1 is used is shown, but as another example, the junction temperature Tj of the low-side second transistor M2 may be used.

[0092] An example of the operation of the frequency detection circuit J22 will be shown below. The pulse generator 821 generates a pulse signal with a predetermined period and inputs the pulse signal to the CLK terminal, which is the clock terminal of the shift register 822 . The voltage Vsw is input to the input terminal of the n-bit shift register 822 .

[0093] The output voltage from the n-bit shift register 822 is input to the input terminal of the n-bit XOR 823 . The output voltage from the XOR 823 is input to the other input terminal of the second AND 832. The frequency detection circuit J22 determines whether the potential of the voltage Vsw has changed.

[0094] Here, the clock is, for example, the maximum value of the frequency of the voltage Vsw, and is operated only when the frequency of the voltage Vsw changes. In this manner, in this embodiment, the timing for acquiring the voltage Vgate is detected based on the frequency of the waveform of the first drive signal COMA. Specifically, the maximum current flows when the voltage is not constant around 50% duty.

[0095] Now, with reference to FIG. 5, an example of the operation of the XOR 823 will be shown. 5, the frequency of the gate driver is highest, and all outputs from the shift register 822 are 1. As a result, the output from the XOR 823 is 0. 5, the frequency of the gate driver is at an intermediate value, and the outputs from the shift register 822 are 0 and 1. This causes the output from the XOR 823 to be 1. 5, the frequency of the gate driver is lowest, and all outputs from the shift register 822 are 0. As a result, the output from the XOR 823 is 0.

[0096] An example of the operation of the ADC841 is shown below. In the ADC 841, the voltage Vgate is input to the input terminal, and the output voltage from the second AND 832 is input to the enable terminal. The output voltage from the ADC 841 is input to one input terminal of a calculator 861 .

[0097] Here, when the frequency changes, that is, when the voltage Vcom changes, the ADC 841 acquires the voltage Vgate when the voltage Vsw reaches the threshold value. The condition for acquiring such voltage Vgate and obtaining temperature information is, for example, when voltage Vsw is at an intermediate potential and the potential of voltage Vsw is changing.

[0098] The delay circuit J24 has a plurality of flip-flops, receives the voltage Vsw as an input, and outputs it after giving it a predetermined delay. The delayed voltage Vsw output from the delay circuit J24 is input to the other input terminal of the calculator 861.

[0099] The calculator 861 uses the acquired voltages Vgate and Vsw to perform conversion using the relational expression Tj=f(Vgate, Vsw). As a result, the computer 861 outputs the junction temperature Tj.

[0100] Here, the calculator 861 derives the junction temperature Tj from the voltage Vgate and the voltage Vsw. At this time, the calculator 861 uniquely determines the junction temperature Tj using predetermined table information. Note that the voltage Vgate is related to the voltage Vgs. Furthermore, the voltage Vsw is proportional to the drain current Id.

[0101] FIG. 6 schematically shows a first route Rt1 through which information about the voltage Vgate flows, a second route Rt2 through which information about the voltage Vsw flows, and a third route Rt3 through which information about the junction temperature Tj obtained by these routes is output.

[0102] FIG. 7 is a diagram showing an example of the relationship between the drain current, the gate-source voltage, and the junction temperature according to the embodiment. In this embodiment, the computer 861 stores information such as that shown in FIG. 7 as table information. In the example of FIG. 7, the relationship between the voltage Vgs(th) [V] and the junction temperature Tj [° C.] is defined for each drain current Id. In the example of FIG. 7, a first characteristic 1211 when the drain current Id is 130 [μA] and a second characteristic 1221 when the drain current Id is 13 [μA] are shown.

[0103] Note that any method may be used to create table information such as that shown in FIG. 7 in advance. Furthermore, the table information may be called by any name, such as relationship information, correspondence information, or characteristic information.

[0104] As described above, in the liquid ejection device 1 according to this embodiment, for example, even in a situation where the thermal resistance or thermal dispersion cannot be accurately determined, the junction temperature can be accurately determined. Furthermore, in the liquid ejection device 1 according to this embodiment, for example, the junction temperature can also be grasped in real time. Furthermore, in the liquid ejection device 1 according to this embodiment, for example, it is possible to grasp the junction temperature at the timing when the heat generating portion reaches the maximum temperature within the ejection cycle.

[0105] For example, in conventional technology, a method of calculating the temperature from the surface temperature was used to determine the temperature of transistors in a class-D amplifier that uses self-oscillating pulse density modulation. However, this conventional technology had issues with the accuracy of temperature detection. Therefore, the liquid ejection device 1 according to this embodiment is configured to be able to calculate the temperature more accurately by finding the junction temperature from the gate-source voltage and drain current at appropriate timing.

[0106] In this embodiment, we focus on the fact that, in a situation where the relationship information between the gate-source voltage Vgs and the junction temperature Tj at a desired drain current Id is known, if the gate-source voltage Vgs at the timing when the drain current Id flowing through the piezo reaches its maximum value can be obtained, the maximum junction temperature Tj_max can be known. In a class-D amplifier using self-oscillating pulse density modulation, the drain current Id reaches its maximum value when the voltage changes near a 50% duty. Therefore, the voltages Vsw and Vgate of the class D amplifier circuit are observed. Here, the voltage Vsw is proportional to the drain current Id, and the voltage Vgate corresponds to the result of adding the voltage Vsw to the gate-source voltage Vgs. At this time, in order to detect the timing at which the voltage changes near 50% duty, the voltage detection circuit J21 and the frequency detection circuit J22 are used, and the voltage Vgate is input to the conversion microcomputer 733 only when the voltage Vsw satisfies a predetermined condition.

[0107] The conversion microcomputer 733 derives the maximum junction temperature Tj_max by comparing the maximum value Id_max of the drain current Id and the gate-source voltage Vgs with previously determined relationship information. The relationship information may be, for example, a graph or a data sheet. Thereafter, the conversion microcomputer 733 outputs information on the maximum junction temperature Tj_max to the SoC 751 . Then, the SoC 751 determines whether or not there is a failure based on the input information on the maximum junction temperature Tj_max.

[0108] As one configuration example, the liquid ejection device 1 includes a first ejection section 600-1 to an Nth ejection section 600-N including a first piezoelectric element 60-1 to an Nth piezoelectric element 60-N whose volume changes in response to a drive signal VOUT to eject liquid, a drive signal generation section including a class D amplifier circuit J1 that generates the drive signal VOUT, and a temperature calculation section J2 that calculates the temperature of the class D amplifier circuit J1. The class D amplifier circuit J1 has a DAC511 that converts the reference drive signal into an analog reference drive signal, a modulation circuit J11 that pulse density modulates the analog reference drive signal and outputs a modulated signal Ms, an amplifier circuit J12 that amplifies the modulated signal Ms and outputs an amplified modulated signal, a demodulation circuit J13 that demodulates the amplified modulated signal and outputs a drive signal, and a feedback circuit that feeds back the drive signal to the modulation circuit J11. The amplifier circuit J12 includes a gate driver that outputs a gate signal based on the modulation signal Ms, and a half-bridge circuit in which a first transistor M1 and a second transistor M2 are connected at a connection point and an amplified modulation signal is output from the connection point in response to the gate signal. The temperature calculation unit J2 includes a signal acquisition circuit that acquires first information, which is the voltage value of the gate signal, and second information, which is the voltage value of the amplified modulation signal, at a first timing when the amplified modulation signal satisfies a predetermined condition, and a temperature calculation circuit that outputs a temperature information signal of the first transistor M1 based on the first information and the second information. Therefore, with the liquid ejection device 1, for example, even in a situation where it is not possible to accurately determine the thermal resistance or thermal dispersion, it is possible to accurately determine the junction temperature. Furthermore, with the liquid ejection device 1, it is also possible to, for example, determine the junction temperature in real time.

[0109] Here, the ink ejected from the nozzles of the first ejection section 600-1 to the N-th ejection section 600-N is an example of the ejected liquid. The first unit drive signal dA and the second unit drive signal dB are examples of unit drive signals. The first analog base drive signal aA is an example of an analog base drive signal, and the same applies to the second analog base drive signal obtained by converting the second base drive signal dB into an analog signal. The first drive signal COMA and the second drive signal COMB are examples of drive signals from the demodulation circuit J13. The feedback circuit including the first feedback circuit 570 and the feedback circuit including the second feedback circuit 572 are examples of feedback circuits. The first gate driver 521 is an example of a gate driver, and the signal output from the first gate driver 521 is an example of a gate signal. Note that instead of the signal from the first gate driver 521, a signal from the second gate driver 522 may be used as the gate signal. The voltage Vgate is an example of the voltage of the gate signal, and the voltage value of the voltage Vgate is an example of the first information. The voltage Vsw is an example of an amplified modulation signal, and the voltage value of the voltage Vsw is an example of the second information. In the temperature calculation unit J2, the circuit portion up to the ADC 841 in the stage preceding the calculator 861 is an example of a signal acquisition circuit, and the calculator 861 is an example of a temperature calculation circuit. The signal output from the computer 861 is an example of a temperature information signal.

[0110] As one example of configuration, the predetermined condition is that the voltage value of the amplified modulation signal is equal to the sum of the reference high potential and the reference low potential divided by 2. Therefore, in the liquid ejection device 1, by using the condition that the voltage of the amplified modulation signal is an intermediate potential between the reference high potential and the reference low potential as the predetermined condition, it is possible to acquire highly accurate temperature information. This condition may have a range of, for example, ±5 percent, that is, the condition that the voltage of the amplified modulation signal is equal to or greater than (midpoint potential - 5 percent of that) and equal to or less than (midpoint potential + 5 percent of that) may be used.

[0111] Here, the potential of the voltage VHV shown in FIG. 3 is an example of a reference high potential, and the ground potential GND shown in FIG. 3 is an example of a reference low potential. Furthermore, the timing when a predetermined condition is satisfied is the first timing.

[0112] In one configuration, the predetermined condition is when the frequency of the amplified modulated signal is not at a maximum or minimum. Therefore, in the liquid ejection device 1, by using the condition that the frequency of the amplified modulation signal is neither maximum nor minimum as the predetermined condition, it is possible to acquire temperature information with high accuracy. The intermediate potential of the drive signal generated from the amplified modulation signal is, for example, half the reference high potential.

[0113] As one configuration example, the signal acquisition circuit has a voltage detection circuit J21 that outputs a first enable signal when the voltage of the amplified modulation signal is within a predetermined range, a frequency detection circuit J22 that outputs a second enable signal when the frequency of the amplified modulation signal is within a predetermined range, and a limiting circuit that outputs first information when the first enable signal and the second enable signal are input. Therefore, in the liquid ejection device 1, such a circuit can acquire the first information when a predetermined condition is satisfied.

[0114] Here, the signal output from the voltage detection circuit J21 is an example of a first enable signal, and the signal output from the frequency detection circuit J22 is an example of a second enable signal. Moreover, the circuit portion including the ADC 841 in the example of FIG. 6 is an example of a limiting circuit.

[0115] As one configuration example, the voltage detection circuit J21 includes a first operational amplifier 811 that outputs a first reference value corresponding to the difference between the voltage of the amplified modulation signal and a first reference voltage, and a second operational amplifier 812 that outputs a second reference value corresponding to the difference between the voltage of the amplified modulation signal and a second reference voltage that is lower than the first reference voltage. The predetermined range for the voltage of the amplified modulated signal is a range higher than the second reference voltage and lower than the first reference voltage. Therefore, in the liquid ejection device 1, a circuit for satisfying predetermined conditions can be realized.

[0116] In the example of FIG. 6, the voltage Vref_h input to the positive input terminal of the first operational amplifier 811 is an example of a first reference voltage, and the value of the output signal from the first operational amplifier 811 is an example of a first reference value. In the example of FIG. 6, the voltage Vref_l input to the negative input terminal of the second operational amplifier 812 is an example of a second reference voltage, and the value of the output signal from the second operational amplifier 812 is an example of a second reference value.

[0117] As an example configuration, the frequency detection circuit J22 includes a shift register 822 that inputs the voltage of the amplified modulated signal and sequentially shifts it bit by bit, and an XOR 823 that inputs two values ​​shifted at different times by the shift register 822 and outputs a value corresponding to these values. Therefore, in the liquid ejection device 1, a circuit for satisfying predetermined conditions can be realized.

[0118] As one configuration example, the limiting circuit includes an AND section that inputs a first permission signal and a second permission signal and outputs a value corresponding to these values, and an ADC841 that inputs the voltage of the gate signal and the value output from the AND section, and outputs first information when the value output from the AND section is a predetermined value. Therefore, in the liquid ejection device 1, a circuit for satisfying predetermined conditions can be realized. In the example of FIG. 6, the first AND 831 and the second AND 832 are examples of an AND section.

[0119] As one configuration example, the liquid ejection device 1 includes a control unit that determines the state of the first transistor M1 based on the temperature information signal and stops the transistor. Therefore, in the liquid ejection device 1, by using the temperature information signal to stop the transistor, it is possible to prevent the transistor from being destroyed by high temperatures, for example. In the example of FIG. 2, the SoC 751 of the determination unit J3 is an example of a control unit. Also, the transistors that are turned off are, for example, the first transistor M1 and the second transistor M2.

[0120] In one configuration, the first transistor M1 is high-side. Therefore, a high-side transistor can be used as the transistor that acquires the temperature information signal, and a fault or other determination can be made based on the temperature information signal.

[0121] In another configuration, the first transistor is low-side. Therefore, a low-side transistor can be used as the transistor that acquires the temperature information signal, and a fault or other determination can be made based on the temperature information signal. In this configuration example, the temperature information of the low-side second transistor M2 is used instead of the temperature information of the high-side first transistor M1 in the embodiment.

[0122] In the embodiment, the liquid ejection device 1 including the temperature calculation unit J2 has been described as an example, but the temperature calculation unit J2 may also be applied to other devices, for example. As an example of the configuration, the temperature calculation device is a temperature calculation device that calculates the temperature of a class D amplifier circuit, and has the following configuration. The class D amplifier circuit has a DAC that converts the master drive signal into an analog master drive signal, a modulation circuit that pulse density modulates the analog master drive signal and outputs a modulated signal, an amplifier circuit that amplifies the modulated signal and outputs an amplified modulated signal, a demodulation circuit that demodulates the amplified modulated signal and outputs a drive signal, and a feedback circuit that feeds back the drive signal to the modulation circuit. The amplifier circuit includes a gate driver that outputs a gate signal based on the modulation signal, and a half-bridge circuit in which a first transistor and a second transistor are connected at a connection point and an amplified modulation signal is output from the connection point in response to the gate signal. The temperature calculation device includes a signal acquisition circuit that acquires first information, which is the voltage value of the gate signal, and second information, which is the voltage value of the amplified modulation signal, at a first timing when the amplified modulation signal satisfies a predetermined condition, and a temperature calculation circuit that outputs a temperature information signal of the first transistor based on the first information and the second information. Therefore, the temperature calculation device can accurately determine the junction temperature even in a situation where the thermal resistance or thermal dispersion cannot be accurately determined. The temperature calculation device can also determine the junction temperature in real time.

[0123] A program for implementing the functions of any of the components of any of the above-described devices may be recorded on a computer-readable recording medium and loaded into a computer system for execution. Here, "computer system" includes hardware such as an operating system or peripheral devices. "Computer-readable recording medium" refers to portable media such as flexible disks, optical magnetic disks, ROMs (Read Only Memory), and CDs (Compact Discs)-ROMs, as well as storage devices such as hard disks built into computer systems. "Computer-readable recording medium" also includes devices that retain a program for a certain period of time, such as volatile memory within a computer system that acts as a server or client when a program is transmitted over a network such as the Internet or a communication line such as a telephone line. Such volatile memory may be RAM. The recording medium may also be non-transitory.

[0124] The above program may be transmitted from a computer system that stores the program in a storage device or the like to another computer system via a transmission medium or by transmission waves in the transmission medium. The "transmission medium" that transmits the program refers to a medium that has the function of transmitting information, such as a network such as the Internet or a communication line such as a telephone line. The above program may be for realizing some of the above functions. The above program may be a so-called differential file that can realize the above functions in combination with a program already recorded in a computer system. The differential file may also be called a differential program.

[0125] The functions of any of the components in any of the above-described devices may be implemented by a processor. Each process in the embodiments may be implemented by a processor operating based on information such as a program and a computer-readable recording medium storing information such as the program. The functions of each unit of the processor may be implemented by separate hardware, or may be implemented by integrated hardware. The processor includes hardware, and the hardware may include at least one of a circuit for processing digital signals and a circuit for processing analog signals. The processor may be configured using one or more circuit devices mounted on a circuit board, or one or both of one or more circuit elements. An integrated circuit (IC) or the like may be used as the circuit device, and a resistor or a capacitor may be used as the circuit element.

[0126] The processor may be a CPU. However, the processor is not limited to a CPU, and various types of processors such as a GPU (Graphics Processing Unit) or a DSP (Digital Signal Processor) may be used. The processor may be a hardware circuit using an ASIC (Application Specific Integrated Circuit). The processor may be configured with multiple CPUs, or may be configured with a hardware circuit using multiple ASICs. The processor may be configured with a combination of multiple CPUs and a hardware circuit using multiple ASICs. The processor may include one or more of an amplifier circuit or a filter circuit that processes analog signals.

[0127] Although the embodiments have been described above in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and includes designs within the scope of the gist of this disclosure.

[0128] [Note] Below, the dependent configuration examples may or may not apply. (Configuration example 1) a discharge unit including a piezoelectric element whose volume changes in response to a drive signal to discharge liquid; a drive signal generating unit including a class D amplifier circuit that generates the drive signal; a temperature calculation unit that calculates the temperature of the class-D amplifier circuit; A liquid ejection device comprising: The class D amplifier circuit comprises: a DAC for converting the base drive signal into an analog base drive signal; a modulation circuit that pulse-density modulates the analog base drive signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs an amplified modulated signal; a demodulation circuit that demodulates the amplified modulated signal and outputs the drive signal; a feedback circuit that feeds back the drive signal to the modulation circuit; and The amplifier circuit a gate driver that outputs a gate signal based on the modulated signal; a half-bridge circuit in which a first transistor and a second transistor are connected at a connection point, and which outputs the amplified modulated signal from the connection point in response to the gate signal; Including, The temperature calculation unit a signal acquisition circuit that acquires first information, which is a voltage value of the gate signal, and second information, which is a voltage value of the amplified modulation signal, at a first timing when the amplified modulation signal satisfies a predetermined condition; a temperature calculation circuit that outputs a temperature information signal of the first transistor based on the first information and the second information; Including, Liquid discharge device.

[0129] (Configuration example 2) The predetermined condition is: The voltage value of the amplified modulation signal is the sum of the reference high potential and the reference low potential divided by 2. The liquid ejection device according to (Configuration Example 1).

[0130] (Configuration example 3) The predetermined condition is: When the frequency of the amplified modulated signal is not at a maximum or minimum, The liquid ejection device according to (Configuration Example 2).

[0131] (Configuration Example 4) The signal acquisition circuit a voltage detection circuit that outputs a first enable signal when the voltage of the amplified modulation signal is within a predetermined range; a frequency detection circuit that outputs a second enable signal when the frequency of the amplified modulated signal is within a predetermined range; a limiting circuit that outputs the first information when the first enabling signal and the second enabling signal are input; having The liquid ejection device according to any one of (Configuration Example 1) to (Configuration Example 3).

[0132] (Configuration Example 5) The voltage detection circuit a first operational amplifier that outputs a first reference value corresponding to a difference between a voltage of the amplified modulation signal and a first reference voltage; a second operational amplifier that outputs a second reference value corresponding to a difference between a voltage of the amplified modulation signal and a second reference voltage that is lower than the first reference voltage; Including, the predetermined range is higher than the second reference voltage and lower than the first reference voltage; The liquid ejection device according to (Configuration Example 4).

[0133] (Configuration Example 6) The frequency detection circuit a shift register that receives the voltage of the amplified modulation signal and sequentially shifts it bit by bit; an XOR that receives two values ​​shifted by the shift register at different times and outputs a value corresponding to these values; Including, The liquid ejection device according to (Configuration Example 4) or (Configuration Example 5).

[0134] (Configuration Example 7) The limiting circuit an AND unit that receives the first permission signal and the second permission signal and outputs a value according to these values; an ADC that receives the voltage of the gate signal and the value output from the AND circuit, and outputs the first information when the value output from the AND circuit is a predetermined value; Including, The liquid ejection device according to any one of (Configuration Example 4) to (Configuration Example 6).

[0135] (Configuration Example 8) a control unit that determines a state of the first transistor based on the temperature information signal and stops the transistor; The liquid ejection device according to any one of (Configuration Example 1) to (Configuration Example 7).

[0136] (Configuration Example 9) The first transistor is a high-side transistor. The liquid ejection device according to any one of (Configuration Example 1) to (Configuration Example 8).

[0137] (Configuration Example 10) The first transistor is a low-side transistor. The liquid ejection device according to any one of (Configuration Example 1) to (Configuration Example 8).

[0138] A temperature calculation device may also be provided. (Configuration Example 11) A temperature calculation device for calculating the temperature of a class D amplifier circuit, The class D amplifier circuit comprises: a DAC for converting the base drive signal into an analog base drive signal; a modulation circuit that pulse-density modulates the analog base drive signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs an amplified modulated signal; a demodulation circuit that demodulates the amplified modulated signal and outputs a drive signal; a feedback circuit that feeds back the drive signal to the modulation circuit; and The amplifier circuit a gate driver that outputs a gate signal based on the modulated signal; a half-bridge circuit in which a first transistor and a second transistor are connected at a connection point, and which outputs the amplified modulated signal from the connection point in response to the gate signal; Including, The temperature calculation device a signal acquisition circuit that acquires first information, which is a voltage value of the gate signal, and second information, which is a voltage value of the amplified modulation signal, at a first timing when the amplified modulation signal satisfies a predetermined condition; a temperature calculation circuit that outputs a temperature information signal of the first transistor based on the first information and the second information; Including, Temperature calculation device. [Explanation of symbols]

[0139] 1...liquid ejection device, 2...head unit, 3...movement mechanism, 4...transport mechanism, 10...control unit, 20...head, 22...ink cartridge, 24...carriage, 31...carriage motor, 32...carriage guide shaft, 33...timing belt, 35...carriage motor driver, 40...platen, 41...transport motor, 42...transport roller, 45...transport motor driver, 70...capping member, 71...wiper member, 72...flushing box, 80...maintenance unit, 81...cleaning mechanism, 82...wiping mechanism, 50-a ...first drive circuit, 50-b...second drive circuit, 60-1...first piezoelectric element, 60-2...second piezoelectric element, 60-3...third piezoelectric element, 60-N...Nth piezoelectric element, 90...linear encoder, 100...control circuit, 190...flexible flat cable, 210...selection control circuit, 230-1...first selection circuit, 230-2...second selection circuit, 230-3...third selection circuit, 230-N...Nth selection circuit, 500...integrated circuit, 511...DAC, 512...first adder, 513...second adder, 514...comparator, 515...inverter, 516...integral attenuator, 517...attenuator 520...gate drive circuit, 521...first gate driver, 522...second gate driver, 530...reference voltage generation circuit, 550...amplifying section, 551...first accommodation section, 552...second accommodation section, 560...smoothing circuit, 570...first feedback circuit, 572...second feedback circuit, 580...power supply circuit, 600-1...first output section, 600-2...second output section, 600-3...third output section, 600-N...Nth output section, 711...capacitor, 712...first IC, 713...high-side amplifier, 714...low-side amplifier, 715...LC filter, 731...first voltage detector, 732 ...Second voltage detector, 733...conversion microcontroller, 751...SoC, 811...first operational amplifier, 812...second operational amplifier, 821...pulse generator, 822...shift register, 823...XOR, 831...first AND, 832...second AND, 841...ADC, 851...first flip-flop, 852...second flip-flop, 853...third flip-flop, 861...computer, 1011...first section, 1012...second section, 1013...third section, 1021...section a1, 1022...section a2, 1031...section b1, 1032...section b2, 1211...first characteristic,1221...second characteristic, As...voltage signal, aA...first analog group drive signal, C1...first capacitor, C2...second capacitor, C3...third capacitor, C4...fourth capacitor, C5...fifth capacitor, CH...change signal, COMA...first drive signal, COMB...second drive signal, CTR1...first control signal, CTR2...second control signal, DAC_HV...first voltage signal, DAC_LV...second voltage signal, dA...first group drive signal, dB...second group drive signal, In...first terminal, Bst...second terminal, Hdr...third terminal, Sw...fourth terminal, Gvd...fifth terminal, Ldr...sixth terminal, Gnd...seventh terminal, Vbs...eighth terminal, Vfb...ninth terminal, Ifb...tenth terminal, Out... Output terminal, J1...D-class amplifier circuit, J2...temperature calculation unit, J3...judgment unit, J4...piezoelectric element, J11...modulation circuit, J12...amplification circuit, J13...demodulation circuit, J21...voltage detection circuit, J22...frequency detection circuit, J23...acquisition circuit, J24...delay circuit, J25...conversion circuit, L1...first coil, LAT...latch signal, M1...first transistor, M2...second transistor, Ms...modulation signal, P...medium, Qa1...main scanning direction, Qa2...sub-scanning direction, R1...first resistor, R2...second resistor, R3...third resistor, R4...fourth resistor, R5...fifth resistor, R6...sixth resistor, Rt1...first route, Rt2...second route, Rt3...third route, SCK...clock signal, SI...print data signal,

Claims

1. a discharge unit including a piezoelectric element whose volume changes in response to a drive signal to discharge liquid; a drive signal generating unit including a class D amplifier circuit that generates the drive signal; a temperature calculation unit that calculates a temperature of the class D amplifier circuit; A liquid ejection device comprising: The class D amplifier circuit comprises: a DAC for converting the base drive signal into an analog base drive signal; a modulation circuit that pulse-density modulates the analog base drive signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs an amplified modulated signal; a demodulation circuit that demodulates the amplified modulated signal and outputs the drive signal; a feedback circuit that feeds back the drive signal to the modulation circuit; and The amplifier circuit a gate driver that outputs a gate signal based on the modulated signal; a half-bridge circuit in which a first transistor and a second transistor are connected at a connection point, and which outputs the amplified modulated signal from the connection point in response to the gate signal; Including, The temperature calculation unit a signal acquisition circuit that acquires first information, which is a voltage value of the gate signal, and second information, which is a voltage value of the amplified modulation signal, at a first timing when the amplified modulation signal satisfies a predetermined condition; a temperature calculation circuit that outputs a temperature information signal of the first transistor based on the first information and the second information; Including, Liquid discharge device.

2. The predetermined condition is: The voltage value of the amplified modulation signal is equal to the sum of the reference high potential and the reference low potential divided by 2. The liquid ejection device according to claim 1 .

3. The predetermined condition is: When the frequency of the amplified modulated signal is not at a maximum or minimum, The liquid ejection device according to claim 2 .

4. The signal acquisition circuit a voltage detection circuit that outputs a first enable signal when the voltage of the amplified modulation signal is within a predetermined range; a frequency detection circuit that outputs a second enable signal when the frequency of the amplified modulated signal is within a predetermined range; a limiting circuit that outputs the first information when the first enabling signal and the second enabling signal are input; having The liquid ejection device according to any one of claims 1 to 3.

5. The voltage detection circuit a first operational amplifier that outputs a first reference value corresponding to a difference between a voltage of the amplified modulation signal and a first reference voltage; a second operational amplifier that outputs a second reference value corresponding to a difference between a voltage of the amplified modulation signal and a second reference voltage that is lower than the first reference voltage; Including, the predetermined range is higher than the second reference voltage and lower than the first reference voltage; The liquid ejection device according to claim 4 .

6. The frequency detection circuit a shift register which receives the voltage of the amplified modulation signal and sequentially shifts it bit by bit; an XOR that receives two values ​​shifted by the shift register at different timings and outputs a value corresponding to these values; Including, The liquid ejection device according to claim 4 .

7. The limiting circuit an AND unit that receives the first permission signal and the second permission signal and outputs a value corresponding to these values; an ADC that receives the voltage of the gate signal and the value output from the AND unit, and outputs the first information when the value output from the AND unit is a predetermined value; Including, The liquid ejection device according to claim 4 .

8. a control unit that determines a state of the first transistor based on the temperature information signal and stops the transistor; The liquid ejection device according to claim 1 .

9. The first transistor is a high-side transistor. The liquid ejection device according to claim 1 .

10. The first transistor is a low-side transistor. The liquid ejection device according to claim 1 .

11. A temperature calculation device for calculating a temperature of a class D amplifier circuit, The class D amplifier circuit comprises: a DAC for converting the base drive signal into an analog base drive signal; a modulation circuit that pulse-density modulates the analog base drive signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs an amplified modulated signal; a demodulation circuit that demodulates the amplified modulated signal and outputs a drive signal; a feedback circuit that feeds back the drive signal to the modulation circuit; and The amplifier circuit a gate driver that outputs a gate signal based on the modulated signal; a half-bridge circuit in which a first transistor and a second transistor are connected at a connection point, and which outputs the amplified modulated signal from the connection point in response to the gate signal; Including, The temperature calculation device a signal acquisition circuit that acquires first information, which is a voltage value of the gate signal, and second information, which is a voltage value of the amplified modulation signal, at a first timing when the amplified modulation signal satisfies a predetermined condition; a temperature calculation circuit that outputs a temperature information signal of the first transistor based on the first information and the second information; Including, Temperature calculation device.

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