High-level synthesis device, information processing system, and high-level synthesis method

Abstract

To provide a technique that, when accessing a storage area designated by discontinuous addresses of an external memory, can prevent a reduction of access speed.SOLUTION: A high-level synthesis device 10 comprises a processor 100 and a storage 200. The processor 100 includes: an access pattern acquisition unit 130 that acquires an access pattern 230; a map creation unit 140 that creates an address map 240 by using the acquired access pattern 230; a code reconfiguration unit 170 that replaces the address of each data in a high-level synthesis code 270 stored in advance in the storage 200 with the address of the address map 240 to reconfigure the high-level synthesis code 270; and a high-level synthesis unit 180 that reads the reconfigured high-level synthesis code 270a and converts it into a hardware description language to update and generate a hardware description code 280.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a high-level synthesis apparatus, an information processing system, and a high-level synthesis method. [Background technology]

[0002] Conventionally, a technique related to a high-level synthesis device that generates hardware description code that describes the configuration of an integrated circuit connected to an external memory is known (Patent Document 1). In this technique, the high-level synthesis device determines that burst transfer, in which multiple data are continuously read from the external memory, is possible if the access pattern when reading data from the external memory is at least one of increment and decrement. If it determines that burst transfer is possible, the high-level synthesis device outputs high-level synthesis code that has been reconstructed by adding burst transfer code to the high-level synthesis code that describes the processing to be executed by the integrated circuit. Then, by inputting the reconstructed high-level synthesis code, the high-level synthesis device generates hardware description code written in a hardware description language. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-2185 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional technology, burst transfer is performed when data stored in consecutive addresses is read, so when data stored in non-consecutive addresses is accessed, it is determined that the data is not subject to burst transfer, which may result in a decrease in the speed of access to the desired data stored in the external memory. [Means for solving the problem]

[0005] The present disclosure can be realized in the following forms.

[0006] According to a first aspect of the present disclosure, there is provided a high-level synthesis device (10, 10a) for updating and generating a hardware description code (280) that describes in a hardware description language the configuration of an integrated circuit (60) connected to an external memory (70). The external memory (70) includes banks (B0 to B1) in which a plurality of memory cells (CE) that constitute a storage area are arranged in a matrix along rows and columns. Z ), and the high-level synthesis device (10, 10a) comprises a processing device (100, 100a) and a storage device (200, 200a) that stores in advance a high-level synthesis code (270) that describes a process to be executed by the integrated circuit (60), and the processing device (100, 100a) includes an access pattern acquisition unit (130) that acquires an access pattern (230) that indicates an access order for each piece of data when writing and / or reading a plurality of pieces of data to each of the storage areas designated by an address of the external memory (70) by referring to the high-level synthesis code (270) that is stored in advance in the storage device (200, 200a), and performs, using the acquired access pattern (230), (i) a first map process that allocates consecutive addresses in the order of consecutively accessed data, and (ii) a second data that is accessed consecutively after the first data to one of the banks (B0 to B Z a map generation unit (140) that generates an address map (240) by executing at least one of the following processes: a first map process that places the address of each data in the high-level synthesis code (270) in the address map (240); a code reconfiguration unit (170) that reconfigures the high-level synthesis code (270) by replacing the address of each data in the high-level synthesis code (270) pre-stored in the storage device (200, 200a) with the address of the address map (240); and a high-level synthesis unit (180) that reads the reconfigured high-level synthesis code (270a) and converts it into the hardware description language, thereby updating and generating the hardware description code (280).

[0007] According to this embodiment of the high-level synthesis device, the high-level synthesis device can generate an address map by executing a first map process that assigns consecutive addresses in the order of consecutively accessed data. This reduces the possibility that a memory area specified by discontinuous addresses in the external memory will be determined to be outside the scope of burst transfer when accessed. Furthermore, according to this embodiment of the high-level synthesis device, the high-level synthesis device can generate an address map by executing a second map process that allocates second data, which is accessed consecutively after first data, in a different bank from the first data. This makes it possible to parallelize at least a portion of the processing for the first data and the second data. This prevents a decrease in the speed of accessing the external memory, even when accessing memory areas specified by discontinuous addresses in the external memory.

[0008] According to a second aspect of the present disclosure, there is provided an information processing system (1, 1a) including a high-level synthesis device (10, 10a) that updates and generates a hardware description code (280) that describes in a hardware description language the configuration of an integrated circuit (60) connected to an external memory (70), the external memory (70) including banks (B0 to B1) in which a plurality of memory cells (CE) that constitute a storage area are arranged in a matrix along rows and columns. Z ), and the information processing system (1, 1a) includes the high-level synthesis device (10, 10a) according to the above aspect, (i) a first map process for allocating consecutive addresses in the order of data consecutively accessed in the external memory (70), and (ii) a second data consecutively accessed after the first data in the bank (B0 to B Za second map process for arranging the addresses of the data in the address map (240) in a location corresponding to the address of the data in the address map (240), and a conversion table (250) generated from the address map (240) by executing at least one of the following processes: a first map process for arranging the addresses of the data in the address map (240) in a location corresponding to the address of the data in the address map (240); an arrangement conversion device (80) for rearranging the data before activating the integrated circuit (60) in accordance with the hardware description code (280a) so that the data are arranged in the same location as in the address map (240); and a circuit activation device (90) for activating the integrated circuit (60) in accordance with the hardware description code (280a) after the data have been rearranged using the conversion table (250), and activation of the integrated circuit (60) executes information processing predetermined by the hardware description code (280a).

[0009] According to this information processing system, before starting the integrated circuit, the conversion table can be referenced and each piece of data can be rearranged so that it is located at the same address as in the address map. Then, after each piece of data has been rearranged using the conversion table, the integrated circuit can be started in accordance with the hardware description code. As a result, the information processing system can access each piece of data while it is located at the same address as in the address map, and can therefore execute predetermined information processing while suppressing a decrease in the speed of access to the external memory.

[0010] According to a third aspect of the present disclosure, there is provided a high-level synthesis method for updating and generating a hardware description code (280) that describes in a hardware description language the configuration of an integrated circuit (60) connected to an external memory (70), the external memory (70) being configured with banks (B0 to B1) in which a plurality of memory cells (CE) that constitute a storage area are arranged in a matrix along rows and columns. Z), and the high-level synthesis method includes an access pattern acquisition step of acquiring an access pattern (230) indicating an access order for each piece of data when writing and / or reading a plurality of pieces of data to each of the storage areas specified by addresses of the external memory (70) by referring to a high-level synthesis code (270) stored in advance in a storage device (200, 200a), the high-level synthesis code (270) describing a process to be executed by the integrated circuit (60); and performing, using the acquired access pattern (230), (i) a first map process of allocating consecutive addresses in the order of consecutively accessed data, and (ii) storing second data, which is accessed consecutively after first data, in the bank (B0 to B1), which is different from the first data. Z a map generation process for generating an address map (240) by executing at least one of the following processes: ...; a code reconfiguration process for reconfiguring the high-level synthesis code (270) by replacing the address of each data in the high-level synthesis code (270) pre-stored in the storage devices (200,

[0011] According to this embodiment of the high-level synthesis method, an address map can be generated by performing a first mapping process that assigns consecutive addresses in the order of consecutively accessed data. This reduces the possibility that a memory area specified by discontinuous addresses in the external memory will be determined to be outside the scope of burst transfer when accessed. Furthermore, according to this embodiment of the high-level synthesis method, the high-level synthesis device can allocate second data, which is accessed consecutively after first data, to a different bank from the first data. This makes it possible to parallelize at least a portion of the processing for the first data and the second data. This prevents a decrease in the speed of accessing the external memory, even when memory areas specified by discontinuous addresses in the external memory are accessed. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of an information processing system according to a first embodiment. [Figure 2] FIG. 2 is a schematic diagram showing the configuration of an external memory according to the first embodiment. [Figure 3] FIG. 2 is a schematic diagram showing the configuration of a bank. [Figure 4] 3 is a flowchart showing a high-level synthesis method according to the first embodiment. [Figure 5] 6 is a flowchart showing details of a map generation process in the first embodiment. [Figure 6] FIG. 10 is a diagram showing an example of data arrangement in a first map process. [Figure 7] FIG. 4 is an image diagram showing an example of processing content in a map generation step according to the first embodiment. [Figure 8] FIG. 1 is a diagram showing an example of an information processing method by an information processing system. [Figure 9] FIG. 10 is a diagram for explaining a difference in access speed. [Figure 10] FIG. 10 is a block diagram showing a schematic configuration of an information processing system according to a second embodiment. [Figure 11] 10 is a flowchart showing a high-level synthesis method according to a second embodiment. [Figure 12] FIG. 10 is an image diagram showing an example of processing content in a map generation step according to the second embodiment. [Figure 13] 10 is a flowchart showing details of a map generation process in the second embodiment. [Figure 14] 10 is a flowchart showing details of a map generation process in the third embodiment. [Figure 15] 13 is a first flowchart showing details of a map generation process in the fourth embodiment. [Figure 16] 20 is a second flowchart showing details of the map generation process in the fourth embodiment. [Figure 17] FIG. 13 is an image diagram showing the processing content in a map generation step of the fourth embodiment. [Figure 18] 13 is a flowchart showing details of a map generation process in the fifth embodiment. [Figure 19] FIG. 13 is an image diagram showing the processing content in a map generation step according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] A. First embodiment: The information processing system 1 shown in FIG. 1 includes hardware 50 including an integrated circuit 60 and an external memory 70, and a high-level synthesis device 10 that updates and generates hardware description code 280 that describes the configuration of the hardware 50.

[0014] The integrated circuit 60 communicates data with the external memory 70 connected via a memory bus 67 or the like in accordance with the hardware description code 280, and executes various information processing. The integrated circuit 60 generates an output image by, for example, executing an integration process to combine a first image and a second image read from the external memory 70 and an inversion process to invert the image after the integration process in accordance with the hardware description code 280, 280a. The integrated circuit 60 may also execute a process to write processed data calculated by executing predetermined arithmetic processing on numerical data read from the external memory 70 in accordance with the hardware description code 280, 280a to the external memory 70. The integrated circuit 60 is, for example, a field programmable gate array (FPGA) whose circuit configuration can be changed by rewriting the hardware description code 280, 280a.

[0015] 2 is a semiconductor memory device having a storage area designated by an address. In this embodiment, the external memory 70 is a DRAM (Dynamic Random Access Memory) capable of burst transfer of data. The external memory 70 is divided into a plurality of banks B0 to B Z It has.

[0016] In FIG. 3, the plurality of banks B0 to B Z The configuration of the first bank B1 is shown as a representative. Z The configuration of each of the banks B0 to B1 is the same as that of the first bank B1 shown in FIG. ZThe external memory 70 has a memory cell array CA in which a plurality of memory cells CE constituting a storage area are arranged in a matrix along rows and columns. Each memory cell CE has a transistor (not shown) and a capacitor (not shown). Each memory cell CE is connected to a word line WL and a bit line BL. As shown in FIGS. 2 and 3, a specific memory cell CE1 to be accessed is designated by specifying a bank address (B1), a row address (R1), and a column address (C1). The banks B0 to B1 constituting the external memory 70 are Z The number of the memory cells CE (FIG. 2) and the number of the memory cells CE (FIG. 3) are not limited to these.

[0017] The high-level synthesis device 10 (FIG. 1) updates and generates hardware description code 280 that describes the configuration of the integrated circuit 60 (hardware 50) connected to an external memory 70, using high-level synthesis code 270 that describes the processing to be executed by the integrated circuit 60 and external memory information 290. The high-level synthesis device 10 is a computer that includes a communication unit (not shown), an input device 300, a display device 400, a storage device 200, a main memory 101, and a processing device (processor) 100.

[0018] A communication unit (not shown) communicatively connects the high-level synthesis apparatus 10 to other components in the information processing system 1. The input device 300 has, for example, a keyboard, a mouse, and a touch panel, and receives instructions from a user. The display device 400 is, for example, a liquid crystal display, and displays information in response to various commands.

[0019] The storage device 200 stores high-level synthesis codes 270, 270a, external memory information 290, hardware description codes 280, 280a, and various data 210-260 acquired or generated in the process of updating and generating the hardware description code 280. The high-level synthesis codes 270, 270a include definitions and algorithms of processes performed in the integrated circuit 60. The high-level synthesis codes 270, 270a are codes written in high-level languages ​​such as C, C++, Python, etc. The external memory information 290 is information about the external memory 70 connected to the integrated circuit 60. Specifically, the external memory information 290 includes, for example, banks B0-B1 of the external memory 70 as shown in FIGS. 2 and 3. Z The hardware description code 280, 280a includes information about the configuration of the external memory 70, such as the number of memory cells CE and the addresses of the memory cells CE that configure the external memory 70, as well as access variable information 291 (see FIG. 4, which will be described later). The hardware description codes 280, 280a shown in FIG. 1 are codes that determine the configuration of the hardware 50. The hardware description codes 280, 280a are codes written in a hardware description language (HDL), such as Verilog or VHDL. The hardware description codes 280, 280a are generated by converting the high-level synthesis code 270 into a hardware description language.

[0020] The main memory 101 stores various programs such as a program (not shown) that controls the operation of the high-level synthesis device 10.

[0021] The processing device 100 expands various programs stored in the main memory 101, thereby functioning as a loop processing extraction unit 110, an access variable determination unit 120, an access pattern acquisition unit 130, and a map generation unit 140. Furthermore, the processing device 100 expands various programs stored in the main memory 101, thereby functioning as a table generation unit 150, a burst transfer determination unit 160, a code reconstruction unit 170, and a high-level synthesis unit 180.

[0022] The loop processing extraction unit 110 extracts loop processing included in high-level synthesis code 270 pre-stored in the storage device 200. The access variable determination unit 120 determines array variables to be set for each loop processing. The access pattern acquisition unit 130 acquires an access pattern 230 when the integrated circuit 60 accesses the external memory 70 in the loop processing. The map generation unit 140 generates an address map 240 using the acquired access pattern 230. The table generation unit 150 generates a conversion table 250 using the generated address map 240. The burst transfer determination unit 160 references the access pattern 230, the access variable determination result 220, and the address map 240 to determine whether access to data in the loop processing is subject to burst transfer. The code reconstruction unit 170 reconstructs the high-level synthesis code 270 pre-stored in the storage device 200 using the address map 240 and a burst transfer determination result 260 indicating whether the data is subject to burst transfer. The high-level synthesis unit 180 converts the reconstructed high-level synthesis code 270a into a hardware description language, thereby updating and generating the hardware description code 280 stored in advance in the storage device 200.

[0023] The information processing system 1 further includes a layout transformation device 80, a circuit activation device 910, and a control device 90 that controls the operations of the layout transformation device 80 and the circuit activation device 910. The layout transformation device 80 refers to the conversion table 250 and rearranges each piece of data before activating the integrated circuit 60 according to the hardware description code 280a updated and generated by the high-level synthesis device 10 so that each piece of data has the same layout as that of the address map 240. After the data has been rearranged using the conversion table 250, the circuit activation device 910 activates the integrated circuit 60 according to the hardware description code 280a updated and generated by the high-level synthesis device 10. This executes information processing predetermined by the hardware description code 280a. The function of the control device 90 may be implemented as one function of the processing device 100 in the high-level synthesis device 10, or may be implemented by a component different from the high-level synthesis device 10 (e.g., a CPU of the information processing system 1).

[0024] 4, the high-level synthesis method is started when an instruction is received from a user or the like via, for example, the input device 300 (FIG. 1). In this embodiment, prior to the start of the high-level synthesis method, the high-level synthesis code 270, the hardware description code 280, and the external memory information 290 are each stored in advance in the storage device 200.

[0025] In the high-level synthesis method, first, a loop processing extraction step (step S100) is executed. In the loop processing extraction step (step S100), the loop processing extraction unit 110 reads high-level synthesis code 270 stored in advance in the storage device 200, and extracts loop processing from the high-level synthesis code 270. Then, the loop processing extraction unit 110 stores the loop processing extraction result 210 (hereinafter, loop extraction result 210) in the storage device 200.

[0026] After the loop processing extraction step (step S100), an access variable determination step (step S200) is executed. In the access variable determination step (step S200), the access variable determination unit 120 first reads external memory information 290 stored in advance in the storage device 200. At this time, the external memory information 290 pre-stores access variable information 291. The "access variable information 291" here refers to information including array variables and the like used when reading data from the external memory 70 or writing data to the external memory 70. The access variable information 291 is set in advance, for example, according to the external memory 70 mounted on the hardware 50 and design information of the integrated circuit 60 that accesses the external memory 70. After reading the external memory information 290, the access variable determination unit 120 determines array variables (hereinafter, loop array variables) to be used in the loop processing of the high-level synthesis code 270. The "loop array variables" here refer to, for example, array variables set for each loop processing extracted by the loop processing extraction unit 110. Then, the access variable determination unit 120 stores the determined loop array variables in the storage device 200 as the access variable determination results 220.

[0027] After the access variable determination step (step S200), an access pattern acquisition step (step S300) is executed. In the access pattern acquisition step (step S300), the access pattern acquisition unit 130 first acquires an access pattern 230 when the integrated circuit 60 accesses the external memory 70 in the loop process extracted by the loop process extraction unit 110. In other words, the access pattern acquisition unit 130 acquires an access pattern 230 for each loop array variable included in the access variable determination result 220. The "access pattern 230" here refers to pattern data indicating the order of access to each piece of data when at least one of writing and reading multiple pieces of data is performed on each storage area specified by an address in the external memory 70. The access pattern acquisition unit 130 acquires the access pattern 230 by, for example, referencing a high-level synthesis code 270 stored in advance in the storage device 200 and analyzing the order of access to each piece of data in the high-level synthesis code 270. Then, the access pattern acquisition unit 130 stores the acquired access pattern 230 in the storage device 200.

[0028] Each piece of data included in each loop array variable may be stored in a variable (hereinafter referred to as a data variable) declared by a variable declaration statement such as var. When each piece of data is stored in a data variable, the access pattern 230 may be pattern data indicating the order of access to each data variable. That is, when each piece of data is stored in a data variable, the access pattern acquisition unit 130 may analyze the access pattern 230 for the external memory 70 for each data variable.

[0029] After the access pattern acquisition step (step S300), a map generation step (step S400) is executed. As shown in FIG. 5, in step S410, the map generation unit 140 first acquires the access pattern 230. Next, in step S420, the map generation unit 140 generates the address map 240 using the acquired access pattern 230. In this embodiment, the map generation unit 140 generates the address map 240 by executing a first map process that assigns consecutive (adjacent) addresses in the order of consecutively accessed data. The term "consecutive addresses" here refers to a case where both row addresses and column addresses are consecutive (the left diagram in FIG. 6) and a case where only row addresses are consecutive (the right diagram in FIG. 6). Which case in FIG. 6 applies is determined, for example, depending on the number of output bits (e.g., 4 bits or 8 bits) of the external memory 70 and the data size. Then, in step S490, the map generation unit 140 stores the generated address map 240 in the storage device 200. When each piece of data is stored in a data variable, the address map 240 may be a map in which consecutive addresses are assigned in the order of the data variables that are accessed consecutively.

[0030] FIG. 7 illustrates an example in which an address map 240 is generated for three data items E to G that are accessed consecutively in the order of data E, data F, and data G. As shown in the left diagram of FIG. 7, the consecutively accessed data items E to G may be allocated storage areas designated by discontinuous addresses. Here, the "storage areas designated by discontinuous addresses" refers to storage areas with at least different row addresses, as shown in the left diagram of FIG. 7, for example. When accessing the multiple data items E to G stored at discontinuous addresses and reading the data items E to G sequentially, the access areas may be determined to be out of burst transfer range, which may reduce the access speed to the desired data items E to G stored in the external memory 70. Similarly, when writing the multiple data items E to G sequentially to storage areas designated by discontinuous addresses, the access areas may be determined to be out of burst transfer range. Furthermore, even when consecutive addresses are allocated to the consecutively accessed data items E to G, the accesses may be deemed to be discontinuous by, for example, referencing a pointer, and may be determined to be out of burst transfer range.

[0031] Therefore, as shown in the right diagram of FIG. 7 , the high-level synthesis device 10 generates an address map 240 by executing a first map process that allocates consecutive addresses in the order of consecutively accessed data E to G. In other words, the address map 240 is a map that indicates an ideal data layout for the integrated circuit 60 to efficiently access the external memory 70. Then, in a later process, the high-level synthesis device 10 updates and generates a hardware description code 280 based on the data layout in the address map 240. Furthermore, before starting up the integrated circuit 60, the layout conversion device 80 actually rearranges each piece of data to the same layout as in the address map 240. In this way, the information processing system 1 prevents a decrease in the access speed to each piece of data E to G by arranging (storing) each piece of data E to G at addresses suitable for burst transfer.

[0032] Note that a method for generating the address map 240 when the acquired access pattern 230 includes multiple access order patterns will be described in the third and subsequent embodiments. As will be described in detail later, when the access pattern 230 includes multiple access order patterns, if it is not possible to generate an address map 240 that satisfies all of the access orders, an address map 240 may be generated that prioritizes an access order that is highly likely to be executed by the integrated circuit 60. Furthermore, when the access pattern 230 includes multiple access order patterns, only the address map 240 corresponding to the access order with the highest execution probability may be generated. In other words, for an access order that is low in the probability of being executed by the integrated circuit 60 among the multiple access order patterns included in the access pattern 230, an address map 240 that satisfies this access order may not be generated.

[0033] As shown in FIG. 4, after the map generation step (step S400), a table generation step (step S500) is executed. In the table generation step (step S500), the table generation unit 150 first acquires the address map 240. Next, the table generation unit 150 generates a conversion table 250 that links the addresses of each piece of data E to G in the address map 240 (for example, FIG. 7) with each piece of data E to G. Then, the table generation unit 150 stores the generated conversion table 250 in the storage device 200. Note that when each piece of data E to G is stored in a data variable, the conversion table 250 may be a table that links the address of each data variable with each data variable.

[0034] After the conversion table generation step (step S500), a burst transfer determination step (step S600) is executed. In the burst transfer determination step (step S600), the burst transfer determination unit 160 first acquires the address map 240. Next, the burst transfer determination unit 160 uses the address map 240 to determine whether or not access to data E to G in the loop processing is subject to burst transfer. In detail, when the address map 240 is referenced, the burst transfer determination unit 160 determines that the data is subject to burst transfer if consecutive addresses are assigned in the order of consecutively accessed data for the access order included in the access pattern 230. On the other hand, when the address map 240 is referenced, the burst transfer determination unit 160 determines that the data is not subject to burst transfer if consecutive addresses are not assigned in the order of consecutively accessed data for the access order included in the access pattern 230. At this time, if the access pattern 230 includes a plurality of patterns of access orders, the burst transfer determination unit 160 may determine that only some of the access orders are subject to burst transfer, according to the arrangement of each data in the address map 240. The burst transfer determination unit 160 stores a determination result 260 (hereinafter, burst transfer determination result 260) as to whether or not a data is subject to burst transfer in the storage device 200.

[0035] If the high-level synthesis code 270 stored in advance in the storage device 200 includes multiple loop processes, each step from the access variable determination step (step S200) to the burst transfer determination step (step S600) is executed for each loop process. When each step up to the burst transfer determination step (step S600) has been executed for all loop processes, the code reconstruction step (step S700) is executed.

[0036] After the burst transfer determination step (step S600), a code reconstructing step (step S700) is executed. In the code reconstructing step (step S700), the code reconstructing unit 170 reconstructs the high-level synthesis code 270 by replacing the addresses of each of the data E to G in the high-level synthesis code 270 pre-stored in the storage device 200 with addresses in the address map 240. Furthermore, the code reconstructing unit 170 acquires the burst transfer determination result 260. Then, when it is determined that the access to the data E to G in the loop processing is subject to burst transfer, the code reconstructing unit 170 reconstructs the high-level synthesis code 270 by adding code for performing burst transfer to the loop processing of the high-level synthesis code 270. The code reconstructing unit 170 stores the reconstructed high-level synthesis code 270a in the storage device 200.

[0037] After the code reconfiguration step (step S700), a high-level synthesis step (step S800) is executed. In the high-level synthesis step (step S800), the high-level synthesis unit 180 reads the reconfigured high-level synthesis code 270a and converts it into a hardware description language, thereby updating and generating the hardware description code 280 pre-stored in the storage device 200. The high-level synthesis unit 180 then stores the updated and generated hardware description code 280a in the storage device 200. The high-level synthesis method ends with the execution of each step up to the high-level synthesis step (step S800). After the high-level synthesis method ends, an information processing method (see FIG. 8, described below) is executed.

[0038] In this embodiment, the functional units 120 to 180 of the processing device 100 execute the processes in the above steps by appropriately referencing the various data 210 to 260 stored in the storage device 200, respectively. However, this is not limited to this. The functional units 110 to 170 of the processing device 100 may directly output the various data 210 to 270a to be used in subsequent steps to the functional units 120 to 180, respectively. In this embodiment, the high-level synthesis code 270 and the external memory information 290 are stored in the storage device 200 in advance, but this is not limited to this. The high-level synthesis code 270 and the external memory information 290 may be acquired by being input from outside via the input device 300 at the start of the high-level synthesis method shown in FIG. 4, for example.

[0039] 8 shows an example of a data layout conversion method using the generated conversion table 250 and an information processing method using the updated and generated hardware description code 280a. In FIG. 8, an example is shown in which a layout conversion device 80 equipped with a DMAC (Direct Memory Access Controller) or the like, instead of the control device 90, rearranges the data E to G on the external memory 70 by referring to the conversion table 250.

[0040] In the information processing method shown in FIG. 8, first, the rearrangement device 80 acquires the conversion table 250 (step S910). Next, when the access pattern 230 is a read of the data E to G, the rearrangement device 80 executes the following process (step S920). Specifically, the rearrangement device 80 refers to the conversion table 250 in accordance with a preset program and rearranges the data E to G stored in the external memory 70 so that the data E to G are arranged at the same addresses as those in the address map 240 (step S920). Then, the rearrangement device 80 transmits a first completion notification indicating that rearrangement of the data E to G on the external memory 70 has been completed to the control device 90 (step S930). In other words, the rearrangement of the data E to G by the rearrangement device 80 is executed before starting up the integrated circuit 60 in accordance with the hardware description code 280a updated and generated by the high-level synthesis device 10.

[0041] When the first completion notification is received, the circuit activation device 910 activates the integrated circuit 60 in accordance with the hardware description code 280a (step S950). As a result, the integrated circuit 60 is activated and performs information processing (for example, the above-mentioned accumulation processing and inversion processing) in accordance with the updated hardware description code 280a (step S960). When all of the predetermined information processing is completed, a second completion notification indicating that the series of information processing has been completed is transmitted to the control device 90 (step S970).

[0042] The function of the rearrangement device 80 may be realized as one function of the control device 90. In other words, the information processing system 1 may have the control device 90 rearrange the data E to G in the external memory 70 without having the rearrangement device 80 such as a DMAC. For example, when the access pattern 230 is a write of the data E to G, the control device 90 may refer to the conversion table 250 and store each of the data E to G at the same address as in the address map 240. Furthermore, the external memory 70 has banks B0 to B1, in which a plurality of memory cells CE are arranged in a matrix along rows and columns. Z However, the present disclosure is not limited to this.

[0043] According to the first embodiment, as shown in FIGS. 4 and 7 , the high-level synthesis device 10 can generate the address map 240 by executing a first mapping process that assigns consecutive addresses to consecutively accessed data E to G in that order. In this way, by assigning consecutive addresses to consecutively accessed data E to G in that order, even when a storage area specified by a discontinuous address is accessed, it can be subject to burst transfer. In other words, when a storage area specified by a discontinuous address is accessed, it is possible to avoid determining that the storage area is not subject to burst transfer. Therefore, by executing the first mapping process to generate the address map 240, the high-level synthesis device 10 can expand the scope of applications of burst transfer, thereby suppressing a decrease in the access speed to the external memory 70.

[0044] Furthermore, according to the first embodiment, the high-level synthesis device 10 can reconstruct the high-level synthesis code 270 by replacing the addresses of the data E to G in the high-level synthesis code 270 pre-stored in the storage device 200 with addresses in the address map 240. The high-level synthesis device 10 can then read the reconstructed high-level synthesis code 270a and convert it into a hardware description language, thereby updating and generating the hardware description code 280 that describes the processing to be executed by the integrated circuit 60. In other words, the high-level synthesis device 10 can generate the hardware description code 280a on the premise that the data E to G are arranged in the external memory 70 so as to have the same data arrangement as the address map 240.

[0045] Furthermore, according to the first embodiment, as shown in FIGS. 7 and 8, the information processing system 1 can refer to the conversion table 250 and rearrange the data E to G so that the data E to G are arranged in the same order as in the address map 240. This allows the information processing system 1 to rearrange the data E to G in the external memory 70 in the order of consecutively accessed data E to G. This allows the data E to G to be arranged in consecutive addresses suitable for burst transfer. After the data E to G are rearranged using the conversion table 250, the information processing system 1 can activate the integrated circuit 60 in accordance with the hardware description code 280a. This allows the information processing system 1 to prevent a decrease in the access speed to the data E to G even when accessing data E to G stored at discontinuous addresses. In other words, the information processing system 1 can perform burst transfer even when the access pattern 230 does not correspond to either increment or decrement, thereby preventing a decrease in the access speed to the external memory 70.

[0046] Furthermore, according to the first embodiment, when each of the data E to G is stored in a data variable, the access pattern 230 can be pattern data indicating the order in which the data variables are accessed. When each of the data E to G is stored in a data variable, the address map 240 can be a map in which consecutive addresses are assigned to the data variables in the order in which they are accessed consecutively, using the acquired access pattern 230. Furthermore, when each of the data E to G is stored in a data variable, the conversion table 250 can be a table in which the address of each data variable is associated with each data variable. In other words, according to the first embodiment, the information processing system 1 can handle each of the data E to G in the external memory 70 in units of data variables.

[0047] Furthermore, according to the first embodiment, as shown in FIG. 4, the high-level synthesis device 10 can generate a conversion table 250 based on the generated address map 240. Then, as shown in FIG. 8, the layout transformation device 80 can rearrange the data E to G stored in the external memory 70 to the same layout as the address map 240 by referring to the generated conversion table 250 in accordance with a preset program. Therefore, a software developer only needs to create a program that specifies rearranging the data E to G by referring to the conversion table 250. In other words, the software developer does not need to create a program from scratch to rearrange the data E to G by analyzing the access pattern 230, etc., in order to optimize the access efficiency to the data E to G stored in the external memory 70. This reduces the amount of work required of the software developer.

[0048] 8, the rearrangement device 80 can directly rearrange the data E to G stored in the external memory 70 without going through the control device 90. This reduces the workload of the control device 90, further preventing a decrease in the speed of access to the external memory 70.

[0049] B. Second embodiment: 9 to 13, a method for generating the address map 240 that can further suppress a decrease in the access speed to the external memory 70 will be described. In the second embodiment, part of the method for generating the address map 240 in the map generation step (step S400) is different from that in the first embodiment (FIGS. 5 and 7). Accordingly, part of the configuration of the high-level synthesis device 10a (FIG. 10) having the processing device 100a and the storage device 200a in the information processing system 1a, and part of the processing in the high-level synthesis method (FIG. 11) are different from those in the first embodiment (FIGS. 1 and 4). Steps that are the same as those in the first embodiment and configurations that are the same as those in the first embodiment are assigned the same reference numerals, and descriptions thereof will be omitted.

[0050] As shown in Figure 9, when the integrated circuit 60 attempts to access a specific storage area in the external memory 70, a memory cell CE located at an address specified by an active command for enabling access to the specific storage area is activated. After the storage area to be accessed is activated, data is read from or written to the active storage area via a buffer (not shown). After the access to the storage area is completed, the active state of the memory cell CE constituting the accessed storage area is released. In other words, when accessing a storage area in the external memory 70 to read or write data, an open process for opening the storage area to be accessed and a close process for closing the accessed storage area are required before and after the data processing for reading or writing data.

[0051] Here, due to the nature of the external memory 70, the same banks B0 to B Z On the other hand, the external memory 70 has multiple banks B0 to B Z , each process is performed in banks B0 to B Z Therefore, the second data, which is accessed consecutively after the first data, can be read from a bank B0 to B1 that is different from the first data. Z 9 is possible. For example, after the first open process, a first data process for reading and writing the first data from and to the first storage area and a second open process are performed in two banks B0 to B1. Z This allows the second data processing to be executed in parallel after the first data is read or written to the first storage area, and the second data to be read or written to the second storage area. Z When the second data is arranged in the same bank B0 to B1 as the first data, Z13, the map generating unit 140 executes both the first map processing and the second map processing to generate the address map 240, thereby further suppressing a decrease in the speed of access to the external memory 70.

[0052] In the high-level synthesis method of this embodiment shown in FIG. 11, the steps from the loop processing extraction step (step S100) to the access pattern acquisition step (step S300), the table generation step (step S500), the burst transfer determination step (step S600), and the high-level synthesis step (step S800) are the same as those in the first embodiment (FIG. 4), and therefore will not be described.

[0053] FIG. 12 illustrates an example in which the address map 240 is generated by performing the first map process and the second map process in this order for two pieces of data E and F that are accessed consecutively in this order.

[0054] 13, in step S410, the map generating unit 140 acquires the access pattern 230. Next, in step S425, the map generating unit 140 uses the acquired access pattern 230 to execute a first mapping process of allocating consecutive addresses to consecutively accessed data E, F in that order (the central diagram in FIG. 12). Next, in step S430, the map generating unit 140 allocates data E as the first data and data F as the second data to be consecutively accessed to different banks B0, B2 to B3. Z 12. In this case, when each data is stored in a data variable, the address map 240 allocates consecutively accessed data variables to different banks B0 to B1. Z Alternatively, the address map 240 may be arranged in the address space 240a.

[0055] In this embodiment, as shown in FIG. 11, a parallelization processing extraction step (step S650) is executed after the burst transfer determination step (step S600). In the parallelization processing extraction step (step S650), the parallelization processing extraction unit 165 (FIG. 10) first acquires the high-level synthesis code 270 and the address map 240 that are pre-stored in the storage device 200a. Next, when the address map 240 is applied to the pre-stored high-level synthesis code 270, that is, when the high-level synthesis code 270 is reconstructed, the parallelization processing extraction unit 165 extracts processes that can be parallelized from among the processes included in the reconstructed high-level synthesis code 270a. In detail, the parallelization processing extraction unit 165 extracts processes that can be parallelized from among the open processing, data processing, and close processing shown in FIG. 9, in which the first data and the second data are different between the banks B0 to B1. Z The parallelization process extraction unit 165 then stores the extracted parallelization processes in the storage device 200a as a parallelization extraction result 265 (FIG. 10).

[0056] 11, a code reconfiguration step (step S700) is executed after the parallelization processing extraction step (step S650). In this embodiment, in the code reconfiguration step (step S700), the code reconfiguration unit 170 reconfigures the high-level synthesis code 270 by adding code for performing parallelization processing to the loop processing in addition to the processing in the first embodiment. That is, the code reconfiguration unit 170 reflects the data arrangement in the address map 240, the burst transfer determination result 260, and the parallelization extraction result 265 in the high-level synthesis code 270 stored in advance in the storage device 200a, thereby updating and generating the high-level synthesis code 270.

[0057] According to the second embodiment, as shown in FIG. 13, the map generating unit 140 stores the second data, which is accessed consecutively after the first data, in the banks B0, B2 to B3, which are different from the first data. Z In this way, the map generating section 140 performs a second map process to allocate the first data and the second data to different banks B0 to B1. Z9, it is possible to parallelize at least a part of the processing for the first data and the second data. Therefore, by shortening the access time to the external memory 70, it is possible to improve the access speed to the external memory 70.

[0058] 12 and 13, the map generation unit 140 can generate the address map 240 by executing both the first map processing and the second map processing. This can expand the scope of applications for burst transfer and can parallelize part of the processing when accessing the external memory 70. This can further improve the speed of accessing the external memory 70.

[0059] C. Third embodiment: A method for generating the address map 240 when the access pattern 230 includes multiple access order patterns will be described using FIG. 14. Specifically, in the third embodiment, when the access pattern 230 includes multiple access order patterns, the access order with the highest probability of being executed by the integrated circuit 60 (hereinafter referred to as execution probability) is extracted, and the address map 240 is generated according to the extracted access order. Therefore, in the third embodiment, part of the method for generating the address map 240 in the map generation step (step S400) is different from that in the above embodiments (FIGS. 5 and 13). Steps other than the map generation step (step S400) are the same as those in the above embodiments (FIGS. 4 and 11). Furthermore, the configuration of the information processing systems 1 and 1a is the same as that in the above embodiments (FIGS. 1 and 10). Steps and configurations that are the same as those in the above embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0060] In step S410, the map generation unit 140 acquires the access pattern 230. Next, in step S440, the map generation unit 140 determines whether the acquired access pattern 230 includes multiple access order patterns. If it is determined that the access pattern 230 does not include multiple access order patterns, that is, if it is determined that only a single access order is included (step S440: No), the map generation unit 140 executes step S445. In step S445, the map generation unit 140 executes at least one of a first mapping process and a second mapping process to generate the address map 240. On the other hand, if it is determined that the access pattern 230 includes multiple access order patterns (step S440: Yes), the map generation unit 140 executes step S441. In step S441, the map generation unit 140 extracts the access order with the highest execution probability from the multiple access order patterns. Next, in step S443, the map generating unit 140 generates the address map 240 by performing at least one of the first mapping process and the second mapping process on the access order extracted in step S441.

[0061] 14, when the access pattern 230 includes multiple access order patterns, the map generation unit 140 can extract the access order with the highest execution probability and generate the address map 240 according to the extracted access order. This makes it easy to determine the access order to be used when generating the address map 240.

[0062] D. Fourth embodiment: 15 to 17, another method for generating the address map 240 when the access pattern 230 includes multiple access order patterns will be described. In the fourth embodiment, when the access pattern 230 includes multiple access order patterns, the address map 240 is generated using a different method depending on whether it is possible to generate an address map 240 that satisfies all of the multiple access order patterns. Therefore, in the fourth embodiment, part of the method for generating the address map 240 in the map generation step (step S400) is different from that of the above embodiments (FIGS. 5, 13, and 14). Steps other than the map generation step (step S400) are the same as those in the second embodiment (FIG. 11). Furthermore, the configuration of the information processing system 1a is the same as that of the second embodiment (FIG. 10). Steps and configurations that are the same as those in the above embodiments are assigned the same reference numerals, and descriptions thereof will be omitted.

[0063] As shown in FIG. 15, in step S410, the map generation unit 140 acquires the access pattern 230. Next, in step S440, the map generation unit 140 determines whether the acquired access pattern 230 includes multiple access order patterns. For example, FIG. 17 illustrates a case where the access pattern 230 includes multiple patterns: a first access order and a second access order that is different from the first access order. In FIG. 17, the first access order is the access order for five pieces of data E to I. Furthermore, the second access order is the access order for two discontinuous pieces of data out of the five pieces of data E to I included in the first access order. As in the example shown in FIG. 17, when it is determined that the acquired access pattern 230 includes multiple access order patterns (step S440: Yes), the map generation unit 140 executes step S450. On the other hand, if it is determined that the acquired access pattern 230 does not include multiple patterns of access orders (step S440: No), the map generating unit 140 executes step S445.

[0064] In step S450, the map generation unit 140 determines whether it is possible to generate an address map 240 that satisfies all access orders included in the access pattern 230. Here, "satisfying all access orders" means that all access orders are compatible. Furthermore, "address map 240 that satisfies all access orders" refers to an address map 240 that can suppress a decrease in access speed by making all access orders subject to at least one of burst transfer and parallel processing. If the acquired access pattern 230 is as shown in FIG. 17, the map generation unit 140 determines that it is possible to generate an address map 240 that satisfies all access orders included in the access pattern 230 (step S450: Yes).

[0065] If it is determined that an address map 240 that satisfies all access orders included in the access pattern 230 can be generated (step S450: Yes), the map generation unit 140 executes at least one of the first map processing and the second map processing for all access orders to generate the address map 240. In this embodiment, the map generation unit 140 executes each of the processes from step S460 to step S475 to execute the first map processing for the first access order and the second map processing for the second access order to generate the address map 240.

[0066] In step S460, the map generating unit 140 executes the first map processing for the first access order to generate a candidate map 241 (the center diagram in FIG. 17). Next, in step S470, when the map generating unit 140 refers to the generated candidate map 241, it determines whether the data to be accessed consecutively in the second access order are in different banks B0 to B1. Z For example, in FIG. 17, in the candidate map 241, data E and data I, which are accessed consecutively in the second access order, are arranged in the same bank B0. Therefore, in this case, the map generating unit 140 determines whether data E and data I are arranged in the same bank B0 to B1 in the second access order. ZIt is determined that there are consecutive accesses within the same bank B0 to B1 in the second access order (step S470: Yes). Z If it is determined that there are consecutive accesses within the second access order (step S470: Yes), the map generating unit 140 executes step S471. In step S471, the map generating unit 140 executes the second map processing for the second access order, and generates the address map 240 (right diagram in FIG. 17) by modifying the candidate map 241 (center diagram in FIG. 17). On the other hand, if there are consecutive accesses within the second access order, the map generating unit 140 executes the second map processing for the second access order. Z If it is determined that there is no consecutive access within the address map 240 (step S470: No), the map generating unit 140 executes step S475. In step S475, the map generating unit 140 adopts the candidate map 241 generated in step S460 as the address map 240.

[0067] In the example shown in FIG. 17, consecutive row addresses R1 to R4 are assigned to each of data E to H that are accessed consecutively in the first access order. As a result, when accessing according to the first access order, consecutive accesses to each of data E to H can be subject to burst transfer. Furthermore, data H and data I that are accessed consecutively in the first access order are arranged in different banks B0 and B1. Therefore, when accessing according to the first access order, consecutive accesses to data H and data I can be subject to parallel processing. Furthermore, data E and data I that are accessed consecutively in the second access order are arranged in different banks B0 and B1. Therefore, when accessing according to the second access order, consecutive accesses to data E and data I can be subject to parallel processing. In other words, in the example shown in FIG. 17, all access orders are subject to at least one of burst transfer and parallel processing. Therefore, in the example shown in FIG. 17, an address map 240 that satisfies all the access orders included in the access pattern 230, that is, that is compatible with all the access orders included in the access pattern 230, can be generated.

[0068] On the other hand, if it is determined that an address map 240 that satisfies all of the access orders included in the access pattern 230 cannot be generated (step S450: No), the map generation unit 140 executes steps S481 and S483 shown in Fig. 16 in this order. As a result, the map generation unit 140 generates an address map 240 that corresponds to an access order with a higher execution probability, instead of an address map 240 that satisfies all of the access orders included in the access pattern 230.

[0069] In step S481, the map generation unit 140 extracts an access order with a higher execution probability from the multiple access order patterns included in the access pattern 230 so as to generate an address map 240 that satisfies all of the extracted access orders. At this time, if the access pattern 230 includes three or more access order patterns, the map generation unit 140 may extract multiple access order patterns with a higher execution probability, as long as it is possible to generate an address map 240 that satisfies all of the extracted access orders. Next, in step S483, the map generation unit 140 generates an address map 240 that satisfies all of the access orders extracted in step S481.

[0070] 15, the map generation unit 140 can generate the address map 240 so that all access orders included in the access pattern 230 are subject to at least one of burst transfer and parallel processing. This makes it possible to further prevent a decrease in the access speed to the external memory 70 when the access pattern 230 includes multiple access order patterns.

[0071] Furthermore, according to the fourth embodiment, as shown in FIG. 17 , the access pattern 230 includes a first access order and a second access order different from the first access order. The first access order is an access order for M pieces of data E to I (M is an integer equal to or greater than 3). The second access order is an access order for N pieces of discontinuous data E and I (N is an integer equal to or greater than 2 and less than M) among the M pieces of data E to I included in the first access order. In this case, the map generation unit 140 can generate the address map 240 so that the data are subject to either burst transfer or parallel processing regardless of whether the access order is the first access order or the second access order. This makes it possible to prevent a decrease in the access speed to the external memory 70 even when the access pattern 230 includes the first access order and the second access order indicating the access order for the N pieces of discontinuous data E and I among the M pieces of data E to I included in the first access order.

[0072] 15 and 16, when the access pattern 230 includes multiple access order patterns, the map generation unit 140 can extract an access order with a higher execution probability. As a result, even when the access pattern 230 is unable to generate an address map 240 that satisfies all of the access orders, the map generation unit 140 can easily determine the access order to use when generating the address map 240. Even when it is unable to generate an address map 240 that satisfies all of the access orders, the map generation unit 140 can easily generate an address map 240 that prioritizes an access order with a higher execution probability, instead of an address map 240 that satisfies all of the access orders.

[0073] E. Fifth embodiment: 18 and 19, another method for generating the address map 240 will be described when the access pattern 230 includes multiple access order patterns and an address map 240 that satisfies all of the access orders can be generated. In the fourth embodiment, as shown in FIGS. 15 and 17, the address map 240 is generated by performing a first map process on the first access order and then a second map process on the second access order. In contrast, in the fifth embodiment, as shown in FIG. 18, when the access pattern 230 includes both the first and second access orders, the address map 240 is generated by performing a second map process on both the first and second access orders. Therefore, in the fifth embodiment, part of the method for generating the address map 240 in the map generation step (step S400) is different from that in the fourth embodiment (FIG. 15). Steps other than the map generation step (step S400) are the same as those in the second embodiment (FIG. 11). Furthermore, the configuration of the information processing system 1a is the same as that in the second embodiment (FIG. 10). The same steps and configurations as those in the above embodiment are given the same reference numerals and descriptions thereof will be omitted.

[0074] In this embodiment, when it is determined that an address map 240 satisfying all of the access orders included in the access pattern 230 can be generated (step S450: Yes), the map generating unit 140 executes step S465. In step S465, the map generating unit 140 generates an address map 240 satisfying all of the access orders included in the access pattern 230, as shown in FIG. Z In this way, the map generating unit 140 performs the second map processing for both the first access order and the second access order so that consecutively accessed data are arranged in different banks B0 to B1 regardless of which access order is used for accessing the data in the access pattern 230. Z The address map 240 is generated.

[0075] 18 and 19, according to the fifth embodiment, the map generation unit 140 can generate the address map 240 so that all access orders included in the access pattern 230 are subject to parallel processing. This makes it possible to more reliably prevent a decrease in the speed of access to the external memory 70 when the access pattern 230 includes multiple access pattern orders.

[0076] F. Other Embodiments: (F1) In the above embodiment, an FPGA is used as an example of the integrated circuit 60, but the present disclosure is not limited to this. The integrated circuit 60 may be, for example, an ASIC (Application Specific Integrated Circuit) or a PLD (Programmable Logic Device).

[0077] (F2) In the above embodiment, a DRAM is used as the external memory 70, but the present disclosure is not limited to this. The external memory 70 may be, for example, a DRAM having a plurality of banks B0 to B Z It may also be other volatile memory (RAM) having

[0078] The present disclosure is not limited to the above-described embodiments and can be realized in various configurations without departing from the spirit thereof. For example, the technical features of each embodiment corresponding to the technical features in each aspect described in the Summary of the Invention section can be appropriately replaced or combined to solve some or all of the above-described problems or achieve some or all of the above-described effects. Furthermore, if a technical feature is not described as essential in this specification, it can be appropriately deleted. [Explanation of symbols]

[0079] 1, 1a...information processing system, 10, 10a...high-level synthesis device, 50...hardware, 60...integrated circuit, 67...memory bus, 70...external memory, 80...layout transformation device, 90...control device, 100, 100a...processing device, 101...main memory, 110...loop processing extraction unit, 120...access variable determination unit, 130...access pattern acquisition unit, 140...map generation unit, 150...table generation unit, 160...burst transfer determination unit, 165...parallelization processing extraction unit, 170...code reconstruction unit, 180...high high-level synthesis unit, 200, 200a...storage device, 210...loop extraction result, 220...access variable determination result, 230...access pattern, 240...address map, 241...candidate map, 250...conversion table, 260...burst transfer determination result, 265...parallelization extraction result, 270, 270a...high-level synthesis code, 280, 280a...hardware description code, 290...external memory information, 291...access variable information, 300...input device, 400...display device, 910...circuit activation device, B0 to B Z …bank, BL…bit line, C1~C Y ...column, CA...memory cell array, CE, CE1...memory cell, R1 to R x ...row, WL...word line

Claims

1. A high-level synthesis device (10, 10a) that updates and generates hardware description code (280) that describes the configuration of an integrated circuit (60) connected to an external memory (70) in a hardware description language, comprising: The external memory (70) has a bank (B) in which a plurality of memory cells (CE) constituting a storage area are arranged in a matrix along rows and columns. ０ ~B Ｚ ) and The high-level synthesis apparatus (10, 10a) a processing device (100, 100a); a storage device (200, 200a) for storing in advance a high-level synthesis code (270) describing a process to be executed by the integrated circuit (60); The processing device (100, 100a) an access pattern acquisition unit (130) that acquires an access pattern (230) indicating an access order for each piece of data when writing and / or reading a plurality of pieces of data to each of the storage areas designated by an address of the external memory (70) by referring to the high-level synthesis code (270) that is pre-stored in the storage device (200, 200a); Using the acquired access pattern (230), (i) a first map process is performed to allocate consecutive addresses in the order of consecutively accessed data, and (ii) a second data that is consecutively accessed after the first data is allocated to the bank (B) different from the first data. ０ ~B Ｚ a map generating unit (140) for generating an address map (240) by executing at least one of the following processes: a code reconfiguration unit (170) that reconfigures the high-level synthesis code (270) by replacing the address of each piece of data in the high-level synthesis code (270) pre-stored in the storage device (200, 200a) with the address in the address map (240); a high-level synthesis unit (180) that reads the reconstructed high-level synthesis code (270a) and converts it into the hardware description language, thereby updating and generating the hardware description code (280).

2. 2. The high-level synthesis apparatus according to claim 1, When the acquired access pattern (230) includes a plurality of patterns of the access order, The map generation unit (140) extracts the access order that is most likely to be executed by the integrated circuit (60), and generates the address map (240) according to the extracted access order.

3. 2. The high-level synthesis apparatus according to claim 1, When the acquired access pattern (230) includes a plurality of patterns of the access order, The map generation unit (140) generates the address map (240) that satisfies all of the access orders.

4. 4. The high-level synthesis apparatus according to claim 3, the plurality of patterns of access orders include a first access order and a second access order different from the first access order; the first access order is an access order for M pieces of data (M is an integer equal to or greater than 3); When the second access order is an access order for N pieces of data (N is an integer equal to or greater than 2 and less than M) that are discontinuous with respect to the first access order, among the M pieces of data included in the first access order, The map generating unit (140) executes at least the second map processing for the second access order.

5. 4. The high-level synthesis apparatus according to claim 3, If it is not possible to generate the address map (240) that satisfies all of the access orders, The map generation unit (140) generates the address map (240) according to the access order that is more likely to be executed by the integrated circuit (60), instead of the address map (240) that satisfies all of the access orders.

6. 6. The high-level synthesis apparatus according to claim 1, The processing device (100, 100a) further includes a table generation unit (150) that generates a conversion table (250) that links the addresses of each piece of data in the address map (240) with each piece of data.

7. An information processing system (1, 1a) including a high-level synthesis device (10, 10a) that updates and generates hardware description code (280) that describes the configuration of an integrated circuit (60) connected to an external memory (70) in a hardware description language, The external memory (70) has a bank (B) in which a plurality of memory cells (CE) constituting a storage area are arranged in a matrix along rows and columns. ０ ~B Ｚ ) and The information processing system (1, 1a) A high-level synthesis apparatus (10, 10a) according to claim 6; (i) a first mapping process for allocating consecutive addresses to the external memory (70) in the order of data that are consecutively accessed; and (ii) storing second data that are consecutively accessed after the first data in the bank (B) different from the first data. ０ ~B Ｚ a second map process for arranging the data in a location corresponding to the address of the data in the address map (240) in a location corresponding to the address of the data in the address map (240), and a second map process for arranging the data in a location corresponding to the address of the data in the address map (240). a circuit activation device (90) that activates the integrated circuit (60) in accordance with the hardware description code (280a) after the data has been rearranged using the conversion table (250); An information processing system in which the integrated circuit (60) is activated to execute information processing predetermined by the hardware description code (280a).

8. A high-level synthesis method for updating and generating hardware description code (280) that describes a configuration of an integrated circuit (60) connected to an external memory (70) in a hardware description language, comprising: The external memory (70) has a bank (B) in which a plurality of memory cells (CE) constituting a storage area are arranged in a matrix along rows and columns. ０ ~B Ｚ ) and The high-level synthesis method includes: an access pattern acquisition step of acquiring an access pattern (230) indicating an access order for each piece of data when writing and / or reading a plurality of pieces of data to each of the storage areas designated by addresses in the external memory (70) by referring to a high-level synthesis code (270) stored in advance in a storage device (200, 200a), the high-level synthesis code (270) describing a process to be executed by the integrated circuit (60); Using the acquired access pattern (230), (i) a first map process is performed to allocate consecutive addresses in the order of consecutively accessed data, and (ii) a second data that is consecutively accessed after the first data is allocated to the bank (B) different from the first data. ０ ~B Ｚ a map generation step of generating an address map (240) by executing at least one of the following processes: a code reconstructing step of reconstructing the high-level synthesis code (270) by replacing the address of each data in the high-level synthesis code (270) stored in advance in the storage device (200, 200a) with the address in the address map (240); a high-level synthesis step of acquiring the reconstructed high-level synthesis code (270a) and converting it into the hardware description language, thereby updating and generating the hardware description code (280).

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