printed wiring board

Abstract

The printed wiring board of the present disclosure has a base film having a wiring region and a non-wiring region, a plurality of wiring portions including an outermost wiring portion and a plurality of inner wiring portions other than the outermost wiring portion, the outermost wiring portion being formed at the outermost portion of the plurality of wiring portions and at the boundary between the wiring region and the non-wiring region, the non-wiring region being a region extending from the outermost surface of the outermost wiring portion to a point 100 μm or more away, an average height H1 of the outermost wiring portion and an average height H2 of the inner wiring portion being 5 μm or more and 35 μm or less, The average spacing L between the wiring portion and the inner wiring portion, and between the inner wiring portions, is 25 μm or less, the difference U1 between the average width W1 and the average bottom width G1 in the outermost wiring portion, and the difference U2 between the average width W2 and the average bottom width G2 in the inner wiring portion are 3 μm or less, the ratio H1 / G1 of the average height H1 to the average bottom width G1 in the outermost wiring portion is 2.00 or less, and the ratio H2 / G2 of the average height H2 to the average bottom width G2 in the inner wiring portion is 2.00 or less.

Description

[Technical Field]

[0001] The present disclosure relates to printed wiring boards. [Background technology]

[0002] As electronic devices become smaller and lighter, efforts are being made to achieve finer pitches in the wiring portions of printed wiring boards. Additive and semi-additive methods are being adopted to achieve high-density, finer pitches in the wiring portions of printed wiring boards. For example, in the semi-additive method, a seed layer is formed on the surface of an insulating resin layer, and the area other than the area where the circuit will be formed is covered with a plating resist. Then, a metal layer is selectively formed only in the circuit area by electroplating. The plating resist is then peeled off, and the seed layer other than the circuit area is etched to form a printed wiring board (see JP 2004-6773 A). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-6773 Summary of the Invention

[0004] The printed wiring board of the present disclosure comprises an insulating base film and a plurality of wiring portions formed on a surface of the base film, the wiring portions having a metal layer laminated directly or indirectly on the surface of the base film, the base film having a wiring region having the plurality of wiring portions and a non-wiring region located outside the wiring region and not having the wiring portions, the plurality of wiring portions including one or a plurality of outermost wiring portions and a plurality of inner wiring portions other than the outermost wiring portions, the outermost wiring portion being formed at the outermost of the plurality of wiring portions and at the boundary between the wiring region and the non-wiring region, and the non-wiring region extending from the outermost surface of the outermost wiring portion the average height H1 of the outermost wiring portion and the average height H2 of the inner wiring portion are 5 μm or more and 35 μm or less; the average spacing L between the outermost wiring portion and the inner wiring portion and between the inner wiring portions is 25 μm or less; the difference U1 between the average width W1 and the average bottom width G1 of the outermost wiring portion and the difference U2 between the average width W2 and the average bottom width G2 of the inner wiring portion are 3 μm or less; the ratio H1 / G1 of the average height H1 to the average bottom width G1 of the outermost wiring portion is 2.00 or less; and the ratio H2 / G2 of the average height H2 to the average bottom width G2 of the inner wiring portion is 2.00 or less. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a schematic partial plan view showing a printed wiring board according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic partial cross-sectional view showing a printed wiring board according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a schematic cross-sectional view showing an outermost wiring portion of a printed wiring board according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a schematic cross-sectional view showing an inner wiring portion of a printed wiring board according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a cross-sectional view showing a state after a seed layer lamination step in the method for manufacturing a printed wiring board according to an embodiment of the present disclosure. [Figure 6]FIG. 6 is a cross-sectional view showing a state after a resist pattern forming step in the method for manufacturing a printed wiring board according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a cross-sectional view showing a state after a metal layer lamination step in the method for manufacturing a printed wiring board according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a schematic partial plan view showing a printed wiring board according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0006] [Problem to be solved by this disclosure] As described above, when forming wiring portions, areas other than those where the wiring portions are to be formed are covered with plating resist, so if the spacing between the wiring portions is wide, a wide resist pattern is used. The inventors have discovered that when a wide resist pattern is used, the wiring portions are more likely to collapse, even when the wiring portions are low in height and stable. This is presumably because a large amount of uncured resist components leach out of the wide resist in processes subsequent to the resist pattern formation process, causing gouges around the interface between the wiring portion and the base film. In response to this, it is thought that treating the resist with a dilute aqueous solution of magnesium salt after development and pseudo-crosslinking the uncured resist components with the magnesium ions in the aqueous solution can reduce the leaching of resist components in subsequent processes.

[0007] However, a certain processing time is required to prevent leaching of resist components in subsequent processes. Furthermore, leaching in subsequent processes is likely to occur under conditions where the moisture content of the resist pattern is high, such as during post-development rinsing, pre-plating degreasing and acid pickling, and humidity in the storage environment. Meanwhile, the roll-to-roll method has recently been adopted, in which hundreds of meters of rolled substrate, such as film, is fed and processed, then rewound into a roll. The roll-to-roll method is a highly efficient production method that performs multiple processes continuously while unwinding a long roll of material. Compared to the batch method, which processes flat substrates individually, this method makes it difficult to maintain a sufficient treatment time with a dilute magnesium salt aqueous solution, shortening the rinsing time, and making it difficult to drain and dry. Furthermore, when printed wiring boards are stored in a rolled state, they are tightly wound, making them susceptible to the effects of leached resist components even during storage.

[0008] If a wiring section of a printed wiring board falls over, it may come into contact with adjacent wiring sections, causing a short circuit. Also, if a portion of the bottom surface of a wiring section lifts off the base film, the wiring section may tear off, resulting in a disconnection. Furthermore, since a wiring section that falls over and falls off becomes a conductive foreign object, it may contaminate other printed wiring boards, causing mounting defects, or malfunctions of other components.

[0009] The present disclosure aims to provide a printed wiring board that can reduce collapse of wiring portions due to leaching of resist components from a resist pattern when there is a large non-wiring area adjacent to the wiring portion.

[0010] [Effects of this disclosure] According to the present disclosure, it is possible to reduce collapse of wiring portions due to leaching of resist components from a resist pattern when there is a large non-wiring area adjacent to the wiring portion.

[0011] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0012] (1) A printed wiring board according to the present disclosure includes an insulating base film and a plurality of wiring portions formed on a surface of the base film, the wiring portions having a metal layer directly or indirectly laminated on the surface of the base film, the base film having a wiring region having the plurality of wiring portions and a non-wiring region located outside the wiring region and not having the wiring portions, the plurality of wiring portions including one or more outermost wiring portions and a plurality of inner wiring portions other than the outermost wiring portions, the outermost wiring portion being formed at the outermost portion of the plurality of wiring portions and at the boundary between the wiring region and the non-wiring region, and the non-wiring region being formed at the outermost portion of the outermost wiring portion. the average height H1 of the outermost wiring portion and the average height H2 of the inner wiring portion are 5 μm or more and 35 μm or less; the average spacing L between the outermost wiring portion and the inner wiring portion, and between the inner wiring portions, is 25 μm or less; the difference U1 between the average width W1 and the average bottom width G1 of the outermost wiring portion and the difference U2 between the average width W2 and the average bottom width G2 of the inner wiring portion are 3 μm or less; the ratio H1 / G1 of the average height H1 to the average bottom width G1 of the outermost wiring portion is 2.00 or less; and the ratio H2 / G2 of the average height H2 to the average bottom width G2 of the inner wiring portion is 2.00 or less.

[0013] The printed wiring board can reduce collapse of the wiring portion due to leaching of resist components from the resist pattern when the non-wiring region adjacent to the wiring portion is wide. While the reason for this is unclear, the following reason is presumed. When the non-wiring region adjacent to the wiring portion is wide, the resist pattern adjacent to the wiring portion becomes wide. This makes the wiring portion more likely to collapse due to leaching of resist components, even when the wiring portion is low and relatively stable. The inventors have found that collapse of the wiring portion is particularly likely when a wide resist pattern is used in which the outermost wiring portion is formed at the boundary between the wiring region and the non-wiring region, and the non-wiring region extends to a point 100 μm or more away from the outermost surface of the outermost wiring portion. Furthermore, they have found that collapse of the wiring portion does not occur even under such conditions if the average height H1 of the outermost wiring portion and the average height H2 of the inner wiring portion are less than 5 μm.

[0014] On the other hand, it has been found that even if the average height H1 of the outermost wiring portion and the average height H2 of the inner wiring portion are 5 μm or more, by appropriately setting the upper limit of the average height, average spacing, average width, average bottom width, etc. of the outermost wiring portion and the inner wiring portion, it is possible to reduce the collapse of the wiring portion due to the leaching of resist components from the resist pattern when the non-wiring area adjacent to the wiring portion is large. That is, the average heights H1 and H2 are 35 μm or less, the average spacing L between the outermost wiring portion and the inner wiring portion and between the inner wiring portions is 25 μm or less, the difference U1 between the average width W1 and the average base width G1 of the outermost wiring portion and the difference U2 between the average width W2 and the average base width G2 of the inner wiring portion are 3 μm or less, the ratio H1 / G1 of the average height H1 to the average base width G1 of the outermost wiring portion is 2.00 or less, and the ratio H2 / G2 of the average height H2 to the average base width G2 of the inner wiring portion is 2.00 or less. This reduces the influence of leaching of resist components from the adjacent wide resist pattern and reduces waviness of the base film, thereby reducing collapse of the wiring portion. Therefore, the printed wiring board can reduce collapse of the wiring portion due to leaching of resist components from the resist pattern when there is a large non-wiring area adjacent to the wiring portion.

[0015] In this disclosure, "the non-wired region is a region extending to a point 100 μm or more away from the outermost surface of the outermost wiring portion" means that the shortest point of the non-wired region is at least 100 μm away from the outermost surface of the outermost wiring portion. The "average width" of the wiring portion refers to the average of the width of the wiring portion in a planar view measured at any five points in the longitudinal direction of the wiring portion. Furthermore, the measurement of the "average width" of the wiring portion excludes areas scooped out by resist components leached from the resist pattern described below. The "average spacing between the outermost wiring portion and the inner wiring portion, and between the inner wiring portions" refers to the average of the average distances between the side of the outermost wiring portion and the side of the adjacent inner wiring portion, and the distances between the side of adjacent inner wiring portions, measured at any five points. The "average height" of the wiring portion refers to the average of the heights measured at any five points. The "average bottom width" of the wiring portion refers to the average value of the width of the surface where the bottom surface of the wiring portion contacts the base film in a cross section perpendicular to the longitudinal direction of the wiring portion, measured at any five points in the longitudinal direction of the wiring portion.

[0016] (2) In (1) above, the wiring portion may have a seed layer laminated between the base film and the metal layer, and the average thickness of the seed layer may be 0.01 μm or more and less than 3 μm. By having the printed wiring board have a seed layer, migration of metal ions from the metal layer can be prevented. Furthermore, by having the average thickness of the seed layer be 0.01 μm or more and less than 3 μm, the formation of discontinuities on the surface of the seed layer can be prevented while increasing the removal efficiency by etching. The "average thickness" refers to the average value of thicknesses measured at any five points.

[0017] (3) In the above (1) or (2), the average width W1 of the outermost wiring portion may be larger than the average width W2 of the inner wiring portion. By making the average width W1 of the outermost wiring portion larger than the average width W2 of the inner wiring portion, collapse due to leaching of resist components from the resist pattern can be reduced even in the outermost wiring portion, which is most susceptible to collapse.

[0018] (4) In any of (1) to (3) above, the base film may have an average thickness of 25 μm or less. When the average thickness of the base film is 25 μm or less, the base film is more likely to waviness, which makes it more susceptible to the effects of resist components leaching out of the resist pattern, which is a problem of the present disclosure, and therefore the effects of the present disclosure can be more effectively achieved.

[0019] [Details of the embodiments of the present disclosure] A printed wiring board according to an embodiment of the present disclosure will be described below with reference to the drawings.

[0020] <Printed wiring board> The printed wiring board includes an insulating base film and a plurality of wiring portions formed on the surface of the base film. The wiring portions include a metal layer laminated directly or indirectly on the surface of the base film. FIG. 1 is a schematic partial plan view showing a printed wiring board 50 according to one embodiment, and FIG. 2 is a schematic partial cross-sectional view of the printed wiring board 50 in region X of FIG. 1. FIG. 3 is a schematic cross-sectional view showing the outermost wiring portion of the printed wiring board 50. FIG. 4 is a schematic cross-sectional view showing the inner wiring portion of the printed wiring board 50. As shown in FIG. 1, the printed wiring board 50 includes a conductive pattern 20 including a plurality of wiring portions having a curved region in a planar view. The base film 1 includes a wiring region S1 having a plurality of wiring portions and a non-wiring region S2 located outside the wiring region S1 and not including the wiring portions. The plurality of wiring portions of the conductive pattern 20 include an outermost wiring portion 11 and a plurality of inner wiring portions 10 other than the outermost wiring portion 11. The outermost wiring portion 11 is formed at the outermost portion of the multiple wiring portions of the conductive pattern 20, and at the boundary between the wiring region S1 and the non-wiring region S2. The wiring region S1 is a region in the base film 1 that includes multiple wiring portions. On the other hand, the non-wiring region S2 is a region in the base film 1 that is further outside the outermost wiring portion 11 located at the outermost portion of the wiring region S1, and that does not have any wiring portions.

[0021] More specifically, the plurality of wiring portions are provided at the boundary between a wiring region S1 in which the plurality of wiring portions are formed and a non-wiring region S2 in which no wiring portions are present, and include an outermost wiring portion 11 that defines the outermost edge of the wiring region S1, and inner wiring portions 10 that are a plurality of wiring portions other than the outermost wiring portion 11. In FIG. 1, the plurality of wiring portions include one outermost wiring portion 11 and a plurality of inner wiring portions 10 other than the outermost wiring portion 11. Also, as shown in FIGS. 2 to 4, in the printed wiring board 50, the outermost wiring portion 11 and the inner wiring portion 10 have a metal layer 3 that is laminated directly or indirectly on the surface of the base film 1. Furthermore, the outermost wiring portion 11 and the inner wiring portion 10 may have a conductive seed layer 2 that is laminated between the base film 1 and the metal layer 3.

[0022] The non-wired region S2 is a region extending from the outermost surface of the outermost wiring portion 11 to a point 100 μm or more away. When the shortest distance from the outermost surface of the outermost wiring portion 11 in the non-wired region S2 is 100 μm or more, the effects of the present disclosure can be achieved. The lower limit of the shortest distance from the outermost surface of the outermost wiring portion 11 in the non-wired region S2 is 100 μm, and may be 120 μm. On the other hand, the upper limit of the shortest distance from the outermost surface of the outermost wiring portion 11 in the non-wired region S2 is not particularly limited, and may be, for example, 1500 μm.

[0023] [Base film] The base film 1 is mainly composed of a synthetic resin and has electrical insulation properties. The base film 1 is a base layer for forming a conductive pattern. The base film 1 may be flexible. When the base film 1 is flexible, the printed wiring board 50 can be used as a flexible printed wiring board.

[0024] Examples of the synthetic resin include polyimide, polyethylene terephthalate, liquid crystal polymer, and fluororesin.

[0025] When the printed wiring board 50 is used as a flexible printed wiring board, the upper limit of the average thickness of the base film 1 may be 25 μm or 20 μm. When the base film 1 is thin, with an average thickness of 25 μm or less, the base film 1 is prone to waviness and is susceptible to the leaching of resist components from the resist pattern, which is a problem of the present disclosure, and therefore the effects of the present disclosure can be more effectively achieved. On the other hand, the lower limit of the average thickness of the base film 1 may be 5 μm or 10 μm. When the average thickness of the base film 1 is 5 μm or more, the insulating strength of the base film 1 can be sufficient.

[0026] [Wiring section] The plurality of wiring portions formed on the surface of the base film 1 includes an outermost wiring portion 11 and a plurality of inner wiring portions 10 other than the outermost wiring portion 11, and forms a conductive pattern 20 which will be described later.

[0027] (seed layer) The seed layer 2 is a conductive layer for electroplating one surface of the base film 1. The printed wiring board 50 has the seed layer 2, which can prevent migration of metal ions from the metal layer 3. The seed layer 2 may be a sputtered layer formed by sputtering, or a sintered layer of metal particles formed by applying ink containing metal particles to one surface of the base film 1 and sintering the metal particles. Examples of the main component of the seed layer 2 include nickel, gold, silver, tungsten, molybdenum, copper, tin, cobalt, chromium, iron, and zinc. Among these, copper may be used because it has high adhesion to the base film 1 and is suitable as a plating starting surface.

[0028] The average thickness of the seed layer 2 may be 0.01 μm or more and less than 3 μm, or 0.02 μm or more and 2.8 μm or less. When the average thickness of the seed layer 2 is 0.01 μm or more and less than 3 μm, it is possible to prevent discontinuities from occurring on the surface of the seed layer 2 and to increase the removal efficiency by etching.

[0029] (metal layer) The metal layer 3 is formed by electroplating. Examples of the main component of the metal layer 3 include copper, nickel, and silver. Among these, copper may be used, which is highly conductive and relatively inexpensive, and provides high adhesion to the seed layer 2 when the main component of the seed layer 2 is copper. When the main component of the metal layer 3 is copper, the metal layer 3 may be formed by electroplating using a copper sulfate plating bath containing an additive, from the viewpoints of being relatively inexpensive and easy to adjust the height, etc.

[0030] The average height of the metal layer 3 can be, for example, 5 μm or more and 35 μm or less.

[0031] [Conductive pattern] The multiple wiring portions forming the conductive pattern 20 are provided on the boundary with the non-wiring region S2 and include an outermost wiring portion 11 that defines the outermost edge of the wiring region S1, and multiple inner wiring portions 10 other than the outermost wiring portion 11. The multiple inner wiring portions 10 are formed linearly and have approximately the same shape. The multiple inner wiring portions 10 each have a small width and are arranged at a narrow pitch. In other words, the multiple inner wiring portions 10 are arranged at a fine pitch.

[0032] The lower limit of the average width W1 of the outermost wiring portion 11 is 2 μm, and may be 3 μm. When the average width W1 is 2 μm or more, the effect of reducing collapse of the outermost wiring portion 11 can be improved. On the other hand, the upper limit of the average width W1 of the outermost wiring portion 11 is 30 μm, and may be 25 μm. When the average width W1 is 30 μm or less, a desired wiring density can be easily obtained.

[0033] The lower limit of the average height H1 of the outermost wiring portion 11 is 5 μm, and may be 6 μm. When the average height H1 is 5 μm or more, the effects of the present disclosure can be achieved. On the other hand, the upper limit of the average height H1 of the outermost wiring portion 11 is 35 μm, and may be 30 μm or 25 μm. When the average height H1 of the outermost wiring portion 11 is 35 μm or less, the effect of leaching of resist components from the resist pattern when the non-wiring region S2 adjacent to the outermost wiring portion 11 is wide is reduced, and collapse of the wiring portion can be reduced.

[0034] As shown in Fig. 3, the average bottom width G1 is a value obtained by subtracting the sum U1 of the widths U11 and U12 of the hollows at both ends hollowed out by the resist components leached from the resist pattern from the average width W1 of the outermost wiring portion 11. As shown in Fig. 3, the sum U1 of the hollow widths in the cross section of the outermost wiring portion 11 means the maximum width of the region hollowed out by the resist components leached from the resist pattern.

[0035] The upper limit of the difference U1 between the average width W1 and the average bottom width G1 in the outermost wiring portion 11 (the total U1 of the recessed widths at both ends) is 3 μm, and may be 2.9 μm, 2.8 μm, or 2.5 μm. When the difference U1 between the average width W1 and the average bottom width G1 in the outermost wiring portion 11 (the total U1 of the recessed widths at both ends) is 3 μm or less, it is possible to improve the effect of reducing collapse of the wiring portion due to leaching of resist components from the resist pattern when the non-wiring region S2 adjacent to the outermost wiring portion 11 is wide.

[0036] The upper limit of the ratio H1 / G1 of the average height H1 to the average bottom width G1 of the outermost wiring portion 11 is 2.00, but may also be 1.95, 1.90, or 1.85. When the upper limit of the ratio H1 / G1 of the average height H1 to the average bottom width G1 is within the above range, collapse of the outermost wiring portion 11 can be reduced. On the other hand, the lower limit of the ratio H1 / G1 of the average height H1 to the average bottom width G1 may be 1.20, 1.25, 1.30, or 1.40. This embodiment is more effective when the ratio H1 / G1 of the average height H1 to the average bottom width G1 is 1.20 or more.

[0037] The lower limit of the average width W2 of the inner wiring portion 10, which is a wiring portion other than the outermost wiring portion 11, is 2 μm, and may be 3 μm. When the average width W2 is 2 μm or more, the effect of reducing collapse of the inner wiring portion 10 can be improved. On the other hand, the upper limit of the average width W2 of the inner wiring portion 10 is 30 μm, and may be 25 μm. When the average width W2 is 30 μm or less, a desired wiring density can be easily obtained.

[0038] The average width W1 of the outermost wiring portion 11 may be larger than the average width W2 of the inner wiring portion 10. By making the average width W1 of the outermost wiring portion 11 larger than the average width W2 of the inner wiring portion 10, collapse of the outermost wiring portion 11, which is prone to collapse, can be reduced.

[0039] The lower limit of the average height H2 of the inner wiring portion 10 is 5 μm, and may be 6 μm. When the average height H2 is 5 μm or more, the effects of the present disclosure can be achieved. On the other hand, the upper limit of the average height H2 of the inner wiring portion 10 is 35 μm, and may be 30 μm or 25 μm. When the average height H2 of the inner wiring portion 10 is 35 μm or less, the inner wiring portion 10 is less susceptible to the effects of leaching of resist components from the resist pattern when the non-wiring region S2 adjacent to the outermost wiring portion 11 is wide, and collapse of the wiring portion can be reduced.

[0040] The upper limit of the average spacing L between the outermost wiring portion 11 and the inner wiring portion 10, and between the inner wiring portions 10, is 25 μm, or may be 20 μm. When the average spacing L is 25 μm or less, waviness of the base film is reduced, and the effect of reducing collapse of the wiring portion can be improved. On the other hand, the lower limit of the average spacing L may be 2 μm or may be 5 μm. When the average spacing L is 2 μm or more, it becomes easy to manufacture multiple inner wiring portions 10.

[0041] As shown in Fig. 4, the average bottom width G2 is the average width W2 of the inner wiring portion 10 minus the total U2, which is the sum of the widths U21 and U22 of the gouges at both ends caused by the resist components leached from the resist pattern. As shown in Fig. 4, the total gouge width U2 in the cross section of the inner wiring portion 10 means the maximum width of the region gouged out by the resist components leached from the resist pattern.

[0042] The upper limit of the difference U2 between the average width W2 and the average bottom width G2 in the inner wiring portion 10 (the total U2 of the recessed widths at both ends) is 3 μm, and may be 2.9 μm, 2.8 μm, or 2.5 μm. When the difference U2 between the average width W2 and the average bottom width G2 in the inner wiring portion 10 (the total U2 of the recessed widths at both ends) is 3 μm or less, the inner wiring portion 10 is less susceptible to the effects of leaching of resist components from the resist pattern when the non-wiring region S2 adjacent to the outermost wiring portion 11 is wide, and collapse of the wiring portion can be reduced.

[0043] The upper limit of the ratio H2 / G2 of the average height H2 to the average bottom width G2 of the inner wiring portion 10 is 2.00, and may be 1.95, 1.90, 1.8, or 1.7. When the upper limit of the ratio H2 / G2 of the average height H2 to the average bottom width G2 is within the above range, collapse of the inner wiring portion 10 can be reduced. On the other hand, the lower limit of the ratio H2 / G2 of the average height H2 to the average bottom width G2 may be 1.15, 1.20, 1.25, or 1.30. This embodiment is more effective when the ratio H2 / G2 of the average height H2 to the average bottom width G2 is 1.15 or more.

[0044] <Printed wiring board manufacturing method> Next, an example of a method for manufacturing printed wiring board 50 of Fig. 1 will be described with reference to Fig. 2 and Fig. 5 to Fig. 7. Printed wiring board 50 of this embodiment may be manufactured by performing continuous processing using a roll-to-roll method.

[0045] In the method for manufacturing printed wiring board 50 of this embodiment, for example, by a semi-additive method, conductive pattern 20 including a plurality of wiring portions is formed directly or indirectly on the surface of insulating base film 1. Specifically, the method for manufacturing printed wiring board 50 of this embodiment can include, for example, a step of laminating a seed layer (seed layer lamination step), a step of forming a resist pattern (resist pattern formation step), a step of laminating a metal layer by electroplating (metal layer lamination step), a step of peeling off the resist pattern (resist pattern peeling step), and a step of peeling off the seed layer (seed layer peeling step).

[0046] [Seed layer lamination process] 5, in the seed layer lamination step, a seed layer 2 for plating is laminated on substantially the entire surface of one side of the base film 1. The method for laminating the seed layer 2 in the seed layer lamination step is not particularly limited, and the seed layer 2 may be laminated by, for example, sputtering, electroless plating, vapor deposition, or by applying and baking a dispersion of metal fine particles.

[0047] Furthermore, before the seed layer lamination step, a thin adhesive layer having high adhesion to the base film 1 and the seed layer 2 may be laminated on the surface of the base film 1. The material of the adhesive layer may be a metal containing nickel as a main component, particularly a nickel-chromium alloy, which has high adhesive strength. Examples of methods for laminating the adhesive layer include electroless plating, sputtering, vapor deposition, and coupling agent application, but sputtering, which can form an adhesive layer with particularly excellent adhesion, may also be used.

[0048] [Resist pattern formation process] In the resist pattern forming step, a resist pattern R is formed on the surface of the seed layer 2 laminated in the seed layer laminating step to define the formation regions of the outermost wiring portion 11 and the inner wiring portion 10. In the resist pattern forming step, a resist film is laminated on the surface of the seed layer 2, and the resist pattern R is formed by photolithography, as shown in FIG.

[0049] The resist film may be formed by, for example, coating and drying a liquid resist composition, or by thermocompression bonding of a dry film photoresist that does not have fluidity at room temperature. By using the dry film photoresist, the thickness of the resist film can be freely selected within a wide range, and workability is improved.

[0050] In the resist pattern forming step, a resist film is first laminated on substantially the entire surface of the seed layer 2 laminated in the seed layer laminating step. This resist film is formed from a positive resist composition that is exposed to light to weaken the bonds of polymers and increase the solubility in a developer.

[0051] Next, in the resist pattern formation process, the resist film is selectively exposed using a photomask or the like to form developer-soluble and insoluble portions in the resist film. Subsequently, the developer is used to wash away the soluble portions, thereby forming a resist pattern R having openings corresponding to the formation regions of the outermost wiring portion and the multiple inner wiring portions, as shown in FIG.

[0052] The resist film that has been exposed and developed as described above is then treated with a dilute aqueous solution of magnesium salt. By treating with the dilute aqueous solution of magnesium salt, the magnesium in the solution causes pseudo-crosslinking of uncured resist components, thereby reducing leaching of resist components in subsequent processes.

[0053] The dilute aqueous solution of magnesium salt may contain magnesium ions at 0.05% to 5.0%, 0.1% to 3.0%, or 0.5% to 1.5%. The magnesium salt is not particularly limited, but specific examples include magnesium sulfate, magnesium chloride, and magnesium hydroxide. These magnesium salts may be used alone or in combination of two or more. The treatment time with the dilute aqueous solution of magnesium salt is not particularly limited, and may be, for example, 100 to 600 seconds.

[0054] The temperature for treatment with a dilute aqueous solution of a magnesium salt is not particularly limited, and may be, for example, 0°C to 50°C, 5°C to 40°C, or 10°C to 30°C.

[0055] The method of treatment with a dilute aqueous solution of magnesium salt is not particularly limited, but may be, for example, immersion in the treatment solution or spraying the treatment solution.

[0056] In the resist pattern R, the average thickness and the openings corresponding to each wiring portion are set so that, as described above, the average height H1 of the outermost wiring portion 11 and the average height H2 of the inner wiring portion 10 are 5 μm or more and 35 μm or less, and the average spacing L between the outermost wiring portion 11 and the inner wiring portion 10, and between the inner wiring portions 10 themselves, is 25 μm or less.

[0057] [Metal layer lamination process] In the metal layer lamination step, a metal layer 3 is laminated by electroplating on the surface of the seed layer 2 exposed from the resist pattern formed in the resist pattern formation step. In the metal layer lamination step, as shown in Fig. 7, the metal layer 3 is laminated on the surface of the seed layer 2. In the metal layer lamination step, the metal layer 3 is laminated on the non-laminated regions of the resist pattern R (regions corresponding to the openings of the resist pattern R) on the surface of the seed layer 2.

[0058] Examples of metals used in the metal layer lamination step include copper, nickel, and silver. Among these, copper may be used, which is highly conductive, relatively inexpensive, and, when the seed layer 2 is mainly composed of copper, provides high adhesion to the seed layer 2. When the metal used in this step is copper, the method for laminating the metal layer 3 is not particularly limited, but electroplating using a copper sulfate plating bath containing an additive may be used, from the viewpoints of being relatively inexpensive and easily adjusting the height of the metal layer 3.

[0059] [Resist pattern stripping process] In the resist pattern peeling step, the resist pattern R formed in the resist pattern forming step is peeled off. In the resist pattern peeling step, the resist pattern R is first removed by peeling it off from the seed layer 2. Specifically, the laminate having the base film 1, the seed layer 2, the metal layer 3, and the resist pattern R after the metal layer lamination step is immersed in a stripping solution, causing the resist pattern R to expand with the stripping solution. This generates a repulsive force between the resist pattern R and the seed layer 2, causing the resist pattern R to peel off from the seed layer 2. A known stripping solution can be used.

[0060] [Seed layer removal process] In the seed layer peeling step, the seed layer 2 exposed after the resist pattern peeling step is peeled off. An etching solution that corrodes the metal that forms the seed layer 2 is used for this etching. In this way, the resist pattern R and the regions of the seed layer 2 that overlap with the resist pattern R in a planar view are removed to produce a plurality of inner wiring portions 10 and outermost wiring portions 11. The conductive pattern 20 after the resist pattern peeling step and the seed layer peeling step is as shown in FIG. 2.

[0061] As described above, in printed wiring board 50 manufactured by the method for manufacturing printed wiring board 50, base film 1 has wiring region S1 including a plurality of wiring portions and non-wiring region S2 including no wiring portions. Outermost wiring portion 11 is formed at the outermost portion of base film 1 in wiring region S1 and at the boundary between wiring region S1 and non-wiring region S2. A difference U1 between an average width W1 and an average bottom width G1 in outermost wiring portion 11 and a difference U2 between an average width W2 and an average bottom width G2 in inner wiring portion 10 are 3 μm or less, a ratio H1 / G1 of an average height H1 to an average bottom width G1 in outermost wiring portion 11 is 2.00 or less, and a ratio H2 / G2 of an average height H2 to an average bottom width G2 in inner wiring portion 10 is 2.00 or less.

[0062] This printed wiring board is less susceptible to the effects of resist components seeping out from adjacent wide resist patterns, and by reducing waviness in the base film, it is possible to reduce collapse of the wiring portion due to the seeping out of resist components from the resist pattern when there is a large non-wiring area adjacent to the wiring portion.

[0063] [Other embodiments] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is not limited to the configurations of the above-described embodiments, but is defined by the scope of the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0064] Although the above embodiment has been described as having a configuration in which a conductive pattern is laminated on one side of a base film, the printed wiring board may have conductive patterns laminated on both sides of the base film. Also, in the method for manufacturing the printed wiring board, a conductive pattern may be formed on both sides of the base film.

[0065] In the above embodiment, a configuration in which conductive patterns having curved regions in a planar view are laminated has been described. However, the shape of the conductive patterns is not particularly limited, and various shapes such as linear and spiral can be employed. Other specific examples of conductive patterns include a conductive pattern that does not have curved regions, but is linear, substantially parallel, and arranged at substantially equal intervals, as shown in FIG. 8 . The printed wiring board 100 shown in FIG. 8 includes a base film 1 and a conductive pattern 55 including multiple wiring portions formed on the surface of the base film 1. The multiple wiring portions are arranged at substantially equal intervals without short-circuiting the wiring. The base film 1 has a wiring region S11 including multiple wiring portions and a non-wiring region S12 that does not include the wiring portions. The multiple wiring portions include two outermost wiring portions 31 and multiple inner wiring portions 30 other than the outermost wiring portion 31. The outermost wiring portion 31 is formed at the boundary between the wiring region S11 and the non-wiring region S12 in the base film 1. The non-wiring region S12 is a region extending from the outermost surface of the outermost wiring portion 31 to a point 100 μm or more away, the average height H1 of the outermost wiring portion 31 and the average height H2 of the inner wiring portion 30 are 5 μm or more and 35 μm or less, the difference U1 between the average width W1 and the average bottom width G1 of the outermost wiring portion 31 and the difference U2 between the average width W2 and the average bottom width G2 of the inner wiring portion 30 are 3 μm or less, the ratio H1 / G1 of the average height H1 to the average bottom width G1 of the outermost wiring portion 31 is 2.00 or less, and the ratio H2 / G2 of the average height H2 to the average bottom width G2 of the inner wiring portion 30 is 2.00 or less. Therefore, the printed wiring board 100 is less susceptible to the leaching of resist components from the resist pattern when the non-wiring region S2 adjacent to the outermost wiring portion 31 is wide, and collapse of the wiring portion can be reduced.

[0066] In the above embodiment, the wiring portion has a seed layer on the surface of the base film and a metal layer laminated on the seed layer, but the wiring portion may not have a seed layer, and the metal layer may be laminated directly on the surface of the base film. Such a wiring portion can be manufactured, for example, by an additive method. In the additive method, for example, a resist pattern is formed on the base film, a metal layer is formed in the area other than the resist pattern, and then the resist pattern is removed. Then, a conductive pattern is formed in the area other than the resist pattern. Thus, even in a printed wiring board in which a metal layer is laminated directly on the surface of a base film, the non-wiring area is an area extending to a point 100 μm or more away from the outermost surface of the outermost wiring part, the average height H1 of the outermost wiring part and the average height H2 of the inner wiring part are 5 μm or more and 35 μm or less, the difference U1 between the average width W1 and the average bottom width G1 of the outermost wiring part and the difference U2 between the average width W2 and the average bottom width G2 of the inner wiring part are 3 μm or less, the ratio H1 / G1 of the average height H1 to the average bottom width G1 of the outermost wiring part is 2.00 or less, and the ratio H2 / G2 of the average height H2 to the average bottom width G2 of the inner wiring part is 2.00 or less, thereby making it less susceptible to the effects of leaching of resist components from the resist pattern when the non-wiring area adjacent to the wiring part is wide, and reducing collapse of the wiring part. [Example]

[0067] The present invention will be described in more detail below with reference to examples, but the present invention is not limited to these examples.

[0068] [Printed wiring boards No. 1 to No. 23] A base film made of polyimide film with an average height of 25 μm was prepared. A conductive pattern including 250 parallel wiring portions, as shown in FIG. 8, was formed on one side of this base film by a semi-additive process. Specifically, a copper seed layer with an average width of 0.5 μm was first laminated (seed layer lamination process). Next, a resist film was laminated on substantially the entire surface of the seed layer by thermocompression bonding of an acrylic dry film resist. The resist film was then selectively exposed to light using a photomask to form developer-soluble and developer-insoluble portions in the resist film. The developer-soluble portions were then washed away, and the substrate was then immersed in an aqueous solution containing 1% magnesium ions for the time listed in Table 1. A resist pattern having openings corresponding to the regions where multiple wiring portions were to be formed was then formed (resist pattern formation process).

[0069] Next, electrolytic copper plating was performed on the surface of the seed layer after the plasma treatment process using a copper sulfate plating bath containing 100 g / L of copper sulfate pentahydrate at 25°C, thereby laminating a metal layer having an average height shown in Table 1 (metal layer lamination process).

[0070] Next, after the metal layer lamination step, the resist pattern was removed using a dry film remover (resist pattern removal step).

[0071] Tables 1 and 2 show the average spacing between wiring sections, the average height, average width, difference between the average width and the average bottom width, average bottom width, and ratio of the average height to the average bottom width for the outermost and inner wiring sections of printed wiring boards No. 1 to No. 23.

[0072] [Table 1]

[0073] [Table 2]

[0074] [evaluation] (Determining whether wiring has fallen over) 100 samples of each printed wiring board No. 1 to No. 23 were manufactured. The percentage of samples in which the outermost wiring section had collapsed and the percentage of samples in which the inner wiring section had collapsed during the manufacturing process were judged visually using a microscope. Specifically, the percentage of samples in which the outermost wiring section and the inner wiring section had collapsed was evaluated on a four-level scale from A to D below. A and B are considered pass. The evaluation results are shown in Table 2. (Evaluation criteria) A: The percentage of fallen wiring sections is 5% or less. B: The percentage of fallen wiring sections is more than 5% and less than 10%. C: The percentage of fallen wiring sections is more than 10% and less than 20%. D: The percentage of fallen wiring sections is over 20%.

[0075] As shown in Tables 1 and 2, the non-wiring region is a region extending from the outermost surface of the outermost wiring portion to a point 100 μm or more away, the average height H1 of the outermost wiring portion and the average height H2 of the inner wiring portion are 5 μm or more and 35 μm or less, the average spacing L between the outermost wiring portion and the inner wiring portion and between the inner wiring portions is 25 μm or less, the difference U1 between the average width W1 and the average bottom width G1 of the outermost wiring portion and the average width L of the inner wiring portion are 25 μm or less, Tests Nos. 1 to 7, 9 to 12, 15, 17 and 20, in which the difference U2 between the average width W2 and the average bottom width G2 was 3 μm or less, the ratio H1 / G1 of the average height H1 to the average bottom width G1 in the outermost wiring portion was 2.00 or less, and the ratio H2 / G2 of the average height H2 to the average bottom width G2 in the inner wiring portion was 2.00 or less, showed good effects in reducing collapse of the outermost wiring portion and the inner wiring portion. Furthermore, a comparison between No. 3 and No. 4 reveals that when the average width W1 of the outermost wiring portion is larger than the average width W2 of the inner wiring portion, the effect of reducing the collapse of the outermost wiring portion is high. In addition, Reference Example No. 14, in which the non-wiring area is an area less than 100 μm from the outermost surface of the outermost wiring part, Reference Example No. 19, in which the average thickness of the base film exceeds 25 μm and the average spacing L between each wiring part exceeds 25 μm, and Reference Example No. 21, in which the average height of the outermost wiring part and the inner wiring part is less than 5 μm, are less likely to suffer from the problems disclosed herein, and therefore resulted in less collapse of the outermost wiring part and the inner wiring part.

[0076] On the other hand, No. 8, in which the average height H1 of the outermost wiring portion and the average height H2 of the inner wiring portion exceeded 35 μm and the difference U1 between the average width W1 and the average bottom width G1 of the outermost wiring portion exceeded 3 μm, had a low effect in reducing the collapse of the outermost wiring portion. Nos. 13, 16 and 23, in which the ratio H1 / G1 of the average height H1 to the average bottom width G1 of the outermost wiring portion exceeded 2.00, were less effective in reducing the collapse of the outermost wiring portion. No. 18, in which the average distance L between the wiring portions exceeds 25 μm, was less effective in reducing the collapse of the outermost wiring portions. No. 22, in which the ratio H1 / G1 of the average height H1 to the average bottom width G1 in the outermost wiring portion and the ratio H2 / G2 of the average height H2 to the average bottom width G2 in the inner wiring portion exceeded 2.00, had a significantly lower effect in reducing collapse of the outermost wiring portion and the inner wiring portion adjacent to the outermost wiring portion.

[0077] The above results demonstrate that the printed wiring board of the present disclosure can reduce collapse of the outermost wiring portion and the inner wiring portion when the non-wiring area adjacent to the outermost wiring portion and the inner wiring portion is large.

[0078] The printed wiring board of the present disclosure is suitable as a printed wiring board for small electronic devices because it can reduce collapse of wiring parts due to leaching of resist components from the resist pattern when there is a large non-wiring area adjacent to the wiring parts. [Explanation of symbols]

[0079] 1 base film 2. Seed layer 3 metal layer 10, 30 Inner wiring section 11, 31 Outermost wiring section 20, 55 Conductive pattern 50, 100 Printed wiring board S1, S11 wiring area S2, S12 Non-wired area R resist pattern

Claims

1. an insulating base film; a plurality of wiring portions formed on the surface of the base film; It is equipped with the wiring portion has a metal layer laminated directly or indirectly on the surface of the base film, the base film has a wiring region having the plurality of wiring portions and a non-wiring region located outside the wiring region and not having the wiring portions; the plurality of wiring portions include one or a plurality of outermost wiring portions and a plurality of inner wiring portions other than the outermost wiring portions, the outermost wiring portion is formed at the outermost portion of the plurality of wiring portions and at the boundary between the wiring region and the non-wiring region, the non-wiring region is a region extending from the outermost surface of the outermost wiring portion to a point 100 μm or more away, an average height H1 of the outermost wiring portion and an average height H2 of the inner wiring portion are 5 μm or more and 35 μm or less; the average distance L between the outermost wiring portion and the inner wiring portion, and between the inner wiring portions, is 25 μm or less; a difference U1 between the average width W1 and the average bottom width G1 of the outermost wiring portion and a difference U2 between the average width W2 and the average bottom width G2 of the inner wiring portion are 3 μm or less; a ratio H1 / G1 of an average height H1 to an average bottom width G1 of the outermost wiring portion is 2.00 or less; A printed wiring board in which the ratio H2 / G2 of the average height H2 to the average bottom width G2 of the inner wiring portion is 2.00 or less.

2. the wiring portion has a seed layer laminated between the base film and the metal layer, The printed wiring board according to claim 1, wherein the seed layer has an average thickness of 0.01 μm or more and less than 3 μm.

3. 3. The printed wiring board according to claim 1, wherein an average width W1 of the outermost wiring portion is greater than an average width W2 of the inner wiring portion.

4. 3. The printed wiring board according to claim 1, wherein the average thickness of the base film is 25 [mu]m or less.

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