Semiconductor element mounting board and semiconductor package

Abstract

To provide a technique for suppressing corrosion of base materials while suppressing cracks in an insulating layer in a substrate for mounting a semiconductor element.SOLUTION: A substrate for mounting a semiconductor element has a base material consisting of a metal, an electrode connected to the semiconductor element, an insulating layer placed between the base material and the electrode, with the outer circumference located inside the base material circumference, and an intermediate layer positioned between the base material and the insulating layer, which covers the entire surface of the insulating layer side of the base material.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor element mounting board and a semiconductor package. [Background technology]

[0002] Conventionally, semiconductor element mounting boards for mounting semiconductor elements have been known. For example, Patent Document 1 discloses a semiconductor element mounting board including a metal substrate, wiring portions connected to the semiconductor elements, and an insulating layer disposed between the substrate and the wiring portions. The insulating layer described in Patent Document 1 has an outer periphery located inside the outer periphery of the substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-139648 Summary of the Invention [Problem to be solved by the invention]

[0004] However, even with prior art such as that disclosed in Patent Document 1, there is still room for improvement in the technology for suppressing corrosion of the substrate while suppressing cracks in the insulating layer in a semiconductor device mounting substrate. For example, in the semiconductor device mounting substrate described in Patent Document 1, the outer periphery of the insulating layer is positioned more inward than the outer periphery of the substrate to suppress cracks in the insulating layer. However, the portion of the surface of the substrate facing the insulating layer where the insulating layer is not formed is prone to corrosion because the metal forming the substrate is exposed. For this reason, there has been a demand for a technology for suppressing corrosion of the substrate while suppressing cracks in the insulating layer.

[0005] An object of the present invention is to provide a technique for suppressing the occurrence of cracks in an insulating layer and corrosion of a substrate in a semiconductor element mounting board. [Means for solving the problem]

[0006] The present invention has been made to solve at least part of the above-mentioned problems, and can be realized in the following aspects.

[0007] (1) According to one aspect of the present invention, there is provided a semiconductor device mounting board comprising: a metal substrate, electrodes connected to a semiconductor device, an insulating layer disposed between the substrate and the electrodes, the insulating layer having an outer periphery located inside the outer periphery of the substrate, and an intermediate layer disposed between the substrate and the insulating layer, the intermediate layer covering the entire surface of the substrate facing the insulating layer.

[0008] According to this configuration, the outer periphery of the insulating layer is located inside the outer periphery of the substrate. As a result, for example, in a manufacturing process for producing multiple semiconductor device mounting substrates from a single metal wafer, when cutting a metal wafer on which an insulating layer or the like has already been formed, cutting only the portion on which the insulating layer is not formed can prevent cracks from occurring in the insulating layer. Furthermore, the intermediate layer disposed between the substrate and the insulating layer covers the entire insulating layer-side surface of the substrate, including the exposed portion of the insulating layer-side surface of the substrate that is exposed because the insulating layer is not formed. This allows the intermediate layer to prevent corrosion of the exposed portion of the substrate. In this way, while preventing cracks from occurring in the insulating layer, the intermediate layer covers the entire insulating layer-side surface of the substrate, thereby preventing corrosion of the substrate.

[0009] (2) In the semiconductor element mounting substrate of the above embodiment, the intermediate layer may be formed of any one of nickel, a nickel compound, chromium, a chromium compound, titanium, and a titanium compound. According to this configuration, the intermediate layer is formed of any one of nickel, a nickel compound, chromium, a chromium compound, titanium, and a titanium compound, which have relatively high corrosion resistance. This can further suppress corrosion of the exposed portion of the surface of the base material on the insulating layer side, which is exposed because the insulating layer is not formed.

[0010] (3) In the semiconductor device mounting board of the above embodiment, the base material may be made of copper or aluminum. With this configuration, the base material is made of copper or aluminum, which has high heat dissipation properties, and therefore the heat dissipation properties of the semiconductor device mounting board can be improved.

[0011] (4) According to another aspect of the present invention, a semiconductor package is provided. The semiconductor package includes the semiconductor element mounting board described above, a semiconductor element electrically connected to the electrodes, and a resin portion covering the semiconductor element, the resin portion covering an exposed portion of the intermediate layer that is exposed outside the outer periphery of the insulating layer. According to this configuration, the resin portion encapsulates the semiconductor element while covering the exposed portion of the intermediate layer that is exposed outside the outer periphery of the insulating layer. The exposed portion of the intermediate layer covers the exposed portion of the surface of the base material facing the insulating layer that is exposed because the insulating layer is not formed, thereby suppressing corrosion of the exposed portion of the base material. This ensures adhesion between the base material and the resin portion via the intermediate layer, allowing the semiconductor element to be encapsulated by the resin portion.

[0012] The present invention can be realized in various forms, for example, in the form of a product including a semiconductor element mounting board, an apparatus including a semiconductor package, a method for manufacturing a semiconductor element mounting board and a semiconductor package, etc. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view of a semiconductor device mounting board according to a first embodiment. [Figure 2] FIG. 1 is a cross-sectional view illustrating a semiconductor package according to a first embodiment. [Figure 3] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 4] FIG. 4 is a cross-sectional view of a semiconductor device mounting board according to a second embodiment. [Figure 5] FIG. 10 is a schematic cross-sectional view of a semiconductor package according to a second embodiment. [Figure 6] FIG. 5 is a cross-sectional view taken along line BB in FIG. 4. DETAILED DESCRIPTION OF THE INVENTION

[0014] First Embodiment FIG. 1 is a cross-sectional view of a semiconductor device mounting board 1 according to a first embodiment. FIG. 2 is a cross-sectional view of a semiconductor package 6 according to the first embodiment. The semiconductor device mounting board 1 according to this embodiment supports an optical semiconductor, such as a light-emitting diode (LED) or a laser diode (LD), as a semiconductor device 6a and functions as a heat dissipation substrate that dissipates heat generated during light emission. The semiconductor device mounting board 1 includes a base material 10, an intermediate layer 20, an adhesion layer 30, an insulating layer 40, an adhesion layer 50, a bonding layer 60, an electrode 70, and a protective layer 80. Note that, for ease of explanation, the thickness relationships among the base material 10, the intermediate layer 20, the adhesion layer 30, the insulating layer 40, the adhesion layer 50, the bonding layer 60, the electrode 70, the protective layer 80, and the semiconductor device 6a are illustrated differently from the actual thickness relationships.

[0015] The substrate 10 is a member having a flat plate shape and serves as the base of the semiconductor element mounting board 1. In this embodiment, the thickness of the substrate 10 is 1 mm. The substrate 10 is made of metal. In this embodiment, the substrate 10 is made of copper (Cu). The substrate 10 may be made of aluminum (Al). The substrate 10 may be made of a material containing copper as a main component, a material containing aluminum as a main component, or an alloy of copper and aluminum. By forming the substrate 10 from these metals, heat generated in the semiconductor element 6a can be efficiently released to the outside via the substrate 10.

[0016] The intermediate layer 20 is disposed between the substrate 10 and the electrode 70. More specifically, the intermediate layer 20 is disposed between the substrate 10 and the adhesive layer 30. In this embodiment, the intermediate layer 20 is provided on one surface 11 of the substrate 10 on which the insulating layer 40 described below is formed, and covers the entire one surface 11 of the substrate 10. In this embodiment, as shown in FIG. 1 , the widths of the adhesive layer 30 and the electrode 70 are smaller than the width of the substrate 10, and therefore at least a portion of the intermediate layer 20 is disposed between the substrate 10 and the adhesive layer 30.

[0017] The intermediate layer 20 is formed from a material different from the material forming the substrate 10, which has relatively high corrosion resistance and is resistant to oxidation. In this embodiment, the intermediate layer 20 is formed from nickel, which has higher corrosion resistance and oxidation resistance than copper, which forms the substrate 10. The intermediate layer 20 may be formed from any of a nickel compound such as a nickel-cobalt alloy, chromium, a chromium compound, titanium, or a titanium compound. Furthermore, the material forming the intermediate layer 20 is not limited to nickel, a nickel compound, chromium, a chromium compound, titanium, or a titanium compound. It is desirable that the intermediate layer 20 be formed from a material that is more corrosion resistant than the substrate 10 or that is resistant to oxidation than the substrate 10.

[0018] The adhesion layer 30 is disposed between the intermediate layer 20 and the insulating layer 40. In this embodiment, the adhesion layer 30 is made of titanium and has a thickness of, for example, 0.5 μm. The adhesion layer 30 adheres the intermediate layer 20 and the insulating layer 40 together and reduces the difference in thermal expansion between the substrate 10 and the insulating layer 40, thereby preventing cracks from forming in the insulating layer 40.

[0019] The insulating layer 40 is disposed between the substrate 10 and the electrode 70, more specifically, between the adhesive layer 30 and the adhesive layer 50. The insulating layer 40 is made of alumina (Al2O3) and has a thickness of, for example, 5 μm. The insulating layer 40 insulates the substrate 10, which is made of metal, from the electrode 70. Details of the characteristics of the insulating layer 40 of this embodiment will be described later.

[0020] The adhesion layer 50 is disposed between the insulating layer 40 and the bonding layer 60. In this embodiment, the adhesion layer 50 is made of titanium and has a thickness of, for example, 0.2 μm. The adhesion layer 50 adheres the insulating layer 40 and the bonding layer 60 and reduces the difference in thermal expansion between the insulating layer 40 and the bonding layer 60, thereby preventing cracks from forming in the insulating layer 40. In this embodiment, two adhesion layers 50 are formed on the insulating layer 40 by patterning.

[0021] The bonding layer 60 is disposed between the adhesion layer 50 and the electrode 70. The bonding layer 60 is made of palladium (Pd) and has a thickness of, for example, 0.07 μm. The bonding layer 60 improves the bonding strength between the adhesion layer 50 and the electrode 70. In this embodiment, the bonding layer 60 is formed on each of the two adhesion layers 50 by patterning.

[0022] The electrodes 70 are connected to the semiconductor element 6a via bumps (not shown) (see FIG. 2). The electrodes 70 are made of gold (Au) and have a thickness of, for example, 3.0 μm. In this embodiment, the electrodes 70 are formed on each of the two bonding layers 60 by patterning.

[0023] The protective layer 80 is provided on the other surface 12 of the substrate 10, opposite the one surface 11. The protective layer 80 covers the entire other surface 12 of the substrate 10. Like the intermediate layer 20, the protective layer 80 is made of nickel. The protective layer 80 may be made of any of a nickel compound, chromium, a chromium compound, titanium, or a titanium compound. The protective layer 80 suppresses corrosion on the other surface 12 side of the substrate 10. The protective layer 80 may be formed simultaneously with the formation of the intermediate layer 20 on a single metal member before it is divided into a plurality of semiconductor device mounting substrates 1 in the manufacturing process of the semiconductor device mounting substrate 1.

[0024] As shown in Fig. 2, the semiconductor package 6 includes a semiconductor element mounting board 1, a semiconductor element 6a, a phosphor 6b, and a resin portion 6c (see Fig. 2). The semiconductor element 6a is connected to an electrode 70 of the semiconductor element mounting board 1 via a bump (not shown). The phosphor 6b is provided on the opposite side of the semiconductor element 6a from the semiconductor element mounting board 1. The phosphor 6b converts the wavelength of light emitted by the semiconductor element 6a, which is an optical semiconductor, and emits the wavelength-converted light to the outside of the semiconductor package 6.

[0025] The resin portion 6c is formed to cover the semiconductor element 6a. An end 6d of the resin portion 6c on the base material 10 side is in contact with the intermediate layer 20 that covers the entire one surface 11 of the base material 10. The resin portion 6c seals the semiconductor element 6a.

[0026] Next, the features of the semiconductor device mounting board 1 of this embodiment will be described. In the semiconductor device mounting board 1, the outer periphery of the insulating layer 40 is located inside the outer periphery of the base material 10, and the intermediate layer 20 covers the entire surface of the base material 10 on the insulating layer 40 side.

[0027] 3 is a cross-sectional view taken along line AA in FIG. 1, showing the semiconductor device mounting board 1 as viewed from the electrode 70 side. As shown in FIG. 3, the outer periphery 40a of the insulating layer 40 is located more inward than the outer periphery 10a of the base material 10. Specifically, the outer periphery 40a of the insulating layer 40 is located closer to the central axis C1 in the stacking direction of the semiconductor device mounting board 1 than the outer periphery 10a of the base material 10. In this embodiment, the insulating layer 40 is formed so that the cross section perpendicular to the central axis C1 has a substantially rectangular shape. In the cross section shown in FIG. 3, the outer contour lines of the four corner portions 40b of the outer periphery 40a of the insulating layer 40 each have a curved shape.

[0028] The intermediate layer 20 covers the entire surface of the base material 10 facing the insulating layer 40. As a result, the intermediate layer 20 has an exposed portion 21 that is exposed outside the outer periphery 40a of the insulating layer 40, as shown in FIG. 3, which is a view of the semiconductor device mounting board 1 viewed from the electrode 70 side. The exposed portion 21 is formed to surround the periphery of the insulating layer 40. As a result, when the semiconductor device mounting board 1 is viewed from the electrode 70 side as shown in FIG. 3, one surface 11 of the base material 10 is not exposed. An end 6d of the resin portion 6c of the semiconductor package 6 is in contact with the exposed portion 21 of the intermediate layer 20.

[0029] For example, when manufacturing multiple semiconductor device mounting boards, an insulating layer is formed on a single metal substrate, and the substrate is then cut into individual pieces. To prevent cracks from forming in the insulating layer when the substrate is cut, multiple insulating layers are formed on a single substrate, and the exposed portions of the substrate between adjacent insulating layers are cut. As a result, in a single semiconductor device mounting board, the outer periphery of the insulating layer is located inside the outer periphery of the substrate. However, in a single semiconductor device mounting board, the surface of the substrate where no insulating layer is formed is exposed, which may cause corrosion of the exposed portion of the substrate by etching solutions used in the manufacturing process or saltwater during actual use. Corrosion of the substrate forms gaps between the substrate and the resin portion of the semiconductor package, thereby reducing adhesion between the substrate and the resin portion. This reduced adhesion between the substrate and the resin portion makes it difficult to maintain the encapsulation of the semiconductor device by the resin portion.

[0030] In the semiconductor element mounting board 1 of this embodiment, one surface 11 of the base material 10 is entirely covered with the intermediate layer 20, including the exposed portion where the insulating layer 40 is not formed. This prevents cracks from occurring in the insulating layer 40 when the base material is cut into individual pieces, and the intermediate layer 20 covering the entire one surface 11 of the base material 10 prevents corrosion of the base material 10. When corrosion of the base material 10 is prevented, adhesion between the base material 10 and the resin portion 6c of the semiconductor package 6 via the intermediate layer 20 is ensured. This prevents cracks from occurring in the insulating layer 40, and allows the semiconductor element 6a to be reliably sealed by the resin portion 6c in the semiconductor package 6.

[0031] In the semiconductor device mounting board 1 of this embodiment described above, the outer periphery 40a of the insulating layer 40 is located inside the outer periphery 10a of the base material 10. As a result, for example, in a manufacturing process for manufacturing multiple semiconductor device mounting boards 1 from a single metal wafer, when cutting a metal wafer on which an insulating layer 40 or the like has already been formed, cutting the portion on which the insulating layer 40 is not formed can prevent cracks from occurring in the insulating layer 40. Furthermore, the intermediate layer 20 covers the entire one surface 11 of the base material 10, including the exposed portion of the one surface 11 of the base material 10 that is exposed because the insulating layer 40 is not formed. As a result, the intermediate layer 20 can prevent corrosion of the exposed portion of the base material 10. As described above, the outer periphery 40a of the insulating layer 40 is located inside the outer periphery 10a of the base material 10, preventing cracks from occurring in the insulating layer 40. Furthermore, the intermediate layer 20 covers the entire one surface 11 of the base material 10 on the insulating layer 40 side, preventing corrosion of the exposed portion of the base material 10.

[0032] Furthermore, in the semiconductor device mounting board 1 of this embodiment, the intermediate layer 20 is formed of nickel, which has relatively high corrosion resistance, and this makes it possible to suppress corrosion of the exposed portion of one surface 11 of the base material 10, which is exposed because the insulating layer 40 is not formed thereon.

[0033] Furthermore, according to the semiconductor device mounting board 1 of this embodiment, the base material 10 is made of copper, which has high heat dissipation properties, so that the heat dissipation properties of the semiconductor device mounting board 1 can be improved.

[0034] Furthermore, according to the semiconductor package 6 of this embodiment, the resin portion 6c seals the semiconductor element 6a while covering the exposed portion 21 of the intermediate layer 20 that is exposed outside the outer peripheral portion 40a of the insulating layer 40. The exposed portion 21 of the intermediate layer 20 is formed so as to cover the portion of one surface 11 of the base material 10 that is exposed because the insulating layer 40 is not formed, thereby suppressing corrosion of the exposed portion of the base material 10. This ensures adhesion between the base material 10 and the resin portion 6c, allowing the resin portion 6c to seal the semiconductor element 6a.

[0035] Second Embodiment Fig. 4 is a cross-sectional view of a semiconductor device mounting board 2 of the second embodiment. Fig. 5 is a cross-sectional schematic view of a semiconductor package 7 of the second embodiment. The semiconductor device mounting board 2 of the second embodiment differs from the semiconductor device mounting board 1 of the first embodiment (Fig. 1) in that it is patterned down to the insulating layer.

[0036] The semiconductor element mounting board 2 of the second embodiment includes a base material 10, an intermediate layer 20, an adhesion layer 30, an insulating layer 40, an adhesion layer 50, a bonding layer 60, an electrode 70, and a protective layer 80. For ease of explanation, the thickness relationships among the base material 10, the intermediate layer 20, the adhesion layer 30, the insulating layer 40, the adhesion layer 50, the bonding layer 60, the electrode 70, the protective layer 80, and the semiconductor element 6a are illustrated in Figures 4 and 5 as being different from the actual thickness relationships.

[0037] The intermediate layer 20 is disposed between the substrate 10 and the electrode 70, more specifically, between the substrate 10 and two adhesion layers 30. In this embodiment, as shown in FIG. 4, the widths of the adhesion layers 30 and the electrodes 70 are smaller than the width of the substrate 10, and therefore at least a portion of the intermediate layer 20 is disposed between the substrate 10 and the adhesion layers 30. The intermediate layer 20 is formed from a material different from the material forming the substrate 10, which has relatively high corrosion resistance and is resistant to oxidation. The intermediate layer 20 of this embodiment is formed from nickel, which has higher corrosion resistance and oxidation resistance than copper, which forms the substrate 10. It is desirable that the intermediate layer 20 be formed from a material that is more corrosion resistant than the substrate 10 or is resistant to oxidation than the substrate 10.

[0038] The semiconductor element mounting substrate 2 includes two adhesion layers 30 and two insulating layers 40. The two adhesion layers 30 are formed on an intermediate layer 20 that covers the entire surface 11 of one of the substrates 10. Two insulating layers 40 are formed on each of the two adhesion layers 30. An adhesion layer 50, a bonding layer 60, and an electrode 70 are formed on each of the two insulating layers 40.

[0039] 5, the semiconductor package 7 includes a semiconductor element mounting board 2, a semiconductor element 6a, a phosphor 6b, and a resin portion 7c. The resin portion 7c is formed to cover the semiconductor element 6a. An end portion 7d of the resin portion 7c on the base material 10 side is in contact with an intermediate layer 20 that covers the entire one surface 11 of the base material 10.

[0040] FIG. 6 is a cross-sectional view taken along line BB in FIG. 4 , showing the semiconductor device mounting board 2 as viewed from the electrode 70 side. As shown in FIG. 6 , the outer peripheral portions 40a of the two insulating layers 40 are located more inward than the outer peripheral portion 10a of the base material 10 (closer to the central axis C2 in the stacking direction of the semiconductor device mounting board 2). The intermediate layer 20 covers the entire surface of the base material 10 facing the insulating layer 40, and thus has an exposed portion 22 that is exposed because the insulating layer 40 is not formed thereon. The exposed portion 22 is formed so as to surround the periphery of each of the two insulating layers 40. As a result, when the semiconductor device mounting board 2 is viewed from the electrode 70 side, one surface 11 of the base material 10 is not exposed. An end portion 7d of the resin portion 7c of the semiconductor package 7 is in contact with the exposed portion 22 of the intermediate layer 20.

[0041] In the semiconductor device mounting board 2 of this embodiment described above, the outer periphery 40a of the insulating layer 40 is located inside the outer periphery 10a of the base material 10. This makes it possible to prevent cracks from occurring in the insulating layer 40 by cutting off the portion where the insulating layer 40 is not formed. The intermediate layer 20 covers the entire one surface 11 of the base material 10, and therefore can prevent corrosion of the exposed portion of the base material 10. In this way, the outer periphery 40a of the insulating layer 40 is located inside the outer periphery 10a of the base material 10, thereby preventing cracks from occurring in the insulating layer 40, and the intermediate layer 20 covers the entire one surface 11 of the base material 10, thereby preventing corrosion of the exposed portion of the base material 10.

[0042] Furthermore, according to the semiconductor package 7 of this embodiment, the resin portion 7c seals the semiconductor element 6a while covering the exposed portion 22 of the intermediate layer 20 that is exposed outside the outer peripheral portion 40a of the insulating layer 40. The exposed portion 22 of the intermediate layer 20 is formed so as to cover the exposed portion of one surface 11 of the base material 10 on which the insulating layer 40 is not formed, thereby suppressing corrosion of the exposed portion of the base material 10. This ensures adhesion between the base material 10 and the resin portion 7c, allowing the resin portion 7c to seal the semiconductor element 6a.

[0043] <Modification of this embodiment> The present invention is not limited to the above-described embodiment, and can be embodied in various forms without departing from the spirit of the invention. For example, the following modifications are also possible.

[0044] [Variation 1] In the above-described embodiment, the semiconductor device mounting board supports the optical semiconductor and functions as a heat dissipation board that dissipates heat generated during light emission to the outside. However, the semiconductor device mounted on the semiconductor device mounting board is not limited to an optical semiconductor.

[0045] [Variation 2] In the above-described embodiment, the intermediate layer 20 is formed of nickel. However, the intermediate layer 20 may be formed of any of a nickel compound such as a nickel-cobalt alloy, chromium, a chromium compound, titanium, or a titanium compound. The material forming the intermediate layer 20 is not limited to these, but it is desirable that the intermediate layer 20 be formed of a material different from the material forming the base material 10, which has higher corrosion resistance than the base material 10, or a material that is less susceptible to oxidation than the base material 10.

[0046] [Variation 3] In the first embodiment, two layers from the adhesion layer 50 to the electrode 70 are formed on the insulating layer 40. In the second embodiment, two layers from the adhesion layer 30 to the electrode 70 are formed on the intermediate layer 20. The configuration of the semiconductor element mounting board is not limited to this. For example, it may be in a state immediately after the layers from the intermediate layer 20 to the electrode 70 are formed in this order on the base material 10, before they are patterned.

[0047] [Variation 4] In the above-described embodiment, the semiconductor element mounting board has the protective layer 80 provided on the other surface 12 of the substrate 10 on which the insulating layer 40 or the like is not formed. The protective layer 80 is not always necessary, but it can suppress corrosion on the other surface 12 side of the substrate 10.

[0048] This aspect has been described above based on embodiments and modifications. However, the above-described embodiments are intended to facilitate understanding of this aspect and are not intended to limit this aspect. This aspect may be modified or improved without departing from the spirit and scope of the claims, and equivalents thereof are included in this aspect. Furthermore, if a technical feature is not described as essential in this specification, it may be deleted as appropriate.

[0049] (Application example 1) A semiconductor element mounting board, a substrate made of metal; an electrode connected to the semiconductor element; an insulating layer disposed between the substrate and the electrode, the insulating layer having an outer periphery located inside the outer periphery of the substrate; an intermediate layer disposed between the base material and the insulating layer, the intermediate layer covering the entire surface of the base material on the insulating layer side; A semiconductor element mounting board characterized by: (Application example 2) The semiconductor element mounting board according to Application Example 1, the intermediate layer is formed of any one of nickel, a nickel compound, chromium, a chromium compound, titanium, or a titanium compound; A semiconductor element mounting board characterized by: (Application example 3) The semiconductor element mounting board according to Application Example 1 or Application Example 2, The substrate is formed of copper or aluminum. A semiconductor element mounting board characterized by: (Application example 4) A semiconductor package comprising: The semiconductor element mounting board according to any one of Application Examples 1 to 3, a semiconductor element electrically connected to the electrode; a resin portion that covers the semiconductor element, the resin portion covering an exposed portion of the intermediate layer that is exposed outside the outer periphery of the insulating layer, A semiconductor package characterized by: [Explanation of symbols]

[0050] 1, 2...Semiconductor element mounting board 6,7...Semiconductor packages 6a...Semiconductor element 6c,7c…Resin part 10...Base material 10a...Outer periphery (of the substrate) 11,12…Surface 20...Middle class 21,22...Exposed part 40...insulating layer 40a...Outer periphery (of insulating layer) 70...Electrode

Claims

1. A semiconductor element mounting board, a substrate made of metal; an electrode connected to the semiconductor element; an insulating layer disposed between the substrate and the electrode, the insulating layer having an outer periphery located inside the outer periphery of the substrate; an intermediate layer disposed between the base material and the insulating layer, the intermediate layer covering the entire surface of the base material on the insulating layer side; When the semiconductor element mounting board is viewed along the direction in which the base material, the intermediate layer, and the insulating layer are stacked, the insulating layer has a rectangular shape, and the outer contour of the corners of the insulating layer is formed to have a curved shape inside the outer contour of the intermediate layer. A semiconductor element mounting board characterized by:

2. 2. The semiconductor element mounting board according to claim 1, the intermediate layer is formed of any one of nickel, a nickel compound, chromium, a chromium compound, titanium, or a titanium compound; A semiconductor element mounting board characterized by:

3. 2. The semiconductor element mounting board according to claim 1, The substrate is formed of copper or aluminum. A semiconductor element mounting board characterized by:

4. A semiconductor package comprising: The semiconductor element mounting board according to claim 1 or 2, a semiconductor element electrically connected to the electrode; a resin portion that covers the semiconductor element, the resin portion covering an exposed portion of the intermediate layer that is exposed outside the outer periphery of the insulating layer, A semiconductor package characterized by:

Images