Clock generation method and system for I2S audio bus, DAC circuit

Abstract

I 2 A clock generation method and system for an S audio bus, and a DAC circuit are provided. Solution: This I 2 The clock generation method for the S audio bus is as follows: 2 A step of reading an audio file transmitted by an S audio bus; the main controller reading the sampling rate, data bit length and number of channels of the audio file, calculating and obtaining the amount of data of each frame according to the data bit length and the number of channels, and generating a master clock signal according to a multiple request of the master clock signal by the controller, wherein the frequency of the master clock signal is f s ×X, and f s where x is the sampling rate and x is a selected multiple, and the slave controller receives the master clock signal, and uses the master clock signal as a clock source to realize a modulation filter for audio digital-to-analog conversion. The present invention eliminates the need for an external crystal oscillator with a special frequency, simplifying the design of hardware circuits and reducing device costs.

Description

[Technical Field]

[0001] This application claims priority to a Chinese patent application filed on December 7, 2021, application number CN2021114846754.

[0002] The present invention belongs to the field of audio systems. 2 Clock generation method and system for S audio bus, DAC (digital-analog conversion) system, especially I 2 This invention relates to a crystal-free clock generation method and system for the S audio bus. [Background technology]

[0003] Due to the strong anti-interference capability of the audio bus, it is increasingly being used in car entertainment systems or alarm systems. 2 The signal is transmitted in S-bus format and reduced by the DAC chip or DAC function module on the receiving end. Most DAC conversion chips require a master clock signal, which is a multiple of the sampling frequency, to be fed to a modulator and digital filter using the "ΔΣ" format to generate the analog audio signal.

[0004] Currently, the mainstream binaural audio formats generally require controllers with audio bus peripherals, and in many cases, only the built-in peripheral modules (DIN, DOUT) provide data ports (DBCLK and LRCK), but do not provide a high-frequency MCLK. Meanwhile, the recommended reference solutions and mainstream product designs provided by DAC or integrated I2S bus receiver chip-level solution providers all use a 12.288MHz (or its multiples, such as 24.576MHz) active crystal oscillator to accommodate audio information with different sampling rates.

[0005] There are also some chips for digital audio systems, such as CODEC chips and audio DSP chips. These chips have a dedicated MCLK pin to provide corresponding clock information. However, these chip systems require a 12.288MHz (or its multiple, such as 24.576MHz) crystal oscillator to be externally mounted on the main chip, which may be an active crystal oscillator, a passive crystal oscillator, or other oscillator devices.

[0006] Based on the above situation, I 2 In most designs and applications using the S method, such a special frequency oscillator circuit is used to provide the MCLK signal to the slave chip. While the hardware cost is high, the higher the signal frequency, the higher the requirements for the circuit, especially the PCB design, and the more complex the hardware circuit design. Summary of the Invention [Problem to be solved by the invention]

[0007] In response to the above problem, the present invention eliminates the need for an external frequency crystal oscillator, simplifies the design of the hardware system, and reduces device costs. 2 The present invention aims to provide a clock generation method and system for an S audio bus, and a DAC circuit. [Means for solving the problem]

[0008] One aspect of the present invention is The main controller is 2 reading an audio file carried by the S audio bus; the main controller reads the sampling rate, data bit length and number of channels of the audio file, calculates and obtains the amount of data for each frame according to the data bit length and number of channels, and generates a master clock signal according to the multiple requirement of the master clock signal from the controller, where the frequency of the master clock signal is fs×X, where fs is the sampling rate and X is the selected multiple; The slave controller receives the master clock signal, and a modulation filter for audio digital-to-analog conversion is implemented using the master clock signal as a clock source. 2 A clock generation method for the S audio bus is provided.

[0009] In a preferred embodiment, X is an integer multiple of at least twice the amount of data in each frame.

[0010] In a preferred embodiment, the amount of data for each frame is calculated using the following formula (1). Data=L×2 (1) Here, L is the data bit length.

[0011] In a preferred embodiment, the signal after digital-to-analog conversion is a double-channel analog signal.

[0012] In a preferred embodiment, the main controller is a main chip having an MCLK output port, and the slave controller is a slave chip having an MCLK input port, and the MCLK output port and the MCLK input port are electrically connected so as to output the master clock signal generated from the main chip to the slave chip.

[0013] Another aspect of the present invention is a clock generator including a main chip having an MCLK output port and a slave chip having an MCLK input port, the MCLK output port and the MCLK input port being electrically connected; The main chip is2 The audio file transmitted through the S audio bus is read, the sampling rate, the data bit length and the number of channels of the audio file are read, and the amount of data per frame is calculated and obtained based on the data bit length and the number of channels. A master clock signal is generated according to a master clock signal multiple request from the slave chip, and output from the MCLK output port, and the frequency of the master clock signal is f s × X and f s is the sampling rate, X is the selected multiple, The slave chip receives the master clock signal through the MCLK input port and uses the master clock signal as a clock source to implement a modulation filter for audio digital-to-analog conversion. 2 A clock generation system for the S audio bus is provided.

[0014] In a preferred embodiment, X is an integer multiple of at least two times the amount of data per frame, and the amount of data per frame is calculated by the following formula (1). Data=L×2 (1) Here, L is the data bit length.

[0015] In a preferred embodiment, the signal after digital-to-analog conversion is a double-channel analog signal.

[0016] In a preferred embodiment, the main chip further comprises a DBCLK port for outputting serial data bits to the slave chip, an LRCLK port for outputting left and right channel clock signals to the slave chip, and a DOUT port for outputting data to the slave chip; the slave chip further comprises a DBCLK port for inputting serial data bits, an LRCLK port for inputting left and right channel clock signals, and a DIN port for inputting data; the DBCLK port of the main chip and the DBCLK port of the slave chip are connected directly or via a resistor; the LRCLK port of the main chip and the LRCLK port of the slave chip are connected directly or via a resistor; and the DOUT port of the main chip and the DIN port of the slave chip are connected directly or via a resistor.

[0017] In a preferred embodiment, the MCLK output port and the MCLK input port are directly connected, or a resistor is connected in series between them.

[0018] In a preferred embodiment, the slave chip further includes a DOUT port for outputting data to the main chip, and the main chip further includes a DIN port for inputting data, and the DOUT port of the slave chip and the DIN port of the main chip are connected directly or via a resistor.

[0019] A third aspect of the present invention provides a DAC circuit for a car audio system including the clock generation system described above.

[0020] In some embodiments, the DAC circuit is 2 It has an input terminal electrically connected to an MCU chip via an S audio bus, and an output terminal electrically connected to an input terminal of an amplifier, wherein the MCU chip is for receiving audio files, and the amplifier is for driving the car speaker to emit sound.

[0021] In some embodiments, the audio file is transmitted to the MCU chip via the vehicle interface and vehicle bus, and the MCU chip receives the I 2 The DAC circuit is electrically connected to the input terminal of the amplifier via the I2S audio bus, and the DAC circuit is electrically connected to the input terminal of the amplifier, and the output terminal of the amplifier is electrically connected to the car speakers. The DAC circuit implements the clock generation method described above, and does not require an external crystal oscillator, converts the audio file transmitted by the I2S audio bus into a binaural analog signal and feeds it to the amplifier.

[0022] A fourth aspect of the present invention provides a DAC circuit for a pedestrian warning device including the clock generation system described above.

[0023] In some embodiments, the DAC circuit is 2 The audio device has an input terminal electrically connected to an MCU chip via an S audio bus, and an output terminal electrically connected to an input terminal of an amplifier, wherein the MCU chip is for receiving an audio file, and the amplifier is for driving the pedestrian warning speaker to emit sound.

[0024] The pedestrian warning device is an external audio device that can improve the sound quality of the low-speed pedestrian warning sound for new energy vehicles such as electric vehicles and hybrid vehicles. It includes a speaker (installed in the vehicle and broadcasting the sound outside the vehicle) for reproducing the warning sound, and an amplifier for driving the speaker. It also includes an on-board serial bus interface circuit (CAN, LIN, etc.) for acquiring the vehicle speed signal of the new energy vehicle. [Effects of the Invention]

[0025] Using the above solution, the present invention has the following advantages over the prior art:

[0026] In the clock generation method and system of the present invention, 2By analyzing the audio file transmitted by the S audio bus, the sampling rate, data bit length and number of channels of the audio file are obtained, and based on the multiple request for the DAC master clock by the slave controller, the converted master clock signal from the slave controller DAC is output to the slave controller, and 2 The SDAC circuit eliminates the need for an external frequency crystal oscillator, simplifying the hardware system design and reducing the device cost. [Brief explanation of the drawings]

[0027] In order to more clearly describe the technical solutions of the present invention, the following briefly introduces the necessary drawings used in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative work required.

[0028] [Figure 1] 3 is a flowchart of a clock generation method according to an embodiment of the present invention. [Figure 2a] 1 is a structural block diagram of a clock generation system according to an embodiment of the present invention; [Figure 2b] FIG. 10 is a structural block diagram of another clock generation system according to an embodiment of the present invention. [Figure 2c] FIG. 2 is a structural block diagram of another clock generation system according to an embodiment of the present invention. [Figure 2d] FIG. 10 is a structural block diagram of a fourth clock generation system according to an embodiment of the present invention. [Figure 3] 1 is a schematic diagram of a car audio system to which the present embodiment is applied; [Figure 4] The Master table from the I2S DAC conversion chip manual is shown below. [Figure 5] Shows the call of the FTM0 program in the main program. DETAILED DESCRIPTION OF THE INVENTION

[0029] In order to facilitate understanding of the advantages and features of the present invention by those skilled in the art, preferred embodiments will be described in detail below with reference to the accompanying drawings. Note that the description of these embodiments contributes to understanding the present invention, but does not constitute a limitation on the present invention. Furthermore, the technical features of various embodiments of the present invention described below can be combined with each other as long as they are not inconsistent with each other.

[0030] According to one embodiment of the present invention, the sampling rate, data bit length, and number of channels of the audio file are extracted based on the analysis result of the audio file. Then, a square wave signal can be generated by the main controller's built-in peripheral modules (including, but not limited to, a clock module, a PWM module, a comparator output module, a PLL module, etc.) or by pure software code without calling any of the above peripheral modules, which can generate a corresponding inverted output at a chip port conforming to the MCLK characteristics (either by a peripheral module or by pure code, hereinafter collectively referred to as the "frequency multiplication function module"). A frequency multiplication of one LRCK is generated, and the octave frequency generates a frequency multiplied clock signal according to the MCLK requirement in the slave chip description.

[0031] As shown in FIG. 2 The clock generation method for the S audio bus is The main controller is 2 reading an audio file carried by the S audio bus; The main controller reads the sampling rate, data bit length and number of channels of the audio file, calculates and obtains the amount of data for each frame according to the data bit length and number of channels, and generates a master clock signal according to the multiple request of the master clock signal by the controller, and the frequency of the master clock signal is f s × X and f s is the sampling rate, X is the step multiple selected, receiving a master clock signal from the controller, and using the master clock signal as a clock source to implement a modulation filter for audio digital-to-analog conversion, and outputting an analog signal to be fed to an amplifier.

[0032] Specifically, the main controller is the main chip, and the slave controller is the slave chip. The program of the main chip is I 2 Reads the following information from the audio file transmitted via the S Audio Bus. The predetermined multiple is X, The data word length is L, The number of channels is 2, Frame frequency is f w , If the sampling rate is f s and The amount of data per frame is calculated as Data = L × 2.

[0033] The selected multiple X is taken from the Master table in the slave chip manual or application notes, and is usually an integer multiple of Data that is at least twice as large. According to the actual application of the multiple required by the slave chip for the master clock signal MCLK, one appropriate master clock signal MCLK is generated for the slave chip.

[0034] The frequency of the master clock signal MCLK is f s ×X.

[0035] For example, an audio file is analyzed and found to have a data length of 16 bits, a sampling rate of 16 kHz, and two channels. The main chip analyzes and obtains the audio file as a 16-bit data word length, and requests that the MCLK be 1024, 512, 256, 128, or 64 times the LRCK frequency. Since the data volume per frame is 32 bits, 64 times the LRCK frequency is used. Therefore, the MCLK frequency is 16 kHz x 64 = 1 MHz. The main controller's built-in peripheral module uses a frequency multiplication function module to generate a 1 MHz signal whose duty cycle (e.g., 50%) matches the MCLK duty cycle of the slave chip. This signal is connected to the slave chip's MCLK port. Of course, a 128-times multiplication function could also be selected to generate a 2 MHz clock.

[0036] The number of channels is two, and the signal after digital-to-analog conversion by the slave chip is a double-channel analog signal.

[0037] 2a shows a clock generation system according to this embodiment. As shown in FIG. 2a, this clock generation system includes a main chip 100 and a slave chip 200. The main chip 100 has a DBLCK port, an LRCLK port, a DOUT port, a DIN port, and an MCLK port, and the slave chip 200 has a DBCLK port, an LRCLK port, a DIN port, a DOUT port, and an MCLK port.

[0038] The main chip 100 is I 2 The audio file transmitted through the S audio bus is read, the sampling rate, data bit length, and number of channels of the audio file are read, and the amount of data per frame is calculated and obtained based on the data bit length and number of channels. A master clock signal is generated according to a master clock signal multiple request from the slave chip 200, and output from the MCLK output port. The frequency of the master clock signal is f s× X and f s is the sampling rate and X is the selected multiple.

[0039] A slave chip 200 for receiving a master clock signal via an MCLK input port, and for using the master clock signal as a clock source to implement a modulation filter for audio digital-to-analog conversion and output an analog signal to be fed to an amplifier.

[0040] The DBCLK port of the main chip 100 and the DBCLK port of the slave chip 200 are electrically connected, and the main chip 100 transmits a serial data bit clock signal (DBCLK) to the slave chip 200. The LRCLK port of the main chip 100 and the LRCLK port of the slave chip 200 are electrically connected directly, and the main chip 100 transmits left and right channel clock signals (LRCLK) to the slave chip 200. The DOUT port of the main chip 100 and the DIN port of the slave chip 200 are electrically connected directly, and the main chip 100 transmits audio data to the slave chip 200. The MCLK output port of the main chip 100 and the MCLK input port of the slave chip 200 are electrically connected directly, and the main chip 100 transmits a generated master clock signal (MCLK) to the slave chip 200. Furthermore, since the DOUT port of the slave chip 200 and the DIN port of the main chip 100 are electrically connected directly, the slave chip 200 can transmit audio data to the main chip 100. In other words, bidirectional data transmission can be performed between the main chip 100 and the slave chip 200. The main chip 100 executes a bus audio analysis program to 2The slave chip 200 can analyze audio files received from the S audio bus and generate a master clock signal according to the above method. The slave chip 200 uses the master clock signal as its clock source, implements a modulation filter for audio digital-to-analog conversion using a "Δ-σ" type modulator and digital filter, and modulates and converts the audio data received from the main chip 100 using the master clock signal, serial data bit clock signal, and left and right channel clock signals received from the main chip 100 to generate an analog audio signal to feed to the amplifier, which then drives the speaker. In this system, the master clock signal is not provided by any passive or active oscillator device (e.g., a crystal oscillator, ceramic oscillator, discrete logic device, etc.), but is implemented by the main chip 100 and its internal program.

[0041] 2b shows another clock generation system according to this embodiment. As shown in FIG. 2b, this clock generation system is almost the same as the clock generation system shown in FIG. 2a, except that a resistor 300 is connected in series between the port of the main chip 100 and the port of the slave chip 200, and the two are electrically connected via the resistor 300, thereby achieving a better signal transmission effect. Specifically, one resistor 300 is connected in series between the DBCLK port of the main chip 100 and the DBCLK port of the slave chip 200, one resistor 300 is connected in series between the LRCLK port of the main chip 100 and the LRCLK port of the slave chip 200, one resistor 300 is connected in series between the DIN port of the main chip 100 and the DOUT port of the slave chip 200, one resistor 300 is connected in series between the DOUT port of the main chip 100 and the DIN port of the slave chip 200, and one resistor 300 is connected in series between the MCLK output port of the main chip 100 and the MCLK input port of the slave chip 200.

[0042] 2c shows another clock generation system according to this embodiment. As shown in FIG. 2c, this clock generation system is almost the same as the clock generation system shown in FIG. 2a, except that the main chip 100 does not have a DIN port and the slave chip 200 does not have a DOUT port, meaning that bidirectional data transfer between the main chip 100 and the slave chip 200 is not possible, and audio data can only be transmitted from the main chip 100 to the slave chip 200.

[0043] 2d shows another clock generation system according to this embodiment. As shown in FIG. 2d, this clock generation system is almost the same as the clock generation system shown in FIG. 2a, except that main chip 100 does not have a DIN port, and slave chip 200 does not have a DOUT port, so audio data can only be transmitted from main chip 100 to slave chip 200. A resistor 300 is connected in series between the port of main chip 100 and the port of slave chip 200, and the two are electrically connected via one resistor 300, thereby achieving a better signal transmission effect. Specifically, one resistor 300 is connected in series between the DBCLK port of the main chip 100 and the DBCLK port of the slave chip 200, one resistor 300 is connected in series between the LRCLK port of the main chip 100 and the LRCLK port of the slave chip 200, one resistor 300 is connected in series between the DOUT port of the main chip 100 and the DIN port of the slave chip 200, and one resistor 300 is connected in series between the MCLK output port of the main chip 100 and the MCLK input port of the slave chip 200.

[0044] FIG. 3 illustrates a specific application of the method and system according to this embodiment to a car audio system. This embodiment also provides a DAC circuit for a car audio system, including the main chip 100 and slave chip 200 described above. The DAC circuit 3 is connected between the MCU chip 1 and the amplifier 4, converting an audio file into a multi-channel analog signal for amplification by the amplifier and then feeding it to the car speakers for sound playback. As shown in FIG. 3 , the DAC circuit 3 includes the clock generation system of this embodiment. The audio file is transmitted to the MCU chip 1 via a vehicle interface (vehicle bus). The MCU chip 1 is electrically connected to the DAC circuit 3 via an I2S audio bus 2. The DAC circuit 3 is electrically connected to the input terminal of the amplifier 4, and the output terminal of the amplifier 4 is electrically connected to the car speakers 5. The DAC circuit 3 implements the clock generation method of this embodiment, eliminating the need for an external crystal oscillator and providing an I2S clock. 2 The audio file transmitted by S Audio Bus 2 is converted into a binaural analog signal and fed to Amplifier 4.

[0045] This embodiment also provides a DAC circuit of a pedestrian alarm device, which includes the above-mentioned main chip 100 and slave chip 200, and the DAC circuit is connected between the MCU chip 1 and the amplifier 4, for converting the audio file into a multi-channel analog signal, so that the signal can be amplified by the amplifier and then fed to the pedestrian alarm speaker to emit an alarm sound.

[0046] example 1. By analyzing the beginning section of the audio file, the audio information is understood as 16-bit, 2-channel, sampling rate 16KHz.

[0047] 2.I 2 Refer to the Master table in the S DAC conversion chip manual (shown in Figure 4) to select the appropriate MCLK / LRCLK multiple, and select 64 here.

[0048] 3. Calculate the characteristics shown in Table 1 using the above method.

[0049] [Table 1]

[0050] Therefore, we can conclude that the required MCLK clock for this example is 1 MHz.

[0051] 4. The MCU (microcontroller, hereafter referred to as the single-chip microcomputer) used in this example is the FS32K144, and the external crystal oscillator is 8MHz. The peripheral module with a built-in clock uses the FTM module specific to the single-chip microcomputer, specifically FTM0.

[0052] 1) First, place the ports, then place MCLK on FTM0, port B13, 2) Place a clock source for FTM0 and select the clock source equal to the crystal oscillator clock, 3) The placement of the FTM0 function module is as follows: the efficiency placement is 1MHz, and the placement duty cycle is 50%; 4) As an IDE for FS series single-chip microcontrollers, once the configuration is complete, generate the ProcessorExpert code once, 5) The call of the FTM0 program in the main program is shown in Figure 5.

[0053] As used in this specification and claims, the terms "comprises" and "comprised" only indicate the inclusion of explicitly labeled steps and elements, but these steps and elements do not constitute an exclusive list, and other steps or elements may also be included in the method or apparatus.

[0054] Additionally, it will be understood that "plurality" in this disclosure refers to two or more and other quantifiers similar thereto.

[0055] Furthermore, while terms such as "first" and "second" are used to describe various pieces of information, it is understood that these pieces of information should not be limited to these terms. These terms are merely used to distinguish between pieces of information of the same type and do not imply a particular order or importance. In fact, terms such as "first" and "second" can be used interchangeably. For example, first information can also be referred to as second information, and similarly, second information can also be referred to as first information, without departing from the scope of this disclosure.

[0056] In this embodiment, unless expressly stated and limited otherwise, a first feature being "above" or "below" a second feature may include direct contact between the first and second features, or may include contact between the first and second features via other features between them rather than direct contact. Furthermore, a first feature being "above," "above," and "on the upper surface" of a second feature may include the first feature being directly above or diagonally above the second feature, or may simply indicate that the horizontal height of the first feature is higher than that of the second feature. A first feature being "below," "below," and "on the lower surface" of a second feature may include the first feature being directly below or diagonally below the second feature, or may simply indicate that the horizontal height of the first feature is lower than that of the second feature.

[0057] The above examples are merely for the purpose of illustrating the technical ideas and features of the present invention and are preferred examples, and their purpose is to enable those skilled in the art to understand the contents of the present invention and to practice it, but they do not limit the scope of protection of the present invention.

Claims

1. I ２ 1. A method of clock generation for an S audio bus, comprising: The main controller is ２ reading an audio file transmitted by the S audio bus; The main controller reads the sampling rate, data bit length and number of channels of the audio file, calculates and obtains the amount of data for each frame based on the data bit length and number of channels, and generates a master clock signal according to a multiple request of the master clock signal from the slave controller, and the frequency of the master clock signal is f ｓ ×X, and f ｓ is a sampling rate, and X is an integer multiple of at least two times the amount of data per frame, the integer being selected from the Master table in the chip manual; the slave controller receives the master clock signal, and a modulation filter for audio digital-to-analog conversion is realized using the master clock signal as a clock source. A clock generation method comprising:

2. The amount of data per frame is calculated by the following formula (1): Data=L×2 (1) where L is the data bit length.

2. The clock generation method according to claim 1.

3. The signal after digital-to-analog conversion is a double-channel analog signal.

2. The clock generation method according to claim 1.

4. The main controller is a main chip having an MCLK output port, and the slave controller is a slave chip having an MCLK input port, and the MCLK output port and the MCLK input port are electrically connected to each other so that the master clock signal generated from the main chip is output to the slave chip.

2. The clock generation method according to claim 1.

5. a main chip having an MCLK output port and a slave chip having an MCLK input port, the MCLK output port and the MCLK input port being electrically connected to each other; ２ 1. A clock generation system for an S audio bus, comprising: The main chip is ２ The audio file transmitted through the S audio bus is read, the sampling rate, the data bit length, and the number of channels of the audio file are read, and the amount of data per frame is calculated and acquired based on the data bit length and the number of channels. A master clock signal is generated according to a master clock signal multiple request from the slave chip, and output from the MCLK output port, and the frequency of the master clock signal is f ｓ ×X, and f ｓ is the sampling rate, X is an integer multiple of the amount of data per frame that is equal to or greater than two, and the integer is selected from the Master table in the chip manual; The slave chip receives the master clock signal through the MCLK input port, and uses the master clock signal as a clock source to implement a modulation filter for audio digital-to-analog conversion. A clock generation system comprising:

6. The amount of data per frame is calculated by the following formula (1): Data=L×2 (1) where L is the data bit length.

6. The clock generation system according to claim 5.

7. The signal after digital-to-analog conversion is a double-channel analog signal.

7. The clock generation system according to claim 6.

8. The main chip further comprises a DBCLK port for outputting serial data bits to the slave chip, an LRCLK port for outputting left and right channel clock signals to the slave chip, and a DOUT port for outputting data to the slave chip; the slave chip further comprises a DBCLK port for inputting serial data bits, an LRCLK port for inputting left and right channel clock signals, and a DIN port for inputting data; the DBCLK port of the main chip and the DBCLK port of the slave chip are connected directly or via a resistor; the LRCLK port of the main chip and the LRCLK port of the slave chip are connected directly or via a resistor; and the DOUT port of the main chip and the DIN port of the slave chip are connected directly or via a resistor.

6. The clock generation system according to claim 5.

9. The MCLK output port and the MCLK input port are directly connected, or a resistor is connected in series between them.

9. The clock generation system according to claim 5 or 8.

10. The slave chip further includes a DOUT port for outputting data to the main chip, and the main chip further includes a DIN port for inputting data, and the DOUT port of the slave chip and the DIN port of the main chip are connected directly or via a resistor.

9. The clock generation system according to claim 5 or 8.

11. The clock generation system according to claim 6 1. A DAC circuit for a car audio system comprising:

12. The DAC circuit is ２ The input terminal is electrically connected to an MCU chip via an S audio bus, and the output terminal is electrically connected to an input terminal of an amplifier, the MCU chip is for receiving audio files, and the amplifier is for driving a car speaker to produce sound.

12. The DAC circuit of claim 11.

13. The clock generation system according to claim 6 DAC circuit of a pedestrian warning device.

14. The DAC circuit is ２ an input terminal electrically connected to an MCU chip via an S audio bus, and an output terminal electrically connected to an input terminal of an amplifier, the MCU chip for receiving an audio file, and the amplifier for driving a pedestrian warning speaker to emit sound.

14. The DAC circuit of claim 13.

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