Amplifier Bias Circuit

Abstract

A method and apparatus for an amplifier including first and second transistors coupled in a stacked configuration with first and second current mirrors to provide respective bias signals to the amplifier transistors, wherein a reference transistor is coupled to the first and second current mirrors to jointly reference the bias signals.

Description

[Background technology]

[0001] As is known in the art, a key consideration in the design of radio frequency (RF) transistor amplifiers is establishing stable DC operating conditions. Such conditions affect many of the amplifier's performance characteristics, such as gain, frequency response, noise, linearity, and efficiency. Furthermore, DC operating conditions, such as quiescent drain current, must be predictable and invariant over temperature, power supply, and process variations. As shown in Figure 1, setting this quiescent drain current (Id) in a field-effect transistor (FET) amplifier is typically accomplished by adjusting the DC voltage Vg supplied to the gate of the transistor (Q1). While, in principle, Vg can be easily determined from the Id vs. Vg transfer characteristic of a typical device, the inherent sensitivity of FET characteristics to manufacturing process and temperature precludes the use of a fixed Vg.

[0002] As is known in the art, a commonly used DC bias element in analog circuit design is a current mirror, such as that described by Paul R. Gray and Robert G. Meyer in "Analysis and Design of Analog Integrated Circuits, 3rd ed., New York: Wiley, 1993." Figure 2 is a schematic diagram of a conventional current mirror for a D-mode GaAs MESFET operational amplifier, as demonstrated by N. Scheinberg (see, for example, N. Scheinberg, "Design of high-speed operational amplifiers with GaAs MESFETs," procs. 1987 IEEE ISCAS (Philadelphia), May 1987, pp. 193-198, and C. Tamazou and D. Haigh, "Gallium Arsenide Analog Integrated Circuit Design Techniques," Chapter 8 in "Analogue IC design: the current-mode approach," edited by C. Toumazou, F.J. Lidgey & D.G. Haigh. London: Peter Peregrinus Ltd. 1990). By appropriately sizing the widths of transistors Q1 and Q2, the current mirror allows a stable, controllable current ID2 to be established through the main circuit transistor Q2, where current ID2 "mirrors" (i.e., is proportional to) the reference current Iref. One of the factors in the operation of a current mirror is the availability of a stable reference current, Iref. This current relationship is given by the following equation:

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[0003] Note that as long as Q1 and Q2 are fabricated close to each other on the same chip, the relationship between the currents will be maintained regardless of process variations, especially voltage threshold (Vt) variations.The circuit of Figure 2 can be easily implemented to control the drain current of a high-efficiency, high-power RF amplifier.

[0004] Figure 3 shows a simplified circuit diagram embodiment with appropriate inductors and capacitors connected to RF amplifier FET Q2. For high power and high efficiency RF amplifiers, it is essential that the FET source potential must be connected directly to ground reference, which is also shown in Figure 3 by Vss being connected to ground potential. Also note that Vss1 is more negative than ground potential, and the drains of Q1, Q2, and Q3 are more positive than ground potential.

[0005] Without a bias circuit to compensate for process variations, some means of adjusting the gate voltage Vg, preferably for each amplifier, must be implemented so that the quiescent drain current Id is set near its nominal target value. Typical implementations include externally supplying a separate Vg voltage for each amplifier, adding a resistor ladder network on-chip to generate multiple potential Vg voltages from a fixed supply voltage, or screening and dividing the components into multiple Vg bins. However, these options first require some testing to determine how each component or group of components needs to be biased. Then, the assembly is tailored to the specific component or group of components. These steps significantly increase the time and cost of the product. One of the purposes of the DC bias circuit is to avoid the need for these Vg bins. Examples of patents relating to these types of circuits are U.S. Patent Nos. 5,889,429, 6,304,130, 6,114,901, 5,793,194, 4,896,121, 7,928,804, and 8,854,140, ​​all of which are incorporated herein by reference.

[0006] Stacked transistor RF amplifier topologies are commonly used to improve performance over single-transistor approaches. Balanced cascode and conventional cascode stacked transistor FET amplifiers require a repeatable DC drain current bias point and proper distribution of the DC supply voltage across the transistor drains for proper RF operation. Summary of the Invention

[0007] The DC quiescent current and voltage requirements of stacked FET amplifiers are typically determined by resistor divider networks or adjustable power supplies that require continuous changes from amplifier to amplifier due to inherent process variations in semiconductor technology. It is highly desirable to set the DC conditions without having to continuously change the network and supply voltage.

[0008] Embodiments of the present disclosure provide a method and apparatus for cascode and stacked FET RF amplifiers with a two-stage depletion-mode current mirror in which a process-insensitive reference current is mirrored to the cascode and stacked FET amplifiers. This arrangement establishes a source reference potential for the common gate of the top FET in the stack of amplifier circuits.

[0009] In one embodiment, the bias circuit is based on using first and second current mirrors to set the quiescent control of the amplifier. The first mirror establishes a current control signal at the gate electrode of the amplifier's bottom or common-source FET. The voltage output of the first mirror is also sent to a reference FET to establish the source potential of a common-gate reference in a second mirror circuit. In one embodiment, the common-gate reference FET in the second mirror circuit has a drain current from a second fixed current reference. The output of the second current mirror can be sent to a top-gate FET or a common-gate FET in a cascode or stacked FET network.

[0010] In one aspect, a circuit includes an amplifier including first and second transistors coupled in a stacked configuration, a first current mirror having a first control loop and a first mirror transistor coupled to a first terminal of the first transistor to provide a first bias control signal, a second current mirror having a second control loop and a second mirror transistor coupled to a first terminal of the second transistor to provide a second bias control signal, and a reference transistor coupled to the first and second current mirrors.

[0011] The circuit may further include one or more of the following features: the first current mirror includes a first mirror transistor, a first fixed current source, and a first follower transistor coupled in a follower configuration to the first mirror transistor; the second current mirror includes a second mirror transistor, a second fixed current source, and a second follower transistor coupled in a follower configuration to the second mirror transistor; a reference transistor is coupled to the first mirror transistor and the second mirror transistor; the first control loop further includes at least one diode or multiple diodes; the output of the first current mirror is configured to establish a source potential of a common gate reference of the second current mirror; the common gate reference of the second mirror has a drain current from the second fixed current source; the amplifier includes a depletion mode FET amplifier; and / or the amplifier includes an RF amplifier.

[0012] In another aspect, a method includes using an amplifier including first and second transistors coupled in a stacked configuration; using a first control loop to provide a first bias control signal and a first current mirror having a first mirror transistor coupled to a first terminal of the first transistor; using a second control loop to provide a second bias control signal and a second current mirror having a second mirror transistor coupled to a first terminal of the second transistor; and using a reference transistor coupled to the first and second current mirrors.

[0013] The method may further include one or more of the following features: the first current mirror includes a first mirror transistor, a first fixed current source, and a first follower transistor coupled to the first mirror transistor in a follower configuration; the second current mirror includes a second mirror transistor, a second fixed current source, and a second follower transistor coupled to the second mirror transistor in a follower configuration; a reference transistor is coupled to the first mirror transistor and the second mirror transistor; the first current loop further includes at least one diode; an output of the first current mirror is configured to establish a source potential of a common gate reference of the second current mirror; the common gate reference of the second current mirror has a drain current from the second fixed current source; the amplifier includes a depletion-mode FET amplifier; and / or the amplifier includes an RF amplifier.

[0014] In embodiments, the diode in the second source follower may include one or more diodes. In some embodiments, the one or more diodes may be replaced with one or more resistors.

[0015] In a further aspect, the circuit includes an input terminal for receiving an RF input signal, an output terminal for outputting an RF output signal, and means for amplifying the RF input signal to generate the RF output signal. [Brief explanation of the drawings]

[0016] The foregoing features of the present disclosure, as well as the disclosure itself, can be more fully understood from the following description of the drawings.

[0017] [Figure 1] FIG. 1 is a circuit diagram of a prior art amplifier. [Figure 2] FIG. 1 is a circuit diagram of a prior art current mirror configuration. [Figure 3] FIG. 1 is a circuit diagram of a prior art amplifier and current mirror configuration. [Figure 4] FIG. 2 is a circuit diagram of an amplifier and bias circuit according to an exemplary embodiment of the present disclosure. [Figure 5] FIG. 1 is a circuit diagram of a prior art amplifier bias circuit. [Figure 6] FIG. 1 is a circuit diagram of a prior art amplifier bias circuit. DETAILED DESCRIPTION OF THE INVENTION

[0018] 4 illustrates an example of an amplifier 400 having an input 402 and an output 404. Exemplary embodiments of the present disclosure may be suitable for RF amplifier applications. The amplifier 400 includes a first transistor 406 and a second transistor 408, which may be configured in a cascode / stack arrangement series-coupled from a voltage source Vdd1 to ground.

[0019] In an embodiment, the first transistor 406 is biased by a first bias signal Vg1 410, and the second transistor 408 is biased by a second bias signal Vg2 412. In the illustrated embodiment, first and second current mirrors are used to provide bias signals to the first transistor 406 and the second transistor 408.

[0020] The first mirror transistor 420 is coupled to the first transistor 406 of the amplifier, and the second mirror transistor 422 is coupled to the second transistor 408 of the amplifier. The first mirror transistor 420 and the second mirror transistor 422 provide first and second control loops for the bias circuit to set the quiescent bias of the amplifier, as described in more detail below. The first mirror transistor 420 and a first fixed current reference 423 in the first control loop 425 establish a quiescent condition for the first (common-source FET) transistor 406 of the amplifier. The voltage output of the first mirror transistor 420 is sent to a reference transistor 424 for establishing the source potential of the common gate reference for the second mirror transistor 422. In embodiments, the second mirror transistor 422 (a common-gate reference FET in the second mirror circuit) has a drain current from a second fixed current reference 426. The output of the second current mirror 422 may flow to the second transistor 408 (a top or common-gate FET in a cascode / stacked FET network).

[0021] FIG. 5 shows a prior art circuit 500 of a depletion-mode cascode amplifier. Typically, the quiescent state is set by applying voltages Vg1 and Vg2 directly from a DC power supply to stacked FETs Q1 and Q2. FIG. 6 shows a prior art circuit with separate voltage divider circuits to derive Vg2 and Vg1. In these prior art configurations, Vgs2 and Vg1 must be adjusted for each circuit due to inherent process variations.

[0022] In contrast, embodiments of the present disclosure have follower networks with reference feedback, resulting in a low input impedance for the bias circuit, maintaining the quiescent voltages of Vg1 and Vg2 as the RF amplifier transitions between small-signal and large-signal operation. If an application desires a higher input impedance, the diodes can be replaced with resistors.

[0023] The exemplary embodiment of FIG. 4 is described in more detail below. In the exemplary embodiment, the current mirrors 420, 422 are positive non-inverting current mirrors. The first mirror comprises a FET Q1 420, whose drain is supplied by a first reference current Iref 423. Note that the FET Q1 420 is placed in saturation, so that the current between its source (S) and drain (D) is approximately constant with respect to changes in the voltage between the source (S) and drain (D). The first transistor 406 of the amplifier has its gate electrode (G) connected to the gate electrode of the FET Q1 420 through a reference transistor 424, so that the current through the drain electrode of the transistor FET 406 can be adjusted by the value Iref 423. Note that both the FET 420 and the FET 406 are placed in saturation.

[0024] The drain electrode (D) of FET 420 is coupled to its gate electrode (G) through a follower network consisting of FET 427 and a network of one or more series-coupled diodes (here, e.g., diode Dn1) and another series element (here, transistor load 429). The source electrode of FET 420 is coupled to ground potential as shown. The gate electrode (G) of FET 420, together with the follower network, generates an output that is supplied to the gate electrode of the RF amplifier's depletion-mode FET 406. The gate electrode (G) of FET 406 is supplied with the input RF signal RFin. Note that because FET 406 is a depletion-mode FET, its gate electrode (G) is typically DC-biased at a potential more negative than ground.

[0025] In the illustrated embodiment, FET 420 has a drain electrode (D) coupled to first current reference 423 and to the gate electrode (G) of FET 427, as shown. The drain electrode (D) of FET 427 is also connected to Vdd2. As shown, the gate electrode (G) of FET 420 is connected to the source electrode (S) of FET 427 through diode Dn1. The source electrode (S) of FET 420 is connected to ground. As shown, the gate electrode (G) of FET 420 is also connected to the gate electrode (G) of amplifier FET 406 through RF blocking inductor L1 and to Vss1 through FET 429a, which is connected as a current source load resistor.

[0026] As shown, the gate electrode (G) of FET 406 is also coupled to the RF input signal RF in through a DC blocking capacitor C1. The source electrode (S) of FET 406 is connected to ground. The drain electrode (D) of FET 406 is coupled to the source (S) of amplifier FET 408 in a stacked arrangement. As shown, an RF blocking inductor L2 is coupled to the output RF out through a DC blocking capacitor C2. In the illustrated embodiment, the FET is a depletion-mode FET (D-FET).

[0027] The second mirror includes a FET 422 coupled to the gate (G) of FET 431 in a follower configuration with a series-coupled diode Dn2. As shown, the gate electrode (G) of FET 422 is also connected to the gate electrode (G) of amplifier FET 408 through RF blocking inductor L2 and to Vss2 through FET 429b, which is connected as a current source load resistor. The drain (D) of FET 422 is coupled to a second current source 426. The source (S) of FET 422 is connected to the drain (D) of FET 424. The source potential (S) of FET 424 is ground-referenced, and its gate potential is set by the first current mirror. The output of the second mirror provides a bias signal Vg2 412 to the second transistor 408 in the stacked FET amplifier. As previously described, the first and second current mirrors are cross-referenced via reference FET 424.

[0028] It is understood that Vss1 and Vss2 may be the same or different reference potentials. The reference potentials may be lower than ground, or one may be lower than ground and the other may be a positive potential, i.e., higher than ground. It is further understood that any practical number of diodes may be used, and that resistors may be used in place of or in combination with diodes in follower configurations. It is further understood that any practical number of transistors may be used in stacked amplifier embodiments with respective control loops.

[0029] While exemplary embodiments of the present disclosure have been described, it will be apparent to those skilled in the art that other embodiments incorporating these concepts may also be used. The embodiments contained herein should not be limited to the disclosed embodiments, but rather should be limited only by the spirit and scope of the appended claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety.

[0030] Elements of different embodiments described herein can be combined to form other embodiments not specifically described above. Various elements that are described in the context of a single embodiment may also be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.

Claims

1. an amplifier including first and second transistors coupled in a stacked configuration; a first current mirror having a first fixed current source, a first control loop, and a first mirror transistor coupled to the first transistor to provide a first bias current, the first control loop including a first follower transistor and at least one first diode connected in series between the drain and gate of the first mirror transistor; a second current mirror having a second fixed current source, a second control loop, and a second mirror transistor coupled to the second transistor to provide a second bias current, the second control loop including a second follower transistor and at least one second diode connected in series between the drain and gate of the second mirror transistor; a reference transistor connected between the source of the second mirror transistor and ground, the gate of the reference transistor being connected to the gate of the first mirror transistor; A circuit including:

2. 2. The circuit of claim 1, wherein the reference transistor is configured to establish a source potential for the second mirror transistor.

3. 3. The circuit of claim 2, wherein the second mirror transistor has a drain current from the second fixed current source.

4. 2. The circuit of claim 1, wherein the amplifier comprises a depletion mode FET amplifier.

5. The circuit of claim 1 , wherein the amplifier comprises an RF amplifier.

6. 1. A method of operating a circuit, the circuit comprising: an amplifier including first and second transistors coupled in a stacked configuration; a first current mirror having a first fixed current source, a first control loop, and a first mirror transistor coupled to the first transistor, the first control loop including a first follower transistor and at least one first diode connected in series between the drain and gate of the first mirror transistor; a second current mirror having a second fixed current source, a second control loop, and a second mirror transistor coupled to the second transistor, the second control loop including a second follower transistor and at least one second diode connected in series between the drain and gate of the second mirror transistor; a reference transistor connected between the source of the second mirror transistor and ground, the gate of the reference transistor being connected to the gate of the first mirror transistor; The method comprises: providing a first bias current to the first transistor via the first current mirror; providing a second bias current to the second transistor via the second current mirror; method.

7. 7. The method of claim 6, wherein the reference transistor is configured to establish a source potential for the second mirror transistor.

8. The method of claim 7 , wherein the second mirror transistor has a drain current from the second fixed current source.

9. 7. The method of claim 6, wherein the amplifier comprises a depletion mode FET amplifier.

10. The method of claim 6 , wherein the amplifier comprises an RF amplifier.

11. an input terminal configured to receive an RF input signal; an output terminal configured to output an RF output signal; an amplifier coupled to the input terminal and the output terminal, the amplifier including first and second transistors coupled in a stacked configuration; a first current mirror having a first fixed current source, a first control loop, and a first mirror transistor coupled to the first transistor to provide a first bias current, the first control loop including a first follower transistor and at least one first diode connected in series between the drain and gate of the first mirror transistor; a second current mirror having a second fixed current source, a second control loop, and a second mirror transistor coupled to the second transistor to provide a second bias current, the second control loop including a second follower transistor and at least one second diode connected in series between the drain and gate of the second mirror transistor; a reference transistor connected between the source of the second mirror transistor and ground, the gate of the reference transistor being connected to the gate of the first mirror transistor; A circuit including:

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