Processing device for handling misalignment data

Abstract

To handle data that may be misaligned in memory, a new type of instruction and a control register for the new type of instruction are provided. A first data portion (which may be misaligned in memory) is loaded into a first set of registers by loading a first atom that includes the first data portion into the registers. A pack instruction is executed by the execution unit to place a data portion (whose length and starting location are indicated by second and third values ​​in the control register) from one set of registers into an identified location (identified by a first value in the control register) in another set of registers.

Description

[Technical Field]

[0001] The present disclosure relates to data processing apparatus, and in particular to data processing apparatus including an execution unit configured to execute instructions to access data from a memory of the data processing apparatus. [Background technology]

[0002] A processing device may include an execution unit and a memory. The execution unit may execute one or more program threads to perform operations on data loaded from the memory and produce results, which are stored in the memory. The results may be subject to subsequent processing by the execution unit or may be dispatched from the processing device.

[0003] When accessing data in memory, there may be certain constraints on the access of that data in memory. Specifically, there may be architectural constraints that limit the memory addresses at which load and store operations can be performed. These memory addresses are determined by the size of the load and store operations provided as part of the instruction set for the processing unit.

[0004] Referring to FIG. 1, FIG. 1 illustrates a memory portion 100 into which data units can be loaded by an execution unit and into which data units can be stored by an execution unit. Assume that the execution unit is configured to execute load instructions for four-byte-wide data units. In this case, each load instruction can load any of four four-byte-wide data units from memory portion 100. For example, a load instruction can load four bytes of data starting at memory address 0x80000, or it can be used to load four bytes of data starting at memory address 0x80004. However, due to architectural constraints of the processing unit, it is not possible to load data starting at memory address 0x80002 because this memory address is not aligned with the size of the memory access. A similar constraint exists for stores. If each store instruction stores four bytes into memory portion 100, only four-byte-aligned stores can be executed due to the architectural constraints of the processing unit. Those memory addresses where a load or store operation is permitted due to the architectural constraints of the processing unit (e.g., memory addresses 0x80000, 0x80004, 0x80008, 0x80012, 0x80016) are referred to herein as aligned memory addresses. Data that has at least one of its boundaries (i.e., its starting address and ending address) not intersecting one of these aligned memory addresses is referred to as misaligned data. Summary of the Invention [Problem to be solved by the invention]

[0005] The restriction on the starting address of data for load and store operations presents a problem: it may sometimes be necessary to perform an operation on a portion of data that is not aligned in memory with the starting address for the load or store operation. For example, in the example of FIG. 1, it may be necessary to load a portion of data starting at memory address 0x80002 in memory portion 100. This portion of data may need to be loaded into a register to perform one or more specific arithmetic operations, or it may be copied to another portion of memory (again by performing a store). However, because of the constraint that only aligned memory addresses are allowed to be accessed, any load operation to load data starting at memory address 0x80002 would need to start at memory address 0x80000, thus requiring the loading of additional data that is not needed (for the arithmetic operation or memory copy). [Means for solving the problem]

[0006] One proposed solution is to reduce the size of the data accessed by the load and store instructions. For example, instead of using a load instruction that loads a four-byte data unit, a load instruction can be provided to perform a load of one-byte data units so that any byte of data can be individually accessed from memory portion 100. However, this embodiment may reduce performance, especially if the portion of data accessed from memory is large, as a large number of load instructions may need to be executed.

[0007] Another proposed solution is to arrange all data accessed from memory so that it is aligned in memory. In this way, whenever a portion of data is loaded from memory, the beginning of that portion of data is at an address that can serve as the starting address for the load operation. However, ensuring that data is aligned in memory requires leaving gaps in memory where no useful data is stored, because it is unlikely that all the data required for an operation will be a multiple of the load access size. Leaving gaps between useful data wastes memory space.

[0008] According to a first aspect, there is provided a data processing apparatus comprising: a memory configured to store a first data unit comprising a first portion and one or more additional portions; at least one execution unit configured to execute a load instruction to perform a load operation to load data from the memory; a second set of one or more registers configured to store a second data unit; and a control register configured to store control values ​​including a first value indicating a starting location within a third data unit where the first portion is to be provided, a second value indicating a starting location of the first portion within the first data unit, and a third value indicating a length of the first portion. The at least one execution unit is configured to execute at least one of the load instructions to perform a first load operation of the load operations to load a first data unit into a first set of one or more registers, and in response to execution of the first type of instruction, provide a third data unit in the set of one or more registers with a first portion located in one or more bit positions starting from a starting position indicated by the first value, and provide data from corresponding bit positions of the second data unit to remaining bit positions of the third data unit, depending on each of the control values.

[0009] To handle data that may be misaligned in memory, a new type of instruction, which may be called a pack instruction, and a control register for the new type of instruction, are provided. The pack instruction is executed by an execution unit to place a data portion (whose length and starting location are indicated by second and third values ​​in the control register) held in a set of registers at an identified location (identified by a first value in the control register) in another set of registers. For example, a first data portion may be misaligned in memory. This first data portion is loaded into a first set of registers by loading a first data unit (or first atom) containing the first data portion into those registers. The second set of registers contains a second data unit. Together, the first unit and the second unit provide data for a third unit of data that is desired to be provided aligned within its own set of registers (for performing arithmetic operations or storing back to memory in aligned form). When the pack instruction is executed, the execution unit provides a portion of the first data in the location identified by the first value to a third data unit, and provides the remaining bits with corresponding bits of the second data unit. The third data unit can then be manipulated or stored back into memory. Pack instructions can be used in conjunction with a second type of instruction called an extract instruction to perform a memory copy.

[0010] In some embodiments, the memory is configured to store a second data unit, and the at least one execution unit is configured to load the second data unit into a second set of one or more registers in response to at least one further execution of the load instruction prior to execution of the first type of instruction.

[0011] In some embodiments, the set of one or more registers in which the third data unit is stored is a third set of one or more registers that is different from the first and second set of one or more registers.

[0012] In some embodiments, the set of one or more registers in which the third data unit is stored is the second set of one or more registers.

[0013] In some embodiments, at least one execution unit is configured to execute a first type instruction to provide a third data unit in a second set of one or more registers such that the first portion overwrites a portion of the second data unit.

[0014] In some embodiments, at least one execution unit is configured to execute, prior to execution of the first type of instruction, an initialization instruction to provide a control value in a control register using one or more operands indicating a location of a buffer of data in memory, the buffer of data including the first portion.

[0015] In some embodiments, one or more operands of the initialization instruction further indicate the location of a memory area in memory to which the buffer of data should be copied.

[0016] In some embodiments, the memory is configured to store the second data unit in the memory region prior to execution of the first type of instruction.

[0017] In some embodiments, the first data unit belongs to a buffer of data.

[0018] In some embodiments, the data processing apparatus includes a further control register configured to store a single value indicating a starting location of the third data portion within the fourth data unit and an ending location of the fourth data portion within the fifth data unit, and the at least one execution unit is configured to execute a further instruction of the second type and to provide a sixth data unit in the set of one or more registers based on the single value, the sixth data unit including the third data portion beginning at the starting location indicated by the single value and the fourth data portion ending at the ending location indicated by the single value.

[0019] In some embodiments, at least one execution unit is configured to perform a memory copy of a buffer in a memory by executing a sequence of instructions, the memory being configured to store the buffer such that at least one of a beginning and an end of the buffer is misaligned with a set of memory addresses supported as starting addresses for load operations, the sequence of instructions including a first instance of an instruction of a first type, multiple instances of further instructions of a second type, and a second instance of the instruction of the first type.

[0020] In some embodiments, the at least one execution unit is configured to, prior to execution of the first instance of the first type of instructions, execute at least one initialization instruction to provide a single value in a further control register for use by at least one instance of the multiple instances of the second type of instructions using one or more operands indicating the location of the buffer in memory, and to provide a control value in the at least one register for use by the first and second instances of the further instructions of the first type.

[0021] In some embodiments, the memory is configured to store the first portion as part of the first data unit such that at least one of the beginning or end of the first portion is misaligned with a set of memory addresses supported for use as starting addresses for load operations.

[0022] In some embodiments, the sets of memory addresses in the memory are separated from each other by a fixed amount, where the fixed amount comprises one of 32 bits, 64 bits, or 128 bits.

[0023] According to a second aspect, there is provided a method implemented in a data processing apparatus including at least one execution unit supporting execution of a load instruction to perform a load operation to load data from a memory, the method comprising the steps of: storing in memory a first data unit including a first portion and one or more additional portions; storing a second data unit in a second set of one or more registers; storing a first value indicating a starting location within a third data unit where the first portion is to be provided; a second value indicating a starting location within the first data unit of the first portion; and a third value indicating a length of the first portion. , storing a control value including: in a control register; executing at least one of the load instructions to perform a first one of the load operations to load a first data unit into a first set of one or more registers; and in response to the execution of the first type of instruction, providing a first portion in one or more bit positions starting from a starting position indicated by the first value to a third data unit in the set of one or more registers in accordance with each of the control values; and providing data from corresponding bit positions of the second data unit to remaining bit positions of the third data unit.

[0024] In some embodiments, the method includes storing a second data unit in memory and loading the second data unit into a second set of one or more registers in response to at least one further execution of a load instruction prior to execution of the first type of instruction.

[0025] In some embodiments, the set of one or more registers in which the third data unit is stored is a third set of one or more registers that is different from the first and second set of one or more registers.

[0026] In some embodiments, the set of one or more registers in which the third data unit is stored is the second set of one or more registers.

[0027] In some embodiments, the method includes executing a first type of instruction to provide a third data unit in a second set of one or more registers such that the first portion overwrites a portion of the second data unit.

[0028] In some embodiments, the method includes, prior to execution of the first type of instruction, executing an initialization instruction to provide a control value in a control register using one or more operands indicating a location of a buffer of data in memory, the buffer of data including the first portion.

[0029] In some embodiments, one or more operands of the initialization instruction further indicate the location of a memory area in memory to which the buffer of data should be copied.

[0030] In some embodiments, the method includes storing a second data unit in the memory region prior to execution of the first type of instruction.

[0031] In some embodiments, the first data unit belongs to a buffer of data.

[0032] In some embodiments, the method includes storing a single value in a further control register indicating a starting location of a third data portion within the fourth data unit and an ending location of the fourth data portion within the fifth data unit, and executing a second type of further instruction to provide a sixth data unit in a set of one or more registers based on the single value, the sixth data unit including the third data portion beginning at the starting location indicated by the single value and the fourth data portion ending at the ending location indicated by the single value.

[0033] In some embodiments, the method includes storing a buffer of data in memory such that at least one of a beginning and an end of the buffer is misaligned with a set of memory addresses supported as starting addresses for load operations, and performing a memory copy of the buffer in memory by executing a sequence of instructions, the sequence of instructions including a first instance of an instruction of a first type, multiple instances of further instructions of a second type, and a second instance of the instruction of the first type.

[0034] In some embodiments, the method includes, prior to execution of the first instance of the first type of instructions, using one or more operands indicating the location of the buffer in memory to provide a single value in a further control register for use by at least one instance of the multiple instances of the second type of instructions, and executing at least one initialization instruction to provide a control value in the at least one register for use by the first and second instances of the further instructions of the first type.

[0035] In some embodiments, the method includes storing the first portion in memory as part of a first data unit such that at least one of a beginning or an end of the first portion is misaligned with a set of memory addresses supported for use as starting addresses for load operations.

[0036] In some embodiments, the sets of memory addresses in the memory are separated from each other by a fixed amount, where the fixed amount comprises one of 32 bits, 64 bits, or 128 bits.

[0037] According to a third aspect, there is provided a computer program comprising a set of computer readable instructions to cause at least one execution unit of a processing device to perform a method according to the second aspect or any embodiment, the computer readable instructions comprising a load instruction to perform a load operation to load data from a memory.

[0038] According to a fourth aspect, there is provided a non-transitory computer readable medium storing a computer program according to the third aspect.

[0039] For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings in which: FIG. [Brief explanation of the drawings]

[0040] [Figure 1] Illustrates the concept of aligned memory addresses. [Figure 2] 1 illustrates a processor in which an embodiment may be implemented. [Figure 3] 10 illustrates an example use of providing a data unit in response to execution of a pack instruction. [Figure 4] 10 illustrates an example use of providing a data unit in response to execution of an extraction command. [Figure 5A] 1 shows the state of the registers and memory after execution of the first initialization instruction. [Figure 5B] 10 illustrates updating the state of registers in response to execution of a load instruction, a first extract instruction, and a first pack instruction. [Figure 5C] 1 shows the update of the state of memory in response to the execution of a store instruction. [Figure 5D] 10 shows the state of the registers and memory after execution of the second initialization instruction. [Figure 5E] 10 illustrates the update of register and memory states in response to execution of a load instruction, a second extract instruction, and a store instruction. [Figure 5F] 10 illustrates the updating of register and memory states in response to execution of a load instruction and a third extract instruction and a store instruction. [Figure 5G] 10 illustrates updating of the state of registers in response to execution of a load instruction, a fourth extract instruction, and a second pack instruction. [Figure 5H] 1 shows the update of the state of memory in response to the execution of a store instruction. [Figure 6] 1 illustrates the use of a single pack instruction to align data being processed in memory. [Figure 7] 1 illustrates a method according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0041] The embodiments are implemented by a processing device that may take the form of a processor 4, which is described in more detail with respect to Figure 2. In some embodiments, the processor 4 may take the form of a tile 4 of a multi-tile processing unit. Examples of such multi-tile processing units are described in more detail in our prior application, U.S. Patent Application Publication No. 16 / 527,410, which is incorporated by reference.

[0042] Referring to FIG. 2, an example of a processor 4 is shown, including details of the execution units 18 and context registers 26. The illustrated processor 4 includes a weight register file 26W, making it particularly suited for machine learning applications in which machine learning models are trained by adjusting their weights. However, embodiments of the present application are not limited to machine learning applications and are more broadly applicable. Furthermore, the illustrated processor 4 is a multi-threaded processor capable of simultaneously executing M threads. The processor 4 can support the execution of M worker threads and one supervisor thread, where the worker threads perform arithmetic operations on data and generate results, and the supervisor thread coordinates the worker threads and controls the synchronization, send, and receive functions of the processor 4.

[0043] The processor 4 includes an individual instruction buffer 53 for each of the M threads that can be simultaneously executed. The context registers 26 include an individual main register file (MRF) 26M for each of the M worker contexts and the supervisor context. The context registers further include an individual auxiliary register file (ARF) 26A for at least each of the worker contexts. The context registers 26 also include a common weight register file (WRF) 26W that can be accessed and read by all currently executing worker threads. The WRF may be associated with the supervisor context in that the supervisor thread is the only thread that can write to the WRF. The context registers 26 may also include respective groups of control status registers 26CSR for each of the supervisor context and the worker context. The execution units 18 include a main execution unit 18M and an auxiliary execution unit 18A. The main execution unit 18M includes a load store unit (LSU) 55 and an integer arithmetic logic unit (IALU) 56. The auxiliary execution unit 18A includes at least a floating point unit (FPU).

[0044] In each of the J interleaved time slots S0...SJ-1, scheduler 24 controls fetch stage 14 to fetch at least one instruction of a respective thread from instruction memory 11 to one of J instruction buffers 53 corresponding to the current time slot. In the embodiment, each time slot is one execution cycle of the processor, although other schemes are not excluded (e.g., weighted round robin). In each execution cycle of processor 4 (i.e., each cycle of the processor clock that clocks the program counter), fetch stage 14 fetches a single instruction or a small "instruction bundle" (e.g., a two-instruction bundle or a four-instruction bundle), depending on the implementation. Each instruction is then issued by decode stage 16 to LSU 55 or IALU 56 of main execution unit 18M or one of FPUs of auxiliary execution unit 18A, depending on whether the instruction is a memory access instruction, an integer arithmetic instruction, or a floating-point arithmetic instruction (according to its opcode). The LSU 55 and IALU 56 of main execution unit 18M execute their instructions using registers from MRF 26M, with particular registers within MRF 26M being specified by the operands of the instruction. The FPU of auxiliary execution unit 18A executes operations using registers within ARF 26A and WRF 26W, with particular registers within the ARF being specified by the operands of the instruction. In embodiments, the registers within the WRF may be implicit in the instruction type (i.e., predetermined for that instruction type). The auxiliary execution unit 18A may also include circuitry in the form of logic latches within the auxiliary execution unit 18A for holding some internal state 57 for use in executing one or more types of operations of floating-point arithmetic instructions.

[0045] In embodiments where instructions are fetched and executed in bundles, the individual instructions in a given instruction bundle are executed simultaneously in parallel down independent pipelines 18M, 18A (shown in FIG. 2). In embodiments where two instruction bundles are executed, the two instructions may be executed simultaneously down their respective auxiliary and main pipelines. In this case, the main pipeline is configured to execute instructions of a type that uses the MRF, and the auxiliary pipeline is used to execute instructions of a type that uses the ARF. The pairing of instructions into appropriate complementary bundles may be handled by the compiler.

[0046] Each worker thread context has its own instance of a main register file (MRF) 26M and an auxiliary register file (ARF) 26A (i.e., one MRF and one ARF for each barrel thread slot). It should be understood that functionality described herein with respect to the MRF or ARF operates on a per-context basis. However, there is a single shared weight register file (WRF) shared among threads. Each thread can only access the MRF and ARF of its own context 26. However, all currently executing worker threads can access a common WRF. The WRF therefore provides a common set of weights for use by all worker threads. In an embodiment, only the supervisor can write to the WRF; workers can only read from the WRF.

[0047] The instruction set of processor 4 includes at least one type of load instruction, the opcode of which, when executed, causes LSU 55 to load data from data memory 22 into the respective ARF 26A of the thread in which the load instruction was executed. The destination location within the ARF is specified by an operand of the load instruction. Another operand of the load instruction specifies an address register within the respective MRF 26M that holds a pointer to the address in data memory 22 from which the data is to be loaded. The instruction set of processor 4 also includes at least one type of store instruction, the opcode of which, when executed, causes LSU 55 to store data from the respective ARF of the thread in which the store instruction was executed to data memory 22. The source location within the ARF is specified by an operand of the store instruction. Another operand of the store instruction specifies an address register within the MRF that holds a pointer to the address in data memory 22 to which the data is to be stored. In general, the instruction set may include separate load and store instruction types and / or at least one load-store instruction type that combines load and store operations into a single instruction.

[0048] In response to the opcode of the associated type of arithmetic instruction, an arithmetic unit (e.g., an FPU) within auxiliary execution unit 18A performs the arithmetic operation, as specified by the opcode, including manipulating values ​​in specified source registers in the thread's respective ARF and, optionally, source registers in the WRF. The arithmetic unit further outputs the result of the arithmetic operation to a destination register in the thread's respective ARF, as explicitly specified by the destination operand of the arithmetic instruction.

[0049] It will be understood that the labels “primary” and “auxiliary” are not necessarily limiting. In embodiments, they may be any first register file (per worker context), second register file (per worker context), and shared third register file (e.g., part of the supervisor context but accessible to all workers). The ARF 26A and auxiliary execution unit 18 may also be referred to as the arithmetic register file and arithmetic execution unit, since they are used for arithmetic instructions (or at least floating-point operations). The MRF 26M and auxiliary execution unit 18 may also be referred to as the memory address register file and arithmetic execution unit, since one of their uses is accessing memory. The weight register file (WRF) 26W is so named because it is used to hold multiplicative weights used for certain types of arithmetic instructions, which will be discussed in more detail shortly. For example, they may be used to represent the weights of nodes in a neural network. Viewed another way, the MRF can be referred to as an integer register file because it is used to hold integer operands, while the ARF can be referred to as a floating-point register file because it is used to hold floating-point operands. In embodiments that execute instructions in two bundles, the MRF is the register file used by the main pipeline and the ARF is the register file used by the auxiliary pipeline.

[0050] Note, however, that in alternative embodiments, register space 26 is not necessarily divided into these separate register files for these different purposes. Instead, instructions executed by the main and auxiliary execution units may be able to specify registers from the same shared register file (one register file per context in the case of a multi-threaded processor). Furthermore, pipeline 13 need not necessarily include parallel constituent pipelines (e.g., auxiliary and main pipelines) for simultaneously executing bundles of instructions.

[0051] The processor 4 may also include an exchange interface 51 for exchanging data between the memory 11 and one or more other resources, such as other instances of the processor and / or external devices, such as a network interface or network-attached storage (NAS) device. As described above, in an embodiment, the processor 4 may form one of an array 6 of interconnected processor tiles, with each tile executing a portion of a broader program. Thus, individual processors 4 (tiles) form part of the broader processor or processing system 6. The tiles 4 may be connected together by an interconnection subsystem 34, to which the tiles 4 connect via their respective exchange interfaces 51. The tiles 4 may be implemented on the same chip (i.e., die), on different chips, or a combination thereof (i.e., an array may be formed from multiple chips each containing multiple tiles 4). Thus, the interconnection system 34 and exchange interface 51 may include an internal (on-chip) interconnection mechanism and / or an external (inter-chip) exchange mechanism accordingly.

[0052] As previously mentioned, LSU 55 can execute load and store instructions to load and store data units to and from tiled memory 11. These operations are subject to the architectural constraint that load and store instruction operations can only be performed on aligned memory addresses. These aligned memory addresses may be 32 bits, 64 bits, 128 bits, or multiples of another number of bits depending on the instruction set architecture. As a result, some of the data loaded from memory 11 may be misaligned, where misalignment means that at least one of the data boundaries (start and / or end) is not located on an aligned memory address. As a result, any load operation to load data necessarily involves loading additional data from memory 11.

[0053] According to an embodiment of the present application, processor 4 can execute load instructions to load data from memory into registers of processor 4 (e.g., registers belonging to ARF 26A). Specifically, a first load instruction is executed to load a first data unit into a first set of one or more registers, and a second load instruction is executed to load a second data unit into a second set of one or more registers. Processor 4 then executes a pack instruction to form a third data unit in the register. The third data unit includes a first portion from the first data unit and data from a corresponding bit position in the second data unit. The first data portion is provided in a location within the third data unit indicated by a control value of the pack instruction, allowing the data to be aligned as needed. This can be used in conjunction with an extract instruction for memory copies, copying a buffer of data spanning a range of memory addresses that cannot be accessed using a single load instruction, or can be used to align a portion of a data unit to the beginning of a set of registers for arithmetic operations.

[0054] Each of the data units discussed herein (i.e., the first data unit, the second data unit, and the third data unit) may also be referred to as an atom. Each atom / data unit represents the amount of data loaded in a single load operation or stored in a single store operation. In the described embodiment, the size of each such atom is 128 bits. Each such load and store operation is performed in response to a load instruction or a store instruction. A load instruction used to execute a load instruction as described may be a double load instruction, in which two load operations are performed in response to executing the same double load instruction. Similarly, a store instruction used to execute a store instruction as described may be a double store instruction, in which two store operations are performed in response to executing the same double store instruction.

[0055] A second type of instruction is also described herein that can be used in combination with the pack instructions. The pack instructions operate to provide a third data unit that is identical to the second data unit except for a certain number of bit positions within the third data unit into which a portion of the first data unit is inserted. On the other hand, a second type of instruction, called "extract instructions," operates to provide a resultant data unit that is composed of data extracted from input data units up to a specified pivot point, from which point the resultant data unit is composed of data extracted from further input data units. As described below, when performing a memory copy of a buffer of data from one memory location to another, both pack instructions and extract instructions are executed as part of the memory copy process.

[0056] In the following description, reference is made to instructions and operations performed by execution units, although different instructions need not be executed by the same execution unit. In an embodiment, load and store instructions are executed by LSU 55, while pack and extract instructions are executed by execution units in auxiliary pipeline 18A. References below to operations performed by an execution unit should be interpreted as referring to operations performed by one or more execution units, or at least one execution unit, of a processor, e.g., processor 4, unless described as being performed by a particular execution unit.

[0057]

[0031] Reference is made to Figure 3, which illustrates an example of the operation of a pack instruction. Figure 3 illustrates a first data unit 300 stored in memory and a second data unit 310 also stored in a different location in memory. In this example, the first data unit 300 is stored in a portion of memory beginning at memory location 0x82000, while the second data unit 310 is stored in a portion of memory beginning at memory location 0x80000.

[0058] Processor 4 executes load instructions to load data units into registers. Each of these load instructions is executed by LSU 55. A first one of the load instructions is executed to load a first data unit 300 into a first set of registers (shown as $a4:7). A second one of the load instructions is executed to load a second data unit 310 into a second set of registers (shown as $a0:3).

[0059] Once both data units are loaded into the registers, a pack instruction is executed by processor 4 to provide the third data unit into another set of registers (shown as $a8:11). The pack instruction is executed by an execution unit in the processor's auxiliary pipeline 18A. The pack instruction takes several operands that identify registers. Specifically, the first operand identifies the destination register ($a8:11 in this example) into which the third data unit will be stored. The second operand identifies the source register ($a0:3 in this example) into which the second data unit will be stored. The third operand identifies the source register ($a4:7 in this example) into which the first data unit will be stored.

[0060] In addition to the operands, the pack instruction utilizes several values ​​held in a control register referred to herein as the $PACK register. These values ​​indicate (among other things) the starting location of a first data portion belonging to a first data unit to be included in the third data unit and the ending location of a second data portion belonging to a second data unit to be included in the third data unit. The value in the $PACK register includes a first value that specifies the starting location in the destination register to which the first data portion is to be written. This first value is shown in FIG. 3 as "INSERT_BYTE" and takes a value of 9 in the example of FIG. 3. The value in the $PACK register includes a second value that specifies the starting location of the first data portion in the source register that contains the first data unit. This second value is shown in FIG. 3 as "EXTRACT_BYTE" and takes a value of 2 in the example of FIG. 3. The value in the $PACK register includes a third value that specifies the size (i.e., number of bytes) of the first data portion. This third value is shown in FIG. 3 as "NUM_BYTES" and takes a value of 3 in the example of FIG. 3.

[0061] When the pack instruction is executed by an execution unit of processor 4 using the value from the $PACK register, it causes the second data unit to be copied into a destination register and overwrites a portion of the second data unit in the destination register with the first data portion from the first data unit. The result is shown in Figure 3. Shown in the destination register is a second data portion 320 taken from the second data unit and a first data portion 330 taken from the first data unit. In this example, the destination register also includes a further data portion 340 taken from the second data unit.

[0062] It will be appreciated that pack instructions can be used to move data portions to new locations within an atom of data. This can be useful when a first data portion 330 and a second data portion 320 need to be processed together. For example, a particular set of arithmetic operations can operate on these two portions of data 320, 330. Given that load and store instructions are limited to a minimum size, it may not be possible to align these portions of data 320, 330 together in the destination register (e.g., if the boundaries where the first and second data portions end are not aligned in memory with boundaries on which the load operation can be performed).

[0063] Once the third data unit is provided in the destination register, it may be immediately manipulated by an arithmetic operation or may be stored back in memory 11 before undergoing any processing.

[0064] 3, the pack instruction is shown as pack128, which is a version of the pack instruction in which the first and second data units operated on and the resulting third data unit are each 128 bits long. However, different versions of the pack instruction may be provided that operate on data units of different sizes. Specifically, in an embodiment, a version of the pack instruction that operates on data units that are each 32 bits long (referred to as pack32) and a version of the pack instruction that operates on data units that are each 64 bits long (referred to as pack64) are provided as part of the instruction set of processor 4.

[0065] Reference is made to FIG. 4, which illustrates an example of the operation of an extract instruction. FIG. 4 illustrates a first data unit 400 stored in memory and a second data unit 410, also stored in a different location within memory. In this example, the first data unit 400 is stored at memory location 0x80000, while the second data unit 410 is stored at memory location 0x80010. As shown, in this case, the first data unit 400 and the second data unit 410 are stored contiguously in memory. The extract instruction is useful for extracting and combining data portions when the data portions do not align with data unit boundaries that can be accessed by load and store instructions. As shown, the first data unit 400 includes a first data portion 420, while the second data unit 410 includes a second data portion 430.

[0066] Before executing the extract instruction, LSU 55 performs two load operations, the first of which loads a first data unit 400 into a first set of registers (shown as $a4:7) and the second of which loads a second data unit 410 into a second set of registers (shown as $a0:3).

[0067] Once both data units are loaded into the registers, an extract instruction is executed by processor 4 to provide the third data unit into another set of registers (shown as $a8:11). The extract instruction is executed by an execution unit in the processor's auxiliary pipeline 18A. The extract instruction takes several operands that identify registers. Specifically, the first operand identifies the destination register ($a8:11 in this example) into which the third data unit will be stored. The second operand identifies the source register ($a0:3 in this example) into which the second data unit will be stored. The third operand identifies the source register ($a4:7 in this example) into which the first data unit 400 will be stored.

[0068] In addition to operands, the extract instruction utilizes a value in a control register, referred to herein as the $EXTRACT register. The value in the $EXTRACT register specifies both the starting location of the first data portion 420 within the first data unit 400 and the ending location of the second data portion 430 within the second data unit 410. Because the third data unit resulting from execution of the extract instruction will consist entirely of the first data portion 420 and the second data portion 430, the same value (referred to herein as the "pivot point") can be used to specify both their starting and ending locations. In Figure 4, this value is shown as "PIVOT_POINT" and takes a value of 11, thereby specifying that the associated starting and ending locations are at the beginning of byte 11, respectively, of the extract instruction's set of source registers.

[0069] When the extract instruction is executed by the execution unit of processor 4, the execution unit uses the value in the $EXTRACT register to copy the first data portion 420 from the source register containing the first data unit 400 to a portion of the destination register. Additionally, in response to executing the extract instruction, the second data portion 430 is copied from the source register containing the second data unit 410 to a portion of the destination register. As shown, the execution unit of processor 4 stores the second data portion 430 in the second portion of the destination register. Additionally, the execution unit of processor 4 stores the first data portion 420 in the first portion of the destination register, and the second portion of the destination register follows the first portion of the destination register. In this manner, the positions of the portions 420, 430 within the set of destination registers are reversed with respect to their positions within the set of source registers. The first data portion 420 is stored at the end (i.e., the least significant bits) of the set of source registers containing the first data unit 400, while it is stored at the beginning (i.e., the most significant bits) of the set of destination registers. The second data portion 430 is stored at the beginning (ie, most significant bits) of the source register containing the second data unit 410, while it is stored at the end (ie, least significant bits) of the set of destination registers.

[0070] Once the third data unit is provided in the destination register, it may be immediately manipulated by an arithmetic operation or may be stored back in memory 11 before undergoing any processing.

[0071] 4, the extract instruction is shown as extract128, which is a version of the extract instruction in which the first and second data units operated on and the resulting third data unit are each 128 bits long, although different versions of the extract instruction may be provided that operate on data units of different sizes.

[0072] 3 and 4 provide examples where all three sets of registers specified by the associated instructions (i.e., the two source register sets and the destination register set) are different. However, in some examples, one of the source register sets may be the same as the destination register set, and the effect of executing the instruction is to overwrite some of the data in the source register set. Such an example is shown in FIG. 6 for a pack instruction.

[0073] If the buffer contains several atoms of data, the extract instruction can be particularly useful when used to perform a memory copy of the buffer from one part of memory to another part of memory (where the buffer is not aligned with a memory access boundary).

[0074] 5A-5H, an example of a memory copy to a misaligned data buffer utilizing both pack and extract instructions will now be described. To perform this memory copy, it will be shown how initialization instructions may be pre-executed by the execution units of processor 4 using certain parameters related to the copy before executing the pack and extract instructions to rearrange the loaded data in the registers.

[0075] 5A, there is shown a memory portion 11 (which may be referred to as a source memory) from which a buffer 500 of data is to be copied. The buffer 500 is to be copied to another memory portion 11 (referred to herein as a destination memory). Although the source memory and destination memory are each referred to as a "memory," they may form part of the same memory unit or memory bank.

[0076] Buffer 500 is copied to memory area 510 in destination memory that is the same size as buffer 500. It can be seen that because load and store operations are limited to accessing data of a minimum size (which may be 128 bits or 64 bits, for example), the boundaries of both buffer 500 and memory area 510 are not aligned with memory access boundaries. As a result, two of the load operations performed to load the data of buffer 500 will also load some data (that is not desired to be copied to memory area 510). Furthermore, two of the store operations performed to store the data of buffer 500 to memory area 510 will also store some data (other than the data of buffer 500) to memory area 510. Pack and extract instructions can be used together to address this situation by loading some data from the destination memory and combining this with the data of buffer 500 to form the appropriate data to be stored in the destination memory; the end result is that the only new data stored in the destination memory is the data from buffer 500.

[0077] Prior to the execution of the pack and extract instructions, a first initialization instruction (called init128headtail) is executed. This init128headtail instruction populates registers used to provide the first and last atoms of data to be stored in the destination memory. The first atom may be called the "head" atom, while the last atom may be called the "tail" atom. These registers include the $PACK register, which is populated with control values ​​used when executing the first pack instruction. This register also includes the $EXTRACT register, which is populated with control values ​​used when executing the first extract instruction. This register also includes a register (denoted as $m5) that contains control values ​​used when executing the second (and last) pack instruction. This register also includes a register (denoted as $m4) from which the address (denoted as the head address) for the first load operation to load data from the source memory is taken.

[0078] The init128headtail instruction has several operands that are used to provide control register values. The first of these is the starting address of buffer 500. In the example of Figure 5A, this is equal to 0x80002 and is located in register $m0. The second of the operands is the starting address of memory region 510. In the example of Figure 5A, this is equal to 0x82004 and is located in register $m1. The third of the operands is the size of buffer 500. In the example of Figure 5A, this is equal to 48 bytes and is located in register $m2.

[0079] In response to executing the init128headtail instruction, the execution unit determines the pivot value for the $EXTRACT register by determining how many bytes the source address (i.e., 0x80002 in this example) is offset from the preceding aligned memory address (0x80000 in this example), which is the starting address from which the first load operation is performed to load the first portion of buffer 500. In this example, the pivot value determined by the extract instruction and stored in the $EXTRACT register is equal to 2 bytes.

[0080] Additionally, in response to executing the init128headtail instruction, the execution unit determines a first control value (i.e., a padding byte) to store in the $PACK register. The execution unit determines the first control value (i.e., a padding byte) by determining how many bytes the source destination (i.e., 0x82004 in this example) is offset from the preceding aligned memory address (i.e., 0x82000 in this example). This preceding aligned memory address is the starting address at which a first store operation is performed to store a data unit comprising a portion of buffer 500 into the destination memory. In this example, the padding byte value determined by the extract instruction and stored in the $PACK register is equal to 4 bytes.

[0081] In response to executing the init128headtail instruction, the execution unit sets a second control value (i.e., extract byte) equal to zero. This value is set to zero for the memory copy of the buffer because the data to be inserted begins at the beginning of the set of registers containing only data from buffer 500. As will be described below, data is provided in this set of registers by execution of the first extract instruction.

[0082] In response to executing the init128headtail instruction, the execution unit sets a third control value (i.e., num bytes) equal to the amount of data in buffer 500 to be stored in destination memory in the first store operation. This is visually represented as being the portion of memory region 510 that falls within the first atom of destination memory (i.e., addresses 0x82000-0x82010). Thus, in the example of Figures 5A-5H, the third control value is the number of bytes between the value of the destination address specified by $m1, i.e., 0x82004, and the next aligned memory address in destination memory, i.e., 0x82010. The third control value in the example of Figures 5A-5F is equal to 12 bytes.

[0083] As mentioned above, the execution unit determines the pack control values ​​for the second (and final) pack instruction in response to executing the init128headtail instruction. These are shown in Figure 5A as labeled tail$PACK and are referred to below as the second pack control values.

[0084] In response to executing the init128headtail instruction, the execution unit determines the first control value (i.e., insert bytes) of the second packed control value. The execution unit determines this first control value by determining the number of bytes of memory region 510 that exist within the last data unit to be stored in destination memory. These byte numbers are the number of bytes of buffer 500 that will be stored within this last data unit in destination memory. In the example of FIG. 5A, the last atom of data begins at address 0x82030. The end of memory region 510 (which the execution unit can determine by adding the number of bytes from $m2 (i.e., 48) to the starting address of memory region 510 from $m1 (i.e., 0x82004)) is at 0x82034. By subtracting the end of memory region from the aligned memory address preceding that address (i.e., 0x82030), the execution unit can determine the number of bytes (i.e., 4) that represent the first control value of the second packed control value.

[0085] In response to executing the init128headtail instruction, the execution unit determines a second control value (i.e., bytes to extract) for the second packed control value. The execution unit sets this value to the same value as the value of the first control value (i.e., 4 bytes in the given example).

[0086] In response to executing the init128headtail instruction, the execution unit determines the third control value (i.e., num bytes) of the second pack control value. The execution unit sets this value equal to the size of the data unit to be loaded in each load operation (i.e., 16 bytes in this example) minus the values ​​of the first and second control values ​​of the second pack control value (i.e., 4 bytes in this example). This represents the amount of data loaded from the destination memory that will be written back to the destination memory in the final store operation (i.e., the store operation starting at memory address 0x82030). This value is equal to 12 bytes in this example.

[0087] 5B, which illustrates the operations that occur after execution of the init128headtail instruction. The execution unit executes a first load instruction (shown as ld128pace) to load a data unit 515 from a source memory into a set of registers. The execution unit executes a second load instruction (shown as ld128step) to load a data unit 516 from a source memory into a further set of registers. The execution unit executes a third load instruction (shown as ld128) to load a data unit 517 from a destination memory into another set of registers.

[0088] Having loaded the data, the execution unit executes an extract instruction (shown in FIG. 5B as extract128). This instance of the extract instruction is executed with a first operand specifying a first set of source registers into which data unit 516 is being loaded and a second source operand specifying a set of registers into which data unit 515 is being loaded. Because the pivot point specified in the $EXTRACT register takes a value of 2, the execution unit stores the first two bytes of data unit 516 into a set of destination registers and stores the bytes of data unit 515 after the first two bytes of unit 515 into the same set of destination registers. In other words, in response to the extract instruction, the execution unit uses the pivot point to retrieve the n-2 most significant bytes of unit 515 and combines them with the least significant two bytes of unit 516 to provide the full n bytes of unit 518. The data unit 518 resulting from the execution of this extract instruction is shown in FIG. 5B. As shown, data unit 518 consists of the data from first unit 515, except for the last two bytes of data unit 518, which are the first two bytes of second unit 516. This resulting data unit 518 is the first complete data unit in buffer 500.

[0089] After obtaining data unit 518, the execution unit executes a pack instruction (shown as pack128 in FIG. 5B). The pack instruction takes a first operand that specifies the register containing data unit 518 as the source register set and a second operand that specifies the register containing data unit 517 as the source register set. The result of executing this pack instruction is that data unit 517 is copied into the destination register set for the pack instruction, with some of its data being overwritten with data from data unit 518. Given an extract value of zero in the $PACK register, the execution unit causes the data to be written to the destination register set starting at the beginning of data unit 518. Given an insert value of 0x04 in the $PACK register, the execution unit causes the extracted data to be written into the destination register set starting at an offset of 4 bytes from the beginning of the destination register set. Given a number of bytes value of 12 (0x0c hexadecimal), the execution unit causes the 12 bytes of data unit 518 to be written to the destination register set. The resulting data unit 519 held in the set of destination registers is shown in Figure 5B. This data unit 519 resulting from execution of the first pack instruction constitutes the first data unit 519 stored in the destination memory.

[0090] Referring to Figure 5C, there is shown how data unit 519 may be stored back to memory. Specifically, an execution unit executes a store instruction (shown as st128) to store data unit 519 in a destination memory. The store instruction takes an operand that specifies the aligned memory address (i.e., 0x82000) of the first atom of data to be stored in the destination memory as part of the memory copy. As shown, the load operation stores data unit 519 starting at a memory address of 0x82000.

[0091] 5D, there is shown how a second initialization instruction (called init128body) can be executed to load values ​​into registers for processing operations to generate data units located between the two end data units in the destination memory. These data units between the two end data units can be referred to as the body portion of buffer 500.

[0092] The init128body instruction causes the value held in the $EXTRACT control register to be modified. This value is modified to enable the extract operation to be used to generate the data units that, when stored in memory region 510, form the body portion of buffer 500. In response to executing the init128body instruction, the execution unit determines a new pivot value by subtracting the previous value held in the $EXTRACT control register (as determined by executing init128headtail) (i.e., 2 bytes in this example) from the number of bytes in each data unit (i.e., 16 bytes in this example). The resulting value in this example (i.e., 14 bytes) is stored in the $EXTRACT control register in place of the previous pivot value used for the first extract instruction.

[0093] In response to executing the init128body instruction, the execution unit determines the number of atoms of data that belong to the body portion of buffer 500. This number is equal to the number of store operations that need to be performed to store the body portion of buffer 500 to the destination memory. The body portion of buffer 500 consists of the data of buffer 500 stored in the destination memory other than the data of buffer 500 stored in the first atom (i.e., atom 519) or the data of buffer 500 stored in the destination memory in the last atom (i.e., the atom starting at memory address 0x80030). In the example of Figures 5A-5H, the body portion of buffer 500 is located between memory addresses 0x82010 and 0x82030 and consists of two atoms of data.

[0094] In response to executing the init128body instruction, the execution unit determines the memory address for the first load operation to be performed on the source memory to determine the body of buffer 500. This memory address (i.e., 0x80000 in this example) is shown in this example as being stored in $m0. In addition, the execution unit determines the memory address of the first store operation to the destination memory (following the store operation of data unit 519) for the body of buffer 500. This memory address (i.e., 0x82010 in this example) is shown in this example as being held in $m1.

[0095] 5E, the operations performed by processor 4 after execution of the init128body instruction are shown. The execution unit executes a first load instruction (shown as ld128pace) to load data unit 515 from source memory and a second load instruction (also shown as ld128pace) to load data unit 516 from source memory. Because these same data units 515, 516 are loaded from source memory to provide head data unit 517, in some embodiments these data units 515, 516 are not loaded again after execution of init128body, but may be retained within the set of registers that were previously loaded to construct head data unit 517.

[0096] Once the data is loaded, the execution unit executes an extract instruction (shown in FIG. 5E as extract128). This instance of the extract instruction executes with a first operand that specifies the set of registers into which data unit 516 is loaded as a first set of source registers and a second operand that specifies the set of registers into which data unit 515 is loaded as a second set of source registers. Because the pivot point specified in the $EXTRACT register takes a value of 14, the execution unit provides data unit 520. Unit 520 contains the bytes of unit 515 after the first 14 bytes of data in data unit 515 (i.e., the last two units). Unit 520 also contains the first 14 bytes of data 516. The 14 bytes extracted from unit 516 follow the two bytes extracted from unit 515 in data unit 520. The execution unit provides data unit 520 in the set of destination registers identified by the operands of the extract instruction. The data units 520 stored in these destination registers form the first atoms of the body of the buffer 500 .

[0097] After providing data unit 520, the execution unit executes a store instruction to store data unit 520 in memory. Data unit 520 is stored at an aligned memory address that is the next aligned memory address from the address at which data unit 519 was stored.

[0098] Referring to FIG. 5F, it is shown how the second atom of data for the body of buffer 500 is generated.

[0099] The execution unit executes a load instruction to load data unit 525 into a set of registers. This data unit 525 is loaded from the next aligned memory address (i.e., 0x80020) after the aligned memory address (i.e., 0x80010) from which data unit 516 was loaded. This address is given by the value of the source address in register $m0, which is incremented after the load instruction is executed to load data unit 516 (i.e., to 0x80030).

[0100] After loading the data, the execution unit executes an extract instruction (shown in FIG. 5F as extract128). This instance of the extract instruction is executed with a first operand that specifies the set of registers into which data unit 525 is loaded as a first set of source registers and a second operand that specifies the set of registers into which data unit 516 is loaded as a second set of source registers. In response to this instance of the extract instruction, the execution unit provides data unit 526. Because the pivot value in the $EXTRACT register is 14, unit 526 includes the bytes of unit 516 after the first 14 bytes of data in data unit 516 (in other words, the last two bytes). Unit 526 also includes the first 14 bytes of unit 525. The 14 bytes extracted from unit 525 follow the two bytes extracted from unit 516 within data unit 526. The execution unit provides data unit 526 within the set of destination registers identified by the extract instruction's associated operand. The data units 526 stored in these destination registers form the second atom of the body of the buffer 500 .

[0101] After providing data unit 526, the execution unit executes a store instruction to store data unit 526 in memory. Data unit 526 is stored at an aligned memory address (i.e., 0x82020) that is the next aligned memory address from the address at which data unit 520 was stored. This next aligned address is given by the value held in the $m1 register. After executing the store operation, the value in this register is incremented to point to the next aligned memory address (i.e., 0x82030).

[0102] Referring to Figure 5G, an example of how a final atom (i.e., tail) for storage in a destination memory may be generated is shown. Providing this final atom involves executing a second pack instruction that uses a second set of pack control values. To make them available when the second pack instruction is executed, the execution unit copies these values ​​(from the $m5 register in this example) determined using the init128headtail instruction into the $PACK control register.

[0103] The execution unit executes a load instruction (shown as ld128) to load the final data unit 527 from source memory into a set of registers. In Figure 5G, only the first half 527a of this data unit 527 is shown in source memory. Execution loads this value from the source address value in $m0.

[0104] After loading data unit 529, the execution unit executes an extract instruction (shown in FIG. 5G as extract128). This instance of the extract instruction is executed with a first operand that specifies the set of registers into which data unit 527 is loaded as a first set of source registers and a second operand that specifies the set of registers into which data unit 525 is loaded as a second set of source registers. In response to this instance of the extract instruction, the execution unit provides data unit 528. Because the pivot value in the $EXTRACT register is 14, unit 528 includes the bytes of unit 525 after the first 14 bytes of data in data unit 525 (in other words, the last two bytes). Unit 528 also includes the first 14 bytes of unit 527. The 14 bytes extracted from unit 527 follow the two bytes extracted from unit 525. The execution unit provides data unit 528 into the set of destination registers identified by the extract instruction's associated operand.

[0105] The execution unit executes a further load instruction (ld128) to load a data unit 529 from the destination memory into the set of registers, of which only the first half 529a is shown in Figure 5G.

[0106] The execution unit executes a second pack instruction (shown as pack128 in FIG. 5G). This instance of the pack instruction takes one operand that specifies the registers containing data unit 528 as the source register set and another operand that specifies the registers containing data unit 529 as the source register set. The result of executing this pack instruction is that data unit 528 is copied into the destination register set for the pack instruction, and a portion of that data 528 is overwritten with data from data unit 529. Given an extract value of 4 in the $PACK register, the execution unit causes the data in data unit 529, starting with the fourth byte, to be written to the destination register set. Given an insert value of 0x04 in the $PACK register, the execution unit causes the extracted data to be written into the destination register set starting at an offset of 4 bytes from the beginning of the destination register set. Given a number of bytes value of 12 (0x0c hexadecimal), the execution unit causes the 12 bytes of data unit 529 to be written to the destination register set. The effect of the pack instruction is to overwrite the portion of the data in unit 528 that is not from buffer 500 being copied with data from the destination memory. The resulting data unit 530 held in the set of destination registers is shown in Figure 5B. This data unit 530 resulting from execution of the second pack instruction constitutes the final atom of data 530 that is stored in the destination memory as part of the memory copy.

[0107] Referring to Figure 5H, there is shown how an execution unit executes a store instruction to store data unit 530 into a destination memory. Executing the store instruction causes data unit 530 to be stored starting at the next aligned memory address (i.e., 0x82030) after the memory address at which data unit 526 was stored. Only the first half 530a of this data unit 530 is shown in Figure 5H.

[0108] Embodiments are not limited to using pack instructions to perform memory copies, for example, pack instructions may be used to place misaligned data from memory into the appropriate locations in one or more registers for processing.

[0109] Referring to Figure 6, an example of the use of pack instructions to place data at the beginning of one or more registers for processing is shown.

[0110] Assume that one or more arithmetic operations need to be performed using data 610 stored in memory. Because data 610 is unaligned in memory, a load instruction cannot be used to directly load data 610 into the appropriate location in one or more registers. Therefore, a load operation is performed to load a data unit containing data 610 into register set $a4:7. This data unit is shown in Figure 6 as starting at memory address 0x82000.

[0111] Once data 610 is stored in register set $a4:7, a pack instruction is executed to store data 610 at the beginning of another register set $a0:3. The remainder of register $a0:3 is occupied by the initial contents of that portion of register $a0:3. One or more arithmetic operations can then be performed on data 610, now aligned at the beginning of its associated one of registers $a0:3.

[0112] It will be understood that the embodiments are described by way of example only, and that the names used for the various instructions (e.g., pack, extract, init128headtail, init128body), registers (e.g., $PACK, $EXTRACT), and register values ​​(e.g., pivot point, insertbyte, extractbyte, numbyte) are names only and should not be construed as limiting.

[0113] 7, a method 700 according to an embodiment of the present application is shown for providing a third data unit in a set of registers using a first data set and a second data set.

[0114] At S710, a first data unit is stored in memory 11 of processing device 4. The first data unit includes a first portion and one or more additional portions. The first data unit may be stored in memory 11 by LSU 55 of processing device 4 or other circuitry of processing device 4 (e.g., a receiving engine) configured to store data received by processing device 4 in memory 11.

[0115] At S720, the second data unit is stored in a second set of registers of the processing unit 4. These registers may be registers of the ARF 26A. The second data unit may be stored in these registers by executing a load instruction to load the second data unit from memory.

[0116] In S730, the control value is stored in the $PACK control register.

[0117] At S740, at least one execution unit executes a load instruction to load a first data unit into a first set of one or more registers.

[0118] At S750, at least one execution unit executes a pack instruction to provide a third data unit based on the control values ​​provided in the set of one or more registers, the third data unit including a first portion in one or more bit positions starting from a starting position indicated by the first value and including data from corresponding bit positions of the second data unit in remaining bit positions of the third data unit.

[0119] It will be understood that the embodiments have been described by way of example only.

Claims

1. a memory configured to store a first data unit including a first portion and one or more additional portions; at least one execution unit configured to execute a load instruction to perform a load operation to load data from the memory; a second set of one or more registers configured to store a second data unit; a control register configured to store control values ​​including a first value indicating a starting location within a third data unit where the first portion is to be provided, a second value indicating a starting location of the first portion within the first data unit, and a third value indicating a length of the first portion; Equipped with The at least one execution unit executing at least one of the load instructions to perform a first one of the load operations to load the first data unit into a first set of one or more registers; in response to execution of a first type of instruction and in response to each of said control values: providing the third data unit in a set of one or more registers with the first portion at a plurality of bit positions starting from the starting position indicated by the first value, and providing data from corresponding bit positions of the second data unit for the remaining bit positions of the third data unit; 20. A data processing apparatus configured to:

2. 2. A data processing apparatus as claimed in claim 1, wherein the memory is configured to store the second data unit, and the at least one execution unit is configured to load the second data unit into a second set of one or more registers in response to execution of at least one further of the load instructions prior to execution of the instructions of the first type.

3. 3. The data processing apparatus according to claim 1, wherein the set of one or more registers in which the third data unit is stored is a third set of one or more registers different from the first and second sets of one or more registers.

4. 3. The data processing apparatus according to claim 1, wherein the set of one or more registers in which the third data unit is stored is a second set of one or more registers.

5. 5. A data processing apparatus as claimed in claim 4, wherein said at least one execution unit is configured to execute said instruction of said first type to provide said third data unit in said second set of one or more registers such that said first portion overwrites a portion of said second data unit.

6. 2. A data processing apparatus as claimed in claim 1, wherein said at least one execution unit is configured to execute, prior to execution of said instruction of said first type, an initialization instruction to provide said control value in said control register using one or more operands indicating the location of a buffer of data in said memory, said buffer of data including said first portion.

7. 7. A data processing apparatus as claimed in claim 6, wherein said one or more operands of said initialization instruction further indicate the location of a memory area within said memory into which said buffer of data should be copied.

8. 8. A data processing apparatus as claimed in claim 7, wherein said memory is configured to store said second data unit in said memory region prior to said execution of said instruction of said first type.

9. 9. A data processing apparatus as claimed in claim 7 or 8, wherein the first data unit belongs to a buffer of the data.

10. a further control register configured to store a single value indicating a starting location of the third data portion within the fourth data unit and an ending location of the fourth data portion within the fifth data unit; the at least one execution unit is configured to execute a further instruction of a second type and to provide a sixth data unit in a set of one or more registers based on the single value; 2. The data processing apparatus of claim 1, wherein the sixth data unit includes the third data portion beginning at the start position indicated by the single value and the fourth data portion ending at the end position indicated by the single value.

11. the at least one execution unit is configured to perform a memory copy of a buffer in the memory by executing a sequence of instructions; the memory is configured to store the buffer such that at least one of a beginning and an end of the buffer is misaligned with a set of memory addresses supported as starting addresses for the load operation; 11. A data processing apparatus as claimed in claim 10, wherein the sequence of instructions comprises a first instance of the instruction of the first type, a plurality of instances of the further instruction of the second type, and a second instance of the instruction of the first type.

12. 12. A data processing apparatus as claimed in claim 11, wherein said at least one execution unit is configured to, prior to execution of said first instance of said instruction of said first type, execute at least one initialization instruction to provide the single value in said further control register for use by at least one instance of said plurality of instances of said instructions of said second type using one or more operands indicating the location of said buffer in said memory, and to provide the control value in at least one register for use by said first and second instances of said further instructions of said first type.

13. 2. The data processing apparatus of claim 1, wherein the memory is configured to store the first portion as part of the first data unit such that at least one of a beginning or an end of the first portion is misaligned with a set of memory addresses supported for use as starting addresses for the load operation.

14. 14. A data processing apparatus as claimed in claim 13, wherein the sets of memory addresses in the memory are separated from each other by a fixed amount, the fixed amount comprising one of 32 bits, 64 bits or 128 bits.

15. 1. A method implemented in a data processing apparatus including at least one execution unit that supports execution of a load instruction to perform a load operation to load data from a memory, the method comprising: storing in the memory a first data unit including a first portion and one or more additional portions; storing a second data unit in a second set of one or more registers; storing control values ​​in a control register, the control values ​​including a first value indicating a starting location within a third data unit where the first portion is to be provided, a second value indicating a starting location of the first portion within the first data unit, and a third value indicating a length of the first portion; executing at least one of the load instructions to perform a first one of the load operations to load the first data unit into a first set of one or more registers; in response to execution of a first type of instruction and in response to each of said control values: providing the first portion at a plurality of bit positions beginning with the starting position indicated by the first value to the third data unit in a set of one or more registers; providing data from corresponding bit positions of the second data unit into remaining bit positions of the third data unit; A method comprising:

16. 1. A computer program product comprising a set of computer readable instructions for causing at least one execution unit of a processing unit to perform a method, the computer readable instructions including a load instruction for performing a load operation for loading data from a memory, the method comprising: storing a first data unit in the memory, the first data unit including a first portion and one or more additional portions; storing a second data unit in a second set of one or more registers; storing control values ​​in a control register, the control values ​​including a first value indicating a starting location within a third data unit where the first portion is to be provided, a second value indicating a starting location of the first portion within the first data unit, and a third value indicating a length of the first portion; performing a first one of the load operations in response to executing at least one of the load instructions to load the first data unit into a first set of one or more registers; in response to execution of a first type of instruction and in response to each of said control values: providing the first portion at a plurality of bit positions beginning with the starting position indicated by the first value to the third data unit in a set of one or more registers; providing data from corresponding bit positions of the second data unit into remaining bit positions of the third data unit; a computer program comprising:

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