Oscillator circuit

Abstract

To provide an oscillation circuit capable of reducing a consumption current during normal operation even if the circuit comprises a circuit through which a large current flows during operation.SOLUTION: An oscillation circuit comprises: a first constant current circuit connected to one terminal of a capacitor; a first switch circuit connected between the other terminal of the capacitor and a second power terminal; a second constant current circuit; a first MOS transistor in which a gate and a drain are connected to the second constant current circuit and a source is connected to the other terminal of the capacitor; a second MOS transistor in which the gate is connected to the gate of the first MOS transistor and the drain is connected to one terminal of the capacitor; a second switch circuit connected between the source of the second MOS transistor and a second power terminal; and an output terminal which outputs a signal based on a voltage of the one terminal of the capacitor. On and off of the first and second switch circuits are controlled by a signal of the output terminal and an inversion signal of the signal of the output terminal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an oscillator circuit. [Background technology]

[0002] An oscillator circuit is required to output a constant frequency without being affected by fluctuations in power supply voltage, temperature, and the like.

[0003] FIG. 4 is a circuit diagram showing a conventional oscillator circuit. The oscillation circuit 400 in FIG. 4 includes a capacitor C1, inverters 41, 42, and 44, a bandgap constant voltage circuit 43 (hereinafter referred to as a BGR circuit), a constant current source circuit 45, a constant current bias generation circuit 46, a PMOS transistor M1, and an NMOS transistor M2.

[0004] BGR circuit 43 supplies voltage VBGR, which is not affected by fluctuations in power supply voltage and temperature. Constant current source circuit 45, bias-controlled by constant current bias generation circuit 46, generates a constant current that is not affected by fluctuations in power supply voltage and temperature. In the oscillator circuit of FIG. 4, voltage VBGR and the constant current control the voltage of capacitor C1, so that inverter 42 can output a constant frequency that is not affected by fluctuations in power supply voltage, temperature, etc. (See, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-217762 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the above-described oscillator circuit includes the BGR circuit 43 and the constant current bias generating circuit 46, which poses a problem of large circuit scale and large current consumption for these circuits.

[0007] The present invention has been made in view of the above problems, and aims to provide an oscillator circuit that can output a constant frequency without being affected by fluctuations in power supply voltage, temperature, etc., even though the circuit scale is small and current consumption is low. [Means for solving the problem]

[0008] An oscillator circuit according to one aspect of the present invention comprises: a capacitor; a first constant current circuit connected between a first power supply terminal and one terminal of the capacitor; a first switch circuit connected between the other terminal of the capacitor and a second power supply terminal; a second constant current circuit having one terminal connected to the first power supply terminal; a first MOS transistor having a gate and drain connected to the other terminal of the second constant current circuit and a source connected to the other terminal of the capacitor; a second MOS transistor having a gate connected to the gate of the first MOS transistor and a drain connected to the one terminal of the capacitor; a second switch circuit connected between the source of the second MOS transistor and the second power supply terminal; and an output terminal that outputs a signal based on the voltage of the one terminal of the capacitor, wherein the first switch circuit and the second switch circuit are controlled to be turned on and off by a signal at the output terminal and an inverted signal of the signal. [Effects of the Invention]

[0009] The oscillator circuit of the present invention includes an NMOS transistor and a switch circuit that raise and lower the capacitor voltage at a constant voltage, and a constant current circuit that charges and discharges the capacitor at a constant current. This makes it possible to provide an oscillator circuit that has a small circuit size and current consumption, and is capable of outputting a constant frequency without being affected by fluctuations in the power supply voltage, temperature, etc. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing an oscillation circuit according to an embodiment of the present invention; [Figure 2] FIG. 1 is a circuit diagram illustrating an example of an oscillation circuit according to an embodiment of the present invention. [Figure 3]4 is a timing chart showing the operation of the oscillation circuit of the present embodiment. [Figure 4] FIG. 1 is a block diagram showing a conventional oscillator circuit. DETAILED DESCRIPTION OF THE INVENTION

[0011] An oscillator circuit according to the present invention will now be described with reference to the drawings.

[0012] FIG. 1 is a block diagram showing an oscillator circuit 100 of this embodiment. 1 includes constant current circuits 10, 11, and 12, NMOS transistors 13, 14, and 15, switch circuits 16 and 17, a capacitor 18, and inverters 30 and 31. The constant current circuit 12 and the NMOS transistor 15 form a constant current inverter.

[0013] One end of each of the constant current circuits 10, 11, and 12 is connected to a power supply terminal. The drain and gate of the NMOS transistor 13 are connected to the other end of the constant current circuit 10, and the source is connected to one end of the switch circuit 16. The other end of the switch circuit 16 is connected to a ground terminal, and the control terminal is connected to the output terminal of the inverter 31. The drain of the NMOS transistor 14 is connected to the other end of the constant current circuit 11, the gate is connected to the gate of the NMOS transistor 13, and the source is connected to one end of the switch circuit 17. The other end of the switch circuit 17 is connected to a ground terminal, and the control terminal is connected to the output terminal of the inverter 30. The capacitor 18 has one end connected to the source of the NMOS transistor 13 and the other end connected to the drain of the NMOS transistor 14. The drain of the NMOS transistor 15 is connected to the other end of the constant current circuit 12, the gate is connected to the drain of the NMOS transistor 14, and the source is connected to a ground terminal. The input terminal of the inverter 30 is connected to the drain of the NMOS transistor 15. The inverter 31 has an input terminal connected to the output terminal of the inverter 30 and an output terminal connected to the output terminal of the oscillation circuit 100 .

[0014] The oscillator circuit 100 shown in FIG. 1 controls the on / off of the switch circuits 16 and 17 with the signals CLK and CLKB to control the constant currents I 10 and I 11 The capacitor 18 is charged and discharged by the CLK signal.

[0015] Here, the oscillator circuit 100 in FIG. 1 is designed under the following conditions. If the duty ratio of the signal CLK is 50%, the constant current I 10 and constant current I 11 However, these constant currents may be appropriately set according to the desired duty ratio of the signal CLK. Furthermore, the voltage V1 of the node N1 when the switch circuit 17 is turned on, that is, ΔVgs=Vgs 14 -Vgs 13 is a positive value.

[0016] The oscillator circuit 100 configured as described above operates as follows. FIG. 3 is a timing chart showing the operation of the oscillator circuit 100. As shown in FIG.

[0017] First, the section from the initial state to time t1 will be described. In the initial state, capacitor 18 is not charged. When power is applied, signal CLK goes high and signal CLKB goes low, turning switch circuit 16 on and switch circuit 17 off. Therefore, voltage V1 at node N1 goes to the voltage of the ground terminal, i.e., low.

[0018] The capacitor 18 controls the constant current I flowing from the node N2 to the node N1. 11 Then, the voltage V2 at the node N2, which is the voltage of the capacitor 18, gradually rises. At time t1, the voltage V2 reaches the threshold Vth of the NMOS transistor 15. 15 When this occurs, the NMOS transistor 15 turns on, and the signal CLK goes to the L level and the signal CLKB goes to the H level.

[0019] Next, the period from time t1 to time t2 will be described. At time t1, when the signal CLK goes low and the signal CLKB goes high, the switch circuit 16 turns off and the switch circuit 17 turns on. 10 The voltage Vgs flows between the gate and source 13 The NMOS transistor 14 generates a constant current I 11 and a constant current I through capacitor 18 10 The voltage Vgs flows between the gate and source 14 Therefore, the voltage V1 at the node N1 is ΔVgs=Vgs 14 -Vgs 13 Here, the NMOS transistor 13 and the NMOS transistor 14 may be designed so that the voltage ΔVgs at this time becomes a positive value.

[0020] Since the voltage V1 becomes the voltage ΔVgs, the voltage V2 at the node N2 increases by the voltage ΔVgs due to the capacitor 18, and becomes Vth 15 +ΔVgs. Then, when the switch circuit 17 is turned on, the voltage charged in the capacitor 18 is discharged to the ground terminal via the NMOS transistor 14. The discharge current at this time is the constant current I 10 That's a considerable amount of current.

[0021] That is, at time t1, the voltage Vth 15 The voltage V2, which is the voltage of capacitor 18 that was +ΔVgs, flows through the constant current I 10 At time t2, the voltage V2 is discharged and gradually decreases. 15 When the voltage drops below 1 V, the NMOS transistor 15 turns off. Therefore, the signal CLK goes to H level and the signal CLKB goes to L level.

[0022] Next, the period from time t2 to time t3 will be described. At time t2, when the signal CLK goes high and the signal CLKB goes low, the switch circuit 16 turns on and the switch circuit 17 turns off. When the switch circuit 16 turns on, the voltage V1 at the node N1 changes from ΔVgs to the voltage of the ground terminal. The voltage V2 at the node N2 drops by the voltage ΔVgs due to the capacitor 18 to Vth 15 It becomes -ΔVgs.

[0023] Then, by repeating the same operation from time t4 onwards, the oscillator circuit 100 outputs the signal CLK with a duty ratio of 50% to the output terminal.

[0024] FIG. 2 is a circuit diagram showing an example of the oscillator circuit 100 of this embodiment. The constant current circuits 10, 11, and 12 are composed of a bias circuit 20 and PMOS transistors 10, 11, and 12. The PMOS transistors 10 and 11 are designed to pass the same current and have the same size. The switch circuits 16 and 17 are composed of NMOS transistors 16 and 17.

[0025] The bias circuit 20 includes NMOS transistors 21 and 22, a resistor 23, and PMOS transistors 24 and 25. The source of the NMOS transistor 21 is connected to the ground terminal via the resistor 23. The source of the NMOS transistor 22 is connected to the ground terminal, and the drain and gate are connected to the gate of the NMOS transistor 21. The source of the PMOS transistor 24 is connected to the power supply terminal, and the drain is connected to the drain of the NMOS transistor 22. The source of the PMOS transistor 25 is connected to the power supply terminal, and the drain and gate are connected to the gate of the PMOS transistor 24 and the drain of the NMOS transistor 21.

[0026] The bias circuit 20 configured as described above controls the current flowing through the PMOS transistor 25 to I 25 Then, I 25 =ΔVgs _B / R. ΔVgs _Bis the difference between the Vgs of the NMOS transistors 21 and 22, and R is the resistance value of the resistor 23.

[0027] The frequency f of the signal CLK of the oscillator circuit 100 is expressed as follows: f=(I / I 25 )(ΔVgs _B / ΔVgs) / 2CR I is the current flowing through the constant current circuits 10 and 11, and C is the capacitance of the capacitor 18. Here, the currents I and I 25 Equally, the voltage difference ΔVgs _B When ΔVgs is designed to be equal to ΔVgs, the frequency f is determined by the capacitance value of the capacitor 18 and the resistance value of the resistor 23.

[0028] That is, the frequency f of the signal CLK of the oscillator circuit 100 can be output at a constant frequency f without being affected by variations in the characteristics of each MOS transistor, nor by fluctuations in the power supply voltage, temperature, etc. As can be seen from the formula, it is obvious that the characteristics of the frequency f will be improved by using a resistor with good temperature characteristics.

[0029] As described above, the oscillator circuit 100 of this embodiment is configured to include NMOS transistors 13-14 and switch circuits 16-17 that increase and decrease the voltage of capacitor 18 at a constant voltage (ΔVgs), and constant current circuits 10-11 that charge and discharge capacitor 18 at a constant current. Therefore, even if the circuit size and current consumption are small, it is possible to output a constant frequency without being affected by fluctuations in power supply voltage, temperature, etc.

[0030] Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications are possible within the scope of the present invention. For example, the entire circuit can be configured inverted with respect to the power supply terminals and ground terminals, and the same effects can be obtained. In this case, the circuit configuration is such that the PMOS transistors and NMOS transistors are interchanged. [Explanation of symbols]

[0031] 10, 11, 12 Constant current circuit (PMOS transistor) 13, 14, 15 NMOS transistors 16, 17 Switch circuit (NMOS transistor) 18 Capacitors 20 Bias circuit 21, 22 NMOS transistor 23 Resistance 24, 25 PMOS transistors 30, 31 Inverter 100 Oscillator Circuit

Claims

1. A capacitor, a first constant current circuit connected between a first power supply terminal and one terminal of the capacitor; a first switch circuit connected between the other terminal of the capacitor and a second power supply terminal; a second constant current circuit having one terminal connected to the first power supply terminal; a first MOS transistor having a gate and a drain connected to the other terminal of the second constant current circuit and a source connected to the other terminal of the capacitor; a second MOS transistor having a gate connected to the gate of the first MOS transistor and a drain connected to one terminal of the capacitor; a second switch circuit connected between the source of the second MOS transistor and the second power supply terminal; a third constant current circuit having one terminal connected to the first power supply terminal; a third MOS transistor having a drain connected to the other terminal of the third constant current circuit, a source connected to the second power supply terminal, and a gate connected to one terminal of the capacitor; an output circuit connected to the drain of the third MOS transistor; Equipped with the output circuit generates a signal whose state is inverted in response to the voltage of one terminal of the capacitor reaching a threshold value of the third MOS transistor, and turns on and off the first switch circuit and the second switch circuit in a complementary manner; an oscillation circuit characterized in that, when the second switch circuit is turned on, the voltage of the source of the first MOS transistor becomes a voltage corresponding to the difference between the gate-source voltages of the first MOS transistor and the second MOS transistor, thereby defining the voltage amplitude of the capacitor.

2. The output circuit a first inverter having an input connected to the drain of the third MOS transistor and outputting an inverted signal based on a threshold value of the third MOS transistor; a second inverter that inverts the inverted signal output from the first inverter to generate the signal; 2. The oscillator circuit of claim 1, comprising:

3. the first switch circuit is controlled to be turned on and off by the signal output from the second inverter, 3. The oscillation circuit according to claim 2, wherein the second switch circuit is controlled to be turned on and off by the inverted signal output from the first inverter.

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