Communication device and method for processing received data in the communication device

Abstract

To reduce the time required for each CPU of a multi-core CPU to finish access of reception data after data is received.SOLUTION: A communication device of the invention includes: a multi-core CPU 2 that has multiple CPUs mounted with an application; a reception frame processing unit 4 that determines the Ethertype of reception data and allocates the reception data for each Ethertype; and multiple reception FIFOs 5A, 5B, 5C that receive the reception data allocated by the reception frame processing unit 4 and store it for each Ethertype. When receiving the reception data, each of the multiple reception FIFOs 5A, 5B, 5C transmits a reception interruption signal to the corresponding CPU of the multi-core CPU 2. The CPU that has received the reception interruption signal performs processing of acquiring the data size of the reception data from the reception FIFO that has transmitted the reception interruption signal and reading the reception data on the basis of the data size.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a communication device and a method for processing received data in a communication device, and more particularly to a communication device equipped with a multi-core CPU configured with multiple CPUs that implement applications, and a method for processing received data in the communication device. [Background technology]

[0002] A technology for improving processing performance in a communication device that processes received data of multiple Ethertypes is described in Patent Document 1. Patent Document 1 discloses the following technology: "A communication device including a data sorting unit that determines, based on the type of received data, a module sorting unit to which received data is to be sorted from among a plurality of module sorting units that manage a plurality of modules, and sorts the received data to the determined module sorting unit." [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-167673 Summary of the Invention [Problem to be solved by the invention]

[0004] Although the conventional technology described in Patent Document 1 can satisfy the requirements of each of the multiple network functions, it does not consider a specific processing method for distributing data allocated by a data allocation unit to multiple modules. If each module cannot quickly access the received data allocated by the data allocation unit, it will be impossible to reduce the time required from when the data is received until the module finishes processing.

[0005] The present invention has been made in consideration of the above situation, and aims to provide a communication device that can shorten the time required from when data is received until each CPU of a multi-core CPU finishes accessing the received data, and a method for processing received data in the communication device. [Means for solving the problem]

[0006] In order to solve the above problems, a communication device of the present invention includes a multi-core CPU configured with a plurality of CPUs that implement applications, a reception frame processing unit that determines the Ethertype of received data and distributes the received data by Ethertype, and a plurality of buffering memories that receive the reception data distributed by the reception frame processing unit and store the data by Ethertype. Prepare. The first communication device of the present invention further comprises: When each of the plurality of buffering memories receives the reception data allocated by the reception frame processing unit, it transmits a reception interrupt signal to a corresponding CPU among the plurality of CPUs, and the CPU that receives the reception interrupt signal acquires the data size of the reception data from the buffering memory that transmitted the reception interrupt signal and performs processing to read the reception data based on this data size. The second communication device of the present invention further includes a plurality of receiving DMACs and a memory for storing data to be processed by each CPU of the multi-core CPU, and when each of the plurality of buffering memories receives the received data allocated by the receiving frame processing unit, it transmits a receiving DMA request signal to a corresponding receiving DMAC among the plurality of receiving DMACs, and the receiving DMAC that receives the receiving DMA request signal reads the received data from the buffering memory that transmitted the receiving DMA request signal and transfers it to memory, and when the transfer of the received data is completed, it transmits a transfer end interrupt signal to the corresponding CPU among the plurality of CPUs notifying that the transfer of the received data to memory has been completed, and the CPU that receives the transfer end interrupt signal obtains the data size of the received data from the DMAC that transmitted the receiving DMA request signal and performs processing to read the received data from the memory based on the data size. The third communication device of the present invention further includes a memory for storing data to be processed by each CPU of the multi-core CPU, and a general-purpose DMAC for reading received data from the plurality of buffering memories and transferring it to the memory, wherein each of the plurality of buffering memories, when receiving received data allocated by the receiving frame processing unit, transmits a receive interrupt signal to a corresponding CPU among the plurality of CPUs, the CPU receiving the receive interrupt signal acquires the data size of the received data from the buffering memory that transmitted the receive interrupt signal, and performs DMA transfer settings and transfer permission for the general-purpose DMAC, the general-purpose DMAC receiving the DMA transfer settings and transfer permission executes DMA transfer from the plurality of buffering memories to the memory, and then transmits a transfer end interrupt signal to the corresponding CPU among the plurality of CPUs, and the CPU receiving the transfer end interrupt signal performs processing to read the received data from the memory.

[0007] In addition, the received data processing method of the present invention for solving the above problem is provided in a communication device having a multi-core CPU consisting of multiple CPUs that implement applications, and includes a processing step of determining the Ether type of the received data and allocating the received data by Ether type, a storage step of storing the received data allocated in the processing step in multiple buffering memories by Ether type, and a read processing step of reading out the received data stored in the multiple buffering memories, wherein in the storage step, when each of the multiple buffering memories receives the received data allocated in the processing step, it sends a receive interrupt signal to a corresponding CPU among the multiple CPUs, and in the read processing step, the CPU that receives the receive interrupt signal obtains the data size of the received data from the buffering memory that sent the receive interrupt signal and performs processing to read the received data based on this data size. [Effects of the Invention]

[0008] According to the present invention, it is possible to reduce the time required from when data is received until each CPU of a multi-core CPU finishes accessing the received data.

[0009] Problems, configurations, and effects other than those described above will become clear from the following description of the embodiments of the invention. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing an example of a hardware configuration of a communication device according to a first embodiment of the present invention. [Figure 2] 5 is a flowchart showing an example of a processing procedure of a received data processing method in the communication device according to the first embodiment of the present invention. [Figure 3] FIG. 10 is a block diagram showing an example of a hardware configuration of a communication device according to a second embodiment of the present invention. [Figure 4] 10 is a flowchart illustrating an example of a processing procedure of a received data processing method in a communication device according to a second embodiment of the present invention. [Figure 5]FIG. 10 is a block diagram showing an example of a hardware configuration of a communication device according to a third embodiment of the present invention. [Figure 6] 10 is a flowchart illustrating an example of a processing procedure of a received data processing method in a communication device according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functions or configurations are designated by the same reference numerals, and redundant description will be omitted. [Example]

[0012] FIG. 1 is a block diagram illustrating an example of a hardware configuration of a communication device according to a first embodiment of the present invention.

[0013] 1, a communication device according to a first embodiment of the present invention includes a multiprocessor system on a chip 10 and a memory 20. The multiprocessor system on a chip 10 includes a plurality of CPUs for implementing applications, i.e., a multicore CPU 2 including three CPUs, CPU(1) 1A, CPU(2) 1B, and CPU(3) 1C, in this embodiment. The memory 20 is a memory for storing data to be processed by each of the CPUs, CPU(1) 1A, CPU(2) 1B, and CPU(3) 1C, of ​​the multicore CPU 2.

[0014] In addition to the multi-core CPU 2, the multiprocessor system-on-chip 10 includes a physical coding sublayer 3, a receive frame processing unit 4, multiple receive FIFOs (in this embodiment, three receive FIFOs: receive FIFO(1) 5A, receive FIFO(2) 5B, and receive FIFO(3) 5C), an interrupt controller 6, a memory controller 7, and an interconnect bridge 8.

[0015] Here, receive FIFO (1) 5A, receive FIFO (2) 5B, and receive FIFO (3) 5C are first-in, first-out (FIFO) memories. In this specification, "FIFO memory" will be referred to simply as "FIFO." Note that receive FIFO (1) 5A, receive FIFO (2) 5B, and receive FIFO (3) 5C are examples of buffering memories within the scope of the claims. Buffering memories are memories that can read and write data at high speeds.

[0016] In the multiprocessor system-on-chip 10 configured as described above, the physical coding sublayer 3 decodes communication frames. The receive frame processing unit 4 has the function of determining the Ethertype of the received data and sorting the received data by Ethertype. Multiple receive FIFOs (1) 5A, (2) 5B, and (3) 5C receive the receive data sorted by Ethertype by the receive frame processing unit 4 and temporarily store the data by Ethertype.

[0017] The interrupt controller 6 distributes a plurality of interrupt causes to each CPU, i.e., CPU(1) 1A, CPU(2) 1B, and CPU(3) 1C, of ​​the multi-core CPU 2. In other words, the interrupt controller 6 can distribute a plurality of interrupt causes to CPU(1) 1A, CPU(2) 1B, and CPU(3) 1C of the multi-core CPU 2 based on receive interrupt signals (to be described later) from receive FIFO(1) 5A, receive FIFO(2) 5B, and receive FIFO(3) 5C.

[0018] The memory controller 7 is connected to the memory 20 and controls memory access for the CPU(1) 1A, CPU(2) 1B, and CPU(3) 1C of the multi-core CPU 2. That is, under the control of the memory controller 7, the CPU(1) 1A, CPU(2) 1B, and CPU(3) 1C that have received a received interrupt signal from the interrupt controller 6 can perform processing to read the received data from the memory 20.

[0019] The interconnect bridge 8 connects the receive FIFO(1) 5A, receive FIFO(2) 5B, receive FIFO(3) 5C to the memory controller 7, and transfers the receive data temporarily stored in the receive FIFO(1) 5A, receive FIFO(2) 5B, and receive FIFO(3) 5C to the memory controller 7. In other words, the provision of the interconnect bridge 8 makes it possible to transfer the receive data temporarily stored in the receive FIFO(1) 5A, receive FIFO(2) 5B, and receive FIFO(3) 5C to the memory controller 7.

[0020] The receive FIFO (1) 5A, receive FIFO (2) 5B, and receive FIFO (3) 5C are mapped to the memory space of the multi-core CPU 2 and have receive interrupt signals for each Ethertype that notify that received data has been stored. The receive FIFO (1) 5A, receive FIFO (2) 5B, and receive FIFO (3) 5C are also mapped to the memory space of the multi-core CPU 2 and have registers that hold the size of the temporarily stored received data.

[0021] Upon receiving a receive interrupt signal from the interrupt controller 6, the CPU(1) 1A, CPU(2) 1B, and CPU(3) 1C read the data size of the receive data from the receive FIFO(1) 5A, receive FIFO(2) 5B, and receive FIFO(3) 5C via the interconnect bridge 8, and perform processing to read the receive data based on the read data size. Here, one example of the "processing to read receive data based on the data size" is processing to read only the receive data equivalent to the data size.

[0022] Next, a description will be given of a received data processing method in the communication device according to the first embodiment with the above configuration. Fig. 2 is a flowchart illustrating an example of a processing procedure of the received data processing method in the communication device according to the first embodiment.

[0023] First, when a communication frame is received (step S101), the physical coding sublayer 3 decodes the communication frame and inputs the communication frame to the received frame processing unit 4 (step S102).

[0024] Next, the received frame processing unit 4 analyzes the Ethertype of the received communication frame and determines whether it matches the predefined Ethertype 1 (step S103). If it is determined that it matches (YES in S103), it inputs the communication frame of Ethertype 1 into the receiving FIFO (1) 5A (step S104).

[0025] The receive FIFO(1) 5A, which has received the EtherType 1 communication frame from the receive frame processing unit 4, transmits a receive interrupt signal to the interrupt controller 6 (step S105). Upon receiving the receive interrupt signal from the receive FIFO(1) 5A, the interrupt controller 6 determines a CPU (in this example, CPU(1) 1A) of the multi-core CPU 2 that will process the receive interrupt from the receive FIFO(1) 5A, and outputs an interrupt signal to the determined CPU (step S106).

[0026] In the process of step S106, in this embodiment, it is assumed that CPU(1) 1A processes the receive interrupt from receive FIFO(1) 5A. Here, the interrupt destination CPU can be set by the interrupt controller 6, and the number of interrupt destination CPUs is not limited to one, but two or more CPUs can also be set.

[0027] The CPU(1) 1A reads the data size of the received data from the receive FIFO(1) 5A via the interconnect bridge 8, and then performs a process of reading the received frame from the receive FIFO(1) 5A based on this data size (step S107), and then ends the series of processes for processing the received data.

[0028] If it is determined in the process of step S103 that the Ethertype of the received communication frame does not match Ethertype 1 (NO in S103), the receive frame processing unit 4 analyzes the Ethertype of the received communication frame and determines whether it matches the predefined Ethertype 2 (step S108).If it is determined that it matches (YES in S108), the receive frame processing unit 4 inputs the Ethertype 2 communication frame into the receive FIFO(2) 5B (step S109).

[0029] The receive FIFO(2) 5B, which has received an EtherType 2 communication frame from the receive frame processing unit 4, transmits a receive interrupt signal to the interrupt controller 6 (step S110). Upon receiving the receive interrupt signal from the receive FIFO(2) 5B, the interrupt controller 6 determines a CPU of the multi-core CPU 2 (in this example, CPU(2) 1B) that will process the receive interrupt from the receive FIFO(2) 5B, and outputs an interrupt signal to the determined CPU (step S111).

[0030] In the process of step S111, in this embodiment, the receive interrupt from receive FIFO(2) 5B is processed by CPU(2) 1B. Here, the interrupt destination CPU can be set by the interrupt controller 6, and the number of interrupt destination CPUs is not limited to one, but two or more CPUs can also be set.

[0031] The CPU(2) 1B reads the data size of the received data from the receive FIFO(2) 5B via the interconnect bridge 8, and then performs a process of reading the received frame from the receive FIFO(2) 5B based on the data size (step S112), and then ends the series of processes for processing the received data.

[0032] In the processing of step S108, if it is determined that the Ethertype of the received communication frame does not match Ethertype 2 (NO in S108), the receive frame processing unit 4 inputs the communication frame of Ethertype 3 into the receive FIFO (3) 5C (step S113).

[0033] The receive FIFO(3) 5C, which has received the EtherType 3 communication frame from the receive frame processing unit 4, transmits a receive interrupt signal to the interrupt controller 6 (step S114). Upon receiving the receive interrupt signal from the receive FIFO(3) 5C, the interrupt controller 6 determines a CPU (in this example, CPU(3) 1C) of the multi-core CPU 2 that will process the receive interrupt from the receive FIFO(3) 5C, and outputs an interrupt signal to the determined CPU (step S115).

[0034] In the process of step S114, in this embodiment, the CPU(3) 1C processes the receive interrupt from the receive FIFO(3) 5C. Here, the interrupt destination CPU can be set by the interrupt controller 6, and the number of interrupt destination CPUs is not limited to one, but two or more CPUs can also be set.

[0035] The CPU (3) 1C reads the size of the received data from the receive FIFO (3) 5C via the interconnect bridge 8, and then performs processing to read the received frame from the receive FIFO (3) 5C based on the data size (step S116 ), after which the series of steps for processing the received data is completed.

[0036] As described above, in the communication device and the received data processing method according to the first embodiment, a plurality of buffering memories capable of reading and writing data at high speed are used as memories for storing received data by Ethertype. When each of the plurality of buffering memories receives received data, it transmits a receive interrupt signal to a corresponding CPU among the plurality of CPUs. The CPU that receives the receive interrupt signal acquires the data size of the received data from the buffering memory and performs processing to read the received data based on the data size.

[0037] In this way, by determining the Ethertype of the received data, distributing it to multiple buffering memories that can read and write data at high speed, and transferring the received data from each buffering memory to each CPU of the multi-core CPU 2, it is possible to reduce the time required from when the data is received until each CPU of the multi-core CPU 2 finishes accessing the received data. In particular, by using first-in, first-out FIFO memories (receive FIFO (1) 5A, receive FIFO (2) 5B, receive FIFO (3) 5C) as multiple buffering memories, the effect of reducing the above-mentioned time is significant. [Example]

[0038] FIG. 3 is a block diagram illustrating an example of a hardware configuration of a communication device according to a second embodiment of the present invention.

[0039] 3, the communication device according to the second embodiment of the present invention is configured to include a multiprocessor system-on-chip 10 and a memory 20, similar to the communication device according to the first embodiment. The multiprocessor system-on-chip 10 includes a multi-core CPU 2 including multiple CPUs for implementing applications, namely, in this embodiment, three CPUs: CPU(1) 1A, CPU(2) 1B, and CPU(3) 1C. The memory 20 is a memory for storing data to be processed by each of the CPUs (1) 1A, CPU(2) 1B, and CPU(3) 1C of the multi-core CPU 2.

[0040] In addition to the multi-core CPU 2, the multiprocessor system-on-chip 10 includes a physical coding sublayer 3, a receive frame processing unit 4, multiple receive FIFOs (in this embodiment, three receive FIFOs: receive FIFO(1) 5A, receive FIFO(2) 5B, and receive FIFO(3) 5C), an interrupt controller 6, a memory controller 7, and an interconnect bridge 8. The multiprocessor system-on-chip 10 further includes multiple receive DMACs (Direct Memory Access Controllers) for different Ethertypes (in this embodiment, three receive DMAC(1) 11A, DMAC(2) 11B, and DMAC(3) 11C).

[0041] In the multiprocessor system-on-chip 10 having the above configuration, the functions of the physical coding sublayer 3, the receive frame processing unit 4, the plurality of receive FIFOs (1) 5A, receive FIFO (2) 5B, receive FIFO (3) 5C, the interrupt controller 6, the memory controller 7, and the interconnect bridge 8 are basically the same as those of the communication device according to the first embodiment.

[0042] The receive FIFO(1) 5A, receive FIFO(2) 5B, and receive FIFO(3) 5C have receive DMA request signals for each Ethertype that notify that receive data has been stored, and when the receive data has been stored, they output receive DMA request signals to the receive DMAC(1) 11A, DMAC(2) 11B, and DMAC(3) 11C for each Ethertype.

[0043] The receiving DMAC(1) 11A, DMAC(2) 11B, and DMAC(3) 11C read the received data from the receiving FIFO(1) 5A, receiving FIFO(2) 5B, and receiving FIFO(3) 5C, and transfer the data to the memory 20 via the interconnect bridge 8. Furthermore, the receiving DMAC(1) 11A, DMAC(2) 11B, and DMAC(3) 11C each have a transfer end interrupt signal that notifies them that the received data transfer has ended when the transfer of the received data to the memory 20 has ended.

[0044] The receive DMAC(1) 11A, DMAC(2) 11B, and DMAC(3) 11C further include a register that is mapped to the memory space of the multi-core CPU 2 and holds the data size of the receive data transferred to memory 20, and a register that sets the memory address to which the receive data stored in receive FIFO(1) 5A, receive FIFO(2) 5B, and receive FIFO(3) 5C is transferred. Upon receiving a receive interrupt signal from the interrupt controller 6, the CPU(1) 1A, CPU(2) 1B, and CPU(3) 1C read the data size of the receive data from the receive DMAC(1) 11A, DMAC(2) 11B, and DMAC(3) 11C via the interconnect bridge 8, and then perform processing to read the receive data from memory 20 under the control of the memory controller 7.

[0045] Next, a description will be given of a received data processing method in the communication device having the above configuration according to the second embodiment. Fig. 4 is a flowchart illustrating an example of a processing procedure of the received data processing method in the communication device according to the second embodiment.

[0046] First, when a communication frame is received (step S201), the physical coding sublayer 3 decodes the communication frame and inputs the communication frame to the received frame processing unit 4 (step S202).

[0047] Next, the received frame processing unit 4 analyzes the Ethertype of the received communication frame and determines whether it matches the predefined Ethertype 1 (step S203). If it is determined that it matches (YES in S203), it inputs the communication frame of Ethertype 1 into the receiving FIFO (1) 5A (step S204).

[0048] The receive FIFO(1) 5A, which has received the EtherType 1 communication frame from the receive frame processor 4, transmits a receive DMA request signal to the receive DMAC(1) 11A (step S205). Having received the receive DMA request signal, the receive DMAC(1) 11A reads the receive data from the receive FIFO(1) 5A and transfers it to the memory 20 via the interconnect bridge 8 (step S206).

[0049] When the data transfer to the memory 20 is completed, the receiving DMAC(1) 11A transmits a transfer end interrupt signal to the interrupt controller 6 (step S207). When the interrupt controller 6 receives the transfer end interrupt signal, it determines a CPU of the multi-core CPU 2 (in this example, CPU(1) 1A) that will process the transfer end interrupt from the receiving DMAC(1) 11A, and outputs an interrupt signal to the determined CPU (step S208).

[0050] In the process of step S208, in this embodiment, it is assumed that the CPU(1) 1A processes the receive interrupt from the receive DMAC(1) 11A. Here, the interrupt destination CPU can be set by the interrupt controller 6, and the number of interrupt destination CPUs is not limited to one, but two or more CPUs can also be set.

[0051] The CPU(1) 1A reads the data size of the received data from the receiving DMAC(1) 11A via the interconnect bridge 8, and then performs a process of reading the received frame from the memory 20 based on this data size (step S209), and then ends the series of processes for processing the received data.

[0052] In the process of step S203, if it is determined that the Ethertype of the received communication frame does not match Ethertype 1 (NO in S203), the receive frame processing unit 4 analyzes the Ethertype of the received communication frame and determines whether it matches the predefined Ethertype 2 (step S210).If it is determined that it matches (YES in S210), the receive frame processing unit 4 inputs the communication frame of Ethertype 2 into the receive FIFO(2) 5B (step S211).

[0053] The receive FIFO(2) 5B, which has received the EtherType 2 communication frame from the receive frame processor 4, transmits a receive DMA request signal to the receive DMAC(2) 11B (step S212). Having received the receive DMA request signal, the receive DMAC(2) 11B reads the receive data from the receive FIFO(2) 5B and transfers it to the memory 20 via the interconnect bridge 8 (step S213).

[0054] When the data transfer to the memory 20 is completed, the receiving DMAC(2) 11B transmits a transfer end interrupt signal to the interrupt controller 6 (step S214). When the interrupt controller 6 receives the transfer end interrupt signal, it determines a CPU of the multi-core CPU 2 (in this example, CPU(2) 1B) that will process the transfer end interrupt from the receiving DMAC(2) 11B, and outputs an interrupt signal to the determined CPU (step S215).

[0055] In the process of step S215, in this embodiment, it is assumed that the CPU(2) 1B processes the receive interrupt from the receive DMAC(2) 11B. Here, the interrupt destination CPU can be set by the interrupt controller 6, and the number of interrupt destination CPUs is not limited to one, but two or more CPUs can also be set.

[0056] The CPU(2) 1B reads the data size of the received data from the receiving DMAC(2) 11B via the interconnect bridge 8, and then performs a process of reading the received frame from the memory 20 based on this data size (step S216), and then ends the series of processes for processing the received data.

[0057] In the processing of step S210, if it is determined that the Ethertype of the received communication frame does not match Ethertype 2 (NO in S210), the received frame processing unit 4 inputs the communication frame of Ethertype 3 into the receive FIFO (3) 5C (step S217).

[0058] The receive FIFO(3) 5C, which has received the EtherType 3 communication frame from the receive frame processor 4, transmits a receive DMA request signal to the receive DMAC(3) 11C (step S218). Having received the receive DMA request signal, the receive DMAC(3) 11C reads the receive data from the receive FIFO(3) 5C and transfers it to the memory 20 via the interconnect bridge 8 (step S219).

[0059] When the data transfer to the memory 20 is completed, the receiving DMAC(3) 11C transmits a transfer end interrupt signal to the interrupt controller 6 (step S220). When the interrupt controller 6 receives the transfer end interrupt signal, it determines a CPU of the multi-core CPU 2 (in this example, CPU(3) 1C) that will process the transfer end interrupt from the receiving DMAC(3) 11C, and outputs an interrupt signal to the determined CPU (step S221).

[0060] In the processing of step S221, in this embodiment, it is assumed that the CPU(3) 1C processes the receive interrupt from the receive DMAC(3) 11C. Here, the interrupt destination CPU can be set by the interrupt controller 6, and the number of interrupt destination CPUs is not limited to one, but two or more CPUs can also be set.

[0061] The CPU (3) 1C reads the data size of the received data from the receiving DMAC (3) 11C via the interconnect bridge 8, and then performs a process of reading the received frame from the memory 20 based on this data size (step S222), and then ends the series of processes for processing the received data.

[0062] As described above, the communication device and the received data processing method thereof according to the second embodiment use multiple receive FIFOs as memories for storing received data by Ethertype, and multiple receive DMACs are provided behind the multiple receive FIFOs. When receive data is received in each of the multiple receive FIFOs, a receive DMA request signal is sent to a corresponding DMAC among the multiple DMACs. Meanwhile, the DMAC that receives the receive DMA request signal reads the received data from the receive FIFO that sent the receive DMA request signal and transfers it to memory 20. When the transfer of the received data is completed, a transfer end interrupt signal is sent to a corresponding CPU among the multiple CPUs.

[0063] In this way, by using a configuration in which receive DMAC(1) 11A, DMAC(2) 11B, and DMAC(3) 11C each having a register for setting a memory address to which received data is transferred, the read of data from receive FIFO(1) 5A, receive FIFO(2) 5B, and receive FIFO(3) 5C is handled by receive DMAC(1) 11A, DMAC(2) 11B, and DMAC(3) 11C. This eliminates the need for address specification for reading received data from the multi-core CPU 2 side, reducing the burden on each CPU of the multi-core CPU 2 and further shortening the time required for each CPU of the multi-core CPU 2 to complete accessing the received data after receiving data. [Example]

[0064] FIG. 5 is a block diagram illustrating an example of a hardware configuration of a communication device according to a third embodiment of the present invention.

[0065] 5, the communication device according to the third embodiment of the present invention is configured to include a multiprocessor system-on-chip 10 and a memory 20, similar to the communication device according to the first embodiment. The multiprocessor system-on-chip 10 includes a multi-core CPU 2 including multiple CPUs for implementing applications, namely, in this embodiment, three CPUs: CPU(1) 1A, CPU(2) 1B, and CPU(3) 1C. The memory 20 is a memory for storing data to be processed by each of the CPUs (1) 1A, CPU(2) 1B, and CPU(3) 1C of the multi-core CPU 2.

[0066] In addition to the multi-core CPU 2, the multiprocessor system-on-chip 10 includes a physical coding sublayer 3, a receive frame processing unit 4, multiple receive FIFOs (in this embodiment, three receive FIFOs: receive FIFO(1) 5A, receive FIFO(2) 5B, and receive FIFO(3) 5C), an interrupt controller 6, a memory controller 7, and an interconnect bridge 8. The multiprocessor system-on-chip 10 further includes a general-purpose DMAC 12 that reads receive data from the multiple receive FIFOs: receive FIFO(1) 5A, receive FIFO(2) 5B, and receive FIFO(3) 5C, and transfers the data to memory 20 via the interconnect bridge 8.

[0067] In the multiprocessor system-on-chip 10 having the above configuration, the functions of the physical coding sublayer 3, the receive frame processing unit 4, the plurality of receive FIFOs (1) 5A, receive FIFO (2) 5B, receive FIFO (3) 5C, the interrupt controller 6, the memory controller 7, and the interconnect bridge 8 are basically the same as those of the communication device according to the first embodiment.

[0068] The receive FIFO (1) 5A, receive FIFO (2) 5B, and receive FIFO (3) 5C are mapped to the memory space of the multi-core CPU 2 and have receive interrupt signals for each Ethertype that notify that received data has been stored. The receive FIFO (1) 5A, receive FIFO (2) 5B, and receive FIFO (3) 5C are also mapped to the memory space of the multi-core CPU 2 and have registers that hold the size of the stored received data.

[0069] Upon receiving the receive interrupt signal, CPU(1) 1A, CPU(2) 1B, and CPU(3) 1C read the data size of the received data from receive FIFO(1) 5A, receive FIFO(2) 5B, and receive FIFO(3) 5C via the interconnect bridge 8. Then, CPU(1) 1A, CPU(2) 1B, and CPU(3) 1C configure the general-purpose DMAC 12 for DMA transfer from receive FIFO(1) 5A, receive FIFO(2) 5B, and receive FIFO(3) 5C to memory 20.

[0070] The general-purpose DMAC 12 receives DMA transfer settings from the CPU(1) 1A, CPU(2) 1B, and CPU(3) 1C and executes DMA transfer from the receive FIFO(1) 5A, receive FIFO(2) 5B, and receive FIFO(3) 5C to the memory 20. When the DMA transfer ends, the general-purpose DMAC 12 sends a transfer end interrupt signal to the interrupt controller 6 to notify the completion of the transfer. Upon receiving the transfer end interrupt signal from the interrupt controller 6, the CPU(1) 1A, CPU(2) 1B, and CPU(3) 1C perform processing to read the received data from the memory 20.

[0071] Next, a description will be given of a received data processing method in the communication device having the above configuration according to the third embodiment. Fig. 6 is a flowchart illustrating an example of a processing procedure of the received data processing method in the communication device according to the third embodiment.

[0072] First, when a communication frame is received (step S301), the physical coding sublayer 3 decodes the communication frame and inputs the communication frame to the received frame processing unit 4 (step S302).

[0073] Next, the received frame processing unit 4 analyzes the Ethertype of the received communication frame and determines whether it matches the predefined Ethertype 1 (step S303). If it is determined that it matches (YES in S303), it inputs the communication frame of Ethertype 1 into the receive FIFO (1) 5A (step S304).

[0074] The receive FIFO(1) 5A, which has received the EtherType 1 communication frame from the receive frame processing unit 4, transmits a receive interrupt signal to the CPU(1) 1A via the interrupt controller 6 (step S305). The CPU(1) 1A, which has received the receive interrupt signal, reads the size of the received data from the receive FIFO(1) 5A via the interconnect bridge 8, and sets the general-purpose DMAC 12 for DMA transfer from the receive FIFO(1) 5A to the memory 20 (step S306).

[0075] When the DMA transfer is completed, the general-purpose DMAC 12 transmits a transfer end interrupt signal notifying the completion of the transfer to the interrupt controller 6 (step S307). The interrupt controller 6 determines a CPU (in this example, CPU(1) 1A) to process the transfer end interrupt from the general-purpose DMAC 12, and outputs an interrupt signal to that CPU (step S308).

[0076] In this embodiment, the transfer end interrupt of the general-purpose DMAC 12 is processed by CPU(1) 1A, but the interrupt destination CPU can be set by the interrupt controller 6, and the interrupt destination CPU is not limited to one, but two or more CPUs can also be set.

[0077] The CPU (1) 1A reads the received frame from the memory 20 (step S309), and then ends the series of steps for processing the received data.

[0078] In the process of step S303, if it is determined that the Ethertype of the received communication frame does not match Ethertype 1 (NO in S303), the receive frame processing unit 4 analyzes the Ethertype of the received communication frame and determines whether it matches the predefined Ethertype 2 (step S310).If it is determined that it matches (YES in S310), the receive frame processing unit 4 inputs the communication frame of Ethertype 2 to the receive FIFO(2) 5B (step S311).

[0079] The receive FIFO(2) 5B, which has received the EtherType 2 communication frame from the receive frame processing unit 4, transmits a receive interrupt signal to the CPU(2) 1B via the interrupt controller 6 (step S312). The CPU(2) 1B, which has received the receive interrupt signal, reads the size of the received data from the receive FIFO(2) 5B via the interconnect bridge 8, and sets the general-purpose DMAC 12 for DMA transfer from the receive FIFO(2) 5B to the memory 20 (step S313).

[0080] When the DMA transfer is completed, the general-purpose DMAC 12 transmits a transfer end interrupt signal notifying the completion of the transfer to the interrupt controller 6 (step S314). The interrupt controller 6 determines a CPU (in this example, CPU(2) 1B) to process the transfer end interrupt from the general-purpose DMAC 12, and outputs an interrupt signal to that CPU (step S315).

[0081] In this embodiment, the transfer end interrupt of the general-purpose DMAC 12 is processed by the CPU (2) 1B, but the interrupt destination CPU can be set by the interrupt controller 6, and the interrupt destination CPU is not limited to one, but two or more CPUs can also be set.

[0082] The CPU (2) 1B reads the received frame from the memory 20 (step S316), and then ends the series of steps for processing the received data.

[0083] In the processing of step S310, if it is determined that the Ethertype of the received communication frame does not match Ethertype 2 (NO in S310), the received frame processing unit 4 inputs the communication frame of Ethertype 3 into the receive FIFO (3) 5C (step S317).

[0084] The receive FIFO(3) 5C, which has received the EtherType 3 communication frame from the receive frame processing unit 4, transmits a receive interrupt signal to the CPU(3) 1C via the interrupt controller 6 (step S318). The CPU(3) 1C, which has received the receive interrupt signal, reads the size of the received data from the receive FIFO(3) 5C via the interconnect bridge 8, and sets the general-purpose DMAC 12 for DMA transfer from the receive FIFO(3) 5C to the memory 20 (step S319).

[0085] When the DMA transfer is completed, the general-purpose DMAC 12 transmits a transfer end interrupt signal notifying the completion of the transfer to the interrupt controller 6 (step S320). The interrupt controller 6 determines a CPU (in this example, CPU(3) 1C) to process the transfer end interrupt from the general-purpose DMAC 12, and outputs an interrupt signal to that CPU (step S321).

[0086] In this embodiment, the transfer end interrupt of the general-purpose DMAC 12 is processed by the CPU (3) 1C, but the interrupt destination CPU can be set by the interrupt controller 6, and the interrupt destination CPU is not limited to one, but two or more CPUs can also be set.

[0087] The CPU (3) 1C reads the received frame from the memory 20 (step S322), and then ends the series of steps for processing the received data.

[0088] As described above, the communication device and the received data processing method thereof according to the third embodiment are configured to use a general-purpose DMAC 12 instead of the plurality of receiving DMAC(1) 11A, DMAC(2) 11B, and DMAC(3) 11C in the second embodiment. Therefore, the configuration of the multiprocessor system-on-chip 10 can be simplified compared to the second embodiment.

[0089] The present invention is not limited to the above-described embodiments, and various other applications and modifications are possible without departing from the spirit of the present invention as defined in the claims. For example, the above-described embodiments have described the device configuration in detail and specifically to clearly explain the present invention, and the present invention is not necessarily limited to devices that include all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. It is also possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0090] 1A...CPU(1), 1B...CPU(2), 1C...CPU(3), 2...Multi-core CPU, 3...Physical coding sublayer, 4...Receive frame processing unit, 5A...Receive FIFO(1), 5B...Receive FIFO(2), 5C...Receive FIFO(3), 6...Interrupt controller, 7...Memory controller, 8...Interconnect bridge, 10...Multiprocessor system-on-chip, 11A...Receive DMAC(1), 11B...Receive DMAC(2), 11C...Receive DMAC(3), 12...General-purpose DMAC, 20...Memory

Claims

1. a multi-core CPU consisting of multiple CPUs that implement applications; a reception frame processing unit that determines the Ethertype of received data and distributes the received data according to the Ethertype; a plurality of buffering memories for receiving the received data sorted by the received frame processing unit and storing the data by Ethertype; Equipped with each of the plurality of buffering memories, when receiving the reception data allocated by the reception frame processing unit, transmits a reception interrupt signal to a corresponding CPU among the plurality of CPUs; The CPU that receives the reception interrupt signal acquires the data size of the received data from the buffering memory that sent the reception interrupt signal, and performs processing to read the received data based on the data size. A communication device comprising:

2. A multi-core CPU consisting of multiple CPUs that implement applications; a reception frame processing unit that determines the Ethertype of received data and distributes the received data according to the Ethertype; a plurality of buffering memories for receiving the received data sorted by the received frame processing unit and storing the data by Ethertype; a plurality of receiving DMACs; a memory for storing data to be processed by each CPU of the multi-core CPU; Equipped with When each of the plurality of buffering memories receives the reception data allocated by the reception frame processing unit, the buffering memories transmits a reception DMA request signal to a corresponding reception DMAC among the plurality of reception DMACs; The receiving DMAC that has received the receiving DMA request signal reads the received data from the buffering memory that has transmitted the receiving DMA request signal and transfers the read data to the memory, and when the transfer of the received data is completed, transmits a transfer completion interrupt signal to a corresponding CPU among the plurality of CPUs, notifying that the transfer of the received data to the memory has been completed; The CPU that has received the transfer end interrupt signal acquires the data size of the received data from the DMAC that has sent the receive DMA request signal, and performs processing to read the received data from the memory based on the data size. A communication device comprising:

3. A multi-core CPU consisting of multiple CPUs that implement applications; a reception frame processing unit that determines the Ethertype of received data and distributes the received data according to the Ethertype; a plurality of buffering memories for receiving the received data sorted by the received frame processing unit and storing the data by Ethertype; a memory for storing data to be processed by each CPU of the multi-core CPU; a general-purpose DMAC that reads received data from the plurality of buffering memories and transfers the data to the memory; Equipped with each of the plurality of buffering memories, when receiving the reception data allocated by the reception frame processing unit, transmits a reception interrupt signal to a corresponding CPU among the plurality of CPUs; The CPU that has received the reception interrupt signal acquires the data size of the received data from the buffering memory that has transmitted the reception interrupt signal, and performs DMA transfer setting and transfer permission for the general-purpose DMAC; The general-purpose DMAC that has received the DMA transfer setting and transfer permission executes the DMA transfer from the plurality of buffering memories to the memory, and then transmits a transfer end interrupt signal to a corresponding CPU among the plurality of CPUs; The CPU that has received the transfer end interrupt signal performs processing to read the received data from the memory. A communication device comprising:

4. The plurality of buffering memories are FIFO memories.

4. The communication device according to claim 1, wherein the first and second communication devices are connected to each other.

5. An interrupt controller that distributes a plurality of interrupt causes to each CPU of the multi-core CPU is further provided.

4. The communication device according to claim 1, wherein the first and second communication devices are connected to each other.

6. Further comprising: a memory for storing data to be processed by each CPU of the multi-core CPU.

2. The communication device according to claim 1.

7. The multi-core CPU further includes a memory controller connected to the memory and controlling memory access of each CPU of the multi-core CPU.

7. The communication device according to claim 2, claim 3, or claim 6.

8. an interconnect bridge for transferring data from the plurality of buffering memories to the memory; 8. The communication device according to claim 7,

9. A method for processing received data in a communication device having a multi-core CPU configured with a plurality of CPUs that implement applications, comprising: a processing step of determining the Ethertype of received data and sorting the received data according to the Ethertype; a storage step of storing the received data sorted in the processing step in a plurality of buffering memories by Ethertype; a read processing step for reading the received data stored in the plurality of buffering memories; and In the storing step, when each of the plurality of buffering memories receives the reception data allocated in the processing step, it transmits a reception interrupt signal to a corresponding CPU among the plurality of CPUs; In the read processing step, the CPU that has received the reception interrupt signal acquires the data size of the reception data from the buffering memory that has transmitted the reception interrupt signal, and performs processing to read the reception data based on the data size. A method for processing received data in a communication device.

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