Amplifier circuit, switching power supply circuit, and switching power supply device

Abstract

An amplification circuit configured to generate an error voltage corresponding to a difference between a subject voltage and a reference voltage, the amplification circuit comprising: a first differential input pair including a first transistor configured to receive the subject voltage at a gate thereof and a second transistor configured to receive the reference voltage at a gate thereof; and a second differential input pair including a third transistor configured to receive the subject voltage at a gate thereof and a fourth transistor configured to receive the reference voltage at a gate thereof. The error voltage is generated using the first differential input pair or the second differential input pair depending on the reference voltage. The first transistor and the second transistor are formed of P-channel MOSFETs. The third transistor and the fourth transistor are formed of N-channel MOSFETs.

Description

[Technical Field]

[0001] The present disclosure relates to an amplifier circuit, a switching power supply circuit, and a switching power supply device. [Background technology]

[0002] Various devices are equipped with amplifier circuits that generate an error voltage corresponding to the difference between two voltages. For example, in a switching power supply device that generates an output voltage by switching an input voltage, an amplifier circuit is provided that compares a feedback voltage based on the output voltage with a reference voltage to generate an error voltage corresponding to the difference between the two, and performs switching operation according to the error voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-221099 Summary of the Invention [Problem to be solved by the invention]

[0004] Low noise is important for amplifier circuits and devices (such as switching power supplies) in which the amplifier circuits are installed.

[0005] An object of the present disclosure is to provide an amplifier circuit, a switching power supply circuit, and a switching power supply device that contribute to noise reduction. [Means for solving the problem]

[0006] An amplifier circuit according to the present disclosure is an amplifier circuit configured to generate an error voltage corresponding to a difference between a target voltage and a reference voltage, comprising: a first differential input pair having a first transistor configured to receive the target voltage at its gate and a second transistor configured to receive the reference voltage at its gate; and a second differential input pair having a third transistor configured to receive the target voltage at its gate and a fourth transistor configured to receive the reference voltage at its gate; the amplifier circuit generates the error voltage using the first differential input pair or the second differential input pair according to the reference voltage, the first transistor and the second transistor being formed of P-channel MOSFETs, and the third transistor and the fourth transistor being formed of N-channel MOSFETs.

[0007] According to the present disclosure, it is possible to provide an amplifier circuit, a switching power supply circuit, and a switching power supply device that contribute to noise reduction. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating the overall configuration of a switching power supply device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is an external view of the semiconductor device according to the embodiment of the present disclosure. [Figure 3] FIG. 3 is a waveform diagram of a signal (SET) according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating the relationships between multiple signals according to an embodiment of the present disclosure. [Figure 5A] FIG. 5A is a configuration diagram of a slope voltage generating circuit according to an embodiment of the present disclosure. [Figure 5B] FIG. 5B is an explanatory diagram of a slope voltage according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is an explanatory diagram of a switching operation performed by a semiconductor device according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram showing how the reference voltage changes according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a configuration diagram of an error amplifier according to a reference example. [Figure 9] FIG. 9 is a configuration diagram of an error amplifier according to a first example belonging to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram illustrating two states according to a first example of the embodiment of the present disclosure. [Figure 11] FIG. 11 is a diagram for comparing noise characteristics between the reference example and the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, identical parts are designated by the same reference numerals, and redundant descriptions of identical parts will be omitted as a general rule. For the sake of simplicity, this specification may use symbols or characters referring to information, signals, physical quantities, elements, or parts, and may omit or abbreviate the names of the information, signals, physical quantities, elements, or parts corresponding to the symbols or characters. For example, the high-side transistor referred to by "M1" (see FIG. 1) described below may be written as high-side transistor M1 or abbreviated as transistor M1, but these terms all refer to the same thing.

[0010] First, some terms used in describing the embodiments of the present disclosure will be explained. A line refers to a wiring through which an electrical signal is propagated or applied. A ground refers to a reference conductive portion having a reference potential of 0V (zero volts), or refers to the 0V potential itself. The reference conductive portion is formed of a conductor such as metal. A 0V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a specific reference represents a potential seen from ground. A level refers to a potential level, and for any given signal or voltage, a high level has a higher potential than a low level. Any digital signal can have a high or low signal level. For any given signal or voltage, a high level signal or voltage strictly means that the signal or voltage level is high, and a low level signal or voltage strictly means that the signal or voltage level is low. For any given signal or voltage, a transition from a low level to a high level is called an up-edge (or rising edge), and a transition from a high level to a low level is called a down-edge (or falling edge).

[0011] For any transistor configured as a FET (field-effect transistor), including a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Hereinafter, the on and off states of any transistor may be simply referred to as on and off. Furthermore, for any transistor, the period in which the transistor is on may be referred to as the on period, and the period in which the transistor is off may be referred to as the off period.

[0012] For any signal that takes a high or low signal level, the period during which the signal level is high is referred to as a high-level period, and the period during which the signal level is low is referred to as a low-level period. The same applies to any voltage that takes a high or low voltage level. Unless otherwise specified, connections between multiple parts that form a circuit, such as any circuit elements, wiring (lines), nodes, etc., refer to electrical connections.

[0013] 1 is a diagram illustrating the overall configuration of a switching power supply device AP according to an embodiment of the present disclosure. IN to input voltage V IN Output voltage V OUT It is configured as a step-down DC / DC converter that generates an input voltage V IN and output voltage V OUT is a positive DC voltage. The switching power supply device AP includes a semiconductor device 1 as a switching power supply circuit and a switching voltage V SW The output voltage V OUT The semiconductor device 1 is a so-called power supply IC. The rectifying and smoothing circuit 2 is made up of an inductor L1 and an output capacitor C1.

[0014] FIG. 2 shows an example of the appearance of the semiconductor device 1. The semiconductor device 1 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals exposed from the housing to the outside of the semiconductor device 1. The semiconductor device 1 is formed by encapsulating the semiconductor chip in a housing (package) made of resin. Each circuit that forms the semiconductor device 1 (including a control block 10, an output stage circuit 20, and an internal power supply circuit 30, which will be described later) is included in the semiconductor integrated circuit. Note that the number of external terminals of the semiconductor device 1 and the type of housing of the semiconductor device 1 shown in FIG. 2 are merely examples, and can be designed as desired.

[0015] 1 shows external terminals IN, SW, GND, and FB as some of the external terminals provided on the semiconductor device 1. The external terminal IN is connected to an input voltage V IN The input terminal IN is the input terminal that receives the input voltage V, and the external terminal GND is the ground terminal that should be connected to ground. IN is applied and the ground terminal GND is connected to ground. IN Since the input terminal IN has a positive DC voltage value, the ground terminal GND is provided at a lower potential side than the input terminal IN. The external terminal SW is a switch terminal connected to a node ND1, which will be described later. The external terminal FB is connected to the feedback voltage V FB In the switching power supply AP, the output voltage V OUT The node ND2 to which the feedback voltage V is applied is directly connected to the feedback terminal FB. FB is the output voltage V OUT is equal to.

[0016] The semiconductor device 1 includes a control block 10, an output stage circuit 20, and an internal power supply circuit 30. In addition, a backflow detection circuit, an abnormality detection and protection circuit, etc. are also provided, but illustration and description of these will be omitted here. The output stage circuit 20 may also be provided outside the semiconductor device 1 and externally connected to the semiconductor device 1.

[0017] The output stage circuit 20 includes a high-side transistor M1 that functions as an output transistor and a low-side transistor M2 that functions as a synchronous rectifier transistor, and is configured to convert an input voltage V INThe transistors M1 and M2 are connected in series. That is, the output stage circuit 20 has a series circuit of the transistors M1 and M2. The switching power supply AP performs DC-DC conversion using the transistors M1 and M2 with synchronous rectification. The transistors M1 and M2 are configured as N-channel MOSFETs. Note that a modification is also possible in which the transistor M1 is configured as a P-channel MOSFET. Furthermore, the transistor M2 can be replaced with a diode, in which case the switching power supply AP performs DC-DC conversion with asynchronous rectification.

[0018] The drain of transistor M1 is connected to the input terminal IN, and therefore to the input voltage V IN The source of the transistor M1 and the drain of the transistor M2 are connected together at a node ND1. The source of the transistor M2 is connected to the ground terminal GND (and therefore to the ground). The voltage generated at the node ND1 is called the switch voltage and is denoted by the symbol "V SW Inside the semiconductor device 1, the switch terminal SW is connected to a node ND1, and outside the semiconductor device 1, the switch terminal SW is connected to one end of the inductor L1. Therefore, the switch terminal SW is interposed between one end of the inductor L1 and the node ND1. The other end of the inductor L1 is connected to a node ND2. An output voltage V OUT An output capacitor C1 is connected between the node ND2 and ground. If the transistor M1 is configured as a P-channel MOSFET, the relationship between the source and drain of the transistor M1 will be reversed (i.e., the source and drain of the transistor M1 will be connected to the input terminal IN and the node ND1, respectively).

[0019] In Figure 1, "LD" represents a load connected between node ND2 and ground. The load LD is connected to the output voltage V OUT The current flowing through the inductor L1 is called the inductor current and is represented by the symbol "I L " is expressed as

[0020] The control block 10 controls the output voltage V OUT information (i.e., feedback voltage V FB ) and the inductor current I L Based on this information, the transistors M1 and M2 are controlled to be on / off, thereby controlling the output voltage V OUT to a predetermined target voltage V TG (for example, 0.9 V). That is, the control block 10 can drive the transistors M1 and M2 by a so-called current mode control method. Here, the current I flowing through the transistor M1 during the ON period of the transistor M1 is M1 , the inductor current I L Used as information.

[0021] The control block 10 controls the state of the transistor M1 by supplying a gate signal G1 to the gate of the transistor M1, and controls the state of the transistor M2 by supplying a gate signal G2 to the gate of the transistor M2. The transistor M1 is in an on state during a high-level period of the gate signal G1 and is in an off state during a low-level period of the gate signal G1. The transistor M2 is in an on state during a high-level period of the gate signal G2 and is in an off state during a low-level period of the gate signal G2. The control block 10 controls and sets the state of the output stage circuit 20 to one of an output high state, an output low state, and a both-off state. In the output high state, the transistor M1 is in an on state and the transistor M2 is in an off state. In the output low state, the transistor M1 is in an off state and the transistor M2 is in an on state. In the both-off state, the transistors M1 and M2 are both in an off state. The transistors M1 and M2 are never both in an on state.

[0022] The internal power supply circuit 30 receives an input voltage V IN A predetermined internal power supply voltage is generated from the internal power supply voltage. Each circuit constituting the control block 10 is driven based on the internal power supply voltage. There may be multiple internal power supply voltages.

[0023] The control block 10 includes an error amplifier 11, a reference voltage supply circuit 12, a slope voltage generation circuit 13, a main comparator 14, a set signal generation circuit 15, a PWM circuit 16, and a gate driver 17. Note that "PWM" is an abbreviation for pulse width modulation.

[0024] The error amplifier 11 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal of the error amplifier 11 is connected to a feedback terminal FB. Therefore, the inverting input terminal of the error amplifier 11 receives a feedback voltage V FB The non-inverting input terminal of the error amplifier 11 is supplied with a reference voltage V REF The output terminal of the error amplifier 11 is connected to the line LN1. The error amplifier 11 detects the feedback voltage V applied to the inverting input terminal. FB and the reference voltage V applied to the non-inverting input terminal REF Error voltage V according to the difference voltage between CMP The error amplifier 11 generates an error voltage V on the line LN1 by inputting and outputting a charge based on an error current signal corresponding to the difference voltage to and from the line LN1. CMP Specifically, the error amplifier 11 generates a reference voltage V REF is the feedback voltage V FB When the error voltage V CMP The current generated by the error current signal is output to line LN1 so that the feedback voltage V FB is the reference voltage V REF When the error voltage V CMP The current due to the error current signal is drawn from the line LN1 to the error amplifier 11 so that the reference voltage V REF and feedback voltage V FB As the absolute value of the difference voltage between the line LN1 and the error current signal increases, the magnitude of the current due to the error current signal also increases. Note that a phase compensation unit (not shown) consisting of a series circuit of a resistor and a capacitor may be provided between the line LN1 and ground, and this phase compensation unit cooperates with the error amplifier 11 to apply the error voltage V CMP This causes

[0025] The reference voltage supply circuit 12 supplies a reference voltage VREF and generate the reference voltage V REF is supplied to the non-inverting input terminal of the error amplifier 11.

[0026] The slope voltage generating circuit 13 controls the current I flowing through the transistor M1 during the ON period of the transistor M1. M1 The slope voltage V SLP Generates a current I M1 Inductor current I L Contains information on:

[0027] The main comparator 14 outputs the slope voltage V SLP and the error voltage V CMP The slope voltage V is compared with the slope voltage V and outputs a digital signal RST that indicates the comparison result. SLP is the error voltage V CMP When the voltage is higher than the reference voltage, the signal RST goes high and the slope voltage V SLP is the error voltage V CMP When the slope voltage V is lower than the reference voltage V, the signal RST is at a low level. SLP is the error voltage V CMP When the signal RST matches the slope voltage V, the signal RST goes to high level or low level. Of the output signals RST from the main comparator 14, only the high level signal RST functions as a reset signal, and the low level signal RST does not correspond to the reset signal. Hereinafter, the output of the high level signal RST from the main comparator 14 may be expressed as issuing or outputting a reset signal. The main comparator 14 operates based on the slope voltage V SLP and error voltage V CMP It functions as a reset signal issuing circuit that issues a reset signal based on the

[0028] The set signal issuing circuit 15 outputs a signal SET, which is a digital signal, to the PWM circuit 16. Of the output signals SET from the set signal issuing circuit 15, only the high level signal SET functions as a set signal, and the low level signal SET does not correspond to a set signal. Hereinafter, the output of the high level signal SET from the set signal issuing circuit 15 may be expressed as issuing or outputting a set signal. The set signal issuing circuit 15 outputs a signal SET at a predetermined frequency f CLK That is, as shown in FIG. 3, the set signal issuing circuit 15 can issue a set signal periodically at a predetermined frequency f CLK The signal SET includes pulses that are at a high level for a predetermined short time, and the pulses in the signal SET have a frequency of f CLK It occurs repeatedly at intervals equal to the reciprocal of .

[0029] The PWM circuit 16 is configured with logic circuits such as flip-flops, and generates and outputs a control signal CNT that specifies the on / off state of the transistors M1 and M2 based on the signal SET from the set signal issuing circuit 15 and the signal RST from the main comparator 14. The gate driver 17 controls a gate signal G1 of the transistor M1 and a gate signal G2 of the transistor M2 based on the control signal CNT.

[0030] FIG. 4 shows the relationship between the signals SET, RST, CNT, G1, and G2. The signals SET, RST, CNT, G1, and G2 are binary signals that are either high or low. When the signal RST is low and a high-level signal SET is input to the PWM circuit 16 (i.e., when a set signal is issued), the control signal CNT goes high. Thereafter, the control signal CNT is held high until a high-level signal RST is input to the PWM circuit 16 (i.e., until a reset signal is issued). When the signal SET is low and a high-level signal RST is input to the PWM circuit 16 (i.e., when a reset signal is issued), the control signal CNT goes low. Thereafter, the control signal CNT is held low until a high-level signal SET is input to the PWM circuit 16 (i.e., until a set signal is issued). While both the signals SET and RST are low, the control signal CNT is maintained at the held level. In the control block 10, the signals SET and RST are never simultaneously high.

[0031] The gate driver 17 sets the gate signals G1 and G2 to high and low levels, respectively, during a high-level period of the control signal CNT, thereby putting the output stage circuit 20 into an output high state. The gate driver 17 sets the gate signals G1 and G2 to low and high levels, respectively, during a low-level period of the control signal CNT, thereby putting the output stage circuit 20 into an output low state. Note that when a backflow current is detected or an abnormality occurs, controls other than those described above are executed, but their explanation will be omitted here. Backflow current refers to a current that flows from inductor L1 through node ND1 and transistor M2 toward ground.

[0032] The control block 10 configured as described above controls the feedback voltage V FB and slope voltage V SLP The output voltage V OUT to a predetermined target voltage V TGIn the switching operation, the transistors M1 and M2 are alternately turned on and off, which is a concept that includes the presence of both off states, taking into account dead time, etc., between the transition between the output low state and the output high state.

[0033] The above switching operation generates an input voltage V IN In other words, the switching operation effectively switches the input voltage V IN The voltage V is a square wave whose level fluctuates between the ground level and the ground level. SW The switch voltage V SW is rectified and smoothed by inductor L1 and output capacitor C1 to produce a DC output voltage V OUT is obtained.

[0034] In the control block 10, the feedback voltage V FB and the reference voltage V REF Therefore, feedback control is performed to reduce the differential voltage between the output voltage V OUT The target voltage V TG is the reference voltage V REF Furthermore, in the switching power supply AP, the output voltage V OUT It is the feedback voltage V FB Therefore, the target voltage V TG is the reference voltage V REF As a result, the output voltage V OUT is the reference voltage V REF Feedback control is then performed to stabilize the output.

[0035] Slope voltage V SLP The current I that flows through the transistor M1 during the ON period of the transistor M1 is M1 is the inductor current I during the on-period of transistor M1. L Therefore, the slope voltage V SLP is the inductor current I during the on-period of transistor M1 LThat is, the slope voltage V SLP contains the current information of the transistor M1 or the inductor L1 during the ON period of the transistor M1. The slope voltage V SLP Any known method can be used to generate the slope voltage V. FIG. 5A shows an example of the configuration of the slope voltage generation circuit 13, and FIG. SLP 5A shows waveforms of current and voltage involved in the above. The slope voltage generating circuit 13 in FIG. 5A includes an IV converter 13a, a ramp voltage generating circuit 13b, and an adder 13c. The IV converter 13a calculates the current I flowing through the transistor M1 during the ON period of the transistor M1. M1 (That is, the inductor current I L ) is converted into a voltage, M1 The sense voltage V is proportional to SNS The ramp voltage generating circuit 13b generates a sawtooth ramp voltage V that gradually increases from 0 V during the ON period of the transistor M1. RMP The adder 13c generates the sense voltage V SNS and lamp voltage V RMP The sum of these voltages is the slope voltage V SLP During periods other than the on-period of the transistor M1, the slope voltage V SLP is 0V (however, it may have a predetermined bias voltage value). As is well known, the lamp voltage V RMP By adding the above, it is possible to suppress oscillation of the output feedback loop in current mode control.

[0036] 6 shows a timing chart of the switching operation performed during feedback control. At a timing t A0 Consider starting from timing t A0 Then the slope voltage V SLP is 0V, and then at timing t A1 A rising edge occurs in the signal SET at timing t A1In response to the issuance of the set signal, the control signal CNT switches from low level to high level, and the output stage circuit 20 switches from an output low state to an output high state. During the period when the output stage circuit 20 is in the output high state, the inductor current I L gradually increases, and the slope voltage V SLP The error voltage V CMP The slope voltage V was less than SLP is timing t A2 Error voltage V CMP When the output voltage V reaches the threshold voltage V , the output signal RST of the main comparator 14 switches from low to high, i.e., a reset signal is issued. In response to the issuance of the reset signal, the control signal CNT switches from high to low, and the output stage circuit 20 switches from an output high state to an output low state. When the output stage circuit 20 enters the output low state, the slope voltage V SLP falls to 0 V, the signal RST returns to low level, and the same operation is then repeated.

[0037] The set signal has frequency f CLK Since the pulses are repeatedly turned on at intervals that are the reciprocal of CLK In other words, in the switching power supply AP, the input voltage V IN is the frequency f CLK The output voltage V OUT The frequency f CLK can be constant or can be varied using spread spectrum techniques at a frequency f CLK Although not shown in the figure, when the current consumption of the load LD decreases based on a certain state, the error voltage V CMP Decrease in inductor current I L When the average value of the error voltage V CMP rise, the inductor current I L and the output duty cycle increases, which causes the output voltage V OUT is the target power supply VTG The output duty represents the ratio of the period during which the output stage circuit 20 is in the output high state to the sum of the period during which the output stage circuit 20 is in the output high state and the period during which the output stage circuit 20 is in the output low state.

[0038] Figure 7 shows the reference voltage V REF The change in the reference voltage V REF is the input voltage V to the input terminal IN IN Timing t after supply begins B1 At the specified lower limit voltage V L The reference voltage supply circuit 12 has a timing t B1 From timing t B1 A timing later than t B2 The reference voltage V REF to the predetermined lower limit voltage V L to a predetermined upper limit voltage V H and the timing t B2 After that, the reference voltage V REF The upper limit voltage V H Lower limit voltage V L is 0V (zero volts), and the upper limit voltage V H is the output voltage V OUT The target voltage V TG As a result, when the semiconductor device 1 and the switching power supply device AP are started up, the output voltage V OUT Gradually change from 0V to the target voltage V TG The soft start operation described with reference to FIG. B1 It is executed at any time thereafter. L may be other than 0V (however, V L <V H ).

[0039] <<Reference example>> The semiconductor device 1 has a unique configuration in the error amplifier 11. Prior to describing this unique configuration, the configuration of an error amplifier 11r according to a reference example is shown in FIG. 8. The error amplifier 11r according to the reference example has a differential input pair 910 consisting of transistors 911 and 912. An output voltage V OUT The divided voltage is the feedback voltage V FB ', and the gate of transistor 912 is connected to the reference voltage V REF is input. The error amplifier 11r then outputs the feedback voltage V FB ' and reference voltage V REF Error voltage V according to the difference voltage between CMP When the semiconductor device 1 and the switching power supply device AP are started, the reference voltage V REF Since the channel type of the transistors 911 and 912 is N-channel, the gate-source voltage required for the operation of the transistors 911 and 912 cannot be secured, and the differential input pair 910 does not operate correctly (the feedback voltage V FB ' and reference voltage V REF Error voltage V according to the difference voltage between CMP Therefore, in the error amplifier 11r, the transistors 911 and 912 are formed by P-channel MOSFETs.

[0040] In addition, the error amplifier 11r FB '=V OUT " is also possible, but "V FB '=V OUT ", the power supply voltage VDD' of the error amplifier 11r is set to the output voltage V OUT and the gate threshold voltage of the P-channel MOSFET. This is disadvantageous for power saving, etc. In order to operate the error amplifier 11r correctly under the constraint that the power supply voltage VDD' cannot be increased, the output voltage V OUT Therefore, in the configuration of Figure 8, the output voltage V OUT The output voltage V OUT and generates a divided voltage of V FB' is used as.

[0041] However, the output voltage V OUT When the resistor divider is used, the output voltage V OUT This will be explained using a simple numerical example. OUT The target voltage V TG is 0.9V, and “V FB '=(1 / 3)V OUT In this case, the reference voltage V REF (i.e., upper limit voltage V H ) is set to 0.3V. Now, after the soft start operation is completed, the reference voltage V REF Suppose that the output voltage V is shifted by 0.1V from the set voltage "0.3V" due to noise and becomes 0.4V. Then, the output voltage V OUT is controlled to 1.2V. That is, the output voltage V OUT is the target voltage V TG On the other hand, in the above numerical example, "V FB '=V OUT ", the reference voltage V after the soft start operation is completed. REF (i.e., upper limit voltage V H ) is set to 0.9V. Then, the reference voltage V REF Even if the output voltage V OUT is controlled to 1.0V, so the output voltage V OUT The target voltage V TG The deviation from this is only 0.1V.

[0042] Thus, the output voltage V OUT The resistor divider of the output voltage V OUT This is a factor that increases noise in the output voltage V OUT Although it would be advantageous to reduce noise if the resistor division is not performed, the configuration of FIG. 8 requires resistor division due to restrictions on the power supply voltage VDD' and other factors.

[0043] Considering these factors, the output voltage V OUT A configuration that contributes to noise reduction is adopted for the error amplifier 11. Below, several specific configuration examples, application techniques, modified techniques, etc. related to the switching power supply device AP (particularly the error amplifier 11) will be described in multiple embodiments. The matters described above in this embodiment (excluding matters related to the reference example) apply to each of the following embodiments unless otherwise specified and unless contradicted. If there are any matters in each embodiment that contradict the matters described above, the description in that embodiment may take precedence. Furthermore, unless contradicted, matters described in any of the multiple embodiments described below can also be applied to any of the other embodiments (i.e., any two or more of the multiple embodiments can be combined).

[0044] <<First Example>> A first embodiment will be described. FIG. 9 is a circuit diagram of an error amplifier 100 according to the first embodiment. In the first embodiment, the error amplifier 100 is used as the error amplifier 11 in FIG. 1. In short, in the first embodiment, the output voltage V OUT output voltage V OUT The feedback voltage V FB When the semiconductor device 1 and the switching power supply device AP are started up (during the soft start operation), the error voltage V CMP After the startup of the semiconductor device 1 and the switching power supply AP is completed (after the soft start operation is completed), the error voltage V is generated using the differential input pair 120 configured with N-channel MOSFETs. CMP The configuration and operation of the error amplifier 100 in FIG. 9 will be described in detail below.

[0045] The error amplifier 100 includes transistors 111, 112, 121, 122, 131, 141 to 148, 161 to 166, and 171 to 174. Of these transistors, the transistors 111, 112, 141 to 144, and 161 to 166 are formed of P-channel MOSFETs, and the transistors 121, 122, 131, 145 to 148, and 171 to 174 are formed of N-channel MOSFETs.

[0046] The error amplifier 100 also includes a constant current source 160 and resistors 149, 150, 167, 170, and 175 to 177. The error amplifier 100 also includes a plurality of lines, including lines LN11 to LN17, LN21, and LN22, shown in FIG. 9. The line LN11 is a power supply line to which a power supply voltage VDD is applied. The power supply voltage VDD has a predetermined positive DC voltage value (e.g., 1.5 V). The power supply voltage VDD may be generated by the internal power supply circuit 30 (see FIG. 1). The line LN17 is a ground line having ground potential (i.e., a potential of 0 V).

[0047] Furthermore, the error amplifier 100 has terminals 101 to 103. The terminals 101 and 102 are the inverting input terminal and the non-inverting input terminal of the error amplifier 100, respectively. Therefore, the terminals 101 and 102 function as the inverting input terminal and the non-inverting input terminal of the error amplifier 11 in FIG. 1, respectively, and the feedback voltage V FB is input, while the reference voltage V REF is input to the terminal 103. The terminal 103 is the output terminal of the error amplifier 100. Therefore, the terminal 103 functions as the output terminal of the error amplifier 11 in FIG. 1, and the terminal 103 is connected to the line LN1 in FIG. 1 outside the error amplifier 100 (the state of connection to the line LN1 is not shown in FIG. 9).

[0048] The transistors 111 and 112 form a differential input pair 110 (first differential input pair). The transistors 111 and 112 are two P-channel MOSFETs having a common structure. The transistors 111 and 112 are arranged close to each other so that the temperatures of the transistors 111 and 112 are substantially the same. The transistors 121 and 122 form a differential input pair 120 (second differential input pair). The transistors 121 and 122 are two N-channel MOSFETs having a common structure. The transistors 121 and 122 are arranged close to each other so that the temperatures of the transistors 121 and 122 are substantially the same. It is preferable to use N-channel MOSFETs with high noise immunity (in other words, low-noise N-channel MOSFETs) as the transistors 121 and 122.

[0049] The transistor 131 forms a flow path switching circuit 130. The function of the flow path switching circuit 130 will become clear from the following description. Furthermore, the transistors 141 to 148 and the resistors 149 and 150 form an error voltage generating circuit 140.

[0050] The connection relationships of the circuit elements of the error amplifier 100 will now be described. The sources of transistors 161, 162, 165, 141, and 142 are connected to the power supply line LN11. Resistors may be individually inserted between the sources of transistors 161, 162, 165, 141, and 142 and the power supply line LN11. The gates of transistors 161, 162, 165, 141, and 142 and the drain of transistor 163 are commonly connected to line LN12. The drains of transistors 161, 162, 165, 141, and 142 are respectively connected to the sources of transistors 163, 164, 166, 143, and 144. The gates of transistors 163, 164, 166, 143, and 144 are commonly connected to line LN13. The drain of transistor 163 is also connected to line LN13 via resistor 167. A constant current source 160 is provided between the line LN13 and ground.

[0051] The drain of the transistor 166 is connected to the line LN14. The sources of the transistors 111 and 112 and the drain of the transistor 131 are also connected to the line LN14. The gates of the transistors 111 and 121 are connected to each other. The gates of the transistors 111 and 121 are connected to the terminal 101 via a resistor 177. It is also possible to omit the resistor 177. In this case, the gates of the transistors 111 and 121 are directly connected to the terminal 101. In either case, a feedback voltage V FB The gates of the transistors 112, 122, and 131 are connected to each other, and the gates of the transistors 112, 122, and 131 are connected to the terminal 102. Therefore, the reference voltage V REF is applied, and the gate of transistor 131 is also applied with the reference voltage V REF The source of transistor 131 is connected to ground.

[0052] The drain of transistor 143, the drain of transistor 145, and the gates of transistors 147 and 148 are commonly connected to line LN21. The drain of transistor 144 and the drain of transistor 146 are commonly connected to line LN22. Line LN22 is also connected to terminal 103. The source of transistor 145, the drain of transistor 147, and the drain of transistor 112 are connected to one another. The source of transistor 146, the drain of transistor 148, and the drain of transistor 111 are connected to one another. The source of transistor 147 is connected to ground line LN17 via resistor 149, and the source of transistor 148 is connected to ground line LN17 via resistor 150.

[0053] The drain of transistor 121 is connected to the drain of transistor 142 and the source of transistor 144. The drain of transistor 122 is connected to the drain of transistor 141 and the source of transistor 143. The sources of transistors 121 and 122 and the drain of transistor 172 are commonly connected to line LN15. The source of transistor 172 is connected to the drain of transistor 174. The source of transistor 174 is connected to ground line LN17 via resistor 176.

[0054] The drain of transistor 164 and the gates of transistors 171, 172, 145, and 146 are commonly connected to line LN16. The drain of transistor 164 is connected to the drain of transistor 171 via resistor 170. The drain of transistor 171 is connected to the gates of transistors 173 and 174. The source of transistor 171 is connected to the drain of transistor 173. The source of transistor 173 is connected to ground line LN17 via resistor 175.

[0055] The operation of the error amplifier 100 will now be described. The constant current source 160 performs a constant current operation, flowing a predetermined constant current from the line LN13 to the ground. When the constant current source 160 performs a constant current operation, a drain current flows through the transistors 161 to 164, and when a positive voltage is applied to the line LN16, the transistors 171, 172, 145, and 146, which function as switches, are turned on. This results in a state in which a drain current flows through the transistors 171 to 174 and a drain current flows through the transistors 141 to 148. When the constant current operation is not performed, no drain current flows through the transistors constituting the error amplifier 100, and the operation of the error amplifier 100 stops. The control block 10 (see FIG. 1) can control whether or not the constant current source 160 performs the constant current operation. At least, at the timing t B1 Thereafter, constant current operation is always performed by the constant current source 160. Hereinafter, it is assumed that the constant current operation by the constant current source 160 is continuously performed.

[0056] Transistors 165 and 166 cooperate with transistors 161 and 163, resistor 167, and constant current source 160 to generate a constant current I having a first predetermined current value. PT Therefore, the error amplifier 100 generates a constant current I PT The main components of the first constant current generating circuit are transistors 165 and 166, but it may also be understood that the components of the first constant current generating circuit include transistors 161 and 163, resistor 167, and constant current source 160. PT flows from the power supply line LN11 through the transistors 165 and 166 toward the line LN14.

[0057] Transistor 174 and resistor 176 cooperate with transistor 173 and resistor 175, transistors 162 and 164, and constant current source 160 to generate a constant current I having a second predetermined current value. NT Therefore, the error amplifier 100 generates a constant current I NT The main components of the second constant current generating circuit are a transistor 174 and a resistor 176, but it may also be understood that the components of the second constant current generating circuit include a transistor 173, a resistor 175, transistors 162 and 164, and a constant current source 160. NT flows from the line LN15 through the transistors 172 and 174 and the resistor 176 toward the ground line LN17.

[0058] However, the voltage V applied to terminals 101 and 102 FB and V REF Only after the second constant current generating circuit is activated does the constant current I NT has a second predetermined current value. That is, for example, the voltage V FB and V REF When the voltage is 0V or close to 0V, no substantial current flows through the transistors 121 and 122, so a constant current I that should correspond to the sum of the drain currents of the transistors 121 and 122 flows. NT The value of V is also essentially zero.FB and V REF is the upper limit voltage V H or when the upper limit voltage V H Lower than the upper limit voltage V H When the voltage is close to NT has a second predetermined current value.

[0059] Hereinafter, the drain current of the transistor 111 is represented by the symbol "I P1 The drain current of the transistor 112 is sometimes referred to as "I P2 In the following description, the drain current of the transistor 121 will be referred to as "I N1 The drain current of transistor 122 is sometimes referred to as "I N2 " may be referred to.

[0060] The flow path switching circuit 130 is connected to a reference voltage V REF Based on the constant current I PT The flow path is switched between a first flow path and a second flow path. The first flow path is a flow path that passes through the differential input pair 110. More specifically, the first flow path is a flow path that passes through the differential input pair 110 and does not pass through the transistor 131. The second flow path is a flow path that does not pass through the differential input pair 110. More specifically, the second flow path is a flow path that does not pass through the differential input pair 110 and passes through the transistor 131.

[0061] The flow path switching circuit 130 is connected to a reference voltage V REF In a state where the current I is relatively low (hereinafter referred to as state ST1), PT The flow path is set as the first flow path, and the reference voltage V REF In a state where the current I PT The flow path is set as the second flow path. The reference voltage V REF is the reference voltage V in state ST1 REF Higher than the reference voltage V REF is the lower limit voltage V L to upper limit voltage V H (See Figure 7) REFis in state ST1. REF If the reference voltage V REF The state of ST2 is reached by at least the reference voltage V REF is the upper limit voltage V H When it matches, the reference voltage V REF The state of is state ST2.

[0062] This can also be considered as follows: Referring to Figure 10, the lower limit voltage V L Higher than the upper limit voltage V H A given voltage lower than the intermediate voltage V M In this case, the reference voltage V REF is the intermediate voltage V M The state where the reference voltage V REF is the intermediate voltage V M The state where the reference voltage V is higher corresponds to state ST2. REF is the intermediate voltage V M A state that exactly matches is classified as either state ST1 or ST2.

[0063] In the configuration example of FIG. 9, a transistor 131 that functions as a flow path switching transistor (flow path switching switch) is used to generate a constant current I PT In state ST1, the transistor 131 is in an off state, while in state ST2, the transistor 131 is in an on state. In the configuration example of FIG. 9, the source of the transistor 131 is connected to ground, so that the intermediate voltage V M corresponds to the gate threshold voltage of the transistor 131. When the gate-source voltage of the transistor 131 (gate potential viewed from the source potential) is equal to or higher than the gate threshold voltage of the transistor 131, the transistor 131 is in an on state, and when not, the transistor 131 is in an off state. However, the source of the transistor 131 may be connected to a terminal (not shown) to which a fixed potential other than 0V is applied. In any case, the reference voltage V REF is the intermediate voltage V M When the voltage is lower than the reference voltage V REF is the intermediate voltage V MIn a state where the potential is higher than the reference potential (i.e., state ST2), the transistor 131 is turned on.

[0064] In state ST1, the transistor 131 is off, so the constant current I PT is the drain current I of transistor 111 P1 and the drain current I of the transistor 112 P2 Therefore, in state ST1, the drain current I P1 and I P2 The magnitude of the sum is the constant current I PT In state ST2, the transistor 131 is on, so the constant current I PT flows to the transistor 131, and the drain current I P1 and I P2 are both zero.

[0065] Strictly speaking, the reference voltage V REF is the lower limit voltage V L to upper limit voltage V H During the transition from state ST1 to state ST2, an intermediate state occurs in which a drain current flows through each of the transistors 111, 112, and 131, even though it is for a short time. In the intermediate state, the reference voltage V REF is applied to the gate of transistor 131, but the constant current I PT The reference voltage V REF This corresponds to a state in which the error amplifier 100 is not yet increased. However, the length of the period in which such an intermediate state is realized is very short, and the existence of the intermediate state does not significantly affect the operation of the error amplifier 100. Therefore, the existence of the intermediate state will be ignored below and the operation of the error amplifier 100 in states ST1 and ST2 will be described.

[0066] First, the operation in state ST1 will be described. In state ST1, the reference voltage V REF is relatively low and the reference voltage V REFThe feedback voltage V should be equal to FB Therefore, in state ST1, “I N1 =I N2 =0”, resulting in a constant current I NT (i.e., "I NT =0"). Instead, in state ST1, the constant current I PT is distributed to the transistors 111 and 112, causing a current I P1 and I P2 In state ST1, the generated current I P1 and I P2 acts on the error voltage generating circuit 140, generating a current I P1 and I P2 Error voltage V according to CMP appears at output terminal 103.

[0067] In state ST1, the magnitude of the current supplied from the power supply line LN11 to the line LN21 through the transistors 141 and 143 (i.e., the magnitude of the drain current of the transistors 141 and 143) is the same as the magnitude of the current supplied from the power supply line LN11 to the line LN22 through the transistors 142 and 144 (i.e., the magnitude of the drain current of the transistors 142 and 144). Furthermore, regardless of whether the state is ST1 or ST2, the same magnitude of drain current flows through the transistors 147 and 148.

[0068] In state ST1, for example, “V FB =V REF "When "I P1 =I P2 =I PT At this time, the drain current I P1 The magnitude of the sum of the drain current of transistor 112 and the drain current of transistor 144 is P2 and the drain current of transistor 143. Therefore, no current flows through output terminal 103, and the error voltage V CMP There will be no fluctuations.

[0069] On the other hand, in state ST1, for example, “V FB >V REF "When "I P1 P2 At this time, the drain current I P1 The magnitude of the sum of the drain current of transistor 112 and the drain current of transistor 144 is P2 and the drain current of transistor 143. Therefore, a current (positive charge) having a magnitude equal to the difference between the sum of these two currents is drawn from output terminal 103 to ground line LN17 through transistors 146 and 148. As a result, the error voltage V CMP The error voltage V CMP A decrease in voltage V FB and V REF In state ST1, the difference between “V FB <V REF ", then "V FB >V REF ", the opposite operation is performed.

[0070] In this way, in state ST1, the constant current I PT Based on the differential input pair 110, the feedback voltage V FB and reference voltage V REF The current (I P1 and I P2 ), and the error voltage generating circuit 140 generates a generated current (I P1 and I P2 ) based on the generated current (I P1 and I P2 ) error voltage V CMP Generate.

[0071] ​Next, the operation in state ST2 will be described. Regardless of whether the state is ST1 or ST2, the drain current of transistor 141 and the drain current of transistor 142 have the same magnitude. Furthermore, regardless of whether the state is ST1 or ST2, the drain current of transistor 147 and 148 have the same magnitude.

[0072] In state ST2, the reference voltage V REF is relatively high and the reference voltage V REF The feedback voltage V should be equal to FB Since the drain current I N1 and I N2 That is, a constant current I NT Based on the differential input pair 120, the drain current I N1 and I N2 occurs, and the drain current I N1 and I N2 The sum of these is the constant current I NT On the other hand, in the state ST2, as described above, no drain current flows through the transistors 111 and 112 (i.e., "I P1 =I P2 In state ST2, the generated current I N1 and I N2 acts on the error voltage generating circuit 140, generating a current I N1 and I N2 Error voltage V according to CMP appears at output terminal 103.

[0073] In state ST2, for example, FB =V REF "When "I N1 =I N2 =I NT At this time, the drain current I of the transistor 122 is calculated from the drain current of the transistor 141. N2 The remaining current flows through the transistor 143, and the drain current I of the transistor 121 is subtracted from the drain current of the transistor 142. N1The remaining current flows through transistor 144. N1 =I N2 =I NT / 2", the drain current of transistor 143 and the drain current of transistor 144 have the same magnitude. In this case, the drain current of transistor 143 and the drain current of transistor 144, which have the same magnitude, flow as the drain current of transistor 147 and the drain current of transistor 148, respectively, so no current flows through output terminal 103, and the error voltage V CMP There will be no fluctuations.

[0074] On the other hand, in state ST2, for example, “V FB >V REF "When "I N1 >I N2 At this time, the drain current I of the transistor 122 is calculated from the drain current of the transistor 141. N2 The remaining current flows through the transistor 143, and the drain current I of the transistor 121 is subtracted from the drain current of the transistor 142. N1 The remaining current flows through transistor 144. N1 >I N2 ” the drain current of the transistor 144 becomes smaller than the drain current of the transistor 143. Therefore, a current (positive charge) having a magnitude different between the drain current of the transistor 144 and the drain current of the transistor 143 is drawn from the output terminal 103 through the transistors 146 and 148 to the ground line LN17. As a result, the error voltage V CMP The error voltage V CMP A decrease in voltage V FB and V REF In state ST2, the difference between “V FB <V REF ", then "V FB >V REF ", the opposite operation is performed.

[0075] In this way, in state ST2, the constant current INT Based on the differential input pair 120, the feedback voltage V FB and reference voltage V REF The current (I N1 and I N2 ), and the error voltage generating circuit 140 generates a generated current (I N1 and I N2 ) based on the generated current (I N1 and I N2 ) error voltage V CMP Generate.

[0076] 11 shows a simulation result comparing the reference example and the first embodiment. In FIG. 11, a dashed waveform 810 shows the output voltage V OUT The solid line waveform 820 represents the frequency dependence of the noise density of the output voltage V when the error amplifier 100 (FIG. 9) according to the first embodiment is used as the error amplifier 11 in FIG. OUT The simulation conditions for obtaining waveforms 810 and 820 are the same except that the configuration of the error amplifier 11 is different. However, in the reference example, the output voltage V OUT The voltage obtained by dividing the voltage by 1 / 3 is the feedback voltage V FB ' (see FIG. 8). In comparison with the reference example, it can be seen that the noise characteristics are improved when the configuration of the first embodiment is used.

[0077] The noise density here is the feedback voltage V REF is the upper limit voltage V H This shows the noise density after the output voltage V OUT The noise of the output voltage V OUT is the target voltage V TG The noise generated when the voltage is stabilized is 0 V, and the magnitude of the noise during the soft start process does not matter.

[0078] As described above, in the switching power supply device AP, in the start-up state ST1, the error voltage V CMP In the subsequent state ST2, an error voltage V is generated using a differential input pair 120 of N-channel MOSFETs. CMP This allows the output voltage V to be generated without being subject to constraints such as the need for a high power supply voltage VDD. OUT The feedback voltage V FB It can be used as an output voltage V OUT Noise reduction is achieved.

[0079] Furthermore, by installing the flow path switching circuit 130, the reference voltage V REF After the reference voltage V is sufficiently increased, no current flows through the transistors 111 and 112, and therefore no malfunction occurs due to the current flow through the transistors 111 and 112. REF After the error voltage V is sufficiently increased, only the N-channel MOSFET transistors 121 and 122 among the transistors 111, 112, 121, and 122 operate, and the error voltage V CMP can be generated.

[0080] <<Second Example>> A second embodiment will be described. Radar devices are often installed on vehicles such as automobiles. A radar device mounted on a vehicle (hereinafter referred to as an on-vehicle radar device) can detect the distance between the vehicle and an object located outside the vehicle, the speed of the object (the relative speed between the vehicle and the object), and so on. A low-noise DC voltage is required as the power supply voltage for the on-vehicle radar device. This is because noise superimposed on the power supply voltage of the on-vehicle radar device adversely affects the detection accuracy of the on-vehicle radar device, and in recent years, the demand for low noise has become significantly stronger.

[0081] Generally, LDO (Low Dropout) regulators, which are a type of linear regulator, produce less noise than DC / DC converters. For this reason, a common method is to use the output voltage of a DC / DC converter to drive an LDO regulator, and then use the output voltage of the LDO regulator to drive an automotive radar device. However, this method results in increased heat loss and an increased number of components. For this reason, with the aim of achieving higher efficiency and smaller size, methods are being considered in which the automotive radar device is driven by a DC / DC converter alone. In this case, there is a strong demand for low noise from the DC / DC converter itself.

[0082] The switching power supply device AP including the error amplifier 100 shown in the first embodiment can meet this requirement. Therefore, when the error amplifier 100 is used as the error amplifier 11 in FIG. 1, the output voltage V OUT It is advantageous to use this voltage as a power supply voltage for an on-board radar device. That is, an on-board radar device is a suitable example of the load LD in FIG.

[0083] However, in the present disclosure, the load LD is not limited to an on-vehicle radar device. For example, the load LD may be any of various sensor devices that are not classified as radar devices, or any electronic device.

[0084] <<Third Example>> A third embodiment will be described. In the third embodiment, modified techniques and applied techniques for the above-described configuration will be described.

[0085] Reference voltage V REF Based on the constant current I PT The configuration of the flow path switching circuit 130 can be changed as desired as long as the flow path can be switched between the first flow path and the second flow path. For example, REF The intermediate voltage V M The flow path switching circuit 130 may be provided with a comparator that compares "V REF <V M", the switching transistor is turned off to supply the constant current I PT Set the flow path of "V" as the first flow path. REF >V M ", the switching transistor is turned on to supply a constant current I PT Similarly, the first constant current generating circuit can be configured to generate a constant current I PT The second constant current generating circuit can be configured as long as it can generate the constant current I NT Similarly, the configuration of the error voltage generating circuit 140 can also be changed arbitrarily.

[0086] The control block 10 controls the feedback voltage V FB and the reference voltage V REF (in other words, the feedback voltage V FB is the reference voltage V REF (to match or track the error voltage V CMP 1, the output stage control circuit is formed by a slope voltage generating circuit 13, a main comparator 14, a set signal issuing circuit 15, a PWM circuit 16, and a gate driver 17.

[0087] Output voltage V OUT information (i.e., feedback voltage V FB ) and inductor current I L However, the inductor current I L Without referring to the information of the output voltage V OUT information (i.e., feedback voltage V FB ) may be adopted in the control block 10 to control the state of the output stage circuit 20 based on the

[0088] Although the switching power supply AP configured as a step-down DC / DC converter has been taken as an example, the switching power supply AP can also be configured as a step-up DC / DC converter or a step-up / step-down DC / DC converter.

[0089] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0090] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0091] In the present disclosure, any first physical quantity and any second physical quantity being "the same" is understood as a concept that includes errors. In other words, the first physical quantity and the second physical quantity being "the same" means that the design or manufacturing is carried out with the aim of making the first physical quantity and the second physical quantity "the same." Even if there is a slight error between the first and second physical quantities, the first physical quantity and the second physical quantity should be understood as being "the same." This applies not only to physical quantities.

[0092] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0093] <<Additional Notes>> The present disclosure is provided with appendices.

[0094] An amplifier circuit according to one aspect of the present disclosure is FB ) and reference voltage (V REF ) error voltage (V CMP ) comprising a first differential input pair (110) having a first transistor (111) configured to receive the target voltage at its gate and a second transistor (112) configured to receive the reference voltage at its gate, and a second differential input pair (120) having a third transistor (121) configured to receive the target voltage at its gate and a fourth transistor (122) configured to receive the reference voltage at its gate, wherein the error voltage is generated using the first differential input pair or the second differential input pair in response to the reference voltage, and the first transistor and the second transistor are formed of P-channel MOSFETs, and the third transistor and the fourth transistor are formed of N-channel MOSFETs (first configuration).

[0095] The target voltage for the amplifier circuit according to the first configuration is the feedback voltage V FB The target voltage for the amplifier circuit according to the first configuration is arbitrary. However, it is preferable that feedback control is performed in the device incorporating the amplifier circuit to reduce the difference between the target voltage and the feedback voltage.

[0096] In the amplifier circuit according to the first configuration (see FIGS. 7 and 10), the reference voltage is a predetermined first voltage (V L ) to a predetermined second voltage (V H ), and then maintained at the second voltage, and the amplifier circuit is configured to operate when the reference voltage reaches a predetermined intermediate voltage (V M), the error voltage is generated using the first differential input pair, and the error voltage is generated using the second differential input pair in a second state (ST2) where the reference voltage is relatively high compared to the intermediate voltage (second configuration).

[0097] In the amplifier circuit according to the second configuration, the amplifier circuit IN ) to the output voltage (V OUT ) based on the output voltage, and the target voltage is a feedback voltage (V FB ) and the switching power supply device may be configured (third configuration) to perform feedback control to reduce the difference between the feedback voltage as the target voltage and the reference voltage.

[0098] The amplifier circuit according to the third configuration may have a configuration (fourth configuration) in which the output voltage itself is input to the amplifier circuit as the feedback voltage.

[0099] The amplifier circuit according to any one of the second to fourth configurations may further include a first constant current generating circuit configured to generate a first constant current, a second constant current generating circuit configured to generate a second constant current, and an error voltage generating circuit configured to generate the error voltage based on a current generated in the first differential input pair based on the first constant current or a current generated in the second differential input pair based on the second constant current, wherein in the first state, the first differential input pair generates a current based on the first constant current that corresponds to a difference between the target voltage and the reference voltage, thereby generating the error voltage that corresponds to the current generated in the first differential input pair, and in the second state, the second differential input pair generates a current based on the second constant current that corresponds to the difference between the target voltage and the reference voltage, thereby generating the error voltage that corresponds to the current generated in the second differential input pair (fifth configuration).

[0100] The amplifier circuit according to the fifth configuration may further include a path switching circuit configured to switch the path of the first constant current based on the reference voltage, and the path switching circuit may be configured to set the path of the first constant current to a path that passes through the first differential input pair in the first state, and to set the path of the first constant current to a path that does not pass through the first differential input pair in the second state (sixth configuration).

[0101] In the amplifier circuit according to the sixth configuration, the flow path switching circuit may have a flow path switching transistor formed of an N-channel MOSFET, the first constant current generation circuit may be provided between a power supply voltage line to which a predetermined power supply voltage is applied and a line to which the sources of the first and second transistors in the first differential input pair and the drain of the flow path switching transistor are commonly connected, the flow path switching transistor has a gate that receives the reference voltage, the flow path switching transistor is in an off state in the first state, and the flow path switching transistor is in an on state in the second state, and the flow path switching circuit may be configured to set the flow path of the first constant current to a flow path that passes through the first differential input pair but does not pass through the flow path switching transistor in the second state (seventh configuration).

[0102] The switching power supply circuit according to the present disclosure is a switching power supply circuit for generating an output voltage from an input voltage, and is configured (eighth configuration) to include an output stage circuit configured to switch the input voltage, a feedback voltage input terminal configured to receive a feedback voltage corresponding to the output voltage, an amplifier circuit according to any of the first to seventh configurations configured to receive the feedback voltage as the target voltage, a reference voltage supply circuit configured to supply the reference voltage to the amplifier circuit, and an output stage control circuit configured to control the output stage circuit based on the error voltage so as to reduce the difference between the feedback voltage as the target voltage and the reference voltage.

[0103] The switching power supply device according to the present disclosure has a configuration (ninth configuration) including a switching power supply circuit according to the eighth configuration described above, and a rectifying and smoothing circuit configured to generate the output voltage by rectifying and smoothing the voltage generated by switching of the output stage circuit. [Explanation of symbols]

[0104] AP Switching Power Supply 1. Semiconductor device 10 Control Blocks 11 Error amplifier 12 Reference voltage supply circuit 13 Slope voltage generation circuit 14 Main Comparator 15 Set signal issuing circuit 16 PWM circuit 17 Gate Driver 20 Output stage circuit 30 Internal power circuit 100 Error Amplifier 110, 120 differential input pair 130 Flow path switching circuit 140 Error voltage generation circuit V IN Input voltage V OUT Output Voltage V FB Feedback Voltage V REF Reference Voltage V CMP Error Voltage

Claims

1. 1. An amplifier circuit configured to generate an error voltage responsive to a difference between a target voltage and a reference voltage, a first differential input pair having a first transistor configured to receive the target voltage at its gate and a second transistor configured to receive the reference voltage at its gate; a second differential input pair having a third transistor configured to receive the target voltage at its gate and a fourth transistor configured to receive the reference voltage at its gate; a first constant current generating circuit configured to generate a first constant current; a second constant current generating circuit configured to generate a second constant current; an error voltage generating circuit configured to generate the error voltage based on a current generated in the first differential input pair based on the first constant current or a current generated in the second differential input pair based on the second constant current in response to the reference voltage; a flow path switching circuit configured to switch a flow path of the first constant current based on the reference voltage, the first transistor and the second transistor are formed of P-channel MOSFETs, and the third transistor and the fourth transistor are formed of N-channel MOSFETs; the reference voltage gradually increases from a predetermined first voltage to a predetermined second voltage, and is then maintained at the second voltage; In a first state in which the reference voltage is relatively low compared to a predetermined intermediate voltage that is higher than the first voltage and lower than the second voltage, the first differential input pair generates a current corresponding to a difference between the target voltage and the reference voltage based on the first constant current, thereby generating the error voltage corresponding to the current generated in the first differential input pair; In a second state in which the reference voltage is relatively higher than the intermediate voltage, the second differential input pair generates a current corresponding to a difference between the target voltage and the reference voltage based on the second constant current, thereby generating the error voltage corresponding to the current generated in the second differential input pair; The flow path switching circuit sets the flow path of the first constant current to a flow path that passes through the first differential input pair in the first state, and sets the flow path of the first constant current to a flow path that does not pass through the first differential input pair in the second state. , amplifier circuit.

2. the amplifier circuit is provided in a switching power supply device configured to generate an output voltage from an input voltage, the target voltage is a feedback voltage based on the output voltage; In the switching power supply device, feedback control is performed to reduce the difference between the feedback voltage as the target voltage and the reference voltage.

10. The amplifier circuit of claim 1.

3. The output voltage itself is input to the amplifier circuit as the feedback voltage.

3. The amplifier circuit according to claim 2.

4. the flow path switching circuit has a flow path switching transistor formed of an N-channel MOSFET, the first constant current generating circuit is provided between a power supply voltage line to which a predetermined power supply voltage is applied and a line to which the sources of the first and second transistors in the first differential input pair and the drain of the flow path switching transistor are commonly connected; the flow path switching transistor has a gate that receives the reference voltage, the flow path switching transistor is in an off state in the first state, and the flow path switching transistor is in an on state in the second state; The flow path switching circuit sets a flow path of the first constant current to a flow path that passes through the first differential input pair but not through the flow path switching transistor in the first state, and sets a flow path of the first constant current to a flow path that does not pass through the first differential input pair but passes through the flow path switching transistor in the second state.

10. The amplifier circuit of claim 1.

5. A switching power supply circuit for generating an output voltage from an input voltage, an output stage circuit configured to switch the input voltage; a feedback voltage input terminal configured to receive a feedback voltage corresponding to the output voltage; an amplifier circuit according to any one of claims 1 to 4, configured to receive the feedback voltage as the target voltage; a reference voltage supply circuit configured to supply the reference voltage to the amplifier circuit; an output stage control circuit configured to control the output stage circuit based on the error voltage so as to reduce the difference between the feedback voltage as the target voltage and the reference voltage; , Circuits for switching power supplies.

6. a switching power supply circuit according to claim 5; a rectifying and smoothing circuit configured to generate the output voltage by rectifying and smoothing a voltage generated by switching of the output stage circuit. , switching power supply.

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