Heterojunction structure element and manufacturing method thereof, field effect transistor using the same, artificial vision system using the same, solar cell using the same, gas sensor using the same, and piezoelectric element using the same

Abstract

To provide a heterojunction structure device.SOLUTION: A heterojunction structure device includes: a gate electrode disposed on a substrate; a ferroelectric layer disposed on the gate electrode and including a material having ferroelectric characteristics; a channel layer disposed on the ferroelectric layer and including a material having ferroelectric and semiconductor characteristics; and a source electrode and a drain electrode disposed on the channel layer while being spaced apart from each other.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a heterojunction structure device and a manufacturing method thereof, and more particularly to a heterojunction structure device having a structure in which different ferroelectric materials are joined together, and a manufacturing method thereof.

[0002] The heterojunction structure element and the manufacturing method thereof according to the present invention can be applied to field effect transistors, artificial vision systems, solar cells, gas sensors, and piezoelectric elements. [Background technology]

[0003] The most complex biological organ is the human brain. Therefore, to build systems that mimic human capabilities, it is essential to study biological neural networks (BNNs) inspired by the brain. More than 80% of external sensations are transmitted to the retina through optical stimuli, and these sensations are sensed, processed, and stored within the brain through BNNs. Artificial neural networks (ANNs) have recently received more attention than algorithm-based digital logic computing because their low power consumption, self-learning, and logical inference capabilities mimic the structural and functional characteristics of BNNs.

[0004] Existing complementary metal-oxide-semiconductor (CMOS) image sensors and charge-coupled device (CCD) cameras, which can sense and process optical signals, are widely used digital imaging devices. However, monolithic CMOS image sensors cannot sense a wide (visible-to-near infrared) wavelength range. Furthermore, existing digital image sensors consist of three modules: a CMOS photosensor, a signal processor, and an electronic memristor. They solve structured problems and process data sets based on CMOS logic operations. However, these devices consume considerable power and are large and expensive for practical applications. Furthermore, as the future Internet of Things (IoT) will have even greater performance requirements, artificial intelligence (AI) cannot meet the needs for low power consumption and high compatibility between separate memory and processing units. In contrast, a neuromorphic vision system inspired by BNNs can integrate a wide range of image sensing, learning, inference, and memory tasks into a single device through self-learning and self-adaptation, thereby overcoming the disadvantages of existing digital computing systems.

[0005] Over the past few decades, various optical sensing and synaptic elements have been integrated to develop artificial vision systems with various device structures, such as diodes, resistive memories, and field-effect transistors (FETs). Many materials, such as transition metal dichalcogenides, carbon nitride, perovskite, and organic materials, have been tried to develop such artificial vision systems.

[0006] Since the optical response of such systems is mostly due to interband transitions or trapping of excited electrons, the devices have the disadvantage of being primarily responsive to a single wavelength or operating with narrow bandwidths and complex device configurations.

[0007] To overcome the aforementioned problems and sense polychromatic light without filtering in a single device, a different strategy is needed. Also, to reduce the complexity of the device structure and control the effect of incident light on the gate voltage, a three-terminal structure based on a minimum number of transistors is needed, which allows various processing tasks to be performed within a single device.

[0008] Ferroelectrics have attracted considerable attention due to their spontaneous electric dipole polarization and domain wall motion under external electric fields, mechanical deformation, or light irradiation. Oxide ferroelectrics based on the ABO3 structure are commonly studied due to the spontaneous polarization caused by the distortion of off-center B ions. In addition to these oxide ferroelectrics, van der Waals (vdW) layered ferroelectrics (CIPS, α-In2Se3, SnS, InSe, 1T WTe2) are driving a paradigm shift in fundamental research and technology due to their small size (atomically thin layers), individual dipoles that can overcome depolarization fields, and strong ferroic coupling between dipoles.

[0009] Among these 2D ferroelectrics, α-In2Se3 has a five-layer structure in which the intermediate layer Se atoms can easily move left and right inside the crystal, resulting in the coexistence of in-plane (IP) polarization and out-of-plane (OOP) polarization. Therefore, various research efforts are being conducted on α-In2Se3.

[0010] For example, Dutta, D.; Mukherjee, S.; Uzhansky, M.; Koren, E., “Cross-field optoelectronic modulation via inter-coupled ferroelectricity in 2D In2Se3”, npj 2D Materials and Applications, 2021, experimentally demonstrated that such dipoles can be locked in both directions within α-In2Se3 controlled by a perpendicular gate voltage.

[0011] Furthermore, Rubio-Marcos, F.; Ochoa, DA; Del Campo, A.; Garcia, MA; Castro, GR; Fernández, JF; Garcia, JE, “Reversible optical control of macroscopic polarization in ferroelectrics”, Nature Photonics, 2017, discovered a change in polar order induced by light in ferroelectrics, suggesting the possibility of switching the polarization domain in a non-contact and remote manner.

[0012] Furthermore, Xue, F.; He, X.; Liu, W.; Periyanagounder, D.; Zhang, C.; Chen, M.; Lin, C.H.; Luo, L.; Yengel, E.; Tung, V.; et al., “Optoelectronic Ferroelectric Domain-Wall Memories Made from a Single Van Der Waals Ferroelectric”, Advanced Functional Materials, 2020, demonstrated a memory effect due to the movement of ferroelectric domain walls controlled by external optical illumination in α-In2Se3 devices.

[0013] Therefore, this application proposes a device with a heterojunction structure that can perform optical signal sensing, processing, and storage in a single device based on α-In2Se3 ferroelectrics, in order to develop an artificial vision system. [Prior art documents] [Non-patent literature]

[0014] [Non-Patent Document 1] Dutta, D.; Mukherjee, S.; Uzhansky, M.; Koren, E., “Cross-field optoelectronic modulation via inter-coupled ferroelectricity in 2D In2Se3”, npj 2D Materials and Applications, 2021, 5 (1) [Non-patent document 2] Rubio-Marcos, F.; Ochoa, DA; Del Campo, A.; Garcia, MA; Castro, GR; Fernαndez, JF; Garcia, JE, “Reversible optical control of macroscopic polarization in ferroelectrics”, Nature Photonics, 2017, 12 (1), 29-32, DOI: 10.1038 / s41566-017-0068-1. [Non-patent document 3] He, X.; Liu, W.; Periyanagounder, D.; Zhang, C.; Chen, M.; Lin, CH; Luo, L.; Yengel, E.; Tung, V.; et al., “Optoelectronic Ferroelectric Domain-Wall Memories Made from a Single Van Der Waals Ferroelectric”, Advanced Functional Materials, 2020, 30 (52) Summary of the Invention [Problem to be solved by the invention]

[0015] SUMMARY OF THE INVENTION An object of the present invention is to provide a heterojunction structure device in which different ferroelectric material layers are joined together, and a method for manufacturing the same.

[0016] Another object of the present invention is to provide a heterojunction structure element capable of controlling the polarization of a channel layer by light irradiated onto the channel layer, and a method for manufacturing the same.

[0017] It is still another object of the present invention to provide a heterojunction structure element in which the polarization of a ferroelectric layer can be controlled by a voltage applied to a gate electrode, and a method for manufacturing the same.

[0018] Another object of the present invention is to provide a heterojunction structure element in which the polarization of the channel layer can be controlled by the voltage applied to the gate electrode, and a method for manufacturing the same.

[0019] Another object of the present invention is to provide a heterojunction structure device capable of sensing, processing, and storing external signals (optical and electrical signals) within a single device, and a method for manufacturing the same.

[0020] Another object of the present invention is to provide a heterojunction structure device capable of sensing optical signals in a wide wavelength range and a method for manufacturing the same.

[0021] Another object of the present invention is to provide a heterojunction structure device capable of sensing optical signals of low intensity and a method for manufacturing the same.

[0022] Another object of the present invention is to provide a field effect transistor to which the above-mentioned heterojunction structure element is applied.

[0023] Another object of the present invention is to provide an artificial vision system to which the above-mentioned heterojunction structure element is applied.

[0024] Another object of the present invention is to provide a solar cell to which the above-mentioned heterojunction structure element is applied.

[0025] Another object of the present invention is to provide a gas sensor to which the above-mentioned heterojunction structure element is applied.

[0026] Another object of the present invention is to provide a piezoelectric element to which the above-mentioned heterojunction structure element is applied.

[0027] The object of the present invention is not limited to the above. [Means for solving the problem]

[0028] To achieve the above object, the present invention provides a heterojunction structure element.

[0029] The heterojunction structure device includes a gate electrode disposed on a substrate, a ferroelectric layer disposed on the gate electrode and including hafnium zirconium oxide (HZO), a channel layer disposed on the ferroelectric layer and including alpha-indium selenide (α-In2Se3), and a source electrode and a drain electrode spaced apart from each other on the channel layer.

[0030] It further includes an insulating layer disposed between the ferroelectric layer and the channel layer.

[0031] The insulating layer includes aluminum oxide (Al2O3).

[0032] The polarization of the channel layer is controlled by light irradiated onto the channel layer.

[0033] The polarization of the ferroelectric layer is controlled by a voltage applied to the gate electrode.

[0034] In order to achieve another object of the present invention, a heterojunction structure device includes: a gate electrode disposed on a substrate; a ferroelectric layer disposed on the gate electrode and including a material having ferroelectric properties; a channel layer disposed on the ferroelectric layer and including a material having ferroelectric and semiconducting properties; and a source electrode and a drain electrode disposed spaced apart from each other on the channel layer.

[0035] The ferroelectric layer includes a material having out-of-plane (OOP) polarization properties.

[0036] The channel layer includes a material having out-of-plane (OOP) polarization and in-plane (IP) polarization.

[0037] The ferroelectric layer may be formed of hafnium zirconium oxide (HZO), arsenic (As), antimony (Sb), bismuth (Bi), tellurium (Te), d1T-MoS2, t-MoS2, WS2, WSe2, WTe2, BiN, SbN, BiP, GaN, GaSe, SiC, BN, AlN, ZnO, GeS, GeSe, SnS, SnSe, SiTE, GeTe, SnTE, PbTe, CrN, CrB2, CrBr3 , Crl3, GaTeCl, AgBiP2Se6, CuCrP2S6, CuCrP2Se6, CuVP2S6, CuVP2Se6, CuInP2Se6, CuInP2S6 (CIPS), Sc2CO2, Bi2O2Se, Bi2O2Te, Bi2O2s, Ba2PbCl4, graphanol, hydroxyl-functionalized graphene, halogen-decorated phosphorene, g-CN6N8H, and Bi-CH2OH.

[0038] The channel layer includes any one of alpha-indium selenide (α-In2Se3), 1T-MoS2, MoSSe, MoTe, SnS, SnSe, SnTe, GeS, GeSe, and GeTe.

[0039] The polarization of the channel layer is controlled by the light irradiated onto the channel layer.

[0040] The polarization of the ferroelectric layer is controlled by a voltage applied to the gate electrode.

[0041] Furthermore, to achieve another object of the present invention, a heterojunction structure device includes: a gate electrode disposed on a substrate; a ferroelectric layer disposed on the gate electrode and containing a material having ferroelectric properties; an insulating layer disposed on the ferroelectric layer; a channel layer disposed on the insulating layer and containing a material having ferroelectric and semiconducting properties; and a source electrode and a drain electrode disposed spaced apart from each other on the channel layer.

[0042] The insulating layer includes aluminum oxide (Al2O3), silicon oxide (SiO2), hafnium oxide (HfO2), and hexagonal boron nitride (h-BN).

[0043] Furthermore, in order to achieve another object of the present invention, the present invention provides a method for manufacturing a heterojunction structure element.

[0044] The method for manufacturing the heterojunction structure device includes the steps of preparing a substrate, forming a gate electrode on the substrate, forming a ferroelectric layer containing a material having ferroelectric properties on the gate electrode, forming an insulating layer on the ferroelectric layer, forming a channel layer containing a material having ferroelectric and semiconducting properties on the insulating layer, and forming a source electrode and a drain electrode spaced apart from each other on the channel layer. [Effects of the Invention]

[0045] The heterojunction structure element according to the present invention can control the polarization of the channel layer (α-In2Se3) by irradiating the channel layer with light, and can control the polarization of the ferroelectric layer by applying a voltage to the gate electrode. This allows the heterojunction structure element to sense, process, and store external signals (optical and electrical signals) within a single element. This makes the heterojunction structure element easily applicable to artificial vision systems.

[0046] In addition, the heterojunction structure device can effectively utilize light in a wide wavelength range (e.g., 405 nm to 850 nm) and very low intensity light (0.03 mW / cm) due to the inherent polarization characteristics (bidirectional polarization characteristics in which horizontal polarization and vertical polarization are connected to each other) of the channel layer (α-In2Se3). 3 ) can be sensed.

[0047] In addition, the heterojunction structure element can embody PPF (Paired Pulse Facilitation), which is an electrical characteristic that an artificial synapse device should have, and a transition characteristic from short-term memory (STM) to long-term memory (LTM), and can perform logic operations such as pattern recognition, light adaptation training, and Pavlov's training. [Brief explanation of the drawings]

[0048] [Figure 1] FIG. 1 is a flowchart illustrating a method for manufacturing a heterojunction structure element according to an embodiment of the present invention. [Figure 2] FIG. 2 is a schematic diagram illustrating step S110 and step S120 in the method for manufacturing a heterojunction structure element according to an embodiment of the present invention. [Figure 3] FIG. 3 is a schematic diagram illustrating steps S130 and S140 in the method for manufacturing a heterojunction structure element according to an embodiment of the present invention. [Figure 4] FIG. 4 is a schematic diagram illustrating step S150 in the method for manufacturing a heterojunction structure element according to an embodiment of the present invention. [Figure 5] FIG. 5 is a schematic diagram illustrating step S160 in the method for manufacturing a heterojunction structure element according to an embodiment of the present invention. [Figure 6] FIG. 6 is a schematic diagram illustrating step S210 in the process of manufacturing an artificial synapse element according to a first modified example of the present invention. [Figure 7] FIG. 7 is a schematic diagram illustrating step S220 in the process of manufacturing an artificial synapse element according to a first modified example of the present invention. [Figure 8] FIG. 8 is a schematic diagram illustrating step S230 in the process of manufacturing an artificial synapse element according to a first modified example of the present invention. [Figure 9]FIG. 9 is a schematic diagram illustrating step S340 in the process of manufacturing an artificial synapse element according to a second modification of the present invention. [Figure 10] FIG. 10 is a schematic diagram illustrating step S350 in the process of manufacturing an artificial synapse element according to a second modification of the present invention. [Figure 11] FIG. 11 is a schematic diagram illustrating step S360 in the process of manufacturing an artificial synapse element according to a second modification of the present invention. [Figure 12] FIG. 12 is a schematic diagram illustrating step S370 in the process of manufacturing an artificial synapse element according to a second modification of the present invention. [Figure 13] FIG. 13 is a schematic cross-sectional view of a ferroelectric field effect transistor according to a third modification of the present invention. [Figure 14] FIG. 14 is a schematic plan view of a ferroelectric field effect transistor according to a third modified example of the present invention. [Figure 15] FIG. 15 is a schematic diagram illustrating the manufacturing process of an Fe FET device according to an experimental example of the present invention. [Figure 16] FIG. 16 is a schematic diagram illustrating an Fe FET device according to an experimental example of the present invention. [Figure 17] FIG. 17 is a diagram illustrating the results of AFM analysis of the ferroelectric layer of the Fe FET device according to an experimental example of the present invention. [Figure 18] FIG. 18 is a diagram illustrating the results of AFM analysis of the insulating layer of the Fe FET element according to an experimental example of the present invention. [Figure 19] FIG. 19 is a diagram illustrating the results of AFM analysis of the channel layer of the Fe FET device according to an experimental example of the present invention. [Figure 20] FIG. 20 is a diagram illustrating the results of Raman analysis of the heterojunction structure of the Fe FET device according to an experimental example of the present invention. [Figure 21] FIG. 21 shows a TEM image and an EDS mapping image of the heterojunction structure of the Fe FET device according to an experimental example of the present invention. [Figure 22] FIG. 22 is a diagram showing the positions where AFM scanning was used to confirm the operation of the Fe FET device according to the experimental example of the present invention. [Figure 23] FIG. 23 is a diagram showing the surface potential measured in the channel layer between the source and drain electrodes when a negative voltage is applied to the gate electrode. [Figure 24] FIG. 24 shows the surface potential measured in the channel layer between the source and drain electrodes when a positive voltage is applied to the gate electrode. [Figure 25] FIG. 25 shows an image of the PFM phase under dark conditions. [Figure 26] FIG. 26 is a diagram showing the values ​​of the PFM phase measured when voltages of opposite polarities are applied to the gate electrodes under dark conditions. [Figure 27] FIG. 27 shows a schematic diagram of dipole polarization under dark conditions. [Figure 28] FIG. 28 shows an image of the PFM phase under bright conditions. [Figure 29] FIG. 29 is a diagram showing the values ​​of the PFM phase measured when voltages of opposite polarities are applied to the gate electrodes under bright conditions. [Figure 30] FIG. 30 shows a schematic diagram of dipole polarization under bright conditions. [Figure 31] FIG. 31 is a diagram illustrating the voltage-current characteristics of an Fe FET device according to an experimental example of the present invention. [Figure 32] FIG. 32 is a diagram illustrating the voltage-current characteristics of an Fe FET device according to a comparative example of the present invention. [Figure 33] FIG. 33 is a diagram illustrating the change in transfer characteristics depending on the scanning voltage range of the Fe FET device according to an experimental example of the present invention. [Figure 34] FIG. 34 is a diagram for explaining the change in transfer characteristics due to a change in read voltage of an Fe FET element according to an experimental example of the present invention. [Figure 35]FIG. 35 is a diagram illustrating the on / off ratio of an Fe FET device according to an experimental example of the present invention. [Figure 36] FIG. 36 is a diagram for explaining the memory window of an Fe FET device according to an experimental example of the present invention. [Figure 37] FIG. 37 is a diagram illustrating the output characteristics of an Fe FET device according to an experimental example of the present invention. [Figure 38] FIG. 38 is a diagram showing a schematic diagram of electrical synapse measurement using an Fe FET device according to an experimental example of the present invention. [Figure 39] FIG. 39 is a diagram illustrating the short-term drop effect of the Fe FET device according to an experimental example of the present invention. [Figure 40] FIG. 40 is a diagram illustrating the short-term enhancement effect of the Fe FET device according to an experimental example of the present invention. [Figure 41] FIG. 41 shows a model for the optical signal sensing and information storage process. [Figure 42] FIG. 42 is a diagram illustrating current values ​​depending on the number of signals input to an Fe FET device according to an experimental example of the present invention. [Figure 43] FIG. 43 is a diagram illustrating normalized attenuation current values ​​according to the number of signals input to an Fe FET device according to an experimental example of the present invention. [Figure 44] FIG. 44 is a diagram illustrating the conversion of short-term memory to long-term memory through an Fe FET device according to an experimental example of the present invention. [Figure 45] FIG. 45 is a diagram for explaining the PPF measurement results of the Fe FET element according to an experimental example of the present invention. [Figure 46] FIG. 46 is a diagram for explaining the PPF ratio of the Fe FET element according to an experimental example of the present invention. [Figure 47] FIG. 47 is a diagram for explaining the PPF ratio of the Fe FET element according to an experimental example of the present invention. [Figure 48] FIG. 48 is a diagram for explaining the PPF ratio of the Fe FET element according to an experimental example of the present invention. [Figure 49]FIG. 49 is a diagram for explaining the PPF ratio of the Fe FET element according to an experimental example of the present invention. [Figure 50] FIG. 50 shows the fast and slow relaxation times of the decay curves for various wavelengths. [Figure 51] FIG. 51 is a diagram for explaining the influence of an electric field on an Fe FET element under the condition that it is irradiated with light having a wavelength of 405 nm. [Figure 52] FIG. 52 is a diagram for explaining the influence of an electric field on an Fe FET element under the condition that it is irradiated with light having a wavelength of 655 nm. [Figure 53] FIG. 53 is a diagram for explaining the influence of an electric field on an Fe FET element under the condition that light with a wavelength of 785 nm is irradiated. [Figure 54] FIG. 54 is a diagram for explaining the influence of an electric field on an Fe FET element under the condition that light with a wavelength of 850 nm is irradiated. [Figure 55] FIG. 55 is a diagram illustrating the synapse weight update characteristics of an Fe FET device according to an experimental example of the present invention. [Figure 56] FIG. 56 is a diagram illustrating the synapse weight update characteristics of an Fe FET device according to an experimental example of the present invention. [Figure 57] FIG. 57 is a diagram illustrating the synapse weight update characteristics of an Fe FET device according to an experimental example of the present invention. [Figure 58] FIG. 58 is a diagram illustrating the synapse weight update characteristics of an Fe FET device according to an experimental example of the present invention. [Figure 59] FIG. 59 is a diagram illustrating the long-term stability of the synaptic weight update characteristics of the Fe FET device according to an experimental example of the present invention. [Figure 60] Figure 60 is a schematic diagram of an ANN for MNIST pattern recognition. [Figure 61] FIG. 61 is a diagram for explaining the pattern recognition accuracy by Epoch. [Figure 62]FIG. 62 is a diagram for explaining the results of the light adaptation test when a weak light stimulus is applied. [Figure 63] FIG. 63 is a diagram for explaining the results of a light adaptation test when a strong light stimulus is applied. [Figure 64] FIG. 64 is a diagram for explaining the results of a light adaptation test when strong light stimuli and electrical stimuli are applied. [Figure 65] FIG. 65 is a diagram showing OR logic operations based on optical and electrical signal changes. [Figure 66] FIG. 66 is a diagram showing an AND logic operation based on optical signal changes and electrical signal changes. [Figure 67] FIG. 67 is a diagram illustrating the multistate characteristics of an Fe FET element according to an experimental example of the present invention. [Figure 68] FIG. 68 is a diagram showing current values ​​when a conditioned stimulus is applied. [Figure 69] FIG. 69 is a diagram showing the current value when an unconditioned stimulus is applied. [Figure 70] FIG. 70 is a diagram showing current values ​​when a conditioned stimulus and an unconditioned stimulus are applied simultaneously. [Figure 71] FIG. 71 shows the current value when only the conditioned stimulus was applied after training. DETAILED DESCRIPTION OF THE INVENTION

[0049] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. The embodiments described herein are provided so that the disclosure will be thorough and complete, and so that the concept of the present invention will be fully conveyed to those skilled in the art.

[0050] In this specification, when a component is described as being on another component, it means that it can be directly formed on the other component, or a third component can be sandwiched between them. Also, in the drawings, shapes and sizes are exaggerated for the purpose of effectively explaining the technical content.

[0051] Furthermore, in various embodiments of this specification, terms such as "first," "second," and "third" are used to describe various components, but these components should not be limited by such terms. These terms are used merely to distinguish one component from another. Thus, what is referred to as a "first" component in one embodiment may also be referred to as a "second" component in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. Furthermore, in this specification, "and / or" is used to mean that at least one of the components listed before and after it is included.

[0052] In this specification, the singular expression includes the plural expression unless the context clearly dictates otherwise. Furthermore, the terms "comprise" or "have" are intended to specify the presence of a feature, number, step, component, or combination thereof described in the specification, and should not be understood to exclude the presence or possible addition of one or more other features, numbers, steps, components, or combinations thereof. Furthermore, in this specification, the term "coupled" is used to mean both indirectly and directly coupling multiple components.

[0053] Furthermore, when describing the present invention, if it is determined that a detailed description of related publicly known functions or configurations would unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0054] (Heterojunction structure element and its manufacturing method) Figure 1 is a flowchart for explaining a method for manufacturing a heterojunction structure element according to an embodiment of the present invention, Figure 2 is a schematic diagram for explaining steps S110 and S120 of the method for manufacturing a heterojunction structure element according to an embodiment of the present invention, Figure 3 is a schematic diagram for explaining steps S130 and S140 of the method for manufacturing a heterojunction structure element according to an embodiment of the present invention, Figure 4 is a schematic diagram for explaining step S150 of the method for manufacturing a heterojunction structure element according to an embodiment of the present invention, and Figure 5 is a schematic diagram for explaining step S160 of the method for manufacturing a heterojunction structure element according to an embodiment of the present invention.

[0055] As shown in FIGS. 1 and 2, a substrate 100 is prepared (S110). In one embodiment, the substrate 100 is a silicon semiconductor substrate. More specifically, the substrate 100 is a substrate in which a silicon oxide (SiO2) layer 120 is formed on a silicon (Si) substrate 110. In another embodiment, the substrate 100 is a compound semiconductor substrate. In another embodiment, the substrate 100 is a glass substrate. In still another embodiment, the substrate 100 is a plastic substrate. The type of the substrate 100 is not limited.

[0056] A gate electrode 200 is formed on the substrate 100 (S120). In one embodiment, the gate electrode 200 includes a metal. For example, the gate electrode 200 includes gold (Au). In one embodiment, the gate electrode 200 is formed using electron beam lithography and electron beam deposition. In another embodiment, the gate electrode 200 is formed to a thickness of 60 nm. The above-described method, material, and thickness of the gate electrode 200 are merely examples, and the method, material, and thickness of the gate electrode 200 are not limited thereto.

[0057] 1 and 3, a ferroelectric layer 300 is formed on the gate electrode 200 (S130). According to an embodiment, the ferroelectric layer 300 is formed of a ferroelectric material such as hafnium zirconium oxide (HZO), arsenic (As), antimony (Sb), bismuth (Bi), tellurium (Te), d1T-MoS2, t-MoS2, WS2, WSe2, WTe2, BiN, SbN, BiP, GaN, GaSe, SiC, BN, AlN, ZnO, GeS, GeSe, SnS, SnSe, SiTE, GeTe, SnTE, PbTe, C The compound may include any one of rN, CrB2, CrBr3, Crl3, GaTeCl, AgBiP2Se6, CuCrP2S6, CuCrP2Se6, CuVP2S6, CuVP2Se6, CuInP2Se6, CuInP2S6 (CIPS), Sc2CO2, Bi2O2Se, Bi2O2Te, Bi2O2s, Ba2PbCl4, graphanol, hydroxyl-functionalized graphene, halogen-decorated phosphorene, g-CN6NH, and Bi-CH2OH.

[0058] According to an embodiment, the ferroelectric layer 300 is formed by dry transfer of a ferroelectric material mechanically peeled from a bulk onto the gate electrode 200. The method for forming the ferroelectric layer 300 is not limited.

[0059] An insulating layer 400 is formed on the ferroelectric layer 300. According to one embodiment, the insulating layer 400 includes hexagonal boron nitride (h-BN). In this case, the insulating layer 400 is formed by dry-transferring hexagonal boron nitride mechanically peeled from a bulk of the ferroelectric layer 300 onto the ferroelectric layer 300. Alternatively, according to another embodiment, the insulating layer 400 includes any one of aluminum oxide (Al2O3), silicon oxide (SiO2), and hafnium oxide (HfO2).

[0060] The insulating layer 400 is provided to reduce gate leakage current between the ferroelectric layer 300 and a channel layer 500 (described later). If the insulating layer 400 is omitted, device degradation due to gate leakage current may occur.

[0061] 1 and 4, a channel layer 500 is formed on the insulating layer 400 (S150). According to one embodiment, the channel layer 500 includes a material having ferroelectric and semiconducting properties. For example, the channel layer 500 may include any one of alpha-indium selenide (α-In2Se3), 1T-MoS2, MoSSe, MoTe, SnS, SnSe, SnTe, GeS, GeSe, and GeTe.

[0062] According to one embodiment, the channel layer 500 is formed by dry-transferring a channel material mechanically peeled from a bulk onto the insulating layer 400. The method for forming the channel layer 500 is not limited.

[0063] As shown in FIGS. 1 and 5, a source electrode (S) and a drain electrode (D) are formed on the channel layer 500 to be spaced apart from each other (S160). According to one embodiment, the source electrode (S) includes titanium (Ti) and gold (Au). More specifically, the source electrode (S) has a structure in which a 60 nm thick layer of gold (Au) is stacked on a 10 nm thick layer of titanium (Ti). According to another embodiment, the drain electrode (D) includes titanium (Ti) and gold (Au). More specifically, the drain electrode (D) has a structure in which a 60 nm thick layer of gold (Au) is stacked on a 10 nm thick layer of titanium (Ti). According to one embodiment, the source electrode (S) and the drain electrode (D) are formed by electron beam evaporation. The materials and formation methods of the source electrode (S) and the drain electrode (D) are not limited.

[0064] That is, the heterojunction structure device according to the embodiment of the present invention may be embodied as a ferroelectric field effect transistor (FeFET) including a gate electrode 200 disposed on a substrate 100, a ferroelectric layer 300 disposed on the gate electrode, an insulating layer 400 disposed on the ferroelectric layer, a channel layer 500 disposed on the insulating layer 400, and a source electrode (S) and a drain electrode (D) disposed spaced apart from each other on the channel layer 500.

[0065] Furthermore, the present invention can be easily applied to artificial vision systems by performing sensing, processing, and storage of external signals (optical and electrical signals) within a single element of the ferroelectric field effect transistor.

[0066] To this end, the present invention may configure the ferroelectric layer 300 to include a material having out-of-plane (OOP) polarization, and the channel layer 500 to include a material having both out-of-plane (OOP) and in-plane (IP) polarization. More specifically, the present invention may configure the ferroelectric layer 300 to include CuInP2S6 (CIPS), and the channel layer 500 to include alpha-indium selenide (α-In2Se3). Furthermore, the present invention may configure the insulating layer 400 to include hexagonal boron nitride so that the electrical potential energy generated by the polarization phenomenon in the ferroelectric layer 300 can maintain its influence on the polarization shape of the channel layer 500.

[0067] In describing the present invention, "polarization" refers to a phenomenon in which negative and positive charges are separated from each other in an electric field, resulting in a dipole moment. Furthermore, "horizontal polarization" refers to a phenomenon in which negative and positive charges are separated from each other in a direction parallel to the linear direction from the source electrode (S) to the drain electrode (D), resulting in a dipole moment. Furthermore, "vertical polarization" refers to a phenomenon in which negative and positive charges are separated from each other in a direction perpendicular to the linear direction from the source electrode (S) to the drain electrode (D), resulting in a dipole moment.

[0068] In a ferroelectric field effect transistor having the above-described structure (bottom electrode / CIPS / h-BN / α-In2Se3), the polarization of the channel layer 500 is controlled by light irradiated onto the channel layer 500, and the polarization of the ferroelectric layer 300 is controlled by a voltage applied to the gate electrode 200. As a result, the ferroelectric field effect transistor can sense, process, and store external signals (optical and electrical signals) within a single device. This allows the ferroelectric field effect transistor to be easily applied to artificial vision systems.

[0069] In addition, the ferroelectric field effect transistor can be used with light in a wide wavelength range (e.g., 405 nm to 850 nm) and very low intensity light (0.03 mW / cm) due to the inherent polarization characteristics of α-In2Se3 (bidirectional polarization characteristics in which horizontal polarization and vertical polarization are connected to each other). 3 ) can be sensed.

[0070] In addition, the ferroelectric field effect transistor embodies PPF (Paired Pulse Facilitation), which are electrical characteristics that an artificial synapse device should have, and a transition characteristic from short-term memory (STM) to long-term memory (LTM), and can perform logic operations such as pattern recognition, light adaptation training, Pavlov's training, etc. The characteristics of the ferroelectric field effect transistor will be specifically explained using experimental examples described below.

[0071] Unlike the above, a ferroelectric field effect transistor having an α-In2Se3 / h-BN / CIPS / top electrode structure has a problem in which the channel layer is blocked by the top electrode, resulting in inefficient light irradiation of the channel layer. Furthermore, while a Van der Waals metal contact is formed in the bottom electrode / CIPS structure, a thermally evaporated metal contact is formed in the CIPS / top electrode structure. In a thermally evaporated metal contact, various defects such as interstitial defects, vacancy defects, and antisite defects are more likely to form than in a Van der Waals metal contact. In other words, a CIPS / top electrode structure has a problem in which various physical and chemical defects are more likely to form in the CIPS and electrode than in a bottom electrode / CIPS structure.

[0072] The heterojunction structure element and the manufacturing method thereof according to the embodiment of the present invention have been described above. Various application examples of the heterojunction structure (CIPS / h-BN / α-In2Se3) according to the embodiment of the present invention will now be described.

[0073] According to one embodiment, the heterojunction structure (CIPS / h-BN / α-In2Se3) according to the present invention is used as a semiconductor layer of a solar cell. More specifically, the heterojunction structure (CIPS / h-BN / α-In2Se3) can be applied to a solar cell that converts light energy into electrical energy using the photovoltaic effect.

[0074] Alternatively, according to another embodiment, the heterojunction structure (CIPS / h-BN / α-In2Se3) can be applied to a gas sensor. More specifically, the heterojunction structure (CIPS / h-BN / α-In2Se3) exhibits spontaneous polarization against electric force, and can adsorb or desorb gas molecules (e.g., NH3 gas molecules, NO2 gas molecules) depending on the polarization direction of the ferroelectric material surface.

[0075] Alternatively, according to another embodiment, the heterojunction structure (CIPS / h-BN / α-In2Se3) can be applied to a piezoelectric sensor. More specifically, since ferroelectrics have piezoelectric properties, the heterojunction structure (CIPS / h-BN / α-In2Se3) can be applied to a piezoelectric sensor that utilizes the phenomenon in which dielectric polarization occurs in the heterojunction structure (CIPS / h-BN / α-In2Se3) due to physical deformation applied to the heterojunction structure (CIPS / h-BN / α-In2Se3).

[0076] Various application examples of the heterojunction structure according to the embodiment of the present invention have been described above. Hereinafter, various modified examples of the heterojunction structure element according to the embodiment of the present invention will be described.

[0077] (First Modification: CIPS / h-BN / α-In2Se3+Mxene Artificial Synapse Element) FIG. 6 is a schematic diagram illustrating step S210 in the manufacturing process of an artificial synapse element according to a first modified example of the present invention, FIG. 7 is a schematic diagram illustrating step S220 in the manufacturing process of an artificial synapse element according to a first modified example of the present invention, and FIG. 8 is a schematic diagram illustrating step S230 in the manufacturing process of an artificial synapse element according to the first modified example of the present invention.

[0078] As shown in FIG. 6, a gate electrode 200, a ferroelectric layer 300, an insulating layer 400, and a first channel layer 500 are sequentially formed on the first region (A1) of a substrate 100 including a first region (A1) and a second region (A2) different from the first region (A1) (S210).

[0079] According to one embodiment, the methods of forming the gate electrode 200, the ferroelectric layer 300, the insulating layer 400, and the first channel layer 500 are similar to the methods of forming the gate electrode 200, the ferroelectric layer 300, the insulating layer 400, and the channel layer 500 of the heterojunction structure device described with reference to FIGS. 1 to 4.

[0080] 7, a second channel layer 600 is formed (S220) on the second region (A2) of the substrate 100. According to one embodiment, the second channel layer 600 includes Mxene.

[0081] 8, a first source electrode (S1), a drain electrode (D), and a second source electrode (S2) are formed on the first channel layer 500 and the second channel layer 600 (S230). More specifically, the first source electrode (S1) is formed on one side of the upper surface of the first channel layer 500, and the drain electrode (D) is formed on the other side. The drain electrode (D) is formed on one side of the upper surface of the second channel layer 600, and the second source electrode (S2) is formed on the other side. The drain electrode (D) is formed so that the first channel layer 500 and the second channel layer 600 share a common electrode. That is, the drain electrode (D) is formed so as to contact both the other side of the upper surface of the first channel layer 500 and one side of the upper surface of the second channel layer 600.

[0082] The first channel layer 500, i.e., α-In2Se3, is responsible for potentiation in the artificial synapse element, and the second channel layer 600, i.e., Mxene, is responsible for depression in the artificial synapse element. Furthermore, in the artificial synapse element having the above-described structure (CIPS / h-BN / α-In2Se3+Mxene), the potentiation of the first channel layer 500 and the depression of the second channel layer 600 are generated by an optical signal. That is, potentiation and depression can be generated by a single signal (optical signal). This reduces the load and complexity of peripheral circuits and improves the processing speed of the system.

[0083] In contrast, in the case of an artificial synapse element having the structure (CIPS / h-BN / α-In2Se3) described in Figures 1 to 5, the unidirectional photoreaction causes the increase in potential due to the optical signal, while the decrease in potential due to the electrical signal. In this way, combining two signals (optical and electrical) not only increases the burden and complexity of the peripheral circuitry, but also limits the processing speed of the system.

[0084] (Second Modification: CIPS / h-BN / α-In2Se3+Mxene+Oxide Layer Artificial Synapse Element) FIG. 9 is a schematic diagram illustrating step S340 in the manufacturing process of an artificial synapse element according to a second modified example of the present invention; FIG. 10 is a schematic diagram illustrating step S350 in the manufacturing process of an artificial synapse element according to a second modified example of the present invention; FIG. 11 is a schematic diagram illustrating step S360 in the manufacturing process of an artificial synapse element according to a second modified example of the present invention; and FIG. 12 is a schematic diagram illustrating step S370 in the manufacturing process of an artificial synapse element according to a second modified example of the present invention.

[0085] The method for manufacturing an artificial synapse element according to the second modification of the present invention includes the steps of sequentially forming a gate electrode 200, a ferroelectric layer 300, an insulating layer 400, and a first channel layer 500 on a first region (A1) of a substrate 100 (S310), forming a second channel layer 600 on the second region (A2) of the substrate 100 (S320), forming a first source electrode (S1), a drain electrode (D), and a second source electrode (S2) on the first channel layer 500 and the second channel layer 600 (S330), forming a mask layer (ML) (S340), etching the mask layer (ML) (S350), forming an oxide layer 700 (S360), and removing the mask layer (ML) (S370).

[0086] The steps S310 to S330 included in the method for manufacturing an artificial synapse element according to the second modification are the same as the steps S210 to S230 included in the method for manufacturing an artificial synapse element according to the first modification, which have been described with reference to Figures 6 to 8. Therefore, detailed description thereof will be omitted.

[0087] 9, a mask layer (ML) is formed on the substrate 100 to cover the first source electrode (S1), the drain electrode (D), the second source electrode (S2), the first channel layer 500, and the second channel layer 600. According to one embodiment, the mask layer (ML) includes a polymer. For example, the polymer includes polymethyl methacrylate (PMMA).

[0088] 10, the mask layer (ML) disposed between the second source electrode (S2) and the drain electrode (D) and overlapping the second channel layer 600 is etched. According to one embodiment, the etching of the mask layer (ML) is performed using oxygen plasma (O2 plasma) treatment and electron beam lithography. As a result, the upper surface of the second channel layer 600 between the second source electrode (S2) and the drain electrode (D) is exposed to the outside.

[0089] 11 and 12, an oxide layer 700 is formed on the exposed upper surface of the second channel layer 600 (S360), and then the mask layer (ML) remaining on the substrate 100 is removed (S370). In one embodiment, the oxide layer 700 includes a metal oxide. For example, the oxide layer 700 includes titanium oxide (TiO).

[0090] In the case of Mxene contained in the second channel layer 600, oxidation easily occurs upon contact with air, and the oxidized regions act as charge trap sites. The charge trap sites act as scattering centers under light illumination, reducing electrical conductivity. That is, when the second channel layer 600 is exposed to the outside, oxidation occurs upon contact with air, resulting in a problem of reduced electrical conductivity. However, in the artificial synapse device according to the second modified example, by forming an oxide layer 700 on the exposed upper surface of the second channel layer 600, the problem of reduced conductivity caused by the second channel layer 600 coming into contact with air can be easily solved.

[0091] (Third Modification: Split Gate Ferroelectric Field Effect Transistor (Split Gate FeFET)) FIG. 13 is a schematic cross-sectional view of a ferroelectric field effect transistor according to a third modification of the present invention, and FIG. 14 is a schematic plan view of the ferroelectric field effect transistor according to the third modification of the present invention.

[0092] As shown in Figures 13 and 14, the ferroelectric field effect transistor according to the third modified example includes a substrate 100, a first gate electrode 210 and a second gate electrode 220 spaced apart from each other on the substrate 100, a ferroelectric layer 300 disposed on the first gate electrode 210 and the second gate electrode 220, an insulating layer 400 disposed on the ferroelectric layer 300, a channel layer 500 disposed on the insulating layer 400, and a source electrode (S) and a drain electrode (D) spaced apart from each other on the channel layer 500.

[0093] According to one embodiment, the substrate 100, the first and second gate electrodes 210 and 220, the ferroelectric layer 300, the insulating layer 400, the channel layer 500, the source electrode (S), and the drain electrode (D) included in the ferroelectric field effect transistor according to the third modified example are the same as the substrate 100, the gate electrode 200, the ferroelectric layer 300, the insulating layer 400, the channel layer 500, the source electrode (S), and the drain electrode (D) included in the heterojunction structure element described in FIGS. 1 to 5.

[0094] The ferroelectric field effect transistor according to the third modified example can achieve a dynamic change in memory window by controlling the areas of the first gate electrode 210 and the second gate electrode 220. In addition, during a write operation, the first gate electrode 210 and the second gate electrode 220 are used to reduce subthreshold swing, whereas during a read operation, only one of the first gate electrode 210 and the second gate electrode 220 is used to increase the memory window. As a result, a spiking neural network (SNN) that combines an artificial synapse and a spiking neuron can be implemented.

[0095] Various modifications of the heterojunction structure element according to the embodiment of the present invention have been described above. Specific experimental examples and characteristic evaluation results of the heterojunction structure element according to the embodiment of the present invention will now be described.

[0096] (Experimental Example 1: Fe FET Device Fabrication and Structural Characteristics) FIG. 15 is a schematic diagram illustrating a manufacturing process of an Fe FET device according to an experimental example of the present invention, and FIG. 16 is a schematic diagram illustrating an Fe FET device according to an experimental example of the present invention.

[0097] As shown in Figures 15 and 16, a 60-nm-thick gold (Au) electrode was deposited as a gate electrode on a SiO2 / Si substrate using electron beam lithography and electron beam evaporation. Then, multiple layers of CuInP2S6 (CIPS), h-BN, and α-In2Se3 were secured using physical peeling. These were then sequentially transferred onto the gate electrode using a dry transfer method to form a heterojunction structure with a CIPS / h-BN / α-In2Se3 (ferroelectric layer / insulating layer / channel layer) structure. Finally, source and drain electrodes were deposited spaced apart on the α-In2Se3 (channel layer). Specifically, both the source and drain electrodes used a structure in which 60-nm-thick gold (Au) was stacked on a 10-nm-thick titanium (Ti) layer.

[0098] FIG. 17 is a diagram illustrating the results of AFM analysis of the ferroelectric layer of the Fe FET device according to an experimental example of the present invention.

[0099] Figure 17 shows the results of AFM (Atomic Force Microscopy) analysis of the ferroelectric layer (CIPS) of the Fe FET device according to the experimental example, and the thickness of the ferroelectric layer measured thereby. From Figure 17, it can be seen that the ferroelectric layer (CIPS) has a thickness of approximately 75 nm.

[0100] FIG. 18 is a diagram illustrating the results of AFM analysis of the insulating layer of the Fe FET element according to an experimental example of the present invention.

[0101] Figure 18 shows the results of AFM (Atomic Force Microscopy) analysis of the insulating layer (hBN) of the Fe FET device according to the experimental example, and the thickness of the ferroelectric layer measured thereby. From Figure 18, it can be seen that the insulating layer (hBN) has a thickness of approximately 12 nm.

[0102] FIG. 19 is a diagram illustrating the results of AFM analysis of the channel layer of the Fe FET device according to an experimental example of the present invention.

[0103] Figure 19 shows the results of AFM (Atomic Force Microscopy) analysis of the channel layer (α-In2Se3) of the Fe FET device according to the experimental example, and the thickness of the channel layer measured thereby. From Figure 19, it can be seen that the channel layer (α-In2Se3) has a thickness of approximately 45 nm.

[0104] FIG. 20 is a diagram illustrating the results of Raman analysis of the heterojunction structure of the Fe FET device according to an experimental example of the present invention.

[0105] Figure 20 shows Raman spectra for the ferroelectric layer (CIPS), channel layer (α-In2Se3), and CIPS / α-In2Se3 junction structure of the FeFET device according to the experimental example. Specifically, the black line shows the measurement results for the channel layer (α-In2Se3), the red line shows the measurement results for the ferroelectric layer (CIPS), and the blue line shows the measurement results for the CIPS / α-In2Se3 junction structure. Figure 20 shows the Raman peaks, confirming that conventional α-In2Se3 and CIPS were used.

[0106] FIG. 21 shows a TEM image and an EDS mapping image of the heterojunction structure of the Fe FET device according to an experimental example of the present invention.

[0107] FIG. 21 shows a TEM (Transmission Electron Microscope) image and an EDS (Energy Dispersive X-ray Spectroscopy) mapping image of the heterojunction structure (CIPS / h-BN / α-In2Se3) of the Fe FET device according to the above experimental example.

[0108] From FIG. 21, it can be seen that CIPS and α-In2Se3 are clearly separated by h-BN, and the composition of each layer (ferroelectric layer, insulating layer, channel layer) is also clearly separated.

[0109] (Experimental Example 2: Operation of Fe FET device) FIG. 22 is a diagram showing the positions where AFM scanning was used to confirm the operation of the Fe FET device according to the experimental example of the present invention.

[0110] Figure 22 shows the locations where AFM (Atomic Force Microscopy) scanning was used to confirm the operation of the FeFET device according to the above experimental example. Specifically, the white dotted line area (channel layer area) between the source electrode (S) and the drain electrode (D) indicates the measurement area using KPFM (Kelvin probe force microscopy) in Figures 23 and 24, which will be described later, and the white box area (channel layer area) indicates the measurement area using PFM (Piezoresponse force microscopy) in Figures 25 and 26, which will be described later.

[0111] FIG. 23 shows the surface potential measured in the channel layer between the source and drain electrodes when a negative voltage is applied to the gate electrode, and FIG. 24 shows the surface potential measured in the channel layer between the source and drain electrodes when a positive voltage is applied to the gate electrode.

[0112] 23 and 24 show the surface potential (V) measured using KPFM (Kelvin probe force microscopy) for the white dotted line area, as described in Fig. 22. More specifically, Fig. 23 shows the surface potential measured when a negative voltage is applied to the gate electrode, and Fig. 24 shows the surface potential measured when a positive voltage is applied to the gate electrode.

[0113] 23 and 24, it can be seen that the gradient of the surface potential when a negative voltage is applied to the gate electrode (increasing from the source electrode to the drain electrode) and the gradient of the surface potential when a positive voltage is applied (decreasing from the source electrode to the drain electrode) show opposite trends. In other words, when a voltage is applied to the gate electrode, horizontal (in-plane, IP) polarization occurs in the channel layer (α-In2Se3), but the positions of the negative and positive charges in the dipole moment are reversed depending on the polarity of the applied voltage (positive or negative voltage).

[0114] In addition, the voltage applied to the gate electrode generates out-of-plane (OOP) polarization in the ferroelectric layer (CIPS), which in turn generates out-of-plane (OOP) polarization in the channel layer (α-In2Se3), and the out-of-plane (OOP) polarization in the channel layer (α-In2Se3) also generates in conjunction with the in-plane (IP) polarization in the channel layer (α-In2Se3).

[0115] FIG. 25 is a diagram showing an image of the PFM phase under dark conditions, FIG. 26 is a diagram showing the values ​​of the PFM phase measured when voltages of opposite polarities are applied to the gate electrodes under dark conditions, and FIG. 27 is a diagram showing a schematic diagram of dipole polarization under dark conditions.

[0116] 25 to 27 show the PFM phase values ​​(Phase) measured using PFM (piezoresponse force microscopy) for the white box area under dark conditions (conditions where no light is irradiated), as explained in FIG. 22. More specifically, FIG. 26 shows the PFM phase values ​​(Phase) measured under dark conditions (conditions where no light is irradiated) for the white box area under dark conditions (conditions where no light is irradiated). G ) is applied with a voltage of -10 V and a voltage of +10 V, and Figure 27 shows the PFM phase values ​​measured when the gate voltage (V G The dipole polarization in the ferroelectric layer (CIPS) and the channel layer (α-In2Se3) is shown when a voltage of -10 V and a voltage of +10 V are applied to the ferroelectric layer (CIPS) and the channel layer (α-In2Se3).

[0117] 25 to 27, it can be seen that spontaneous ferroelectric polarization (180° phase difference) occurs when voltages of opposite polarities (+10V and -10V) are applied under dark conditions. This means that under dark conditions, by controlling the polarity of the voltage applied to the gate electrode inversely, the dipole direction due to the transverse (IP) polarization of the channel layer can be reversed (the positions of the negative and positive charges can be switched by 180°).

[0118] FIG. 28 shows an image of the PFM phase under bright conditions, FIG. 29 shows the values ​​of the PFM phase measured when voltages of opposite polarities are applied to the gate electrodes under bright conditions, and FIG. 30 shows a schematic diagram of dipole polarization under bright conditions.

[0119] 28 to 30, as explained in FIG. 22, the PFM phase values ​​were measured using PFM (piezoresponse force microscopy) for the white box area under bright conditions (conditions where light of 655 nm wavelength was irradiated). More specifically, FIG. 29 shows the PFM phase values ​​measured under the gate voltage (V G ) is applied with a voltage of -10V and a voltage of +10V, and Figure 30 shows the PFM phase value (Phase) measured when the gate voltage (V G ) shows the dipole polarization in the ferroelectric layer (CIPS) and the channel layer (α-In2Se3) when a voltage of -10 V and a voltage of +10 V are applied.

[0120] 28 to 30, it can be seen that weak ferroelectric polarization (<180°) occurs when voltages of opposite polarity (+10 V and -10 V) are applied under bright conditions (light-irradiated conditions). This means that under bright conditions, unlike dark conditions, the dipole direction due to the horizontal (IP) polarization in the channel layer can be reversed (the positions of negative and positive charges can be switched by 180°) even if the polarity of the voltage applied to the gate electrode is reversed. This means that the horizontal (IP) polarization generated in the channel layer is more influenced by the light irradiated on the channel layer than by the voltage applied to the gate electrode.

[0121] (Experimental Example 3: Role of the insulating layer in Fe FET devices) FIG. 31 is a diagram illustrating the voltage-current characteristics of an Fe FET device according to an experimental example of the present invention, and FIG. 32 is a diagram illustrating the voltage-current characteristics of an Fe FET device according to a comparative example of the present invention.

[0122] 31 and 32, after preparing the Fe FET device according to the experimental example and the Fe FET device according to the comparative example, the gate electrode-source electrode voltage (V GS ) drain electrode-source electrode current (I DS ), and gate electrode-source electrode current (I GS More specifically, the Fe FET device used in the comparative example was the same as the Fe FET device used in the experimental example, except that the insulating layer (h-BN) was omitted and the ferroelectric layer (CIPS) and the channel layer (α-In2Se3) were in direct contact with each other.

[0123] It can be seen from Figure 31 that the Fe FET device according to the experimental example had almost no gate leakage current, whereas it can be seen from Figure 32 that the Fe FET device according to the comparative example had severe gate leakage current. In other words, it can be seen that the problem of gate leakage current can be significantly alleviated by disposing an insulating layer (h-BN) between the ferroelectric layer (CIPS) and the channel layer (α-In2Se3).

[0124] (Experimental Example 4: Ferroelectricity and Electrical Synapse Characteristics of Fe FET Devices) FIG. 33 is a graph illustrating the change in transfer characteristics depending on the scanning voltage range of an Fe FET device according to an experimental example of the present invention, and FIG. 34 is a graph illustrating the change in transfer characteristics depending on the read voltage range of an Fe FET device according to an experimental example of the present invention.

[0125] Figure 33 shows the gate voltage (V) sweeping across ±5V, ±8V, and ±10V. GS) conditions, the voltage (V GS , V) due to the current (I DS , A) are measured and shown. From Figure 33, as the gate voltage condition increases (from ±5V to ±10V), the transfer characteristic curve (I D -V G ) increases.

[0126] Figure 34 shows the results for source-drain voltages of 0.2V and 0.5V (V DS ) conditions, the voltage (V GS , V) due to the current (I DS , A) are measured and shown in Figure 34. DS ) conditions change, the transfer characteristic curve (I D -V G ) also appear differently.

[0127] FIG. 35 is a diagram illustrating the on / off ratio of an Fe FET device according to an experimental example of the present invention, FIG. 36 is a diagram illustrating the memory window of an Fe FET device according to an experimental example of the present invention, and FIG. 37 is a diagram illustrating the output characteristics of an Fe FET device according to an experimental example of the present invention.

[0128] FIG. 35 shows the voltage (V GS , V) on / off ratio (x10 5 ) was measured and shown in FIG. 36, the voltage (V GS 35 and 36 show the memory windows (V) measured as a function of the gate voltage. It can be seen from FIGS. 35 and 36 that the FeFET device according to this experimental example has a linear increase in on / off ratio and memory window as the voltage increases. This means that the FeFET device according to this experimental example can control its programmable performance and storage performance by controlling the gate voltage.

[0129] Figure 37 shows the I DS -V DS 37 shows the curves. It can be seen from Figure 37 that as the gate voltage increases to positive values ​​at -10V, the current increases progressively by about two times, which is consistent with the transfer characteristics.

[0130] FIG. 38 is a schematic diagram of electrical synapse measurement using an Fe FET element according to an experimental example of the present invention, FIG. 39 is a diagram illustrating the short-term depression effect of an Fe FET element according to an experimental example of the present invention, and FIG. 40 is a diagram illustrating the short-term potentiation effect of an Fe FET element according to an experimental example of the present invention.

[0131] FIG. 39 shows the effect of short term potentiation (STP) simulated with a 0.2V bias and electrical pulses (-1V, -2V, -3V, -4V, -5V) to read out the Fe FET device according to the above experimental example.

[0132] From Figure 39, it can be seen that the PSC increases rapidly when a negative voltage pulse is applied, and decreases rapidly when the pulse is removed. It can also be seen that the highest PSC value increases with increasing pulse amplitude. This effect can easily be seen as the short-term potentiation (STP) behavior of the device.

[0133] FIG. 40 shows the effect of a simulated short term depression (STD) with a bias of −0.2V and electrical pulses (+1V, +2V, +3V, +4V, +5V) to read out the Fe FET device according to the above experimental example.

[0134] It can be seen from Figure 40 that the PSC value increases under the action of a voltage pulse and then decreases to the lowest current level when the pulse is removed before returning to the initial state. This effect can easily be mimicked by the short-term depression (STD) behavior of the device.

[0135] (Experimental Example 5: Optical signal sensing and memory conversion characteristics of Fe FET device) FIG. 41 shows a model for the optical signal sensing and information storage process.

[0136] Figure 41 shows a model of how external optical signal stimuli are converted from short-term memory (STM) to long-term memory (LTM). More specifically, sensory memory is generated from external optical stimuli, transferred to short-term memory (STM), and then, after several rehearsals, can be converted to long-term memory (LTM).

[0137] FIG. 42 is a diagram illustrating current values ​​depending on the number of signals input to an Fe FET device according to an example of the present invention, FIG. 43 is a diagram illustrating normalized attenuation current values ​​depending on the number of signals input to an Fe FET device according to an example of the present invention, and FIG. 44 is a diagram illustrating conversion of short-term memory to long-term memory through an Fe FET device according to an example of the present invention.

[0138] Figure 42 shows the change in current value when the channel layer of the Fe FET device according to the experimental example is repeatedly irradiated with light of 655 nm wavelength for each pulse number. Figure 43 shows the normalized current decay extracted from Figure 42. The memory state induced by the light pulse can be determined by analyzing the results of Figures 42 and 43 using the Kohlrausch stretched exponential function shown in Equation 1 below. Equation 1 represents a function for modeling spontaneous retention loss.

[0139]

number

[0140] Figure 44 shows the characteristic relaxation time (s) obtained after data fixation as a function of wavelength (nm) and pulse number. Figure 44 confirms that increasing the pulse number from 2 to 10 improves the relaxation time (τ) from 1.08 seconds to 102.2 seconds. This indicates that information can be converted from short-term memory (STM) to long-term memory (LTM) through rehearsal. Furthermore, this relaxation phenomenon is caused by the strong cohesive interaction between α-In2Se3 dipoles induced by multiple light pulses.

[0141] FIG. 45 is a diagram for explaining the PPF measurement results of the Fe FET element according to an experimental example of the present invention.

[0142] FIG. 45 shows the results of applying a wavelength of 655 nm and 0.33 mW / cm to the channel layer of the Fe FET device according to the above experimental example. 2 The figure shows the change in current measured when a pair of lights with intensities of 1 and 2 are irradiated at a time interval of 1 second. The peak amplitude ratio of the second (A2) pulse to the first (A1) pulse received by the synapse of two consecutive signals is defined as the PPF ratio (A2 / A1).

[0143] 46 to 49 are diagrams for explaining the PPF ratio of the Fe FET element according to the experimental example of the present invention.

[0144] Figure 46 shows the change in PPF ratio depending on the time interval (s) between two input signals under the conditions of Figure 45. From Figure 46, it can be seen that a high PPF ratio of up to 170% is achieved during a time interval of 1 second. This high PPF ratio means that the Fe FET device according to this experimental example transfers residual information from the first signal to the second signal while minimizing information loss.

[0145] Figure 47 shows the change in the PPF ratio depending on the time interval (s) between two input signals under the same conditions as Figure 45, 405 nm wavelength. Figure 47 shows that the PPF ratio is approximately 130% for a time interval of 1 second.

[0146] Figure 48 shows the change in the PPF ratio depending on the time interval (s) between two input signals under the same conditions as Figure 45, 785 nm wavelength. Figure 48 shows that the PPF ratio is approximately 130% for a time interval of 1 second.

[0147] Figure 49 shows the change in the PPF ratio depending on the time interval (s) between two input signals under the same conditions as Figure 45, that is, under the condition of 850 nm wavelength. From Figure 49, it can be seen that the PPF ratio is approximately 112% for a time interval of 1 second.

[0148] Furthermore, based on the results of Figures 46 to 49, we derived Equation 2 to calculate PPF (Paired Pulse Facilitation). Equation 2 represents a parameter that indicates the degree of change in synaptic weight when two consecutive pulses are applied.

[0149]

number

[0150] FIG. 50 shows the fast and slow relaxation times of the decay curves for various wavelengths.

[0151] The fast relaxation time (τ1) and slow relaxation time (τ2) of the decay curves for different wavelengths (405 nm, 655 nm, 785 nm, and 850 nm) are shown in Figure 50. The fast relaxation time (τ1) and slow relaxation time (τ2) values ​​in Figure 50 were derived using Equation 2.

[0152] (Experimental Example 6: Optical response characteristics of Fe FET element due to electric field) FIG. 51 is a diagram for explaining the influence of an electric field on an Fe FET element under the condition that it is irradiated with light having a wavelength of 405 nm.

[0153] FIG. 51 shows the normalized conductance measured against the dark current after irradiating the channel layer of the Fe FET device according to the above experimental example with 10 light pulses (405 nm wavelength), each with an on / off time of 1 second, and applying a voltage in the range of −2 V to +2 V to the gate electrode.

[0154] It can be seen from FIG. 51 that the normalized conductance appears higher when a negative (-) voltage is applied to the gate electrode than when a positive (+) voltage is applied.

[0155] FIG. 52 is a diagram for explaining the influence of an electric field on an Fe FET element under the condition that it is irradiated with light having a wavelength of 655 nm.

[0156] FIG. 52 shows the normalized conductance measured for the dark current after irradiating the channel layer of the Fe FET device according to the above experimental example with 10 light pulses (655 nm wavelength), each with an on / off time of 1 second, and applying a voltage in the range of −2 V to +2 V to the gate electrode.

[0157] It can be seen from FIG. 52 that the normalized conductance appears higher when a negative (-) voltage is applied to the gate electrode than when a positive (+) voltage is applied.

[0158] FIG. 53 is a diagram for explaining the influence of an electric field on an Fe FET element under the condition that it is irradiated with light having a wavelength of 785 nm.

[0159] Figure 53 shows the normalized conductance versus dark current measured after irradiating the channel layer of the Fe FET device according to the experimental example with 10 light pulses (785 nm wavelength), each with an on / off time of 1 second, and applying a voltage in the range of -2 V to +2 V to the gate electrode.

[0160] It can be seen from FIG. 53 that the normalized conductance appears higher when a negative (-) voltage is applied to the gate electrode than when a positive (+) voltage is applied.

[0161] FIG. 54 is a diagram for explaining the influence of an electric field on an Fe FET element under the condition that it is irradiated with light having a wavelength of 850 nm.

[0162] Figure 54 shows the normalized conductance versus dark current measured after irradiating the channel layer of the Fe FET device according to the experimental example with 10 light pulses (850 nm wavelength), each with an on / off time of 1 second, and applying a voltage in the range of -2 V to +2 V to the gate electrode.

[0163] It can be seen from FIG. 54 that the normalized conductance appears higher when a negative (-) voltage is applied to the gate electrode than when a positive (+) voltage is applied.

[0164] That is, from Figures 51 to 54, it can be seen that a negative (-) gate voltage shows the maximum response for all wavelengths compared to a positive (+) gate voltage.

[0165] (Experimental Example 7: Pattern Recognition Using Optical Enhancement and Electrical Deactivation of Fe FET Devices) 55 to 58 are diagrams illustrating the synapse weight update characteristics of the Fe FET device according to the experimental example of the present invention.

[0166] In Figure 55, for synaptic weight update of the FeFET device according to the above experimental example, a light pulse (655 nm wavelength) with a pulse width of 1 second was continuously irradiated to control the polarization of the channel layer (α-In2Se3), thereby potentiating the device. After that, the light pulse was removed, and a continuous positive voltage with an amplitude of +2 V was applied to the gate electrode to reposition the dipole to the initial condition, thereby depressing the device. All optical and electrical pulses were used in a number of 64, and the readout voltage (V DS ) was controlled at 0.2V.

[0167] In Figure 56, for synaptic weight update of the FeFET device according to the above experimental example, a light pulse (405 nm wavelength) having a pulse width of 1 second was continuously irradiated to control the polarization of the channel layer (α-In2Se3), thereby potentiating the device. After that, the light pulse was removed, and a continuous positive voltage with an amplitude of +2V was applied to the gate electrode to reposition the dipole to the initial condition, thereby depressing the device. All optical and electrical pulses were used in a number of 64, and the readout voltage (V DS ) was controlled at 0.2V.

[0168] In Figure 57, for updating the synaptic weights of the FeFET device according to the above experimental example, a light pulse (785 nm wavelength) with a pulse width of 1 second was continuously irradiated to control the polarization of the channel layer (α-In2Se3), thereby potentiating the device. After that, the light pulse was removed, and a continuous positive voltage with an amplitude of +2 V was applied to the gate electrode to reposition the dipole to the initial condition, thereby depressing the device. All optical and electrical pulses were used in sets of 64, and the readout voltage (VDS ) was controlled at 0.2V.

[0169] As shown in Figure 58, to update the synaptic weights of the FeFET device according to the experimental example, a series of 1-second light pulses (850 nm wavelength) were applied to control the polarization of the channel layer (α-In2Se3), resulting in potentiation of the device. The light pulses were then removed, and a series of positive voltages with an amplitude of +2V were applied to the gate electrode to reposition the dipoles to their initial conditions, resulting in depression of the device. All optical and electrical pulses were used in sets of 64, and the readout voltage (VDS) was controlled at 0.2V.

[0170] 55 to 58 show that the Fe FET device according to the experimental example increases with an optical signal and decreases with an electrical signal. Furthermore, it can be seen that the Fe FET device according to the experimental example has synaptic weight update characteristics that are essential for the development of HNNs (Human Neural Networks).

[0171] In addition, the synaptic weights are updated through the following equations 3 and 4. More specifically, equation 3 is used to calculate the nonlinearity in the LTP curve, and equation 4 is used to calculate the nonlinearity in the LTD curve.

[0172]

number

[0173]

number

[0174] FIG. 59 is a diagram illustrating the long-term stability of the synaptic weight update characteristics of the Fe FET device according to an experimental example of the present invention.

[0175] Figure 59 shows that the FeFET device according to the above experimental example was irradiated with light to increase the voltage, then the gate voltage was applied and decreased, for one cycle. The change was measured over five consecutive cycles. Figure 59 shows that stable increase and decrease were observed even during five consecutive cycles.

[0176] Figure 60 is a schematic diagram of an ANN for MNIST pattern recognition.

[0177] Figure 60 shows a schematic diagram of an ANN based on a simple perceptron (single layer perceptron) for MNIST pattern recognition. It consists of 400 input neurons, 100 hidden neurons, and 10 output neurons, and the MNIST dataset is image data consisting of 400 pixels ranging from 0 to 10.

[0178] FIG. 61 is a diagram for explaining the pattern recognition accuracy by Epoch.

[0179] Figure 61 shows the results of a pattern recognition simulation using a 10,000-image dataset after training on 8,000 randomly selected images from 60,000 images. Specifically, the gray line shows the simulation results for an ideal synapse, and the red line shows the simulation results for the Fe FET device according to the experimental example. Figure 61 shows that after 125 epochs, the ideal synapse device achieved an accuracy of 94%, while the Fe FET device according to the experimental example achieved an accuracy of 92.5%. This indicates that the Fe FET device according to the experimental example resembles the response of an ideal system for forming an ANN (Artificial Neural Network).

[0180] (Experimental Example 8: Light Adaptation Test of Fe FET Device) Figure 62 is a diagram for explaining the results of the light adaptation test when a weak light stimulus is applied, Figure 63 is a diagram for explaining the results of the light adaptation test when a strong light stimulus is applied, and Figure 64 is a diagram for explaining the results of the light adaptation test when strong light stimulus and electrical stimulus are applied.

[0181] From Figure 62, when the light intensity is low (15.3 μW / cm 2 It can be seen from Figure 63 that the current value measured at high light intensity (0.324 mW / cm , 1 second width, 655 nm wavelength) is lower than the critical current value (approximately 45 pA). 2 ) is higher than the critical current value. This is similar to the situation when the iris does not function properly and the retina is pinched by external lighting.

[0182] To prevent such high currents from flowing through the device due to the high-intensity optical illumination, we applied a positive voltage (+4V) pulse to the gate electrode to modulate synaptic function and control the measured current below the critical current value, as shown in Figure 64. This phenomenon represents a realistic imitation of the biological eye, and this technology can be applied to developing brain-inspired neural networks.

[0183] (Experimental Example 9: Logic operation of Fe FET device) FIG. 65 is a diagram showing an OR logic operation based on optical signal changes and electrical signal changes, and FIG. 66 is a diagram showing an AND logic operation based on optical signal changes and electrical signal changes.

[0184] In Figures 65 and 66, logical operations such as "OR" and "AND" functions were realized from the optical signal changes and electrical signal changes. More specifically, light with wavelengths of 655 nm and 850 nm was used as an optical spike for the optical input signal. At the same time, electrical pulses of +2 V and -2 V were applied to the gate electrodes as electrical inputs to perform the "OR" and "AND" operations, respectively. V was used as the read voltage. DS A voltage of 0.2V was used, and both experiments were performed at the same critical current value (25 pA). Current sizes above and below the critical level can be considered as "1" (S=1) and "0" (S=0), respectively. Thus, "OR" and "AND" logic functions were determined by electrical spikes at the gate electrodes, modulated by the input optical signal. The FeFET device of this example also demonstrates optical logic operations, another step toward performing in-memory calculations in a single device.

[0185] (Experimental Example 10: Multistate of Fe FET element) FIG. 67 is a diagram illustrating the multistate characteristics of an Fe FET element according to an experimental example of the present invention.

[0186] FIG. 67 shows the photocurrent measured after irradiating the FeFET device according to the experimental example with light of four different wavelengths (655 nm, 405 nm, 785 nm, and 850 nm). It can be seen from FIG. 67 that four different current values ​​appear when light of four different wavelengths (655 nm, 405 nm, 785 nm, and 850 nm) is irradiated. This indicates that the FeFET device according to the experimental example has multi-state characteristics. Furthermore, by using light of various wavelengths together with electrical signals, it is expected that more logic functions, such as "XOR" and "NAND" in addition to "OR" and "AND," can be realized.

[0187] (Experimental Example 11: Pavlov's Dog Experiment with Fe FET Device) Figure 68 is a graph showing the current value when a conditioned stimulus is applied, Figure 69 is a graph showing the current value when an unconditioned stimulus is applied, Figure 70 is a graph showing the current value when a conditioned stimulus and an unconditioned stimulus are applied simultaneously, and Figure 71 is a graph showing the current value when only the conditioned stimulus is applied after training.

[0188] Figure 68 shows the current value when a conditioned stimulus (a bell ring, a pulse voltage applied to the gate electrode) is applied. Since the current value is lower than the critical value, this means that there is no saliva secretion. Figure 69 shows the current value when an unconditioned stimulus (food, light irradiated onto the channel layer) is applied. Since the current value is higher than the critical value, this means that saliva secretion occurs. In Figure 70, the current value is higher than the critical value, which means that saliva secretion occurs when the conditioned stimulus and the unconditioned stimulus are applied simultaneously. In Figure 71, the current value is higher than the critical value, which means that saliva secretion occurs even when only the conditioned stimulus is applied after training.

[0189] More specifically, the occurrence of one of the conditioned events, after successful training, among simultaneously occurring events, triggers memory recall of the other events. Here, an optical stimulus, like food (the unconditioned stimulus), was considered visual information and imitated using electrical pulses. To imitate the behavior of a bell, 30 electrical pulses with an amplitude of -4 V and a duration of 1 s were applied (Figure 68), demonstrating that the conditioned stimulus alone is not effective in inducing salivation at currents below the critical level (5 pA). In comparison, the unconditioned stimulus (wavelength 655 nm, intensity 0.33 mW / cm) 2 A 50-second light pulse (50 s wide) can induce salivation, indicating that a current above the critical level is passing through the device (Figure 69). Figure 70 shows the process in which a conditioned event and an unconditioned event occur simultaneously. During the training process, the current passing through the device is higher than the critical level, indicating that the reflex between the optical stimulus and the electrical stimulus has been established as an associated event. Once this training is complete, the conditioned stimulus (electrical pulse) alone can induce a high current (above the critical level) passing through the device, and the sensation is maintained for a long period of time. Figure 71 shows that this event is recognized by repeatedly applying an electrical pulse every 200 seconds. It can be seen that the FeFET device from the above experiment can retain information for more than 2,400 seconds.

[0190] Although the present invention has been described in detail using preferred embodiments, the scope of the present invention should not be limited to the specific embodiments, but should be interpreted by the appended claims. Furthermore, those skilled in the art will understand that many modifications and variations are possible without departing from the scope of the present invention. [Explanation of symbols]

[0191] 100 boards 110 Si substrate 120 SiO2 layer 200 gate electrode 300 Ferroelectric layer 400 insulating layer 500 channel layer (first channel layer) 600 Second channel layer 700 oxide layer S, S1, S2 source electrode, first source electrode, second source electrode D drain electrode

Claims

1. providing a substrate including a first region and a second region different from the first region; forming a gate electrode on the first region of the substrate; On the gate electrode, CuInP 2 S 6 forming a ferroelectric layer comprising (CIPS); forming an insulating layer comprising hexagonal boron nitride (h-BN) on the ferroelectric layer; On the insulating layer, alpha-indium selenide (α-In 2 Se 3 forming a first channel layer comprising: forming a second channel layer comprising Mxene on the second region of the substrate; forming a first source electrode on one side of an upper surface of the first channel layer; forming a drain electrode shared by the first channel layer and the second channel layer so as to contact the other side of the upper surface of the first channel layer and one side of the upper surface of the second channel layer; and forming a second source electrode on the other side of the upper surface of the second channel layer; forming an oxide layer containing titanium oxide on the upper surface of the second channel layer exposed between the drain electrode and the second source electrode.

2. 2. The method for manufacturing a heterojunction structure device according to claim 1, wherein the ferroelectric layer comprises CuInP 2 S 6 (CIPS), and the CIPS has out-of-plane (OOP) polarization characteristics.

3. 2. The method for manufacturing a heterojunction structure element according to claim 1, wherein the first channel layer comprises alpha-indium selenide (α-In 2 Se 3 ), and the alpha-indium selenide (α-In 2 Se 3 ) has out-of-plane (OOP) polarization characteristics and in-plane (IP) polarization characteristics.

4. the gate electrode includes a first gate electrode and a second gate electrode; the first gate electrode and the second gate electrode are formed in the first region of the substrate and spaced apart from each other; 2. The method for manufacturing a heterojunction structure element according to claim 1, wherein the ferroelectric layer is formed on the first gate electrode and the second gate electrode.

Images