Semiconductor Devices

Abstract

To provide a semiconductor device capable of quickly responding to occurring interruption processing at high frequency while guaranteeing reliability of a nonvolatile memory.SOLUTION: In a semiconductor device having a nonvolatile memory capable of electrically writing and erasing and a control circuit for executing a mode control of the writing operation and the erasing operation of the nonvolatile memory, the nonvolatile memory includes: a rewriting interruption / recovery control circuit that responds to an interruption request signal from the control circuit requesting interruption of a rewriting operation, responds to a return request signal from the control circuit requesting returning from the operation for interrupting application of a write voltage and an erase voltage and the interruption of the rewriting operation, and controls the operation to return from the interruption of applied voltage and outputs a voltage applying stop flag to the control circuit when application of the write voltage and the erase voltage is stopped; and a rewriting information holding circuit that holds rewriting position information for identifying a selection line to which a rewriting voltage is applied in response to an interruption request signal.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device including a nonvolatile memory. [Background technology]

[0002] Recent MCUs (Micro Control Units) have become required to support multiple CPU (Central Processing Unit) cores and OTA (Over-The-Air) functionality. Under these circumstances, the frequency of conflicts between write and erase requests to nonvolatile memory has become significant. Specifically, with the adoption of multiple CPU cores, the number of CPU cores exceeds the number of flash banks, which can lead to frequent conflicts between write and erase requests to the same bank. Furthermore, OTA functionality requires firmware updates, which can lead to frequent conflicts between write and erase requests for recording field information, such as for vehicles.

[0003] For example, Patent Document 1 discloses a technology for shortening the transition time from the supply of an interrupt command due to an interrupt during a write or erase operation to the actual interruption. Specifically, in response to an interrupt command during a write or erase operation, the application of a write voltage or erase voltage is asynchronously released, thereby shortening the prohibition period (interruption processing time) of the write or erase operation. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-34045 Summary of the Invention [Problem to be solved by the invention]

[0005] Despite the above-described operational innovations, when a write or erase operation is resumed, the write or erase voltage must be applied to the same area again. Therefore, to ensure the reliability of the nonvolatile memory, the interrupt instruction is limited to a single use. Therefore, the interrupt processing time cannot be shortened from the second interrupt instruction onward, resulting in a slow response to the second interrupt instruction onward. However, as mentioned above, with the increasing need for multi-CPU cores and over-the-air (OTA) functionality, it is expected that conflicts between write and erase requests will occur frequently. In this case, conventional technologies find it difficult to respond quickly to frequently occurring interrupt operations while ensuring the reliability of the nonvolatile memory.

[0006] The present disclosure has been made in view of the above. One of its objectives is to provide a semiconductor device that can respond quickly to interrupt processes that occur frequently while ensuring the reliability of nonvolatile memory. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A typical example of the inventions disclosed in the present application can be briefly outlined as follows: A typical semiconductor device includes an electrically writable or erasable nonvolatile memory, and a control circuit for executing mode control of write and erase operations of the nonvolatile memory, wherein the nonvolatile memory controls an operation of interrupting application of a write voltage or an erase voltage in response to an interrupt request signal from the control circuit requesting interruption of a write operation including at least one of a write operation and an erase operation, and an operation of recovering from the interruption of application of the write voltage or the erase voltage in response to a recovery request signal from the control circuit requesting recovery from the interruption of the write operation, and outputs a voltage application stop flag to the control circuit when application of the write voltage or the erase voltage is stopped; and a rewrite information holding circuit that holds write position information for identifying a selected line to which a write voltage is applied in response to a request signal, or erase position information for identifying a selected line to which an erase voltage is applied in response to an interrupt request signal, wherein the control circuit responds to an interrupt command when the nonvolatile memory is in a write mode or an erase mode and transmits a rewrite interrupt request signal to the rewrite interrupt / restore control circuit, and responds to a command to restore the write mode or erase mode of the nonvolatile memory that was interrupted by the interrupt request signal and outputs a rewrite restore request signal to the rewrite interrupt / restore control circuit when the voltage application stop flag output from the rewrite interrupt / restore control circuit is active. [Effects of the Invention]

[0008] According to one embodiment, it is possible to provide a semiconductor device that can respond quickly to interrupted processing that occurs frequently while ensuring the reliability of the nonvolatile memory. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a timing chart illustrating an example of an outline of the operation of the semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the progress of the rewrite operation of the semiconductor device according to the first embodiment. [Figure 3]FIG. 3 is a block diagram showing an example of the configuration of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a timing chart showing an example of a rewrite operation of the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a timing chart showing an example of a rewrite operation of the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a timing chart showing an example of the rewrite operation of the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a timing chart showing an example of the rewrite operation of the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 shows a part of an example showing the performance of the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a diagram showing the relationship between rewritable areas of a semiconductor device according to a modification of the first embodiment. [Figure 10] FIG. 10 is a diagram showing an example of the progress of the rewrite operation of the semiconductor device according to the modification of the first embodiment. [Figure 11] FIG. 11 is a block diagram showing an example of the configuration of a semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is related to the other as a partial or complete modification, detail, supplementary explanation, etc. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited in principle to a specific number, etc.

[0011] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0012] Furthermore, although not particularly limited, the circuit elements constituting each functional block of the embodiment are formed on a semiconductor substrate such as single crystal silicon by known integrated circuit technology such as CMOS (complementary metal oxide semiconductor).

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations thereof will be omitted. Furthermore, the dimensional proportions in the drawings are exaggerated for the sake of explanation and may differ from the actual proportions.

[0014] (Embodiment 1) Fig. 1 is a diagram showing an example of a schematic timing chart of the semiconductor device according to embodiment 1. The timing chart of Fig. 1 shows an example of the relationship between the application timing of a write voltage or an erase voltage applied to each of a plurality of source lines of a nonvolatile memory, and the timing I1 at which an interrupt request signal for a write operation or an erase operation is generated and the timing R1 at which a resume request signal is generated. Each of the plurality of source lines of the nonvolatile memory is used to divide and select different, consecutive areas of the nonvolatile memory.

[0015] 1 shows the application of a write voltage or erase voltage to source line SL0, which is the source line to be selected first, and source line SL1, which is the source line to be selected next after source line SL0. Therefore, the write operation or erase operation to the nonvolatile memory area corresponding to source line SL0 and source line SL1 is completed. However, if a verify operation is required, the verify operation may be performed after the operation of the timing chart in FIG. 1 is completed.

[0016] 1 also shows a state in which an interrupt request signal is generated at timing I1 during application of a write voltage or erase voltage to source line SL2. In this case, the semiconductor device completes application of the write voltage or erase voltage to the corresponding area of ​​the nonvolatile memory corresponding to source line SL2, and then maintains an interrupted state in which application of the write voltage or erase voltage is interrupted without applying the write voltage or erase voltage to the next source line, source line SL3. After maintaining the interrupted state, when a return request signal is generated at timing R1, the semiconductor device begins applying the write voltage or erase voltage to the next source line, source line SL3. That is, the semiconductor device continues applying the write voltage or erase voltage for time t1 from the timing of generation of the interrupt request signal so as to satisfy a predetermined application width (application time: t2) of the write voltage or erase voltage.

[0017] Furthermore, if an interrupt request signal does not occur during application of the write voltage or erase voltage from source line SL3 to source line SLk (k is a positive integer greater than or equal to 4), the semiconductor device completes application of the write voltage or erase voltage from source line SL3 to source line SLk (k is a positive integer greater than or equal to 4).

[0018] As described above, the semiconductor device according to this embodiment applies the write voltage or erase voltage on a source line-by-source line basis, thereby shortening the interrupt processing time when an interrupt request signal is generated. Furthermore, the semiconductor device according to this embodiment completes the application of the write voltage or erase voltage on a source line-by-source line basis before transitioning to the interrupt state, thereby ensuring a predetermined application width (application time: t2) of the write voltage or erase voltage. Furthermore, the semiconductor device according to this embodiment completes the application of the write voltage or erase voltage on a source line-by-source line basis before transitioning to the interrupt state, and resumes application of the write voltage or erase voltage from the next source line. This prevents an increase in stress on memory cells. This means that the limited number of writable or eraseable times for nonvolatile memory is not wasted. Therefore, it is possible to eliminate the limitation on the number of times interrupt processing is used, as in the prior art. Furthermore, the semiconductor device according to this embodiment completes the application of the write voltage or erase voltage on a source line-by-source line basis in response to one interrupt request signal before accepting the next interrupt request signal. This prevents a situation in which the write operation or erase operation stops progressing even if interrupt request signals are generated frequently.

[0019] Fig. 2 is a conceptual diagram showing an example of a rewrite state of a memory area of ​​a nonvolatile memory corresponding to the timing chart of Fig. 1. In this embodiment, rewrite is a term indicating at least one of writing and erasing, and rewrite may include both writing and erasing.

[0020] As an example, the following description will be given assuming that the semiconductor device including the nonvolatile memory of Fig. 2 is mounted on a vehicle or an IoT device. That is, Fig. 2 shows the conflicting operation of the write operation / erase operation of the nonvolatile memory due to an interrupt request signal that occurs when updating the firmware over the air (FOTA) of the semiconductor device.

[0021] FIG. 2(a) is a conceptual diagram showing the data flash and code flash regions as examples of memory regions of the nonvolatile memory in this embodiment. For example, when the semiconductor device in this embodiment is mounted on a vehicle and used, the data flash may be used to rewrite field information such as the vehicle's speed and temperature. Therefore, the data flash may be used to rewrite high-priority information. Furthermore, the code flash may be used to rewrite firmware, which is a control program for a control device such as an ECU (Electronic Control Unit) of the vehicle. Therefore, firmware rewriting may take a long time. FIG. 2(a) shows a state in which firmware called user program v1.0 is written in a portion of the code flash region and the firmware code at position ta1 is currently being executed.

[0022] Figure 2(b) shows a situation in which, during execution of firmware code at position tb2 of user program v1.0, which is firmware, an erase or write operation of user program v2.0 progresses up to position tb1 in a code flash area different from that of user program v1.0. For example, Figure 2(b) may show a situation in which, during operation of an ECU controlled by user program v1.0, user program v2.0, an update program transmitted via wireless communication, is being partially written. Note that, because an erase operation may be required before writing user program v2.0, position tb1 indicates a midpoint in the erase or write operation.

[0023] FIG. 2(c) shows a state in which an erase or write operation for writing the above-mentioned high-priority field information to the data flash area is in progress during execution of the firmware code at location tb3 in the user program v1.0, which is firmware. In this case, the erase or write operation for writing the user program v2.0 is temporarily suspended. Here, the shorter the interruption processing time from the issuance of an interrupt request signal for the user program v2.0 to the interruption of the erase or write operation for writing the user program v2.0, the shorter the write wait time for the high-priority information to be written to the data flash area. This improves the processing performance of the semiconductor device. Furthermore, the shorter the write wait time, the shorter the total time from the issuance of an interrupt request signal to the completion of the erase and write operations to the data flash area, which also means that high-speed rewrite operations can be achieved.

[0024] FIG. 2(d) shows the state in which, after the erase and write operations for writing field information to the data flash area are completed and the writing of the user program v2.0 to the code flash area is completed, the vehicle's control device such as the ECU is reset and execution of the user program v2.0, which is an update program, is started.

[0025] 3 is a block diagram showing an example of the configuration of a semiconductor device 100 according to this embodiment. The semiconductor device 100 includes a CPU (Central Processing Unit) 110, a RAM (Random Access Memory) 120, a BSC (Bus State Controller) 130, a control unit 140, and a non-volatile memory 150.

[0026] The CPU 110 has a function of fetching the code of the firmware written in the nonvolatile memory 150 and controlling the semiconductor device 100 and an external electronic device (not shown) connected to the semiconductor device 100 in accordance with the firmware.

[0027] The RAM 120 has a function of temporarily storing information such as information generated by the CPU 110 by executing firmware or information written to the nonvolatile memory 150 .

[0028] The BSC 130 has a function of switching between the internal bus (IBUS) and the peripheral bus (PBUS) to switch the bus accessible to the CPU 110. For example, when the CPU 110 reads information written in the nonvolatile memory 150, the BSC 130 functions to allow the CPU 110 to access the IBUS. Also, for example, when the CPU 110 issues a command to instruct an erase operation or a write operation to the nonvolatile memory 150, the BSC 130 functions to allow the CPU 110 to access the control unit 140 via the PBUS.

[0029] When the control unit 140 receives a command from the CPU 110 via the PBUS instructing an erase operation or a write operation on the nonvolatile memory 150, it outputs an erase mode signal and / or a write mode signal S1 to the rewrite sequencer 151 described below. As mentioned above, the term "rewrite" is used in this specification as a term that includes either erasing or writing, or both erasing and writing.

[0030] Furthermore, after outputting the erase mode signal and / or write mode signal S1, the control unit 140 may receive a rewrite command for high-priority information from the CPU 110 before receiving the rewrite voltage application completion signal S2 from the rewrite sequencer 151. In this case, the control unit 140 outputs a rewrite interruption request signal S3 to the rewrite interruption / restore control circuit 153, which will be described later. Furthermore, after the control unit 140 receives an active rewrite voltage application stop flag S5 from the rewrite interruption / restore control circuit 153, when writing of the high-priority information is completed, the control unit 140 outputs a rewrite restoration request signal S4 to the rewrite interruption / restore control circuit 153. Note that writing of the high-priority information is started by the erase mode signal and / or write mode signal S1, and the control unit 140 can recognize the completion of writing of the high-priority information by receiving the rewrite voltage application completion signal S2.

[0031] The nonvolatile memory 150 includes a rewrite sequencer 151 , a nonvolatile memory cell array 152 , a rewrite interruption / recovery control circuit 153 , and a rewrite information holding circuit 154 .

[0032] When the rewrite sequencer 151 receives an erase mode signal and / or a write mode signal S1 from the control unit 140, it enters the erase mode and / or the write mode and executes the erase mode and / or the write mode. The erase mode may include operations such as a preparation stage for applying an erase voltage, an erase voltage application operation, and an erase verify operation. The write mode may include operations such as a preparation stage for applying a write voltage, a write voltage application operation, and a write verify operation. The rewrite sequencer 151 determines an area of ​​the nonvolatile memory cell array 152 to be erased and / or written by source lines SLi (i is 0 or a positive integer) and bit lines BLj (j is 0 or a positive integer).

[0033] An example of the nonvolatile memory cell array 152 is a flash memory. In the nonvolatile memory cell array 152, an area where an erase operation and / or a write operation is performed is selected by a source line, a bit line, etc. The source line is activated by application of an erase voltage during an erase operation and / or a write voltage during a write operation. In this embodiment, the operation of the semiconductor device 100 will be described mainly based on the operation of the source line.

[0034] The rewrite interruption / recovery control circuit 153 has a function of performing the following operations when it receives a rewrite interruption request signal S3 from the control unit 140, indicating a request to rewrite other information with a higher priority than the information being rewritten, while the nonvolatile memory cell array 152 is being rewritten. That is, the rewrite interruption / recovery control circuit 153 has a function of temporarily interrupting the rewrite operation being performed. The rewrite interruption / recovery control circuit 153 also has a recovery function of temporarily interrupting the rewrite operation and then resuming the interrupted rewrite operation. However, the operation of the rewrite interruption / recovery control circuit 153 differs depending on the timing of receiving the rewrite interruption request signal S3 from the control unit 140. Here, the operation of the rewrite interruption / recovery control circuit 153 that receives the rewrite interruption request signal S3 while a rewrite operation is being performed with a source line selected will be described.

[0035] Specifically, when temporarily suspending a rewrite operation in progress, the rewrite suspend / restore control circuit 153 temporarily suspends the rewrite operation after completing application of the voltage to the selected source line. That is, the rewrite suspend / restore control circuit 153 continues to apply the voltage to be applied to the selected source line for a predetermined time without performing the suspend operation. Then, the rewrite suspend / restore control circuit 153 temporarily suspends the rewrite operation before applying the voltage to be applied to the source line to be selected next. After temporarily suspending the rewrite operation, the rewrite suspend / restore control circuit 153 outputs a rewrite voltage application start / stop signal S6, which activates information indicating the suspension of rewrite voltage application, to the rewrite sequencer 151. Upon receiving the rewrite voltage application start / stop signal S6, the rewrite sequencer 151 outputs identification information S7 of the source line to be selected next to the rewrite suspend / restore control circuit 153. The rewrite interruption / recovery control circuit 153 receives the identification information S7 of the source line to be selected next and outputs the identification information S7 as S9 to the rewrite information holding circuit 154. The rewrite interruption / recovery control circuit 153 also activates the rewrite voltage application stop flag S5 and outputs the rewrite voltage application stop flag S5 to the control unit 140.

[0036] In addition, when the rewrite interruption / return control circuit 153 receives a rewrite return request signal S4 from the control unit 140, it reads out the identification information S8 of the source line to be selected next from the rewrite information holding circuit 154, and outputs a rewrite voltage application start / stop signal S6 including the identification information to the rewrite sequencer 151.

[0037] The rewrite information holding circuit 154 has a function of receiving identification information S9 of the source line to be selected next from the rewrite interruption / recovery control circuit 153 and storing the identification information. In addition, the identification information stored in the rewrite information holding circuit 154 can be read by the rewrite interruption / recovery control circuit 153 that has received the rewrite recovery request signal S4.

[0038] (Difference in operation mode depending on timing of receiving rewrite interruption request signal S3) 4 to 7 show different operation modes of the semiconductor device 100 when the rewrite interruption request signal S3 is generated at different timings in the rewrite mode.

[0039] 4 shows the operation mode of the semiconductor device 100 when the semiconductor device 100 is in the rewrite mode M11 and a rewrite interruption request signal S3 is input to the rewrite interruption / restore control circuit 153 before the rewrite voltage is applied to the source line SL0. If the rewrite interruption request signal S3 is input to the rewrite interruption / restore control circuit 153 before the rewrite voltage is applied to the source line SL0, the semiconductor device 100 executes the voltage application sequence process, such as power supply setup for applying the rewrite voltage, regardless of the input of the rewrite interruption request signal S3. The semiconductor device 100 then selects the first source line (SL0) of the rewrite area of ​​the nonvolatile memory cell array 152 and applies the rewrite voltage. The rewrite voltage application period is a predetermined rewrite period (t11) for rewrite. After applying the rewrite voltage for the rewrite period, the semiconductor device 100 causes the rewrite interruption / recovery control circuit 153 to stop applying the rewrite voltage, activate the rewrite voltage application stop flag S5, and output the rewrite voltage application stop flag S5 to the control unit 140. The rewrite interruption / recovery control circuit 153 receives, from the rewrite sequencer 151, identification information of the second source line (SL1) to which the rewrite voltage should be applied next after the first source line (SL0), and outputs the identification information to the rewrite information holding circuit 154. The rewrite information holding circuit 154 stores the identification information of the second source line (SL1).

[0040] 4, when a rewrite recovery request signal S4 is input from the control unit 140 to the rewrite interruption / recovery control circuit 153 at timing R2, the semiconductor device 100 transitions to the rewrite mode M12. Then, the rewrite interruption / recovery control circuit 153 reads out the identification information of the second source line (SL1) from the rewrite information holding circuit 154. The identification information of the second source line (SL1) is included in a rewrite voltage application start / stop signal S6 and is input from the rewrite interruption / recovery control circuit 153 to the rewrite sequencer 151. The rewrite sequencer 151 selects the second source line (SL1) and applies a rewrite voltage to the second source line (SL1). If the rewrite interruption request signal S3 is not input to the rewrite interruption / recovery control circuit 153 before the last source line (SLk (k is an integer equal to or greater than 4) is applied, the rewrite sequencer 151 terminates the application of the rewrite voltage up to the last source line (SLk). Time t12 indicates the time from the start of application of the rewrite voltage to the selected second source line (SL1) to the end of application of the rewrite voltage to the last source line (SLk).

[0041] 5 shows the operation mode of the semiconductor device 100 when the semiconductor device 100 is in the rewrite mode M13 and a rewrite interrupt request signal S3 is input to the rewrite interrupt / restore control circuit 153 at timing I3 while a rewrite voltage is being applied to the selected source line SL2. The selected source line is not limited to the source line SL2. This embodiment can be applied when any one of source lines SL0 to SLk-1 is selected. The rewrite voltage is applied for a predetermined rewrite period (t14). That is, even if the rewrite interrupt request signal S3 is input when any one of source lines SL0 to SLk-1 is selected, the rewrite interrupt / restore control circuit 153 continues to apply the rewrite voltage to the rewrite sequencer 151 until the rewrite period of the selected source line ends. After applying the rewrite voltage for the rewrite period, the semiconductor device 100 causes the rewrite interruption / recovery control circuit 153 to stop applying the rewrite voltage, activate the rewrite voltage application stop flag S5, and output the rewrite voltage application stop flag S5 to the control unit 140. The rewrite interruption / recovery control circuit 153 receives, from the rewrite sequencer 151, identification information for the fourth source line (SL3) to which the rewrite voltage should be applied next after the third source line (SL2), and outputs the identification information to the rewrite information retention circuit 154. The rewrite information retention circuit 154 stores the identification information for the fourth source line (SL3). That is, the rewrite information retention circuit 154 stores the identification information for one of the source lines SL1 to SLk as the source line to which the rewrite voltage should be applied next.

[0042] 5, when a rewrite recovery request signal S4 is input from the control unit 140 to the rewrite interruption / recovery control circuit 153 at timing R3, the semiconductor device 100 transitions to the rewrite mode M14. Then, the rewrite interruption / recovery control circuit 153 reads out the identification information of the fourth source line (SL3) from the rewrite information holding circuit 154. The identification information of the fourth source line (SL3) is included in a rewrite voltage application start / stop signal S6 and is input from the rewrite interruption / recovery control circuit 153 to the rewrite sequencer 151. The rewrite sequencer 151 selects the fourth source line (SL3) and applies a rewrite voltage to the fourth source line (SL4). If the rewrite interruption request signal S3 is not input to the rewrite interruption / recovery control circuit 153 before the last source line (SLk (k is an integer equal to or greater than 4) is reached, the rewrite sequencer 151 terminates the application of the rewrite voltage up to the last source line (SLk). Time t15 indicates the time from the start of application of the rewrite voltage to the source line to be selected next to the source line to which the rewrite interruption request signal S3 was input during the rewrite operation to the end of application of the rewrite voltage to the last source line (SLk).

[0043] 6 shows the operation mode of the semiconductor device 100 when the semiconductor device 100 is in the rewrite mode M15 and a rewrite interrupt request signal S3 is input to the rewrite interrupt / restore control circuit 153 at timing I4 while a rewrite voltage is being applied to the last selected source line SLk. Even if the rewrite interrupt request signal S3 is input when the last source line SLk is selected, the rewrite interrupt / restore control circuit 153 continues to apply the rewrite voltage to the rewrite sequencer 151 until the rewrite period of the last selected source line ends. After applying the rewrite voltage for the rewrite period, the semiconductor device 100 causes the rewrite interrupt / restore control circuit 153 to stop applying the rewrite voltage, deactivate the rewrite voltage application stop flag S5, and output an inactive rewrite voltage application stop flag S5 to the control unit 140. In this case, the rewrite interrupt / restore control circuit 153 does not output the source line identification information S9 to the rewrite information hold circuit 154, so the rewrite information hold circuit 154 does not store any new information. In addition, the control unit 140, which has received an inactive rewrite voltage application stop flag S5, starts the rewrite mode M16 after completing the writing of the new information that generated the rewrite interruption request signal, and completes the information verification operation that was interrupted by the rewrite interruption request signal during the rewrite mode M16.

[0044] 7 shows the operation mode of the semiconductor device 100 when the semiconductor device 100 is in the rewrite mode M17 and the rewrite interrupt request signal S3 is input to the rewrite interrupt / restore control circuit 153 at timing I5 after the application of the rewrite voltage to the last selected source line SLk is completed. The semiconductor device 100 deactivates the rewrite voltage application stop flag S5 and outputs an inactive rewrite voltage application stop flag S5 to the control unit 140. In this case, the rewrite interrupt / restore control circuit 153 does not output the source line identification information S9 to the rewrite information hold circuit 154, so the rewrite information hold circuit 154 does not store new information. Upon receiving the inactive rewrite voltage application stop flag S5, the control unit 140 starts the rewrite mode M18 after the writing of the new information that generated the rewrite interrupt request signal is completed, and completes the verify operation of the information that was suspended by the rewrite interrupt request signal during the rewrite mode M18.

[0045] (Experimental example) FIG. 8 shows the results of measuring the required time for the code flash area (No. 1) and the data flash area (No. 2) of the semiconductor device 100 capable of executing the above-described operations. The required time is shown in two types of time. The first of the two types of time is the suspension response time. The suspension response time indicates the time from when the rewrite interrupt request signal S3 is output for information in the rewrite mode until the application of the rewrite voltage to the selected source line is completed and the interrupt process is completed. Therefore, the suspend response time is also the rewrite inhibit period (interrupt process time) during which rewriting of the code flash area or the data flash area by other information is inhibited.

[0046] The suspend response time in the code flash area (No. 1) in the upper row of FIG. 8 was approximately 1700 μs in a semiconductor device (prior arts) of the prior art, but was approximately 120 μs or less in working examples of the semiconductor device 100 of this embodiment. Furthermore, the suspend response time in the data flash area (No. 2) in the lower row of FIG. 8 was approximately 300 μs in a semiconductor device (prior arts) of the prior art, but was approximately 120 μs or less in working examples of the semiconductor device 100 of this embodiment. Therefore, the semiconductor device 100 of this embodiment can significantly reduce the suspend response time in nonvolatile memory.

[0047] The second of the two types of time is the increasing time for write / erase, which is the time from the completion of application of the rewrite voltage to the selected source line until the completion of the interruption process, the generation of the rewrite recovery request signal S4, and the completion of the rewrite recovery process.

[0048] The increase in time for a write operation / erase operation in the code flash area (No. 1) in the upper row of FIG. 8 was approximately 1700 μs in a semiconductor device (prior art) of the prior art, but was approximately 80 μs or less in working examples (working examples) of the semiconductor device 100 of this embodiment. The increase in time for a write operation / erase operation in the data flash area (No. 2) in the lower row of FIG. 8 was approximately 300 μs in a semiconductor device (prior art) of the prior art, but was approximately 70 μs or less in working examples (working examples) of the semiconductor device 100 of this embodiment. Therefore, the semiconductor device 100 of this embodiment can significantly reduce the increase in time for a write operation / erase operation in a nonvolatile memory.

[0049] According to the semiconductor device 100 of this embodiment, even if a conflict occurs between a write operation and / or an erase operation in the nonvolatile memory cell array 152 region such as a flash memory, the write inhibit period can be significantly shortened. That is, the suspend processing time (suspend response time) of the write operation and / or the erase operation can be significantly shortened. Furthermore, the increase in the time of the write operation and / or the erase operation caused by the suspend processing of the write operation and / or the erase operation can be significantly suppressed.

[0050] Furthermore, according to the semiconductor device 100 of the present embodiment, once a source line is selected, an erase voltage or a write voltage is continuously applied for a predetermined period of time regardless of whether a rewrite interrupt request signal is generated. Therefore, the nonvolatile memory cell array 152 region is not subjected to unnecessary stress, and the number of times the erase voltage or the write voltage is applied, which is guaranteed for the nonvolatile memory cell array 152 region, is not wasted.

[0051] Furthermore, according to the semiconductor device 100 of this embodiment described above, it is possible to eliminate the limitation imposed by the prior art on the number of times high-speed interrupt processing operations can be used.

[0052] Furthermore, according to the semiconductor device 100 of this embodiment, even if the rewrite interrupt request signal is generated repeatedly in a short period of time, the semiconductor device 100 of this embodiment receives the next rewrite interrupt request signal after completing the erase operation or write operation of the selected source line. Therefore, the semiconductor device 100 of this embodiment is configured to be able to continue the rewrite operation of the information to be rewritten even if the interrupt process is repeated.

[0053] Furthermore, according to the semiconductor device 100 of this embodiment described above, there is no need to install multiple control units 140 to respond to a rewrite interruption request, which makes it possible to suppress an increase in the area and cost of the semiconductor device 100.

[0054] (Modification of the first embodiment) In the above-described embodiment, the operation of the semiconductor device 100 according to this embodiment has been described mainly in the case where a rewrite operation to the data flash area occurs during a rewrite operation to the code flash area. However, the interrupt processing operation of the semiconductor device 100 according to this embodiment does not depend on the area of ​​the non-volatile memory cell array 152.

[0055] FIG. 9 is a diagram showing that the interrupt processing operation of the semiconductor device 100 according to this embodiment does not depend on the area of ​​the nonvolatile memory cell array 152. As described above, the "separate flash area" in FIG. 9 indicates whether or not interruption of write and erase operations is possible between the code flash area and the data flash area. FIG. 9 shows that write and erase operations are possible in the separate flash area in the write-suspend state. Furthermore, FIG. 9 shows that write and erase operations are possible in the separate flash area in the erase-suspend state.

[0056] The same flash area in Figure 9 indicates whether or not interrupts for write and erase operations are possible in the code flash area or the data flash area. Figure 9 shows that write and erase operations are possible in the same flash area in a write-suspended state. Furthermore, Figure 9 shows that write and erase operations are possible in the same flash area in an erase-suspended state.

[0057] FIG. 10 is a diagram showing the usage and retention status of valid data (identification information of the source line to be selected next) when an interrupt occurs in a rewrite (write / erase) operation of information B, which has a higher priority than information A, during a rewrite (write / erase) operation of information A in the same flash area.

[0058] Starting from the top of FIG. 10, the semiconductor device 100 is initially in a read mode. Next, when an interrupt for writing and / or erasing information A occurs, the semiconductor device 100 transitions to a write / erase mode for information A. After that, when a write / erase voltage is applied to the semiconductor device 100, valid data (A) is generated as identification information for the source line to be selected next to the source line to which the write / erase voltage is applied. Here, when an interrupt for writing and / or erasing information A occurs, the semiconductor device 100 suspends the writing / erasing of information A. Furthermore, when suspending the writing / erasing of information A, the valid data (A) is saved in the rewrite information holding circuit 154 to prepare for a restoration operation for writing / erasing information A.

[0059] 10, when the valid data (A) is saved in the rewrite information holding circuit 154, the semiconductor device 100 shifts to a read mode once, and then shifts to a write / erase mode for information B. Then, in accordance with the valid data (B) related to the source line to which the write / erase voltage for information B is applied, the semiconductor device 100 applies the write / erase voltage for information B up to the last source line, thereby completing the write / erase operation. No valid data (B) remains in the rewrite sequencer 151, and the valid data (A) has been saved in the rewrite information holding circuit 154.

[0060] 10, when the write / erase operation of information B is completed, the semiconductor device 100 transitions to a read mode and then returns to a write / erase mode of information A. When the semiconductor device 100 returns to the write / erase mode of information A, the semiconductor device 100 reads the valid data (A) saved in the rewrite information retention circuit 154 and resumes the write / erase mode of information A. When the semiconductor device 100 resumes applying the write / erase voltage using the valid data (A), the semiconductor device 100 applies the write / erase voltage of information A up to the last source line and terminates the write / erase operation. Furthermore, when the valid data (A) saved in the rewrite information retention circuit 154 is read, the valid data saved in the rewrite information retention circuit 154 is erased. When the semiconductor device 100 completes the write / erase operation, it transitions to a read mode and starts or continues a control operation in accordance with firmware stored in the nonvolatile memory.

[0061] As described above, the valid data (B) can indicate a source line other than the area where the information A is to be rewritten. Therefore, the valid data (A) and the valid data (B) can be used as identification information for indicating source lines of different areas of the same flash memory. That is, by arranging the rewrite information holding circuit 154 in the nonvolatile memory 150, it becomes possible to execute a write operation / erase operation on an area other than the area where the write operation / erase operation is suspended. Here, the area and the other area refer to any area in the nonvolatile memory cell array 152.

[0062] (Embodiment 2) 11 is a block diagram showing an example of the configuration of a semiconductor device 200 according to embodiment 2. The semiconductor device 200 differs from the semiconductor device 100 according to embodiment 1 in that a rewrite control circuit 155 and an OR circuit 156 are added to a nonvolatile memory 150′ instead of the rewrite information holding circuit 154. Furthermore, a rewrite interruption / recovery control circuit 153′ has the function of outputting a rewrite stop flag S10 to the rewrite control circuit 155 in addition to the function of the rewrite interruption / recovery control circuit 153.

[0063] Similar to the rewrite interruption / restore control circuit 153 according to the first embodiment, the rewrite interruption / restore control circuit 153′ receives a rewrite interruption request signal S3 from the control unit 140 and executes a rewrite interruption process. Furthermore, when the rewrite interruption / restore control circuit 153′ stops the application of the rewrite voltage, it outputs a rewrite voltage application stop flag S5 to the control unit 140. After temporarily suspending the rewrite operation, the rewrite interruption / restore control circuit 153′ outputs a rewrite voltage application start / stop signal S6a, in which information indicating the rewrite voltage application stop has been activated, as the rewrite voltage application start / stop signal S6 to the rewrite sequencer 151 via the OR circuit 156. Furthermore, after temporarily suspending the rewrite operation, the rewrite interruption / restore control circuit 153′ outputs a rewrite stop flag S10 to the rewrite control circuit 155. Furthermore, when the rewrite restore request signal S4 is received from the control unit 140, the rewrite interruption / restore control circuit 153′ executes a rewrite interruption restoration process.

[0064] When the rewrite stop flag S10 is input from the rewrite interruption / recovery control circuit 153′, the rewrite control circuit 155 executes a write / erase operation to write information related to a new interrupt to the nonvolatile memory cell array 152. The application and stop of the write voltage are executed by outputting a rewrite voltage application start / stop signal S6b to the rewrite sequencer 151 as a rewrite voltage application start / stop signal S6 via the OR circuit 156. In addition, source line identification information is input from the rewrite sequencer 151 to the rewrite control circuit 155 and the rewrite interruption / recovery control circuit 153′.

[0065] According to the configuration of the semiconductor device 200 according to the second embodiment described above, it is possible to provide two sets of control circuits capable of applying a rewrite voltage, instead of the rewrite information holding circuit 154. Therefore, when a suspend request occurs, it is possible to temporarily suspend the control circuit that is applying the rewrite voltage, and use another control circuit for the write operation / erase operation to another area of ​​the nonvolatile memory cell array 152 for which the suspend request occurred.

[0066] (Embodiment 3) When a rewrite interrupt request signal S3 is input while a rewrite voltage is being applied to a selected source line, the semiconductor device according to the third embodiment stops applying the rewrite voltage to the selected source line and stores remaining time information for the rewrite voltage to be applied to the selected source line in the rewrite information hold circuit 154. The rewrite information hold circuit 154 also stores identification information for the selected source line in association with the remaining time information for the rewrite voltage. For example, the remaining time for the rewrite voltage can be determined by subtracting the time until the application of the rewrite voltage is interrupted by input of the rewrite interrupt request signal S3 from the predetermined time for which the rewrite voltage should be applied to the selected source line. Therefore, when a rewrite interrupt request signal S3 is input while a rewrite voltage is being applied to the selected source line, the semiconductor device according to the third embodiment stops the rewrite operation midway without completing the application of the rewrite voltage to the selected source line. Then, when the rewrite recovery request signal S4 is input, the semiconductor device according to the third embodiment selects the source line for which the rewrite voltage has been stopped, applies the rewrite voltage for the remaining time of the rewrite voltage, and completes the rewrite operation for the source line. The remaining time of the rewrite voltage can also be configured to be counted in units of clocks at which the semiconductor device is operating.

[0067] According to the semiconductor device of the third embodiment described above, even if a conflict occurs between a write operation and / or an erase operation in the nonvolatile memory cell array 152 region such as a flash memory, it is possible to significantly shorten the write inhibition period. That is, it is possible to significantly shorten the suspend processing time (suspend response time) of the write operation and / or the erase operation. Furthermore, it is possible to significantly suppress the increase in the time of the write operation and / or the erase operation caused by the suspend processing of the write operation and / or the erase operation.

[0068] Furthermore, according to the semiconductor device of the third embodiment, it is possible to divide the erase voltage or write voltage for a selected source line and apply it for a predetermined period of time. Therefore, the nonvolatile memory cell array 152 region is not subjected to unnecessary stress, and the number of times the erase voltage or write voltage is applied, which is guaranteed for the nonvolatile memory cell array 152 region, is not wasted.

[0069] Furthermore, according to the semiconductor device 100 of the third embodiment described above, it is possible to eliminate the limitation imposed by the prior art on the number of times high-speed interrupt processing operations can be used.

[0070] Furthermore, according to the semiconductor device 100 of the third embodiment, even if the rewrite interrupt request signal is generated repeatedly in a short period of time, the erase operation or write operation of the selected source line is interrupted midway, the next rewrite interrupt request signal is received, and the erase operation or write operation is completed continuing from the interrupted operation. Therefore, the semiconductor device 100 of this embodiment is configured to be able to proceed with the rewrite operation of the information to be rewritten without turning back even if the interruption process is repeated.

[0071] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit of the invention. Furthermore, for example, the above embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those having all of the described configurations. Furthermore, it is possible to add, delete, or replace part of the configuration of the above embodiments with other configurations. [Explanation of symbols]

[0072] 100, 200 Semiconductor device 140 Control Unit 150, 150' Non-volatile memory 151 Rewrite Sequencer 152 Non-volatile memory cell array 153, 153' Rewrite interruption / recovery control circuit 154 Rewrite information retention circuit 155 Rewrite control circuit 156 OR Circuit

Claims

1. A semiconductor device having an electrically writable or erasable nonvolatile memory and a control circuit that executes mode control of a write operation and an erase operation of the nonvolatile memory, The nonvolatile memory includes: a rewrite interruption / recovery control circuit that controls an operation of interrupting application of a write voltage or an erase voltage in response to an interruption request signal from the control circuit requesting interruption of a rewrite operation including at least one of a write operation and an erase operation, and that controls an operation of recovering from the interruption of application of a write voltage or an erase voltage in response to a recovery request signal from the control circuit requesting recovery from the interruption of the rewrite operation, and that outputs a voltage application stop flag to the control circuit when application of the write voltage or the erase voltage is stopped; a rewrite information holding circuit for holding source line identification information for identifying a selected line to which a write voltage is applied when responding to an interrupt request signal, or source line identification information for identifying a selected line to which an erase voltage is applied when responding to an interrupt request signal, The control circuit responds to an interrupt request signal when the nonvolatile memory is in a write mode or an erase mode, and transmits a rewrite interrupt request signal to the rewrite interrupt / restore control circuit, and responds to a resumption request signal for the write mode or erase mode of the nonvolatile memory that has been interrupted by the interrupt request signal, and outputs a rewrite resume request signal to the rewrite interrupt / restore control circuit when the voltage application stop flag output from the rewrite interrupt / restore control circuit is active.

2. The rewrite interruption / restart control circuit includes: In a write mode or an erase mode, if the interrupt request signal is received before a write voltage or an erase voltage is applied to the first select line to be selected, selecting the first selection line, suspending the write mode or the erase mode after completing application of the write voltage or the erase voltage to the first selection line, and activating a voltage application stop flag to output it to the control circuit; In the write mode or the erase mode, when the interrupt request signal is received while the write voltage or the erase voltage is being applied to a select line other than the last select line to be selected, After the application of the write voltage or erase voltage to the selection line is completed, the write mode or erase mode is interrupted, and the voltage application stop flag is made active and output to the control circuit; In the write mode or the erase mode, when the interrupt request signal is received while the write voltage or the erase voltage is being applied to the last select line to be selected, After the application of the write voltage or erase voltage to the last selected line is completed, the write mode or erase mode is interrupted, and the voltage application stop flag is made inactive and output to the control circuit; In the write mode or the erase mode, when the interrupt request signal is received after the write voltage or the erase voltage is applied to the last selection line to be selected, The semiconductor device according to claim 1 , wherein the voltage application stop flag is set to an inactive state and output to the control circuit.

3. In the write mode or the erase mode, when the rewrite interrupt / recovery control circuit receives the interrupt request signal before applying the write voltage or the erase voltage to the first selection line to be selected, the rewrite interruption / recovery control circuit selects the first selection line, and after completing application of a write voltage or an erase voltage to the first selection line, the rewrite information holding circuit receives and stores identification information of a selection line to be selected next to the first selection line from the rewrite interruption / recovery control circuit; In a write mode or an erase mode, when the write interrupt / recovery control circuit receives the interrupt request signal while a write voltage or an erase voltage is being applied to a selection line other than the last selection line to be selected, After the rewrite interruption / recovery control circuit has completed application of the write voltage or erase voltage to the selection line, the rewrite information holding circuit receives and stores identification information of a selection line to be selected next to the selection line from the rewrite interruption / recovery control circuit; When the rewrite interruption / recovery control circuit receives the rewrite recovery request signal from the control circuit, the rewrite interruption / recovery control circuit: reading out the identification information of the selection line to be selected next from the rewrite information holding circuit; Selecting the next selection line indicated by the identification information; 2. The semiconductor device according to claim 1, wherein a write voltage or an erase voltage is applied to the select line.

4. The rewrite information holding circuit stores, in addition to identification information of a source line to which the write voltage is applied, remaining time information of a write voltage that should have been applied to the source line, or the rewrite information holding circuit stores, in addition to identification information of the source line to which the erase voltage is applied, remaining time information of the erase voltage that should have been applied to the source line; 2. The semiconductor device according to claim 1, wherein when the rewrite interruption / return control circuit receives the return request signal, it selects a selected line indicated by the identification information of the source line to which the write voltage is applied or the identification information of the source line to which the erase voltage is applied, and applies the write voltage or erase voltage to the selected line for the remaining time to be applied to the selected line based on the remaining time information of the write voltage that should have been applied or the remaining time information of the erase voltage that should have been applied.

5. 5. The semiconductor device according to claim 1, wherein the selection line is a source line of the nonvolatile memory, and there are a plurality of the source lines, each of the plurality of source lines corresponding to a different storage area.

6. 6. The semiconductor device according to claim 5, wherein the selection lines further include bit lines of the nonvolatile memory.

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