Semiconductor structure with sharp angles and method of manufacturing same - Patents.com

Abstract

To provide a semiconductor structure having an acute angle.SOLUTION: A semiconductor structure having an acute angle includes a semiconductor substrate. The first isolation layer covers and contacts the semiconductor substrate. The first conductive element is disposed on the first isolation layer. The first conductive element includes a bottom surface and a sidewall. The bottom surface contacts the first isolation layer. An acute angle is formed between the bottom surface and the sidewall, and the acute angle has a tip. The second conductive element is disposed on one side of the first conductive element, and the tip points to the second conductive element. The extension plane extends from the bottom surface of the first conductive element, and the extension plane intersects the second conductive element. The second isolation layer is sandwiched between the first conductive element and the second conductive element.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to semiconductor structures having sharp angles, and more particularly to flashes having sharp angles and methods for fabricating the same. [Background technology]

[0002] Semiconductor memory devices are broadly classified into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. Volatile semiconductor memory devices have the advantage of fast read / write speeds, but the disadvantage of losing stored data when the external power supply is interrupted. On the other hand, nonvolatile semiconductor memory devices retain their data even when the external power supply is interrupted. For this reason, nonvolatile semiconductor memory devices are used to store data that needs to be saved regardless of whether or not power is supplied.

[0003] Market demands have driven continuous development towards smaller memory units and increased memory capacity. Furthermore, flash memory must be improved and enhanced in performance without increasing additional process costs. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 10,600,797 [Patent Document 2] U.S. Patent No. 10,756,100 [Patent Document 3] US Patent Application Publication No. 2004 / 0183121 [Patent Document 4] U.S. Patent Application Publication No. 2021 / 0358932 [Patent Document 5] U.S. Patent No. 7,560,765 [Patent Document 6] U.S. Patent No. 7,315,057 [Patent Document 7] Chinese Patent No. 102117814 [Patent Document 8] U.S. Patent No. 10,224,278 Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, the present invention provides a flash with a sharp angle, in this way a higher electric field is formed in the flash at the tip of the sharp angle, and the operating speed of the flash can be accelerated. [Means for solving the problem]

[0006] According to a preferred embodiment of the present invention, a semiconductor structure having an acute angle includes a semiconductor substrate. A first isolation layer covers and contacts the semiconductor substrate. A first conductive element is disposed on the first isolation layer, the first conductive element having a bottom surface and a sidewall, the bottom surface contacting the first isolation layer, an acute angle formed between the bottom surface and the sidewall, the acute angle having a tip. A second conductive element is disposed on one side of the first conductive element, the tip facing toward the second conductive element, and an extended surface extending from the bottom surface of the first conductive element and intersecting with the second conductive element. The second isolation layer is sandwiched between the first conductive element and the second conductive element.

[0007] According to another preferred embodiment of the present invention, a method for manufacturing a semiconductor structure having an acute angle includes providing a semiconductor substrate. Next, a first isolation layer and a first conductive element are sequentially formed on the semiconductor substrate, the first isolation layer covering the semiconductor substrate and contacting the semiconductor substrate, the first conductive element including a bottom surface and a sidewall, the bottom surface contacting the first isolation layer, an acute angle formed between the bottom surface and the sidewall, and the acute angle having a tip. Next, a second conductive element is formed on one side of the first conductive element, the tip facing toward the second conductive element, and an extended surface extending from the bottom surface of the first conductive element and intersecting the second conductive element. Finally, a second isolation layer is formed between the first conductive element and the second conductive element. [Brief explanation of the drawings]

[0008] These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

[0009] [Figure 1] 1A-1D illustrate a method for manufacturing a semiconductor structure having an acute angle according to a first preferred embodiment of the present invention. [Figure 2] 1A-1C illustrate a method for manufacturing a semiconductor structure having an acute angle according to a first preferred embodiment of the present invention; [Figure 3] 2A and 2B illustrate a method for manufacturing a semiconductor structure having an acute angle according to a first preferred embodiment of the present invention. [Figure 4] 3A and 3B illustrate a method for manufacturing a semiconductor structure having an acute angle according to a first preferred embodiment of the present invention. [Figure 5] 4A and 4B illustrate a method for manufacturing a semiconductor structure having an acute angle according to a first preferred embodiment of the present invention. [Figure 6] 5A-5D illustrate a method for manufacturing a semiconductor structure having an acute angle according to a second preferred embodiment of the present invention. [Figure 7] 10A-10D illustrate a method for manufacturing a semiconductor structure having an acute angle according to a third preferred embodiment of the present invention. [Figure 8] 7A and 7B illustrate a method for manufacturing a semiconductor structure having an acute angle according to a third preferred embodiment of the present invention. [Figure 9] 8A and 8B illustrate a method for manufacturing a semiconductor structure having an acute angle according to a third preferred embodiment of the present invention. [Figure 10] 10A-10D illustrate a method for manufacturing a semiconductor structure having an acute angle according to a fourth preferred embodiment of the present invention. [Figure 11] 10A-10D illustrate a method for manufacturing a semiconductor structure having an acute angle according to a fifth preferred embodiment of the present invention. [Figure 12] FIG. 10 illustrates an antifuse according to a sixth preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] 1 to 5 illustrate a method for manufacturing a semiconductor structure having an acute angle according to a first preferred embodiment of the present invention.

[0011] As shown in FIG. 1, a semiconductor substrate 1 is provided. The semiconductor substrate 1 may include a silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate, a silicon carbide substrate, or a silicon-on-insulator substrate. Next, an isolation layer 10a, a conductive material layer 12a, an isolation layer 10b, a conductive material layer 12c, an isolation layer 10c, a silicon nitride mask layer 14, and a silicon oxide mask layer 16 are sequentially formed to cover the semiconductor substrate 1. Then, the silicon oxide mask layer 16 and the silicon nitride mask layer 14 are patterned to form an opening 18a.

[0012] As shown in FIG. 2, an isolation layer 10d is formed to conformally cover the silicon oxide mask layer 16 and the opening 18a. At this time, the isolation layer 10d defines an opening 18b. As shown in FIG. 3, the isolation layer 10d is used as a mask to etch the isolation layer 10c, the conductive material layer 12c, the isolation layer 10b, and the conductive material layer 12a to form a trench 18c in the isolation layer 10c, the conductive material layer 12c, the isolation layer 10b, and the conductive material layer 12a. The bottom of the trench 18c is the isolation layer 10a. Here, the isolation layer 10c, the conductive material layer 12c, the isolation layer 10b, and the conductive material layer 12a are all segmented. The conductive material layer 12a is divided into two first conductive elements 112a. The conductive material layer 12c is divided into two third conductive elements 112c. The structures of the two first conductive elements 112a are mirror-symmetric. Taking the left first conductive element 112a as an example, as shown in the enlarged view 20a, the first conductive element 112a has a sidewall 22. The sidewall 22 is V-shaped, with a tip 22a of the V-shaped surface pointing inward toward the first conductive element 112a. The angle of the tip 22a is preferably between 135 and 165 degrees. The first conductive element 112a also has a bottom surface 24. The bottom surface 24 is in contact with the isolation layer 10a. An acute angle A is formed between the bottom surface 24 and the sidewall 22, and the acute angle A has a tip P. According to another preferred embodiment of the present invention, the sidewall 22 may be flat, as shown in the enlarged view 20b. Furthermore, see FIGS. 2 and 3. The trench 18c may be formed using two types of etching gases. During the etching process, one of the etching gases is used to etch the isolation layer 10c, the conductive material layer 12c, the isolation layer 10b, and the conductive material layer 12a, and the other of the etching gases is used to form a protective layer (not shown) during etching. The protective layer covers the isolation layer 10c, the conductive material layer 12c, the isolation layer 10b, and the conductive material layer 12a. In this way, the trench 18c can be formed.

[0013] As shown in FIG. 4, an isolation layer 10e is formed conformally covering trenches 18b and 18c. A trench 18d is then defined in isolation layer 10e. As shown in FIG. 5, isolation layer 10e and isolation layer 10a around tip P are etched to thin a portion of isolation layer 10e and extend trench 18d into isolation layer 10a. A second conductive element 112b is then formed in trench 18d. As shown in enlarged view 20c, the thinning of isolation layer 10e around tip P allows second conductive element 112b to approach tip P. In this way, when the semiconductor structure with an acute angle is turned on, the electric field around tip P is concentrated, and therefore, signals between first conductive element 112a and second conductive element 112b can be transmitted more quickly. This completes the flash E1 with an acute angle of the present invention.

[0014] FIG. 6 illustrates a method for fabricating a semiconductor structure with an acute angle according to a second preferred embodiment of the present invention.

[0015] According to a second preferred embodiment of the present invention, the end of the second conductive element 112b can be embedded in the semiconductor substrate 1. FIG. 6 shows a manufacturing step subsequent to FIG. 4. As shown in FIG. 6, after forming the isolation layer 10e, the isolation layer 10e at the bottom of the trench 18d is etched, and then the isolation layer 10a and the semiconductor substrate 1 are etched to extend the trench 18d into the semiconductor substrate 1. Then, an isolation layer 10f is formed on the sidewall of the trench 18d in the semiconductor substrate 1 using a thermal oxidation process. Then, the second conductive element 112b is formed in the trench 18d. This completes the flash E2 having an acute angle according to the present invention. According to another preferred embodiment of the present invention, the isolation layer 10f can also be formed using a chemical vapor deposition process. Therefore, the isolation layer 10f not only covers the trench 18d in the semiconductor substrate 1 but also covers the isolation layer 10e. In this manner, isolation layer 10e and isolation layer 10f are disposed between second conductive element 112b and third conductive element 112c, and isolation layer 10e and isolation layer 10f are also disposed between second conductive element 112b and first conductive element 112a.

[0016] 7 to 9 are diagrams showing a method for manufacturing an acute-angle semiconductor structure according to a third embodiment of the present invention, in which components that are substantially the same as those in the first embodiment are given the same reference numerals and descriptions thereof will be omitted.

[0017] The third embodiment differs from the first embodiment in that the conductive material layer 12c and the isolation layer 10c are not present in the third embodiment. The remaining configuration and manufacturing method are the same as those of the first embodiment. As shown in FIG. 7, a semiconductor substrate 1 is prepared. Next, an isolation layer 10a, a conductive material layer 12a, an isolation layer 10b, a silicon nitride mask layer 14, and a silicon oxide mask layer 16 are sequentially formed to cover the semiconductor substrate 1. The silicon oxide mask layer 16 and the silicon nitride mask layer 14 are then patterned to form an opening 18a. Next, an isolation layer 10d is formed to conformally cover the silicon oxide mask layer 16 and the opening 18a. At this time, the isolation layer 10d forms an opening 18b. As shown in FIG. 8, the isolation layer 10d is used as a mask to etch the isolation layer 10b and the conductive material layer 12a, thereby forming a trench 18e in the isolation layer 10b and the conductive material layer 12a. Here, the acute angle A of the first conductive element 112a also has a tip P. As shown in FIG. 9, an isolation layer 10e is formed to conformally cover trenches 18b and 18e, thereby defining trench 18d within isolation layer 10e. Next, the isolation layer 10e around tip P is etched. That is, the isolation layer 10e that forms the bottom of trench 18d is etched. Thereafter, second conductive element 112b is formed within trench 18d. This completes the flash E3 having an acute angle according to the present invention.

[0018] FIG. 10 illustrates a method for fabricating an acute-angled semiconductor structure according to a fourth embodiment of the present invention. Components substantially identical to those in the second embodiment are designated by the same reference numerals, and their description will be omitted. FIG. 10 illustrates a manufacturing step subsequent to that of FIG. 8. As shown in FIG. 10, an isolation layer 10e is formed conformally covering trenches 18b and 18e. Trench 18d is defined within isolation layer 10e. The isolation layer 10e at the bottom of trench 18d is then etched. Next, isolation layer 10a and semiconductor substrate 1 are etched to extend trench 18d into semiconductor substrate 1. An isolation layer 10f is then formed within trench 18d embedded in semiconductor substrate 1 using a thermal oxidation process. Finally, a second conductive element 112b is formed within trench 18d. This completes the flash E4 having an acute angle according to the present invention.

[0019] FIG. 11 illustrates a method for fabricating a semiconductor structure having an acute angle according to a fifth preferred embodiment of the present invention. The fifth embodiment is a modification of the fourth embodiment. In the fourth embodiment, the isolation layer 10f is formed by thermal oxidation. In the fifth embodiment, the isolation layer 10f is formed by chemical vapor deposition. Therefore, in the fifth embodiment, the isolation layer 10f not only covers the trench 18d in the semiconductor substrate 1 but also covers the isolation layer 10e. Except for the method for fabricating the isolation layer 10f, the other fabrication steps of the fifth embodiment are the same as those of the fourth embodiment. In detail, FIG. 11 illustrates the successive fabrication steps of FIG. 8. As shown in FIG. 11, the isolation layer 10e is formed to conformally cover the trench 18b and the trench 18e, thereby defining the trench 18d in the isolation layer 10e. Then, the isolation layer 10e at the bottom of the trench 18d is etched. Next, the isolation layer 10a and the semiconductor substrate 1 are etched to extend the trench 18d into the semiconductor substrate 1. Next, a chemical vapor deposition process is used to conformally form an isolation layer 10f over trench 18d. Finally, a second conductive element 112b is formed in trench 18d. This completes the semiconductor structure E5 with an acute angle of the present invention.

[0020] As shown in FIG. 5, the flash E1 having an acute angle includes a semiconductor substrate 1. An isolation layer 10a covers and contacts the semiconductor substrate 1. A first conductive element 112a is disposed on the isolation layer 10a. A third conductive element 112c is disposed on the first conductive element 112a. A second conductive element 112b is disposed on one side of the first conductive element 112a. An isolation layer 10e is sandwiched between the first conductive element 112a and the second conductive element 112b, and between the third conductive element 112c and the second conductive element 112b. An isolation layer 10b is sandwiched between the first conductive element 112a and the third conductive element 112c. See also the enlarged view 20c of FIG. 5. The first conductive element 112a has a bottom surface 24. The bottom surface 24 contacts the isolation layer 10a. An acute angle A is formed between the bottom surface 24 and the sidewall 22, and the acute angle A has a tip P. The tip P points toward the second conductive element 112b, and the acute angle A is preferably 30 to 60 degrees. An extension plane S (indicated by a dotted line) extends from the bottom surface 24 of the first conductive element 112a. The extension plane S is parallel to the upper surface of the semiconductor substrate 1. Furthermore, the extension plane S intersects with the second conductive element 112b. In this embodiment, the second conductive element 112b is located only on the semiconductor substrate 1 and does not contact the semiconductor substrate 1. In this embodiment, the first conductive element 112a is a floating gate, the second conductive element 112b is an erase gate, and the third conductive element 112c is a control gate. The first conductive element 112a includes polysilicon, the second conductive element 112b includes polysilicon or a metal, and the third conductive element 112c includes polysilicon.

[0021] 6, the difference between the flash E1 having an acute angle and the flash E2 having an acute angle is that in the flash E2 having an acute angle, an end of the second conductive element 112b is embedded in the semiconductor substrate 1. In addition, an isolation layer 10f is disposed between the second conductive element 112b and the semiconductor substrate 1. Since the other components are the same as those in the flash E1 having an acute angle, the description of FIG. 5 is referred to and a description thereof will be omitted here.

[0022] As shown in FIG. 10, the flash E4 having an acute angle includes a semiconductor substrate 1. An isolation layer 10a covers and contacts the semiconductor substrate 1. A first conductive element 112a is disposed on the isolation layer 10a. See also the enlarged view 20d of FIG. 10. The first conductive element 112a has a bottom surface 24 and a sidewall 22. The bottom surface 24 is in contact with the isolation layer 10a. An acute angle A is formed between the bottom surface 24 and the sidewall 22, and the acute angle A has a tip P. The acute angle A is preferably 30 to 60 degrees. The second conductive element 112b is disposed on one side of the first conductive element 112a. The tip P faces toward the second conductive element 112b. An extension surface S (shown by a dotted line) extends from the bottom surface 24 of the first conductive element 112a. The extension surface S is parallel to the bottom surface 24. Furthermore, the extension plane S intersects with the second conductive element 112b. The isolation layer 10e is sandwiched between the first conductive element 112a and the second conductive element 112b. The first conductive element 112a includes polysilicon, and the second conductive element 112b includes polysilicon or a metal, with the first conductive element 112a being a floating gate and the second conductive element 112b being a control gate.

[0023] As shown in FIGS. 10 and 11 , the difference between the flash E4 with an acute angle and the flash E5 with an acute angle is that in the flash E5 with an acute angle, the isolation layer 10f not only covers the trench 18d in the semiconductor substrate 1 but also covers the isolation layer 10e, so that the isolation layer 10e and the isolation layer 10f are positioned between the second conductive element 112b and the first conductive element 112a. However, the end of the second conductive element 112b embedded in the substrate 1 only contacts the isolation layer 10f. The isolation layer 10e is not embedded in the substrate 1. In the enlarged view 20e of FIG. 11 , similar to the enlarged view 20d, an acute angle A exists between the bottom surface 24 and the sidewall 22, and the acute angle A has a tip P. The acute angle A is preferably 30 to 60 degrees. Since the other components are the same as those of the flash E4 with an acute angle, please refer to the description of FIG. 10 and will not be described here.

[0024] FIG. 12 shows an antifuse according to a sixth preferred embodiment of the present invention. As shown in FIG. 10, the structure of flash E4 in FIG. 10 can also be used as an antifuse. As shown in FIG. 12, the structure of antifuse E6 is similar to that of flash E4, which has an acute angle, except that one conductive plug 26 is disposed on the first conductive element 112a so as to contact the first conductive element 112a. When a sufficient voltage is applied to the second conductive element 112b and the conductive plug 26, the isolation layer 10e and the isolation layer 10f collapse to form a conductive block 28 between the first conductive element 112a and the second conductive element 112b as a current path. In this way, the antifuse E6 is programmed. The other elements in FIG. 12 are the same as those in FIG. 10, so please refer to the description of FIG. 10 and related descriptions will be omitted here.

[0025] In addition, the material of the separation layers 10a / 10b / 10c / 10d / 10e / 10f in all preferred embodiments of the present invention includes silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, or silicon carbonitride, respectively. The first conductive element 112a, the second conductive element 112b, and the third conductive element 112c each include a conductive material such as polysilicon, copper, tungsten, aluminum, titanium, an alloy, or other conductive materials.

[0026] In the present invention, the corner of the first conductive element is specially etched to have a sharp angle, and the high electric field at the tip of the sharp angle allows the tunneling effect to be quickly formed between the first conductive element and the second conductive element, thereby improving the operating speed of the flash memory.

[0027] Those skilled in the art will readily recognize that numerous modifications and variations of the apparatus and method may be made while retaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. a semiconductor substrate; a first isolation layer covering and contacting the semiconductor substrate; a first conductive element disposed on the first isolation layer, the first conductive element including a bottom surface and a sidewall, the bottom surface contacting the first isolation layer, an acute angle formed between the bottom surface and the sidewall, the acute angle having a tip; a second conductive element disposed on one side of the first conductive element, the tip facing the second conductive element and the extended surface extending from the bottom surface of the first conductive element and intersecting the second conductive element; a second isolation layer sandwiched between the first conductive element and the second conductive element; A semiconductor structure having an acute angle, wherein the sidewalls are planar.

2. 2. The semiconductor structure having an acute angle of claim 1, wherein the first conductive element comprises polysilicon, a conductive plug is disposed on a top surface of the first conductive element, the second conductive element comprises a metal or alloy, and the semiconductor structure having an acute angle is an antifuse.

3. 2. The semiconductor structure having an acute angle of claim 1, wherein the first conductive element comprises polysilicon, the second conductive element comprises polysilicon or a metal, the first conductive element is a floating gate, the second conductive element is a control gate, and the semiconductor structure having an acute angle is flash.

4. a third conductive element disposed on the first conductive element, the second isolation layer being sandwiched between the third conductive element and the second conductive element; and The semiconductor structure having an acute angle of claim 1 , further comprising: a third isolation layer sandwiched between the first conductive element and the third conductive element.

5. 5. The semiconductor structure having an acute angle of claim 4, wherein the first conductive element comprises polysilicon, the second conductive element comprises polysilicon or a metal, the third conductive element comprises polysilicon, the first conductive element is a floating gate, the second conductive element is an erase gate, the third conductive element is a control gate, and the semiconductor structure having an acute angle is flash.

6. The semiconductor structure having an acute angle as recited in claim 1 , wherein the second conductive element is disposed only on the semiconductor substrate.

7. The semiconductor structure having an acute angle as recited in claim 1 , wherein an end of the second conductive element is embedded in the semiconductor substrate.

8. 8. The semiconductor structure having an acute angle of claim 7, further comprising: a fourth isolation layer covering and contacting the second isolation layer, the fourth isolation layer being embedded in the semiconductor substrate and contacting the end of the second conductive element, the fourth isolation layer and the second isolation layer being disposed between the first conductive element and the second conductive element, and the end of the second conductive element not contacting the second isolation layer.

9. providing a semiconductor substrate; sequentially forming a first isolation layer and a first conductive element disposed on the semiconductor substrate, the first isolation layer covering and contacting the semiconductor substrate, the first conductive element including a bottom surface and a sidewall, the bottom surface contacting the first isolation layer, an acute angle formed between the bottom surface and the sidewall, the acute angle having a tip; forming a second conductive element disposed on one side of the first conductive element, the tip facing toward the second conductive element and an extended surface extending from the bottom surface of the first conductive element, the extended surface intersecting the second conductive element; forming a second isolation layer sandwiched between the first conductive element and the second conductive element; A method for manufacturing a semiconductor structure having an acute angle, wherein the sidewalls are planar.

10. 10. The method of claim 9, wherein the first conductive element comprises polysilicon, a conductive plug is disposed on a top surface of the first conductive element, the second conductive element comprises a metal or alloy, and the semiconductor structure with an acute angle is an antifuse.

11. 10. The method of claim 9, wherein the first conductive element comprises polysilicon, the second conductive element comprises polysilicon or a metal, the first conductive element is a floating gate, the second conductive element is a control gate, and the semiconductor structure with an acute angle is flash.

12. forming a third conductive element disposed on the first conductive element, the second isolation layer being sandwiched between the third conductive element and the second conductive element; 10. The method of claim 9, further comprising forming a third isolation layer sandwiched between the first conductive element and the third conductive element.

13. 13. The method for fabricating a semiconductor structure having an acute angle of claim 12, wherein the first conductive element comprises polysilicon, the second conductive element comprises polysilicon or a metal, the third conductive element comprises polysilicon, the first conductive element is a floating gate, the second conductive element is an erase gate, the third conductive element is a control gate, and the semiconductor structure having an acute angle is flash.

14. The method for manufacturing a semiconductor structure having an acute angle of claim 9 , wherein the second conductive element is disposed only on the semiconductor substrate.

15. The method for fabricating a semiconductor structure having an acute angle of claim 9 , wherein an end of the second conductive element is embedded in the semiconductor substrate.

16. 16. The method for fabricating a semiconductor structure having an acute angle of claim 15, further comprising: forming a fourth isolation layer using chemical vapor deposition, wherein the fourth isolation layer covers and contacts the second isolation layer, and the fourth isolation layer is embedded in the semiconductor substrate and contacts the end of the second conductive element.

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