Ceramic substrate, ceramic circuit board, and semiconductor device

Abstract

A ceramic substrate according to one embodiment is characterized in that the ratio A / B of an arc discharge voltage A to a dielectric breakdown voltage B is at least 0.3, in a case where a 50 Hz or 60 Hz alternating-current voltage is applied between the front surface and the rear surface of the ceramic substrate at a voltage rise speed of 200 V / s, and the arc discharge voltage A (kV) obtained by detecting an arc discharge is measured and the dielectric breakdown voltage B (kV) between the front surface and the rear surface is measured in accordance with IEC 672-2. In any cross-section of the ceramic substrate, it is preferable that there be a 90 μｍ × 120 μm region in which the number of first voids having a surface area of less than 1 μm2 is within the range of 30 to 500, and the number of second voids having a surface area of at least 1 μm2 is within the range of 0 to 30.

Description

[Technical Field]

[0001] The embodiments described below generally relate to a ceramic substrate, a ceramic circuit board, and a semiconductor device. [Background technology]

[0002] In recent years, as industrial equipment has become more sophisticated, the power modules installed in them have become increasingly powerful. This has led to an increase in the power output of semiconductor elements. The guaranteed operating temperature for semiconductor elements is 125°C to 150°C, but this may rise to 175°C or higher in the future. Ceramic circuit boards are used as circuit boards on which semiconductor elements are mounted. Examples of ceramic substrates include silicon nitride substrates, aluminum nitride substrates, and aluminum oxide substrates.

[0003] For example, Japanese Patent No. 6293772 (Patent Document 1) discloses a silicon nitride substrate with a thermal conductivity of 50 W / m·K or more and a three-point bending strength of 600 MPa or more. In Patent Document 1, the distribution of grain boundary phases in the thickness direction of the substrate is controlled. In Japanese Patent No. 5928896 (Patent Document 2), the area ratio of voids with a circle-equivalent diameter of 0.5 μm or more is controlled. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6293772 [Patent Document 2] Patent No. 5928896 Summary of the Invention [Problem to be solved by the invention]

[0005] The silicon nitride substrates described in Patent Documents 1 and 2 both have excellent insulating properties. However, there is still room for improvement in terms of long-term reliability. Conventional insulation tests involve measuring dielectric strength, which is a breakdown test. In a dielectric strength test, electrodes are placed on the front and back surfaces of a ceramic substrate, and the voltage at which dielectric breakdown occurs is measured. Despite high dielectric strength, ceramic substrates have sometimes exhibited insufficient long-term reliability. Investigation into the cause of this finding revealed that the conditions used in dielectric strength tests deviate significantly from practical electric fields, and the measured dielectric strength may not be an appropriate indicator of long-term reliability. For example, while the practical voltage of semiconductor devices is approximately 1 kV, a large voltage of approximately 9 kV is applied in a dielectric strength test. The embodiments address these issues and provide a ceramic substrate that can achieve long-term insulating reliability. [Means for solving the problem]

[0006] The ceramic substrate according to the embodiment is characterized in that when an AC voltage of 50 Hz or 60 Hz is applied between the front and back surfaces at a voltage increase rate of 200 V / s, the arc discharge voltage A (kV) when an arc discharge is detected is measured, and the dielectric breakdown voltage B (kV) between the front and back surfaces is measured in accordance with IEC 672-2, the ratio A / B of the arc discharge voltage A to the dielectric breakdown voltage B is 0.3 or more. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic view showing an example of a ceramic substrate according to an embodiment. [Figure 2] FIG. 2 is a schematic diagram showing an example of a cross-sectional structure of a ceramic substrate. [Figure 3] 1 is a schematic view showing an example of a ceramic circuit substrate according to an embodiment; [Figure 4] 1 is a schematic diagram showing an example of a semiconductor device according to an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0008] The ceramic substrate according to the embodiment is characterized in that when an AC voltage of 50 Hz or 60 Hz is applied between the front and back surfaces at a voltage increase rate of 200 V / s, the arc discharge voltage A (kV) when an arc discharge is detected is measured, and the dielectric breakdown voltage B (kV) between the front and back surfaces is measured in accordance with IEC 672-2, the ratio A / B of the arc discharge voltage A to the dielectric breakdown voltage B is 0.3 or more.

[0009] FIG. 1 is a schematic diagram showing an example of a ceramic substrate according to an embodiment. In FIG. 1, reference numeral 1 indicates a ceramic substrate. FIG. 1 shows a rectangular substrate as an example. The ceramic substrate 1 can have various shapes, such as a circle, an ellipse, a triangle, a square, or a pentagon. If necessary, the ceramic substrate 1 may be provided with holes for screwing.

[0010] First, we will explain how to measure the arc discharge voltage. Electrodes are placed on the front and back surfaces of the ceramic substrate 1, and the ceramic substrate 1 is sandwiched between the pair of electrodes. In this state, an AC voltage of 50 Hz or 60 Hz is applied between the electrodes. The voltage increase rate is set to 200 V / s. The voltage when an arc discharge is detected between the electrodes is measured as the arc discharge voltage (kV). Once the arc discharge voltage is measured, the voltage is not increased any further and the application of the voltage is stopped.

[0011] For example, the electrode is a spherical electrode with a tip diameter of 10 mm, as specified in JIS-C-2110-1 (2013). JIS-C-2110-1 corresponds to IEC 60243-1. The measurement environment is controlled at a temperature of 10 to 25°C and a humidity of 30 to 60%, and measurements are performed in the atmosphere. Alternatively, the arc discharge voltage can be measured in an insulating oil, such as silicone oil, that is stable against electric fields.

[0012] The arc discharge voltage is measured at three arbitrary locations on one ceramic substrate, and the average value is recorded as the arc discharge voltage A (kV). The three arbitrary locations are selected so that they do not overlap with each other. The maximum voltage is limited to 20 kV. The ceramic substrate 1 to be measured is placed in a container to prevent the measurement from being affected by air currents. The measurement device used is preferably the AC Withstand Voltage Tester-7473 manufactured by Keisoku Giken Kenkyusho. Alternatively, a device with equivalent or better arc discharge detection capabilities may be used. The unit of arc discharge voltage A may be "kV / mm," which is the voltage divided by the thickness of the ceramic substrate.

[0013] The breakdown voltage is measured in accordance with the dielectric breakdown strength test of JIS-C-2141 (1992). JIS-C-2141 corresponds to IEC672-2. The test is performed using the two-terminal method. Electrodes are placed on the front and back of the ceramic substrate 1, and the ceramic substrate 1 is sandwiched between the pair of electrodes. In this state, a 50 Hz or 60 Hz AC voltage is applied between the electrodes and the voltage is increased. The voltage increase rate is set to 200 V / s. The voltage at which the ceramic substrate 1 experiences dielectric breakdown is measured as the breakdown voltage B (kV).

[0014] For example, a spherical electrode with a tip diameter of 10 mm, as specified in JIS-C-2110-1 (2013), is used as the electrode. The electrode conditions when measuring breakdown voltage B are the same as those when measuring arc discharge voltage A. The maximum voltage is 20 kV. The unit of breakdown voltage B may be "kV / mm", which is the voltage divided by the thickness of the ceramic substrate 1. The units of arc discharge voltage and breakdown voltage should be unified to either "kV" or "kV / mm".

[0015] The electrodes, voltage rise rate, and measurement environment when measuring the breakdown voltage are the same as those when measuring the arc discharge voltage. Furthermore, if the ceramic substrate 1 is small, a catalog value may be used as the breakdown voltage of the ceramic substrate 1. As a guideline for size, if one side is less than 5 mm, it is preferable to use the catalog value.

[0016] For the ceramic substrate 1 according to the embodiment, the arc discharge voltage A (kV) and the dielectric breakdown voltage B When measuring (kV), the ratio A / B is 0.3 or more.

[0017] Arc discharge is detected as a pulse current that occurs periodically when an AC electric field of a constant frequency is applied to the ceramic substrate 1. For example, arc discharge is likely to occur in a structure where the electric field is concentrated. Arc discharge occurs in voids and other areas inside the ceramic substrate 1. When a voltage is applied to the ceramic substrate 1, a shared voltage is applied to the voids and other areas. This is due to a voltage gradient that occurs due to differences in resistance with the ceramic, and in the case of voids, the magnitude of the shared voltage varies depending on their size and shape. When this shared voltage reaches the discharge voltage in the voids and other areas, a partial discharge occurs, which is the source of the arc discharge. The periodic appearance of pulse currents generated by this partial discharge is determined to be the occurrence of an arc discharge. The voltage at which arc discharge begins is detected and measured as arc discharge voltage A.

[0018] The breakdown voltage is measured as the voltage at which current flows between the front and back surfaces of the ceramic substrate. In other words, the structural breakdown voltage at which the ceramic substrate 1 is short-circuited is measured as the breakdown voltage B.

[0019] In recent years, the switching frequency of semiconductor elements has increased with the advancement of their performance. Power semiconductor elements include Si elements, SiC elements, and GaN elements. The switching frequencies of these elements vary from several tens of Hz to several hundreds of kHz. In addition, in recent years, the switching frequency has increased to 1G. HzThere are also semiconductor elements with a switching frequency of about 1000 kHz. The current is repeatedly turned on and off depending on the switching frequency. When the current is repeatedly turned on and off, arc discharge may occur. The lower the arc discharge voltage of a ceramic substrate, the more likely it is that arc discharge will occur when the current is repeatedly turned on and off. When arc discharge occurs repeatedly, the insulation of the ceramic substrate deteriorates. As a result, the insulation of the ceramic substrate cannot be maintained for a long period of time. In other words, the insulation of the ceramic substrate deteriorates even though the breakdown voltage has not been reached.

[0020] Generally, the switching frequency of a Si-IGBT device, which is a type of Si device, is approximately 100 Hz to 50 kHz. The switching frequency of a SiC-MOS device is approximately 8 kHz to 1 MHz. As the switching frequency increases, the output power and power density also increase. For example, a Si-IGBT device with a switching frequency of 25 kHz has an output power of 3.3 kW and a power density of 0.3 W / cm. 3 For a SiC-MOS device with a switching frequency of 160 kHz, the output power is 5 kW and the power density is 1.8 W / cm. 3 There are elements with a switching frequency of about 1G for GaAs-MESFET (Metal semiconductor FET) and HEMT (High Electron Mobility Transistor). Hz ~10G Hz Increasing the switching frequency leads to an increase in output voltage or power density.

[0021] The ceramic substrate according to the embodiment exhibits excellent insulation properties even when the switching frequency is as high as 8 kHz or more. 3 In other words, the insulation properties of ceramic substrates used in semiconductor devices including high-performance semiconductor elements cannot be properly evaluated by the breakdown voltage alone.

[0022] In the ceramic substrate 1 according to the embodiment, the arc discharge voltage A (kV) and the dielectric breakdown voltage B When the arc discharge voltage (kV) is measured, the ratio A / B is 0.3 or more. This indicates that the arc discharge voltage A is 0.3 times or more the breakdown voltage B. On the other hand, an A / B ratio of less than 0.3 indicates that the arc discharge voltage A is lower than 0.3 times the breakdown voltage B. When a ceramic substrate with an A / B ratio of less than 0.3 is used, insulation failure of the ceramic substrate may occur when a semiconductor device with a high switching frequency is mounted and used, despite the high breakdown voltage. In other words, a ceramic substrate with an A / B ratio of less than 0.3 may lack long-term reliability.

[0023] Arc discharge is detected as a pulse current that occurs periodically when an AC electric field of a constant frequency is applied between electrodes. The initial arc discharge phenomenon occurs in voids within the ceramic substrate. Repeated arc discharges cause a phenomenon known as arc degradation. As arc degradation progresses, dielectric breakdown occurs. In other words, arc discharge is a sign of dielectric breakdown. For this reason, the long-term reliability of a ceramic substrate can be confirmed by measuring the voltage at which arc discharge occurs.

[0024] In particular, as the switching frequency of the semiconductor element increases, the number of periodically generated pulse currents increases. As the output voltage and power density increase, arc discharges become more likely to occur inside the ceramic substrate. Therefore, the higher the switching frequency, output voltage, and power density, the more likely the insulation inside the ceramic substrate is to be degraded by arc discharge, even if the ceramic substrate does not experience dielectric breakdown. This can result in long-term reliability issues.

[0025] An A / B ratio of 0.3 or more indicates that the arc discharge voltage A is higher than that of conventional ceramic substrates. Therefore, even when the output voltage and power density of the semiconductor element are high, arc discharge is unlikely to occur. By suppressing the occurrence of arc discharge, the number of arc discharge occurrences can be reduced even when the switching frequency of the mounted semiconductor element is high. In other words, suppressing the occurrence of arc discharge leads to improved reliability of semiconductor devices mounted with semiconductor elements having high switching frequencies.

[0026] The upper limit of the ratio A / B is 1.0. A ratio A / B=1.0 indicates that the arc discharge voltage and the breakdown voltage are substantially the same, or that substantially no arc discharge is observed. A ratio A / B=1.0 indicates that the ceramic substrate does not have a structure that generates a periodic pulse current even when an AC electric field of a constant frequency is applied between the electrodes. There are cases where there are substantially no voids in the ceramic substrate, and cases where voids are present but arc discharge cannot be detected (including below the detection limit). In these cases, it is impossible to predict long-term reliability. For this reason, the ratio A / B is preferably within the range of 0.3 or more but less than 1.0, and more preferably 0.5 or more but 0.9.

[0027] The ceramic substrate according to the embodiment has an area of ​​1 μm in any cross section. 2 The number of voids is within the range of 30 to 500, and the area is less than 1 μm 2 It is preferable that there is a 90 μm×120 μm area in which the number of voids is in the range of 0 to 30. For the sake of convenience, an area of ​​1 μm 2 Voids with an area of ​​less than 1 μm are called "small voids" (primary voids). 2 Voids that are above this level are called "large voids" (secondary voids).

[0028] 2 is a schematic diagram showing an example of a cross-sectional structure of a ceramic substrate. In FIG. 2, reference numeral 2 denotes a cross section of the ceramic substrate, and reference numeral 3 denotes a cross section having an area of ​​1 μm 2 The above large voids, number 4, have an area of ​​1 μm 2In FIG. 2, the large voids 3 are shown filled in black, and the small voids 4 are shown filled in white.

[0029] The method for observing a cross section will now be explained. First, prepare an arbitrary cross section of a ceramic substrate. A polished surface with a surface roughness Ra of 1 μm or less is used as the cross section. The cross section is observed with a scanning electron microscope (SEM) and a 1000x magnification photograph is taken. For the SEM, a JOEL JCM-7000, JSM-7200F or a device with equivalent or higher performance is used. From the enlarged photograph, a 1 μm area is identified. 2 Large voids of 3 or more, area 1 μm 2 Small voids less than 4 are observed.

[0030] To observe voids, SEM photographs are analyzed using image analysis software. Image J or equivalent software is used as the image analysis software. In cross-sectional SEM photographs, contrast occurs between voids and other parts. For example, the color of voids appears darker and more intense than the color of parts other than voids. By utilizing this contrast and binarizing the SEM photograph, it is possible to distinguish between voids and other parts. Note that small voids are defined as those with a size of 0.01 μm. 2 Voids with an area of ​​0.01 μm or more are counted. 2 This is because voids smaller than this size are difficult to distinguish in a 1000x magnification photograph.

[0031] The threshold value for binarization is determined by the "mode method" or "discriminant analysis binarization." If the image analysis software has a discriminant analysis binarization function, the discriminant analysis binarization method of that image analysis software is used. With discriminant analysis binarization, the threshold value is determined uniquely by the analysis software. This makes it easy to identify voids. For example, in an SEM image, the white area around a void is the boundary between the void and the silicon nitride sintered body. Therefore, the white area around a void should not be counted as a void. Also, in an SEM image, the silicon nitride sintered body is gray. Using the threshold value obtained by the "mode method" or "discriminant analysis binarization," voids can be displayed in black, and the white area around the void and the silicon nitride sintered body can be displayed in white. Using the binarized image, it is possible to distinguish between voids and other areas in the SEM image.

[0032] The SEM observation area is set to 180 μm x 430 μm. Three areas are observed, and a 90 μm x 120 μm area is selected from these, where the most voids are observed. If the 180 μm x 430 μm area cannot be observed in a single field of view, multiple 180 μm x 430 μm areas may be observed. In this case, the minimum size of the observed area is 90 μm x 120 μm. The orientation of the sample relative to the 180 μm x 430 μm observation area and the 90 μm x 120 μm area is optional. The orientation of the 180 μm x 430 μm observation area and the 90 μm x 120 μm area may be adjusted to observe the most voids in any cross section.

[0033] In any cross section, it is preferable that there is a 90 μm × 120 μm region in which the number of large voids 3 is in the range of 0 to 30. The large voids 3 affect both the arc discharge voltage and the breakdown voltage. In particular, the large voids 3 cause a decrease in the arc discharge voltage. For this reason, it is preferable that the number of large voids 3 is in the range of 0 to 30, and more preferably in the range of 0 to 20.

[0034] In any cross section, it is preferable that there is a 90 μm × 120 μm region in which the number of small voids 4 is in the range of 30 to 500. The small voids 4 have little effect on the arc discharge voltage and breakdown voltage. However, if the number of small voids 4 exceeds 500, the arc discharge characteristics are affected. If the number of small voids 4 is less than 30, the insulation properties are improved. On the other hand, to manufacture a ceramic substrate with fewer than 30 small voids 4, a hot isostatic pressing (HIP) process is required, which increases costs.

[0035] Furthermore, the presence of small voids 4 can improve the amount of deflection of the ceramic substrate 1. The amount of deflection refers to the amount of "deformation" from a horizontal state when stress is applied to a ceramic substrate placed horizontally. For example, the amount of deflection is the length of deflection when both ends of a ceramic substrate are fixed and the center is pressed. Ceramic circuit substrates are fixed with screws or other fasteners. A large amount of deflection can prevent the ceramic substrate from breaking even when stress from screwing is applied. For this reason, the number of small voids 4 present in a unit area of ​​90 μm x 120 μm is preferably in the range of 30 to 500, and more preferably in the range of 40 to 400.

[0036] The numbers of large voids 3 and small voids 4 are the numbers counted when observing a 90 μm × 120 μm area with the most voids in any cross section. Therefore, when observing a cross section, there may be areas where the number of large voids 3, the number of small voids 4, and the area ratio (described later) are less than the predetermined range. In other words, for the ceramic substrate 1 according to the embodiment, when three 180 μm × 430 μm areas are observed, there is at least one area where the number of large voids 3 and the number of small voids 4 are within the predetermined range. Preferably, no area where the number of large voids 3 and the number of small voids 4 are greater than the predetermined range exists, regardless of which 90 μm × 120 μm area is observed. For example, three arbitrary 180 μm × 430 μm areas may be observed to determine whether there are any areas where the number of large voids 3 and the number of small voids 4 are greater than the predetermined range.

[0037] By controlling the number of large voids 3 and the number of small voids 4, the ratio of arc discharge voltage A to breakdown voltage B can be controlled. Furthermore, after controlling the number of large voids 3 and the number of small voids 4, the total area ratio of the small voids 4 present in a 90 μm × 120 μm area is preferably within a range of 0.01% to 0.8%. By controlling the area ratio of the small voids 4, both insulation properties and deflection can be achieved. Furthermore, after controlling the number of large voids 3 and the number of small voids 4, the total area ratio of the large voids 3 present in a 90 μm × 120 μm area is preferably within a range of 0% to 0.6%. Even if the number of large voids 3 is within the specified range, if the total area ratio exceeds 0.6%, insulation properties may be reduced.

[0038] The area ratio of the large voids 3 and the area ratio of the small voids 4 described above are calculated in a 90 μm × 120 μm region where a predetermined number of large voids 3 and small voids 4 exist. In other words, in the ceramic substrate 1 according to the embodiment, there is a region where the number of large voids 3 and small voids 4 is controlled and the area ratio is also controlled.

[0039] The maximum diameter of voids present in a 90 μm × 120 μm area is preferably 15 μm or less. First, when observing the cross section, the longest diameter of each void shown in the photograph is measured. The "longest diameter" is the distance between the two furthest points on the outer edge of the void. The largest value among the longest diameters of multiple voids is defined as the "maximum diameter." By keeping the maximum diameter of the voids 15 μm or less, deterioration of the insulation properties of the ceramic substrate 1 can be suppressed.

[0040] The maximum diameter of the voids is measured in a 90 μm × 120 μm area where the most voids are observed. More preferably, the maximum diameter of the voids in three 180 μm × 430 μm areas is 15 μm or less. The three areas used to measure the maximum diameter may be the same as the three 180 μm × 430 μm areas observed when counting the number of voids.

[0041] Furthermore, in a 90 μm × 120 μm area, the number of pairs of large voids 3 where the distance between them is 5 μm or less is preferably 0 to 3. The number of pairs of large voids 3 is counted in the 90 μm × 120 μm area where the most voids are observed. If the distance between one large void 3 and another large void 3 is 5 μm or less, those large voids 3 are counted as one pair. If two large voids 3 exist within a 5 μm range from a reference large void 3, the reference large void 3 and each of the two large voids 3 are counted as two pairs. If three or more large voids 3 exist within a 5 μm range from a reference large void 3, those large voids 3 are counted as three or more pairs. For example, if three large voids 3 are distributed in a triangular shape with a distance of 5 μm or less between them, those large voids 3 are counted as three pairs.

[0042] The distance is measured using an enlarged photograph of the observed cross section. A 5 μm range is set around each observed large void 3, and if another large void 3 exists within that range, the number of pairs of voids is counted. When a 5 μm range is then set around another large void 3, the pairs that have already been counted are not counted again.

[0043] If the large voids 3 are close to each other, they may have the same function as larger voids. For example, if the number of pairs of large voids 3 that are 5 μm or less apart exceeds three, the arc discharge voltage and breakdown voltage may decrease, and the insulating properties of the ceramic substrate 1 may deteriorate. For this reason, the number of pairs of large voids 3 that are 5 μm or less apart is preferably in the range of 0 to 3, and more preferably in the range of 0 to 1. Note that even if a small void 4 exists near a large void 3, that pair of a large void 3 and a small void 4 is not counted. This is because the adverse effect on insulating properties is small even if the large voids 3 and the small voids 4 are close to each other. Here, only pairs of large voids 3 that are 5 μm or less apart are counted.

[0044] It is possible to combine two or more conditions selected from the number of voids, the total area ratio, the maximum diameter of the voids, and the number of sets of large voids 3. Most preferably, in any cross section, there is a region in which the number of voids, the total area ratio, the maximum diameter, and the number of sets of large voids 3 are all within the above-mentioned ranges.

[0045] The ceramic substrate 1 is one selected from a silicon nitride substrate, an aluminum nitride substrate, an aluminum oxide substrate, and an aruzirk substrate. An aruzirk substrate is a substrate containing both aluminum oxide and zirconium oxide. Among ceramic substrates, a silicon nitride substrate is preferred. The thermal conductivity of a silicon nitride substrate is 40 W / m·K or more, and preferably 80 W / m·K or more. Furthermore, the three-point bending strength of a silicon nitride substrate is 600 MPa or more, and preferably 700 MPa or more.

[0046] The thermal conductivity of aluminum nitride substrates is 160 W / m·K or higher, and even 200 W / m·K or higher. The three-point bending strength of aluminum nitride substrates is approximately 300 to 450 MPa. The three-point bending strength of aluminum oxide substrates is approximately 300 to 450 MPa, but aluminum oxide substrates are less expensive than other substrates. The thermal conductivity of aluminum oxide substrates is approximately 20 to 30 W / m·K. The three-point bending strength of Al-Si substrates is high at approximately 550 MPa, but their thermal conductivity is approximately 30 to 50 W / m·K.

[0047] The thickness of the ceramic substrate 1 is preferably within the range of 0.2 mm to 3 mm. If the thickness is less than 0.2 mm, the insulating properties of the ceramic substrate 1 may be insufficient. If the thickness exceeds 3 mm, the insulating properties of the ceramic substrate 1 are good, but the heat dissipation properties are reduced.

[0048] Because silicon nitride substrates have high strength, the thickness of the substrate can be set within the range of 0.2 mm to 0.8 mm, or even within the range of 0.2 mm to 0.4 mm. Furthermore, by controlling voids, it is possible to achieve both insulation and deflection. When two ceramic substrates have the same thickness, the one with the larger deflection is less likely to crack.

[0049] The arc discharge voltage A of the ceramic substrate 1 that is guaranteed to have a breakdown voltage B of 10 kV / mm or more is preferably 5 kV / mm or more. electric By setting the arc discharge voltage at 5 kV / mm or more, it is possible to set A / B at 0.3 or more, and even at 0.5 or more. For this reason, the ceramic substrate 1 is preferably a silicon nitride substrate with an arc discharge voltage of 5 kV / mm or more.

[0050] The ceramic substrate described above can be applied to a ceramic circuit substrate. Fig. 3 is a schematic diagram showing an example of a ceramic circuit substrate according to an embodiment. In Fig. 3, reference numeral 1 denotes a ceramic substrate, reference numeral 5 denotes a metal part, reference numeral 6 denotes a bonding layer, and reference numeral 10 denotes a ceramic circuit substrate.

[0051] In the example shown in FIG. 3, two metal parts 5 are bonded to the front side of the ceramic substrate 1, and one metal part 5 is bonded to the back side of the ceramic substrate 1. The ceramic circuit substrate 10 according to the embodiment is not limited to this shape. The ceramic substrate 1 may be provided with as many metal parts 5 as necessary. 3 In the example shown in FIG. 1, a metal part 5 used as a circuit is bonded to the front surface side, and a metal part 5 used as a heat sink is bonded to the back surface side. This example is not limiting, and metal parts 5 used as circuits may be bonded to both surfaces of the ceramic substrate 1. The bonding layer 6 is preferably formed using an active metal brazing material.

[0052] 4 is a schematic diagram showing an example of a semiconductor device according to an embodiment, in which reference numeral 8 denotes a semiconductor element, 10 denotes a ceramic circuit board, and 20 denotes a semiconductor device. As shown in FIG. 4, a semiconductor device 20 can be fabricated by mounting a semiconductor element 8 on a metal portion 5 of a ceramic circuit substrate 10. In the example shown in FIG. 4, one semiconductor element 8 is mounted on one metal portion 5. Multiple semiconductor elements 8 may be mounted on multiple metal portions 5, respectively. Multiple semiconductor elements 8 may be mounted on one metal portion 5. In addition to the semiconductor element 8, a lead frame, wire bonding, or the like may be bonded to the metal portion 5. By improving the arc discharge voltage of the ceramic substrate 1, it is possible to ensure the long-term reliability of the insulation of the semiconductor device 20, even when a semiconductor element 8 with a high switching frequency is mounted.

[0053] Next, a method for manufacturing the ceramic substrate 1 according to the embodiment will be described. The method for manufacturing the ceramic substrate 1 according to the embodiment is not particularly limited as long as it has the above-described configuration. Here, an example of a method for obtaining the ceramic substrate 1 with a good yield will be described. In the following example, a method for manufacturing a silicon nitride substrate will be described.

[0054] First, silicon nitride powder and sintering aid powder are prepared as raw materials. Silicon nitride powder produced by the imide decomposition method or direct nitridation method is used. The average particle size of the silicon nitride powder is preferably in the range of 0.1 μm to 4 μm. The sintering aid is one or more selected from rare earth elements, titanium (Ti), hafnium (Hf), magnesium (Mg), and calcium (Ca). Compounds of these elements may also be used. Examples of compounds include oxides, nitrides, and oxynitrides. Examples of rare earth elements include yttrium (Y) and lanthanoid elements. Examples of lanthanoid elements include ytterbium (Yb), erbium (Er), europium (Eu), lutetium (Lu), lanthanum (La), cerium (Ce), and dysprosium (Dy). The average particle size of the sintering aid powder is preferably in the range of 0.1 μm to 4 μm.

[0055] It is preferable to control the amounts of impurities contained in the silicon nitride powder and the sintering aid powder. Examples of impurities to be controlled include Fe and carbon. The mixture of silicon nitride powder and sintering aid powder is called the raw material mixed powder. The amount of Fe in the raw material mixed powder is preferably 0.05% by mass or less. The amount of carbon in the raw material mixed powder is preferably 0.5% by mass or less.

[0056] Fe and carbon present as impurities in the raw material powder mixture can lead to the formation of structural defects in the sintered body. For example, Fe dissolves into the liquid phase during sintering, significantly reducing the liquid phase viscosity in the dissolved area. In liquid phase sintering, densification progresses through grain boundary diffusion. In areas where the liquid phase viscosity has decreased, the rate of grain boundary diffusion changes, making it more likely that defects such as voids will form. Iron contained as an impurity is particularly likely to cause voids. Carbon also has a strong reducing effect, making it more likely that defects such as voids will form.

[0057] To control the Fe and carbon content of the raw material powder mixture, it is effective to use silicon nitride powder and sintering aid powder with low Fe and carbon content. Methods to prevent impurities from being mixed in during the manufacturing process are also effective. If the raw material powder mixture contains a large amount of Fe, it is also effective to remove the Fe using a magnet. By controlling the Fe and carbon content, it is possible to obtain a void distribution that does not affect the arc discharge characteristics.

[0058] It is also effective to control the fluorine (F) or chlorine (Cl) present as impurities in the raw material mixed powder. The total content of fluorine or chlorine in the raw material mixed powder is preferably 0 wtppm or more and 1000 wtppm or less. The total content of fluorine or chlorine in the sintered body is preferably 0 wtppm or more and 1000 wtppm or less.

[0059] Fluorine and chlorine are elements that are easily contained in silicon nitride powder. Silicon nitride powder is mainly produced by the imide decomposition method or the direct nitridation method. In the imide decomposition method, silicon halide is used as the raw material. In the direct nitridation method, a fluorine compound is used as a catalyst to nitride metallic silicon. For this reason, fluorine or chlorine is likely to remain in the silicon nitride powder.

[0060] Furthermore, the high electronegativity of fluorine or chlorine makes it easy for anion defects to form in the sintered body. This can potentially lead to arc discharge. Therefore, the total fluorine or chlorine content in the raw material powder mixture is preferably 0 wtppm or more and 1000 wtppm or less, and more preferably 0 wtppm or more and 400 wtppm or less. This allows the fluorine or chlorine content in the silicon nitride sintered body to be 1000 wtppm or less, or even 0 wtppm or more and 400 wtppm or less.

[0061] Silicon nitride powder and sintering aid powder are mixed and then further mixed using a mill. Examples of mills include ball mills and bead mills. During the mixing process, binders, solvents, etc. are added to the silicon nitride powder and sintering aid powder to produce a raw powder slurry. It is also preferable to impart hysteresis to the raw powder slurry. Controlling thixotropy is an effective way to impart hysteresis to the slurry. Thixotropy is the property in which the apparent viscosity decreases over time when a constant shear stress is applied, and gradually recovers when the force is removed. Apparent viscosity is thought to reflect the internal structure of the slurry, such as its aggregation state. JIS-R-1665 (2005) specifies the evaluation of thixotropy by measuring the hysteresis of the flow curve.

[0062] In order to impart hysteresis to the slurry, it is effective to increase the thixotropy index (TI value), which is an index of thixotropy. To increase the thixotropy index, for example, it is preferable to increase the particle concentration in the slurry or to use a poor solvent for particle dispersibility. When the particle concentration of the slurry is high, the interaction between particles increases, making it possible to make the particle dispersion non-uniform. As a result, the particle distribution in the compact can be made somewhat non-uniform and coarse / dense. This makes it easier for voids to occur during sintering, making it possible to control the void distribution. The thixotropy index (TI value) is preferably 1.5 or more and 5 or less.

[0063] The TI value is measured using a rotational viscometer in accordance with JIS-R-1665 (2005). When the shear rate is continuously increased using a rotational viscometer, the viscosity of a fluid with aggregation generally decreases. In this case, the ratio of the viscosity η at shear rate a to the viscosity η at shear rate b is the TI value. In other words, the TI value is expressed by the following formula: TI value = ηa / ηb

[0064] The viscosity η is measured with the shear rate a set to 4 (1 / s), and the viscosity η is measured with the shear rate b set to 40 (1 / s). The TI value is calculated using ηa / ηb. The closer the TI value is to 1, the closer it is to the behavior of a Newtonian fluid, meaning it is a highly dispersed slurry with no or very weak cohesion.

[0065] A TI value of 1.5 or more indicates that the slurry has some cohesiveness. Cohesiveness allows for control of the distribution of voids in the molded body. Furthermore, if the TI value exceeds 5, the cohesiveness may be too strong, resulting in too many voids. For this reason, the TI value of the slurry is preferably in the range of 1.5 to 5, more preferably in the range of 2.1 to 3.7. A molded body is produced using a slurry with a controlled TI value. Known molding methods such as doctor blade and mold molding can be used as the molding process. The production of a sheet-shaped molded body is called sheet molding.

[0066] Next, a drying step is performed to dry the compact. It is preferable to derive the constant rate drying period and the falling rate drying period from the weight loss behavior of the solvent, and set the temperature and time of the drying step based on the constant rate drying period and the falling rate drying period. At the beginning of drying, there is a sufficient amount of solvent in the ceramic green body, and the solvent forms a continuous layer at the interface between the ceramic particles. The constant rate drying period is the period during which the solvent in the ceramic green body evaporates at a nearly constant rate through the continuous layer. On the other hand, the falling rate drying period is the period during which the solvent inside the ceramic green body evaporates while the continuous solvent layer is interrupted. During the transition period from the constant rate drying period to the falling rate drying period, the shrinkage stress on the green body is at its maximum. For this reason, controlling the constant rate drying period, falling rate drying period, and transition period leads to the control of voids.

[0067] The rate of weight loss of the solvent during the constant rate drying period is preferably 1% by mass / min or more. There is no particular upper limit to the rate of weight loss of the solvent during the constant rate drying period, but it is preferably 10% by mass / min or less. If the rate of weight loss exceeds 10% by mass / min, voids may become larger. Therefore, the rate of weight loss of the solvent during the constant rate drying period is preferably within the range of 1% by mass / min or more and 10% by mass / min or less.

[0068] The weight loss rate of the solvent during the falling-rate drying period is preferably slower than the weight loss rate of the solvent during the constant-rate drying period. Furthermore, the ratio of the weight loss rates (weight loss rate of the solvent during the constant-rate drying period / weight loss rate of the solvent during the falling-rate drying period) is preferably greater than 1 and less than 20. This allows the solvent inside the ceramic compact to evaporate during the falling-rate drying period using the solvent evaporation route formed during the constant-rate drying period. A weight loss rate ratio (weight loss rate of the solvent during the constant-rate drying period / weight loss rate of the solvent during the falling-rate drying period) exceeding 20 can lead to an excessively fast drying rate, potentially resulting in large voids. A slow weight loss rate during the falling-rate drying period reduces manufacturing efficiency.

[0069] The green body that has been subjected to the drying process is then subjected to a degreasing process. The degreasing process is preferably carried out within a temperature range of 400°C to 800°C. The degreasing process can remove organic substances such as binders. Any remaining solvent is also removed.

[0070] Next, a sintering step is carried out. The sintering step is carried out by heating the compact in a non-oxidizing atmosphere at a temperature range of 1650°C to 1950°C for a period of 4 hours to 24 hours. The non-oxidizing atmosphere is preferably a nitrogen gas atmosphere or a reducing atmosphere containing nitrogen gas. The pressure inside the sintering furnace is preferably a pressurized atmosphere. If the compact is sintered at a sintering temperature below 1650°C, it is difficult to obtain a dense sintered body. On the other hand, if the compact is sintered at a sintering temperature higher than 1950°C, self-decomposition of Si3N4 is likely to occur, making it difficult to obtain a dense sintered body. Therefore, it is preferable to control the sintering temperature within the above range.

[0071] A heat treatment step is preferably carried out during the temperature increase process from the debinding step to the sintering step. In the heat treatment step, the compact is held at a temperature in the range of 1400°C to 1650°C for 1 hour to 8 hours. This treatment promotes and controls the diffusion of the liquid phase consisting of the sintering aid, leading to the control of voids in the sintered compact.

[0072] (Example) (Examples 1 to 9, Comparative Examples 1 to 3) Silicon nitride substrates or aluminum nitride substrates were fabricated as ceramic substrates. The mixing ratios of silicon nitride powder and sintering aid powder, which are raw material powders, are as shown in Table 1. The mixing ratios are values ​​when the total of either silicon nitride powder or aluminum nitride powder and sintering aid powder is 100 mass%. In both the examples and comparative examples, the Fe content in the raw material mixed powder was 0.05 mass% or less, and the carbon content was 0.5 mass% or less. In addition, the total amount of fluorine and chlorine in the raw material mixed powder was 1000 wtppm or less.

[0073] [Table 1]

[0074] A binder and a solvent were added to the raw material powder to prepare a raw material powder slurry. The raw material powder slurry was mixed in a ball mill. The TI value of each raw material powder slurry was adjusted. In the example, the TI value was set to a range of 2.1 or more and 3.7 or less. In comparative examples 1 to 3, the TI value was set to a range of 5.5 or more and 6.5 or less. The TI value was measured in accordance with JIS-R-1665 (2005). The details of the measurement conditions are as described above. A sheet compact was produced using the obtained raw material powder slurry. A doctor blade method was used to produce the sheet compact.

[0075] The obtained sheet-shaped product was subjected to a drying process. In the examples, the weight loss rate of the solvent during the constant rate drying period was in the range of 1% by mass / min to 10% by mass / min. In the examples, the ratio of the weight loss rates (weight loss rate of the solvent during the constant rate drying period / weight loss rate of the solvent during the falling rate drying period) was in the range of more than 1 to 20. In the comparative examples, the weight loss rate of the solvent during the constant rate drying period was in the range of 0.3% by mass / min to 0.8% by mass / min. In the comparative examples, the ratio of the weight loss rates (weight loss rate of the solvent during the constant rate drying period / weight loss rate of the solvent during the falling rate drying period) was in the range of more than 1 to 5. The sheet-shaped product after the drying process was subjected to a degreasing process. The degreasing process was carried out in the atmosphere at a temperature of 400°C to 800°C.

[0076] The obtained degreased body was subjected to a sintering process. During the heating process, the degreased body was held in a non-oxidizing atmosphere at a temperature between 1400°C and 1650°C for 1 hour to 8 hours. The molded body was then sintered by holding it at a temperature between 1650°C and 1950°C for 4 hours to 24 hours.

[0077] Silicon nitride substrates according to the examples and comparative examples were fabricated using the above steps. The silicon nitride substrates obtained measured 100 mm long and 80 mm short. The silicon nitride substrates had a thermal conductivity of 40 W / m·K to 95 W / m·K and a three-point bending strength of 500 MPa or more. The aluminum nitride substrates measured 100 mm long and 80 mm short. The aluminum nitride substrates had a thermal conductivity of 150 W / m·K to 250 W / m·K and a three-point bending strength of 300 MPa to 450 MPa.

[0078] A cross section of each silicon nitride or aluminum nitride substrate was observed using a SEM. Photographs were taken at 1000x magnification for SEM observations. Three randomly selected areas were observed. Each area measured 180 μm × 430 μm. A 90 μm × 120 μm region containing the most voids was extracted from the observed area. Image analysis software was used to determine the number and area ratio of voids in the 90 μm × 120 μm region. Within the 90 μm × 120 μm region with the most voids, the number of large voids (groups of 3) separated by 5 μm or less was counted. The longest diameter of each void was measured in the three 180 μm × 430 μm regions, and the largest diameter was extracted from these. Image J was used for image analysis. The total fluorine and chlorine content of the silicon nitride or aluminum nitride substrates was also measured. The results are shown in Table 2.

[0079] [Table 2]

[0080] As can be seen from Table 2, in the silicon nitride substrate and the aluminum nitride substrate according to the example, 2 The number of small voids less than 1 μm was 30 or more and 500 or less. 2 The number of large voids was in the range of 0 to 30.

[0081] Next, the arc discharge voltage, breakdown voltage, and deflection were measured. The methods for measuring the arc discharge voltage and breakdown voltage were as described above. To measure the deflection, cylindrical support members with a span width of 30 mm were placed on both ends of the silicon nitride substrate in the short side direction. Stress was applied to the center of the substrate, and the length until breakage was determined. The results are shown in Table 3.

[0082] [Table 3]

[0083] As can be seen from Table 3, the ratio of arc discharge voltage A to breakdown voltage B for the silicon nitride substrates and aluminum nitride substrates according to the examples was 0.3 or higher. The arc discharge voltage for each silicon nitride substrate and aluminum nitride substrate according to the embodiments was 5 kV or higher, and the breakdown voltage was 8.5 kV or higher. Furthermore, the breakdown voltage can be converted to kV / mm by dividing it by the ceramic substrate thickness. For example, in Example 1, the thickness of the silicon nitride substrate was 0.32 mm, so the breakdown voltage of the silicon nitride substrate was 30.3 kV / mm. Furthermore, the breakdown voltage of the aluminum nitride substrate according to the examples was 9.3 kV or higher. The examples also achieved favorable results in terms of deflection. Furthermore, when the amount of voids and fluorine content were high, as in Example 9, the A / B ratio slightly decreased to 0.51.

[0084] It can be seen that the arc discharge voltage of the ceramic substrate is improved while maintaining the dielectric breakdown voltage of the ceramic substrate in the examples. This improves the long-term reliability of the insulating properties of the silicon nitride substrate and the aluminum nitride substrate.

[0085] In contrast, in Comparative Examples 1, 2, and 3, although the breakdown voltage was equivalent to that of the Examples, the arc discharge voltage was lower. This was because the number and area ratio of voids were outside the preferred ranges. From this perspective, the silicon nitride substrate and aluminum nitride substrate according to the Examples achieved both long-term reliability in insulation and cost reduction.

[0086] Implementations of the invention may include the following features. (Feature 1) A ceramic substrate in which an AC voltage of 50 Hz or 60 Hz is applied between the front and back surfaces at a voltage increase rate of 200 V / s, the arc discharge voltage A (kV) is measured when an arc discharge is detected, and the dielectric breakdown voltage B (kV) between the front and back surfaces is measured in accordance with IEC 672-2, and the ratio A / B of the arc discharge voltage A to the dielectric breakdown voltage B is 0.3 or more. (Feature 2) 2. The ceramic substrate according to claim 1, having a thickness in the range of 0.2 mm to 3 mm. (Feature 3) In any cross section, the area is 1 μm 2 The number of first voids that are less than 1 μm is in the range of 30 to 500, and the area is less than 1 μm 2 3. The ceramic substrate according to claim 1, wherein there is a 90 μm×120 μm region in which the number of second voids having a value equal to or greater than 10 is within the range of 0 to 30. (Feature 4) The thickness is between 0.2mm and 3mm, In any cross section, the area is 1 μm 2 The number of first voids that are less than 1 μm is in the range of 30 to 500, and the area is less than 1 μm 2 A ceramic substrate having a 90 μm×120 μm area in which the number of second voids is within the range of 0 to 30. (Feature 5) 5. The ceramic substrate according to claim 3, wherein a total area ratio of the primary voids in the 90 μm×120 μm region is within a range of 0.01% to 0.8%. (Feature 6) 6. The ceramic substrate according to claim 3, wherein a total area ratio of the second voids in the 90 μm×120 μm region is within a range of 0% to 0.6%. (Feature 7) 7. The ceramic substrate according to claim 3, wherein the maximum diameter of voids in said 90 μm×120 μm region is 15 μm or less. (Feature 8) 8. The ceramic substrate according to claim 3, wherein the number of pairs of first voids having a distance of 5 μm or less in the 90 μm×120 μm region is 3 or less. (Feature 9) 9. The ceramic substrate according to claim 1, which is a silicon nitride substrate having an arc discharge voltage A of 5 kV or more. (Feature 10) 10. The ceramic substrate according to claim 1, which is a silicon nitride substrate having a thickness of 0.2 mm or more and 3 mm or less. (Feature 11) A ceramic substrate according to any one of claims 1 to 10; a metal portion provided on a surface of the ceramic substrate; A ceramic circuit board comprising: (Feature 12) The ceramic circuit substrate according to claim 11; a semiconductor element mounted on the metal part; A semiconductor device comprising:

[0087] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0088] 1...Ceramic substrate 2...Cross section 3…Area 1μm 2 More than void 4…Area 1μm 2 Less than void 5...Metal part 6...Joining layer 10...Ceramic circuit board

Claims

1. When an AC voltage of 50 Hz or 60 Hz is applied between the front and back surfaces at a voltage increase rate of 200 V / s, the arc discharge voltage A (kV) when an arc discharge is detected is measured, and a breakdown voltage B (kV) between the front and back surfaces is measured in accordance with IEC 672-2, the ratio A / B of the arc discharge voltage A to the breakdown voltage B is 0.3 or more, The thickness is within the range of 0.2 mm to 3 mm, In any cross section, there is a 90 μm×120 μm region in which the number of first voids having an area of ​​0.01 μm or more and less than 1 μm is in the range of 30 to 500, and the number of second voids having an area of ​​1 μm or more is in the range of 0 to 30, In the 90 μm×120 μm region, the total area ratio of the first voids is in the range of 0.01% or more and 0.8% or less, and the total area ratio of the second voids is in the range of 0% or more and 0.6% or less, A ceramic substrate having a fluorine and chlorine content of 1000 wtppm or less.

2. 2. The ceramic substrate according to claim 1, wherein the maximum diameter of voids in said 90 μm×120 μm region is 15 μm or less.

3. The ceramic substrate according to claim 2 , wherein the number of sets of second voids having a distance of 5 μm or less in the 90 μm×120 μm region is 3 or less.

4. 4. The ceramic substrate according to claim 1, which is a silicon nitride substrate having an arc discharge voltage A of 5 kV or more.

5. 4. The ceramic substrate according to claim 1, which is a silicon nitride substrate having a thickness of 0.2 mm or more and 3 mm or less.

6. 5. The ceramic substrate according to claim 4, which is a silicon nitride substrate having a thickness of 0.2 mm or more and 3 mm or less.

7. The ceramic substrate according to any one of claims 1 to 3; a metal portion provided on a surface of the ceramic substrate; A ceramic circuit board comprising:

8. The ceramic substrate according to claim 4; a metal portion provided on a surface of the ceramic substrate; A ceramic circuit board comprising:

9. The ceramic substrate according to claim 6; a metal portion provided on a surface of the ceramic substrate; A ceramic circuit board comprising:

10. The ceramic circuit substrate according to claim 7; a semiconductor element mounted on the metal part; A semiconductor device comprising:

11. The ceramic circuit substrate according to claim 8; a semiconductor element mounted on the metal part; A semiconductor device comprising:

12. The ceramic circuit substrate according to claim 9; a semiconductor element mounted on the metal part; A semiconductor device comprising:

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