Power supply control circuit and memory system

Abstract

To provide a power supply control circuit and a memory system capable of more appropriately supplying power.SOLUTION: A power supply control circuit according to this embodiment includes an input unit, an output unit, and a power supply control unit. The input unit receives an input voltage from a host. A first output voltage is output based on the output unit and the input voltage. The power supply control unit controls the output unit so as to change the output start timing of the first output voltage according to a first time period until the input voltage changes from a first predetermined voltage to a second predetermined voltage.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present embodiment relates to a power supply control circuit and a memory system. [Background technology]

[0002] A memory system is provided in which a power supply circuit including a power supply IC receives power from a host and supplies power (voltage) to a controller, NAND memory, etc. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 9,755,508 Summary of the Invention [Problem to be solved by the invention]

[0004] A power supply control circuit and a memory system capable of supplying power more appropriately are provided. [Means for solving the problem]

[0005] The power supply control circuit according to this embodiment includes an input unit, an output unit, and a power supply control unit. The input unit receives an input voltage from a host. The output unit outputs a first output voltage based on the input voltage. The power supply control unit controls the output unit to change the output start timing of the first output voltage in accordance with a first time period required for the input voltage to change from a first predetermined voltage to a second predetermined voltage. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a diagram illustrating an example of a system configuration of a memory system according to a first embodiment. [Figure 2] 1 is a block diagram showing the configuration of a power supply IC according to a first embodiment. [Figure 3]4 is a timing chart showing an example of the operation of the memory system according to the first embodiment. [Figure 4] FIG. 4 is a diagram illustrating an example of a method for measuring a rise time for determining a delay time according to the first embodiment. [Figure 5] 4 is a timing chart showing an example of the operation of the memory system according to the first embodiment. [Figure 6] FIG. 4 is a flowchart showing an example of the operation of the memory system according to the first embodiment. [Figure 7] 10 is a timing chart showing an example of an operation of a memory system according to a comparative example. [Figure 8] FIG. 10 is a flowchart showing an example of the operation of the memory system according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual, and the proportions of the various parts are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0008] In this specification, some elements are given multiple examples of expressions. Note that these examples are merely illustrative and do not deny that the elements may be expressed using other expressions. Furthermore, elements that do not have multiple expressions may also be expressed using other expressions.

[0009] The drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include portions where the relationship and ratio of dimensions differ from each other.

[0010] (First embodiment) 1 shows an example of a system configuration of a memory system 1 according to the first embodiment. Note that the memory system according to this embodiment is, for example, a memory system such as an SSD (Solid State Drive), but is not limited to this.

[0011] As shown in Fig. 1, the memory system 1 is connected to a host 2. In this embodiment, the host 2 is, for example, a notebook-type portable computer, a tablet terminal, or any of various electronic devices such as a detachable notebook PC or a mobile phone. The host 2 may also be a server device used in a data center or the like. The memory system 1 can be used, for example, as an external memory for the host 2.

[0012] As shown in FIG. 1, the memory system 1 includes a substrate 11, a nonvolatile memory 12, a controller 13, a volatile memory 14 that can operate faster than the nonvolatile memory 12, an oscillator (OSC) 15, an EEPROM (Electrically Erasable and Programmable ROM) 16, a power supply circuit 17, a temperature sensor 18, a connector 21, and other electronic components such as resistors and capacitors.

[0013] The nonvolatile memory 12 is, for example, a NAND flash memory (hereinafter abbreviated as NAND memory). In the following description, the nonvolatile memory 12 will be described as a "NAND memory 12", but the nonvolatile memory 12 is not limited to this and may be other nonvolatile memories such as MRAM (Magnetoresistive Random Access Memory).

[0014] The volatile memory 14 is, for example, a dynamic random access memory (DRAM). In the following description, the volatile memory 14 will be described as a "DRAM 14", but the volatile memory 14 is not limited to this and may be another volatile memory.

[0015] The NAND memory 12 and the controller 13 of this embodiment are mounted as a semiconductor package, which is an electronic component. For example, the semiconductor package of the NAND memory 12 has multiple semiconductor chips (memory chips) stacked and sealed in one package.

[0016] The substrate 11 is a substantially rectangular circuit board made of a material such as glass epoxy resin.

[0017] The connector 21 is also referred to as an interface section, a board interface section, a terminal section, or a connection section. The connector 21 has, for example, a plurality of connection terminals 21a (metal terminals). The connector 21 is electrically connected to the host 2 and exchanges signals (control signals and data signals) with the host 2.

[0018] The memory system 1 is electrically connected to a host 2 via an interface 3. The host 2 performs data access control for the memory system 1, and writes, reads, and erases data to the memory system 1, for example, by sending write requests, read requests, and erase requests to the memory system 1.

[0019] The interface 3 according to this embodiment is, for example, PCIe (Peripheral Component Interconnect Express). That is, a high-speed signal (high-speed differential signal) conforming to the PCIe standard flows between the connector 21 and the host 2.

[0020] The interface 3 may use other standards such as SAS (Serial Attached SCSI), SATA (Serial Advanced Technology Attachment), NVMe (Non Volatile Memory Express), and USB (Universal Serial Bus).

[0021] The memory system 1 is electrically connected to a host power supply unit 4 (power supply circuit) via a power line 5. The host power supply unit 4 provides various power sources used in the memory system 1 via the power line 5 and a connector 21.

[0022] The power supply circuit 17 is electrically connected to the host power supply unit 4 via the connector 21 and the power line 5. The power supply circuit 17 supplies the power required to operate the memory system 1 from the host power supply unit 4. The power supply circuit 17 supplies power to each electronic component such as the NAND memory 12, the controller 13, and the DRAM 14.

[0023] The power supply circuit 17 includes a power supply IC 17a, which is connected to electronic components such as resistors, capacitors, and inductors. The power supply IC 17a will be described later. The power supply IC 17a may also be referred to as a power supply unit, a power supply chip, or a composite power supply control IC, and the power supply IC 17a may be, for example, a PMIC (Power Management Integrated Circuit).

[0024] The power supply IC 17a according to this embodiment is, for example, a WLCSP (Wafer Level Chip Size Package), and at least one chip is packaged (sealed). However, the power supply IC 17a is not limited to this.

[0025] The controller 13 controls the operation of the NAND memory 12. That is, the controller 13 controls writing, reading, and erasing of data to the NAND memory 12. The controller 13 may be an SoC, a circuit, or a firm.

[0026] The controller 13 also has a reset input, and depending on the input signal, initializes (resets) the state of the controller 13 itself or releases the reset state, allowing the memory system 1 to start up normally as a system. The signal used to release the reset state is called, for example, POWER ON RESET. In addition, in the explanations in this specification, the phrase "to put into a reset state" also includes the case where something that is originally in a reset state is kept in the reset state.

[0027] As mentioned above, the DRAM 14 is an example of a volatile memory, and is used to store management information for the NAND memory 12, cache data, etc. The oscillator 15 supplies an operating signal of a predetermined frequency to the controller 13. The EEPROM 16 stores control programs and the like as fixed information.

[0028] The temperature sensor 18 monitors the temperature of, for example, the controller 13. Note that the temperature sensor 18 is mounted, for example, on the substrate 11 near the controller 13, but the position of the temperature sensor 18 is not limited to this. Furthermore, the temperature sensor 18 does not necessarily have to be provided on the substrate 11, and may be provided as a function of the controller 13.

[0029] Furthermore, the temperature sensor 18 measures the temperature around the location where the temperature sensor 18 is mounted, and the temperature measured by the temperature sensor 18 may be referred to as the "temperature of the memory system 1." Furthermore, if the temperature sensor 18 is mounted near the controller 13, the temperature measured by the temperature sensor 18 may be referred to as the "temperature of the controller 13."

[0030] 2 is a block diagram showing the configuration of a power supply IC 17a according to this embodiment. In this embodiment, the power supply IC (power supply control circuit) 17a includes a load switch 170, a power supply control unit 171, and multiple power supply channels CH1 to CH4. Note that each power supply channel may simply be referred to as a power supply. Note that the number of power supply channels is not limited to this.

[0031] The power supply IC 17a is supplied with a ground voltage (GND) that determines the reference potential. The frame ground can suppress noise.

[0032] The load switch 170 is a circuit that supplies power to electronic components. The ON / OFF state of the load switch 170 is controlled by a power supply control unit 171, which will be described later. An input 170i of the load switch 170 is connected to the host 2 (specifically, the host power supply unit 4) via wiring (wiring layer, internal wiring) provided on the substrate 11, a connector 21, and a power line 5. Power (input voltage VIN) is supplied from the host power supply unit 4 to the input 170i of the load switch (input unit) 170.

[0033] The output 170o of the load switch 170 is electrically connected to the inputs CH1i to CH4i of each power supply channel CH via, for example, an external portion of the power supply IC 17a. In other words, when the load switch 170 is in the ON state, power is supplied from the output 170o of the load switch 170 to each power supply channel CH in the power supply IC 17a again via wiring (wiring layer, internal wiring) provided on the substrate 11.

[0034] On the other hand, when the load switch 170 is in the OFF state, the supply of power to each power supply channel CH is stopped (cut off, interrupted).

[0035] In this embodiment, the power supply channel CH1 is, for example, an LDO (Low Drop Out), and the power supply channels CH2 to CH4 are, for example, DC / DC converters.

[0036] An LDO is a linear regulator that uses the on-resistance of power devices (pass transistors) such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and power transistors to forcibly consume input power and convert it to the desired output voltage. An LDO operates as a regulator even when the voltage difference between the input and output is small.

[0037] A DC / DC converter is also a switching regulator that outputs a switching pulse by switching the input voltage, and functions as a DC power supply by smoothing the output pulse with a filter that uses an inductor and a coil.

[0038] In this embodiment, the output CH2o of the power supply channel CH2 is connected to the controller 13 and supplies a predetermined voltage to the controller 13. The output CH3o of the power supply channel CH3 is connected to the DRAM 14 and supplies a predetermined voltage to the DRAM 14. The output CH4o of the power supply channel CH4 is connected to the NAND memory 12 and supplies a predetermined voltage to the NAND memory 12. Note that the types and connection relationships of the power supply channels CH are not limited to those described above and can be changed as appropriate.

[0039] Hereinafter, the multiple power supply channels CH1 to CH4 may also be referred to as an output unit 172. The output unit 172 outputs a first output voltage 172_OUT based on an input voltage VIN. More specifically, the output unit 172 receives a supply of a second output voltage VOUT output from the load switch 170 and outputs the first output voltage 172_OUT.

[0040] The power supply control unit 171 autonomously performs the power output sequence of the output unit 172. In other words, the power supply control unit 171 causes the output unit 172 to output the voltage of each of the multiple power supply channels CH corresponding to the first output voltage 172_OUT at predetermined time intervals and in a predetermined order. The power supply control unit 171 also performs ON / OFF control of the load switch 170. The power supply control unit 171 also has a timer. Using the timer, the power supply control unit 171 measures a rise time T, which will be described later, using a clock signal required to operate the load switch 170 and the power supply channels CH1 to CH4.

[0041] When power supply from the host 2 to the memory system 1 starts, the power supply control unit 171 controls the output unit 172 so that the output start timing of the first output voltage 172_OUT varies depending on the rate of rise of the input voltage VIN of the host 2. More specifically, the power supply control unit 171 instructs the output unit 172 to change the output start timing of the first output voltage 172_OUT depending on the rise time T (first time) required for the input voltage VIN to rise from the measurement start voltage V0 (third voltage) to the measurement end voltage V1 (fourth voltage). The output start timing refers to the timing at which the power supply channel CH set to output power first in the power output sequence starts to output power. This allows for more appropriate power supply, as will be described later with reference to FIGS. 3 to 6.

[0042] Next, the operation of the memory system 1 when power supply from the host 2 to the memory system 1 starts will be described.

[0043] 3 is a timing chart showing an example of the operation of the memory system 1 according to the first embodiment. Fig. 3 shows an example of the operation of the memory system 1 when connected to a host 2 that performs a soft start operation. The soft start operation is an operation in which, when power is supplied from the host 2 to the memory system 1, the power output is gradually increased to avoid an inrush current.

[0044] 4 is a diagram showing an example of a method for measuring a rise time for determining a delay time Td according to the first embodiment, and is an enlarged diagram of the input voltage VIN from time ta to time tb shown in FIG.

[0045] 3, when the host 2 starts supplying power to the memory system 1, a current is supplied from the host power supply unit 4 to the input 170i of the load switch 170. At time t1, the input voltage VIN starts to rise (rises up).

[0046] 3 and 4. At time ta, the input voltage VIN reaches the measurement start voltage V0. The measurement start voltage V0 is, for example, 2 V. The power supply control unit 171 starts measuring the rise time T of the input voltage VIN. The rise time T is used to set a delay time Td. The delay time Td is the time from when the second output voltage VOUT reaches the output start reference voltage to when the first output voltage 172_OUT starts to be output. The output start reference voltage is the voltage at which the output unit 172 becomes operable. In the example shown in FIGS. 3 and 4, the delay time Td is the period from time t4 to time t5.

[0047] Next, at time tb, the input voltage VIN reaches a measurement end voltage V1. The measurement end voltage V1 is, for example, 2.3 V. The power supply control unit 171 ends the measurement of the rise time T and stores the measured rise time T. The measured rise time T is stored, for example, in a memory (not shown) in the power supply IC 17a. The memory is, for example, a non-volatile memory. Note that the memory may also be a volatile memory.

[0048] Next, the power supply control unit 171 determines whether the rise time T is equal to or shorter than the threshold time N. The threshold time N is a value set before shipping the memory system 1. The threshold time N is, for example, 1 ms. In the example in which the soft start operation shown in FIGS. 3 and 4 is performed, the rise time T is longer than the threshold time N. In this case, the power supply control unit 171 changes the delay time Td to a time longer than the delay time Td. The delay time Td is, for example, the minimum value that can be set as the delay time. The power supply control unit 171 changes the delay time Td to a delay time Td1. The delay time Td1 is, for example, a multiple of the rise time T. As a result, the power supply control unit 171 changes the output start timing of the first output voltage 172_OUT based on the rise time T.

[0049] Next, at time t2, the input voltage V reaches the output start threshold. The output start threshold is a preset value, and when the value of the input voltage V reaches this threshold, the output of the second output voltage VOUT starts. As a result, the power supply control unit 171 controls the load switch 170, and the second output voltage VOUT rises.

[0050] Next, at time t3, the rate of increase of the second output voltage VOUT follows the rate of increase of the input voltage VIN.

[0051] Next, at time t4, the second output voltage VOUT reaches the output start reference voltage. After the set delay time Td1 has elapsed, the power supply control unit 171 delays the output start timing, starts the output power sequence, and instructs the output unit 172 to start output. After the delay time Td1 has elapsed from time t4 (time t5), the output unit 172 starts outputting the first output voltage 172_OUT.

[0052] After time t4, the input voltage VIN and the second output voltage VOUT rise completely. The voltage rise completely means that the voltage value has completed rising and has become a substantially stable value over time.

[0053] Next, at time t5, the output unit 172 starts outputting a voltage. In other words, after the delay time Td has elapsed, the output unit 172 (more specifically, the multiple power supply channels CH1 to CH4) starts outputting each voltage corresponding to the first output voltage 172_OUT at predetermined time intervals Ts and in a predetermined order in response to an instruction from the power supply control unit 171. At time t5, the power supply control unit 171 instructs the LDO to output a voltage, and the third output voltage LDO_OUT rises. The third output voltage LDO_OUT rises completely at time t6. Note that the third output voltage LDO_OUT is a part of the first output voltage 172_OUT.

[0054] Next, at time t6, the power supply control unit 171 instructs DC / DC2 and DC / DC3 to output voltages, and the fourth output voltage DC / DC2_OUT and the fifth output voltage DC / DC3_OUT rise. The fourth output voltage DC / DC2_OUT and the fifth output voltage DC / DC3_OUT rise completely at time t7. Note that the fourth output voltage DC / DC2_OUT and the fifth output voltage DC / DC3_OUT are part of the first output voltage 172_OUT.

[0055] Next, at time t7, the power supply control unit 171 instructs the DC / DC1 to output a voltage, and the sixth output voltage DC / DC1_OUT rises. The sixth output voltage DC / DC1_OUT rises completely at time t8. Note that the sixth output voltage DC / DC1_OUT is a part of the first output voltage 172_OUT.

[0056] As described above, when the soft start operation is performed and the input voltage VIN gradually increases, the output unit 172 can start outputting the first output voltage 172_OUT after the input voltage VIN has increased sufficiently.

[0057] Next, we will explain what happens when the soft start operation is not performed or when the soft start operation duration is short. The soft start operation duration is the time from when the soft start operation is performed until the input voltage VIN completely rises.

[0058] 5 is a timing chart showing an example of the operation of the memory system 1 according to the first embodiment. Fig. 5 shows an example of the operation of the memory system 1 when connected to a host 2 with a short soft start operation duration.

[0059] The period from time t11 to time t12 shown in FIG. 5 corresponds to the period from time t1 to time t2 shown in FIG.

[0060] In an example where the soft start operation duration is short, the input voltage VIN rises more steeply compared to the example shown in Fig. 3. Therefore, the rise time T shown in Fig. 5 is shorter than the rise time T shown in Fig. 3.

[0061] In an example where the soft start operation duration is short, the rise time T is equal to or less than the threshold time N. In this case, the power supply control unit 171 does not change the setting of the delay time Td.

[0062] Furthermore, because the input voltage VIN rises quickly, the second output voltage VOUT, which starts to rise at time t12, does not follow the rise in the input voltage VIN. That is, the second output voltage VOUT rises slower than the input voltage VIN.

[0063] After time t12, the input voltage VIN rises completely.

[0064] Next, at time t13, the second output voltage VOUT reaches the output start reference voltage. After the delay time Td has elapsed from time t13 (time t14), the power supply control unit 171 instructs the output unit 172 to output a voltage.

[0065] Next, the output unit 172 starts outputting the first output voltage 172_OUT. That is, the rise interval, rise order, etc. are the same in each of the power supply channels CH1 to CH4 regardless of whether the output start timing is changed or not. As a result, the output voltages of the power supply channels CH1 to CH4 are delayed uniformly. Time t14 to time t17 shown in FIG. 5 corresponds to time t5 to time t8 shown in FIG. 3.

[0066] 5, when the input voltage VIN rises sharply, it is possible to prevent the output start timing of the first output voltage 172_OUT from being delayed, that is, it is possible to shorten the delay time Td.

[0067] As a result, it is possible to suppress a voltage drop in the input voltage VIN and the second output voltage VOUT caused by a sudden increase in the required current.

[0068] Furthermore, the output unit 172 outputs the first output voltage 172_OUT so that the rate of increase of the first output voltage 172_OUT is approximately the same for different output start timings. That is, the soft start time of each of the power supply channels CH1 to CH4 is not changed regardless of whether the output start timing is changed. The soft start time of each of the power supply channels CH1 to CH4 is the time from when the output voltage (first output voltage 172_OUT) of each of the power supply channels CH1 to CH4 starts to rise until it completely rises. The period from time t5 to time t6 shown in FIG. 3 is approximately the same as the period from time t14 to time t15 shown in FIG. 5. The period from time t6 to time t7 shown in FIG. 3 is approximately the same as the period from time t15 to time t16 shown in FIG. 5. The period from time t7 to time t8 shown in FIG. 3 is approximately the same as the period from time t16 to time t17 shown in FIG. 5.

[0069] 5 also illustrates a case where the rate of increase of the second output voltage VOUT is slower than the rate of increase of the input voltage VIN. Even when the rate of increase of the second output voltage VOUT is faster than the rate of increase of the input voltage VIN, as long as the input voltage VIN has fully risen when the second output voltage VOUT has fully risen, the power supply control unit 171 similarly does not delay the start of output of the first output voltage 172_OUT.

[0070] 6 is a flow diagram showing an example of the operation of the memory system 1 according to the first embodiment. First, the host 2 starts supplying power (S10). When the input voltage VIN reaches the measurement start voltage V0 (S20), the power supply control unit 171 starts measuring the rise time T of the input voltage VIN (S30).

[0071] When the input voltage VIN reaches the measurement end voltage V1 (S40), the power supply control unit 171 ends the measurement of the rise time T and stores the measured rise time T in memory (S50).

[0072] Next, the power supply control unit 171 determines whether the rise time T is equal to or shorter than the threshold time N (S60). If the rise time T is longer than the threshold time N (No in S60), the power supply control unit 171 sets the delay time Td to a delay time Td1 that is longer than the delay time Td (S70).

[0073] When the second output voltage VOUT reaches the output start reference voltage (S80), after the delay time Td1 set in step S70 has elapsed, the power supply control unit 171 starts the power output sequence (S90) and instructs the output unit 172 to start outputting the first output voltage 172_OUT, which causes the output unit 172 to start outputting the first output voltage 172_OUT (S100).

[0074] If the rise time T is equal to or shorter than the threshold time N (Yes in S60), the power supply control unit 171 does not change the setting of the delay time Td (S110). When the second output voltage VOUT reaches the output start reference voltage (S120), after the delay time Td has elapsed, the power supply control unit 171 starts the power output sequence (S130) and instructs the output unit 172 to start outputting the first output voltage 172_OUT. This causes the output unit 172 to start outputting the first output voltage 172_OUT (S100).

[0075] The timing of times ta and tb is not limited to the examples shown in Figures 3 and 5. Time tb may be any time before the time when the second output voltage VOUT reaches the output start reference voltage.

[0076] Furthermore, the measurement start voltage V0, the measurement end voltage V1, the threshold time N, and the delay times Td and Td1 can be set to any values.

[0077] As described above, according to the first embodiment, the power supply control unit 171 instructs the output unit 172 to delay the start of output of the first output voltage 172_OUT in accordance with the rise time T required for the input voltage VIN to rise from the measurement start voltage V0 to the measurement end voltage V1. This makes it possible to supply power more appropriately.

[0078] More specifically, the power supply control unit 171 delays the output start timing of the first output voltage 172_OUT when the rise time T is longer than the threshold time N (fourth time) compared to the output start timing of the first output voltage 172_OUT when the rise time T is equal to or shorter than a predetermined time.

[0079] More specifically, when the rise time T is equal to or shorter than the threshold time N, the power supply control unit 171 starts outputting the first output voltage 172_OUT a delay time Td (first delay time) after the second output voltage VOUT reaches a predetermined voltage (third voltage). When the rise time is longer than the predetermined time, the power supply control unit 171 starts outputting the first output voltage 172_OUT a delay time Td1 (second delay time) after the second output voltage VOUT reaches the predetermined voltage. The delay time Td1 is longer than the delay time Td.

[0080] Furthermore, the power supply circuit 17 starts supplying power at different timings depending on the host 2. More specifically, the power supply circuit 17 starts supplying power to each electronic component at different timings depending on hosts 2 that have different rising rates of the input voltage VIN, for example, hosts 2 that take different lengths of time for the input voltage VIN to fully rise. This allows power to be appropriately supplied to each electronic component regardless of the rising rate of the voltage supplied from the host 2. The change (delay) of the output start timing may or may not be performed by the host 2 connected to the memory system 1. For example, the timing at which the output of the third output voltage LDO_OUT starts (rises) may differ by a predetermined time (for example, 10 ms) or more depending on the connected host 2.

[0081] (Comparative Example) 7 is a timing chart showing an example of the operation of a memory system 1 according to a comparative example. FIG. 7 shows an example of the operation of the memory system 1 when connected to a host 2 that has a long soft start operation duration. In the comparative example, the delay time is a fixed delay time Tda. Note that the timing chart when connected to a host 2 that does not perform a soft start operation is approximately the same as FIG. 5.

[0082] In the comparative example, the output start timing is not changed. That is, the delay time Tda is a fixed value. The delay time Tda is set, for example, when the power supply IC 17a is manufactured (before the memory system 1 is shipped). Furthermore, the delay time Tda is, for example, approximately the same as the delay time Td.

[0083] The time t21 to the time t24 shown in FIG. 7 corresponds to the time t1 to the time t4 shown in FIG.

[0084] When a host 2 with a long soft-start operation duration is connected, the output unit 172 starts supplying the first output voltage 172_OUT before the input voltage VIN has fully risen, i.e., while the input voltage VIN is low. In this case, a voltage drop may occur in the input voltage VIN or the second output voltage VOUT. If a voltage drop occurs, for example, the first output voltage 172_OUT may enter an OFF state. When the first output voltage 172_OUT enters an OFF state, it may be necessary to lower the input voltage VIN to near zero V and then restart it. Furthermore, for example, the second output voltage VOUT may repeatedly drop, causing the first output voltage 172_OUT to fluctuate while rising (i.e., the first output voltage 172_OUT may fluctuate frequently in a short period of time).

[0085] In contrast, in the first embodiment, when a host 2 with a long soft-start operation duration is connected, the power supply control unit 171 delays the timing at which the first output voltage 172_OUT starts to be output. This allows the supply of the first output voltage 172_OUT to start after the input voltage VIN has become sufficiently high. As a result, even if a voltage drop occurs, the potential difference up to the threshold at which the output of the first output voltage 172_OUT stops is large, so it is possible to prevent the output of the first output voltage 172_OUT from being stopped or the first output voltage 172_OUT from fluctuating by repeatedly turning on and off. As a result, power can be supplied more appropriately.

[0086] (Second embodiment) FIG. 8 is a flowchart showing an example of the operation of the memory system 1 according to the second embodiment. The second embodiment differs from the first embodiment in the method of determining the delay time Td.

[0087] The power control unit 171 changes the output start timing based on a preset time for each of a plurality of ranges of the rise time T. In the example shown in FIG. 8, different delay times are preset for each of the three ranges of T≦N, N<T≦N2, and N2<T. The threshold time N is, for example, 1 ms. The threshold time N2 is, for example, 5 ms.

[0088] Steps S10 to S60 shown in FIG. 8 are the same as steps S10 to S60 shown in FIG. 6.

[0089] When the rise time T is longer than the threshold time N (No in S60), the power control unit 171 determines whether the rise time T is longer than the threshold time N and less than or equal to the threshold time N2 (S210). When the rise time T is longer than the threshold time N2 (No in S210, S220), the power control unit 171 sets the delay time Td to, for example, the delay time Td2 (S230). The delay time Td2 is a time longer than the delay time T.

[0090] When the second output voltage VOUT reaches the output start reference voltage (S240), after the delay time Td2 set in step S230 has elapsed, the power control unit 171 starts the power output sequence (S250) and instructs the output unit 172 to start outputting the first output voltage 172_OUT. Thereby, the output unit 172 starts outputting the first output voltage 172_OUT (S260).

[0091] When the rise time T is longer than the threshold time N and less than or equal to the threshold time N2 (Yes in S210), the power control unit 171 sets the delay time Td to, for example, the delay time Td3 (S270). The delay time Td3 is a time longer than the delay time T and shorter than the delay time Td2.

[0092] When the second output voltage VOUT reaches the output start reference voltage (S280), the power supply control unit 171 starts the power output sequence after the delay time Td3 set in step S270 has elapsed (S290), and instructs the output unit 172 to start outputting the first output voltage 172_OUT. As a result, the output unit 172 starts outputting the first output voltage 172_OUT (S260).

[0093] If the rise time T is equal to or less than the threshold time N (Yes in S60), the power supply control unit 171 does not change the setting of the delay time Td (S300).

[0094] When the second output voltage VOUT reaches the output start reference voltage (S310), the power supply control unit 171 starts the power output sequence after the delay time Td has elapsed (S320) and instructs the output unit 172 to start outputting the first output voltage 172_OUT, which causes the output unit 172 to start outputting the first output voltage 172_OUT (S260).

[0095] 8, the rise time T is divided into three time ranges in steps S60 and S210, but the number of divisions may be changed arbitrarily.

[0096] Furthermore, the measurement start voltage V0, measurement end voltage V1, threshold times N, N2, and delay times Td, Td3, Td2, etc. are not limited to the example shown in FIG. 8, but can be set to any values.

[0097] The memory system 1 according to the second embodiment sets the delay time more precisely in accordance with the rise time T, and delays the start of output of the first output voltage 172_OUT. This allows for more appropriate power supply. The memory system 1 according to the second embodiment can achieve effects similar to or greater than those of the first embodiment.

[0098] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0099] 1 memory system, 2 host, 12 NAND memory, 13 controller, 17 power supply circuit, 17a power supply IC, 170 load switch, 171 power supply control unit, 172 output unit, 172_OUT first output voltage, CH1 to CH4 power supply channel, VIN input voltage, VOUT second output voltage, V0 measurement start voltage, V1 measurement end voltage, T rise time, Td delay time

Claims

1. an input unit that receives an input voltage from a host; an output unit that outputs at least one first output voltage based on the input voltage; a power supply control unit that controls the output unit to change an output start timing of the first output voltage in accordance with a first time period required for the input voltage to change from a first voltage to a second voltage; A power supply control circuit comprising:

2. 2. The power supply control circuit according to claim 1, wherein the power supply control unit delays the output start timing when the first time is longer than a third time compared to the output start timing when the first time is equal to or shorter than the third time.

3. the output unit receives a second output voltage output from the input unit and outputs the first output voltage; The power supply control unit If the first time is equal to or shorter than the third time, output of the first output voltage is started after a first delay time has elapsed since the second output voltage reached a third voltage; If the first time is longer than the third time, the output of the first output voltage is started after a second delay time has elapsed since the second output voltage reached the third voltage; The power supply control circuit according to claim 2 , wherein the second delay time is longer than the first delay time.

4. the output unit has a plurality of channels that start outputting respective voltages according to the first output voltage at predetermined time intervals and in a predetermined order; 2. The power supply control circuit according to claim 1, wherein the plurality of channels start outputting respective voltages corresponding to the first output voltage so that the predetermined time intervals and the predetermined order are substantially the same for different output start timings.

5. the output unit has a plurality of channels that start outputting respective voltages according to the first output voltage at predetermined time intervals and in a predetermined order; the plurality of channels includes a first channel that is the earliest in the predetermined order; after starting to output a voltage from the first channel according to the first output voltage at the different output start timings, the plurality of channels start to output their respective voltages according to the first output voltage so that the predetermined time intervals and the predetermined order are substantially the same; 2. The power supply control circuit according to claim 1.

6. 2 . The power supply control circuit according to claim 1 , wherein the output section outputs the first output voltage so that the rate of increase of the first output voltage is substantially the same for different output start timings.

7. The power supply control circuit according to claim 1 , wherein the power supply control unit changes the output start timing based on a time obtained by multiplying the first time.

8. 2. The power supply control circuit according to claim 1, wherein the power supply control unit compares the first time period with a plurality of threshold times and changes the output start timing based on a delay time that is set in advance for each of the plurality of comparison results.

9. the output unit receives a second output voltage output from the input unit and outputs the first output voltage; The power supply control unit If the first time is equal to or shorter than a fourth time, output of the first output voltage is started after a third delay time has elapsed since the second output voltage reached a third voltage; when the first time is longer than the fourth time and is equal to or shorter than a fifth time, starting the output of the first output voltage after a fourth delay time has elapsed since the second output voltage reached the third voltage; If the first time is longer than the fifth time, output of the first output voltage is started after a fifth delay time has elapsed since the second output voltage reached the third voltage; the fourth delay time is longer than the third delay time, The fifth delay time is longer than the fourth delay time.

2. The power supply control circuit according to claim 1.

10. 1. A memory system connectable to a host, comprising: a non-volatile memory; a controller that controls the nonvolatile memory; a power supply control circuit that supplies power to the nonvolatile memory and the controller; Equipped with The power supply control circuit an input unit that receives an input voltage from the host; an output unit that outputs at least one first output voltage based on the input voltage; a power supply control unit that controls the output unit to change an output start timing of the first output voltage in accordance with a first time period required for the input voltage to change from a first voltage to a second voltage; A memory system having:

11. The output unit a first channel that outputs a voltage corresponding to the first output voltage to the nonvolatile memory; a second channel that outputs a voltage corresponding to the first output voltage to the controller; 11. The memory system of claim 10, comprising:

12. 1. A memory system connectable to a host, comprising: a non-volatile memory; a controller that controls the nonvolatile memory; a power supply control circuit that supplies power to the nonvolatile memory and the controller; Equipped with The power supply control circuit starts supplying power at different timings depending on the host having a different rate of increase in input voltage.

13. It can connect to multiple hosts, an input unit that receives an input voltage from at least one of the plurality of hosts; an output section that outputs a first output voltage based on the input voltage; a first channel supplied with the first output voltage; setting an output start time of the first output voltage according to a start-up time required for the input voltage to change from a first voltage to a second voltage; the plurality of hosts include a first host whose startup time is a first time and a second host whose startup time is a second time; When the first host is connected, after a first delay time corresponding to the first time has elapsed, the first output voltage is supplied to the first channel; When the second host is connected, the first output voltage is supplied to the first channel after a second delay time corresponding to the second time has elapsed. Power control circuit.

14. the first time period is greater than the second time period; the first delay time is longer than the second delay time; 14. The power supply control circuit of claim 13.

15. a second channel supplied with the first output voltage; When the first host is connected, a first output voltage is supplied to the second channel after a third time has elapsed since the first output voltage was supplied to the first channel; when the second host is connected, supplying the first output voltage to the second channel after the third time has elapsed since supplying the first output voltage to the first channel; 14. The power supply control circuit of claim 13.

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