Chip parts

Abstract

To provide a chip part capable of improving mechanical strength and insulation, miniaturizing and increasing capacity, and adding an ESD protection function.SOLUTION: A chip part (1) includes: a substrate (2); a capacitor portion (32) including a plurality of wall portions (85) having a lengthwise direction and separated from each other by a trench (107) formed on a first main surface (5); and a substrate body portion (54) formed around the capacitor portion (32) using a portion of the substrates (2). The wall portions (85) are formed of a plurality of pillar units. The capacitor portion (32), in plan view, includes a first capacitor portion (321) including wall portions (85) having the lengthwise direction as first lengthwise direction (D1), and a second capacitor portion (322) including the wall portions (85) having the lengthwise direction as a second lengthwise direction (D2) intersecting with the first lengthwise direction (D1).SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to chip components. [Background technology]

[0002] Patent Document 1 discloses a chip capacitor including a substrate, a first conductive film and a first pad film formed on the substrate, a dielectric film formed on the first conductive film and the first pad film, and a second conductive film formed on the dielectric film and including a second connection region and a second capacitor formation region. The first conductive film includes the first connection region and the first capacitor formation region. A first external electrode is bonded to the first connection region of the first conductive film, and a second external electrode is bonded to the second connection region of the second conductive film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-195322 Summary of the Invention [Means for solving the problem]

[0004] A chip part according to one embodiment of the present disclosure includes a substrate having a first main surface and a second main surface opposite to the first main surface; a capacitor portion formed on the first main surface of the substrate in a plan view seen from a normal direction of the first main surface, the capacitor portion having a plurality of wall portions having a longitudinal direction separated from one another by trenches formed in the first main surface; a substrate body portion formed around the capacitor portion using a part of the substrate and connected to at least one end and the other end of the wall portions in the longitudinal direction; a lower electrode formed along an upper surface and a side surface of the wall portions; The capacitor includes a capacitive film formed on the lower electrode along the side surface, and an upper electrode formed on the capacitive film, and the wall portion is formed of a plurality of pillar units, and each pillar unit includes, in the planar view, a central portion and three protrusions extending from the central portion in three different directions, and the wall portion is formed by connecting the protrusions of adjacent pillar units, and the capacitor portion includes, in the planar view, a first capacitor portion including the wall portion whose longitudinal direction is a first longitudinal direction, and a second capacitor portion including the wall portion whose longitudinal direction is a second longitudinal direction intersecting the first longitudinal direction. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a schematic perspective view of a chip part according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic plan view of the chip part. [Figure 3] FIG. 3 is a schematic exploded view of the chip part. [Figure 4] FIG. 4 is a schematic plan view of the chip part. [Figure 5] FIG. 5 is a schematic plan view of the chip part. [Figure 6] FIG. 6 is a schematic plan view of the chip part. [Figure 7] FIG. 7 is a schematic plan view of the chip part. [Figure 8] FIG. 8 is an enlarged view of a main part of the chip part of FIG. [Figure 9]FIG. 9 is a schematic cross-sectional view of the chip part. [Figure 10] FIG. 10 is a schematic cross-sectional view of the chip part. [Figure 11A] FIG. 11A is a schematic cross-sectional view showing a part of the manufacturing process of the chip component. [Figure 11B] FIG. 11B is a diagram showing the next step of FIG. 11A. [Figure 11C] FIG. 11C shows the next step in FIG. 11B. [Figure 11D] FIG. 11D shows the next step in FIG. 11C. [Figure 11E] FIG. 11E shows the next step of FIG. 11D. [Figure 11F] FIG. 11F shows the next step of FIG. 11E. [Figure 11G] FIG. 11G shows the next step in FIG. 11F. [Figure 11H] FIG. 11H shows the next step of FIG. 11G. [Figure 11I] FIG. 11I shows the next step of FIG. 11H. [Figure 11J] FIG. 11J shows the next step of FIG. 11I. [Figure 11K] FIG. 11K shows the next step of FIG. 11J. [Figure 11L] FIG. 11L shows the next step of FIG. 11K. [Figure 11M] FIG. 11M shows the next step in FIG. 11L. [Figure 11N] FIG. 11N shows the next step in FIG. 11M. [Figure 11O] FIG. 11O is a diagram showing the next step of FIG. 11N. [Figure 11P] FIG. 11P shows the next step in FIG. 11O. [Figure 11Q] FIG. 11Q shows the next step after FIG. 11P. [Figure 12] FIG. 12 is a diagram for explaining a modified example of the chip part. [Figure 13]FIG. 13 is a diagram for explaining a modified example of the chip part. [Figure 14] FIG. 14 is a diagram for explaining a modified example of the chip part. [Figure 15] FIG. 15 is a diagram for explaining a modified example of the chip part. [Figure 16] FIG. 16 is a diagram for explaining a modified example of the chip part. [Figure 17] FIG. 17 is a diagram for explaining a modified example of the chip part. [Figure 18] FIG. 18 is a schematic plan view of the chip part according to Sample 1. As shown in FIG. [Figure 19] FIG. 19 is a schematic plan view of the chip part according to Sample 2. As shown in FIG. [Figure 20] FIG. 20 is a schematic plan view of the chip part according to Sample 3. As shown in FIG. [Figure 21] FIG. 21 is a diagram showing the evaluation results of the Q value and capacitance value of Sample 1. [Figure 22] FIG. 22 is a diagram showing the evaluation results of the Q value and capacitance value of Sample 2. As shown in FIG. [Figure 23] FIG. 23 is a diagram showing the evaluation results of the Q value and capacitance value of Sample 3. [Figure 24] FIG. 24 is a diagram showing the evaluation results of the series resistance of Sample 1. [Figure 25] FIG. 25 is a diagram showing the evaluation results of the series resistance of Sample 2. [Figure 26] FIG. 26 is a diagram showing the evaluation results of the series resistance of Sample 3. [Figure 27] FIG. 27 is a diagram for explaining a modified example of the chip part. [Figure 28] FIG. 28 is a diagram for explaining a modified example of the chip part. [Figure 29] FIG. 29 is a diagram for explaining a modified example of the chip part. [Figure 30] FIG. 30 is a diagram for explaining a modified example of the chip part. [Figure 31] FIG. 31 is a diagram for explaining a modified example of the chip part. [Figure 32] FIG. 32 is a diagram for explaining a modified example of the chip part. [Figure 33] FIG. 33 is a diagram for explaining a modified example of the chip part. [Figure 34] FIG. 34 is a diagram for explaining a modified example of the chip part. [Figure 35] FIG. 35 is a diagram for explaining a modified example of the chip part. [Figure 36] FIG. 36 is a schematic plan view of the chip part according to Sample 4. As shown in FIG. [Figure 37] FIG. 37 is a schematic plan view of the chip part according to Sample 5. As shown in FIG. [Figure 38] FIG. 38 is a schematic plan view of the chip part according to Sample 6. As shown in FIG. [Figure 39] FIG. 39 is a schematic plan view of the chip part according to Sample 7. As shown in FIG. [Figure 40] FIG. 40 is a schematic plan view of the chip part according to Sample 8. As shown in FIG. [Figure 41] FIG. 41 is a schematic plan view of the chip part according to Sample 9. As shown in FIG. [Figure 42] FIG. 42 is a schematic plan view of the chip part according to Sample 10. As shown in FIG. [Figure 43] FIG. 43 is a schematic perspective view of a chip part according to an embodiment of the present disclosure. [Figure 44] FIG. 44 is a schematic plan view of the chip part. [Figure 45] FIG. 45 is a schematic plan view of the chip part. [Figure 46] FIG. 46 is a schematic plan view of the chip part. [Figure 47] FIG. 47 is a schematic cross-sectional view of the chip part. [Figure 48A] FIG. 48A is a schematic cross-sectional view showing a part of the manufacturing process of the chip part. [Figure 48B]FIG. 48B shows the next step in FIG. 48A. [Figure 48C] FIG. 48C shows the next step in FIG. 48B. [Figure 48D] FIG. 48D shows the next step in FIG. 48C. [Figure 48E] FIG. 48E shows the next step in FIG. 48D. [Figure 48F] FIG. 48F shows the next step in FIG. 48E. [Figure 48G] FIG. 48G shows the next step in FIG. 48F. [Figure 49] FIG. 49 is a diagram for explaining a modified example of the chip part. DETAILED DESCRIPTION OF THE INVENTION

[0006] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. [External appearance of chip part 1 (horizontal)] Fig. 1 is a schematic perspective view of a chip component 1 according to an embodiment of the present disclosure. Fig. 2 is a schematic plan view of the chip component 1. In Figs. 1 and 2, the longitudinal direction of the rectangular parallelepiped chip component 1 is defined as a first direction X, the width direction of the chip component 1 is defined as a second direction Y, and the thickness direction of the chip component 1 is defined as a third direction Z.

[0007] The chip component 1 is formed in a rectangular parallelepiped shape and has a length L1 along the first direction X, a width W1 along the second direction Y, and a thickness T1 along the third direction Z. The length L1 may be, for example, 0.4 mm or more and 2 mm or less. The width W1 may be, for example, 0.2 mm or more and 2 mm or less. The thickness T1 may be, for example, 0.1 mm or more and 0.5 mm or less.

[0008] The chip component 1 may be a small electronic component designated by its size (length L1 (mm) × width W1 (mm)), such as a 1608 (1.6 mm × 0.8 mm) chip, a 1005 (1.0 mm × 0.5 mm) chip, a 0603 (0.6 mm × 0.3 mm) chip, a 0402 (0.4 mm × 0.2 mm) chip, or a 03015 (0.3 mm × 0.15 mm) chip.

[0009] The chip component 1 includes a substrate 2 , a first external electrode 3 , and a second external electrode 4 .

[0010] The substrate 2 forms the base of the chip component 1. The chip component 1 is formed by supporting a plurality of insulating films and metal films, etc., stacked on top of each other, on the substrate 2. The substrate 2 has a rectangular parallelepiped shape and is approximately the same size as the chip component 1. The substrate 2 has a first main surface 5, a second main surface 6, and four side surfaces 7 to 10. The first main surface 5 is the so-called front surface of the chip component 1, and the second main surface 6 is the back surface of the chip component 1. The four side surfaces 7 to 10 surround the first main surface 5 in a plan view seen from the normal direction n of the first main surface 5 (hereinafter simply referred to as "plan view"). The four side surfaces 7 to 10 may include a pair of a first side surface 7 and a second side surface 8 facing each other in the first direction X, and a pair of a third side surface 9 and a fourth side surface 10 facing each other in the second direction Y. In other words, the side surfaces extending parallel to each other along the second direction Y may be the first side surface 7 and the second side surface 8, and the side surfaces extending parallel to each other along the first direction X may be the third side surface 9 and the fourth side surface 10. The first side surface 7, the second side surface 8, the third side surface 9, and the fourth side surface 10 may also be referred to as the first end surface, the second end surface, the third end surface, and the fourth end surface, respectively.

[0011] The first external electrode 3 and the second external electrode 4 are formed on the first main surface 5. The first external electrode 3 and the second external electrode 4 are spaced apart from each other in the first direction X. In this embodiment, the first external electrode 3 and the second external electrode 4 form both terminals of the chip component 1, and a current flows between the first external electrode 3 and the second external electrode 4 in the horizontal direction along the first main surface 5 of the substrate 2. Therefore, the chip component 1 may be referred to as a horizontal chip component. The horizontal chip component 1 can be used, for example, by flip-chip bonding to a mounting substrate. The first external electrode 3 and the second external electrode 4 may also be referred to as a first terminal electrode and a second terminal electrode, or a first external terminal and a second external terminal, respectively.

[0012] In this embodiment, the first main surface 5, which is rectangular in plan view, has, in the first direction X, a first end 11 close to the first side surface 7 and a second end 12 close to the second side surface 8. The first external electrode 3 is arranged so as to cover the first end 11, and the second external electrode 4 is arranged so as to cover the second end 12. Between the first external electrode 3 and the second external electrode 4, there is an insulating space 13, in which an insulating portion on the first main surface 5 of the substrate 2 is exposed. The insulating space 13 has a quadrangular shape in plan view, and is formed across the entire width direction of the first main surface 5 in the first direction X, from the first external electrode 3 to the second external electrode 4. The length of the insulating space 13 in the first direction X (the distance D between the first external electrode 3 and the second external electrode 4) may be, for example, 0.1 mm or more and 0.5 mm or less.

[0013] The first external electrode 3 is formed in a region on the first main surface 5 of the substrate 2, spaced inward from the four side surfaces 7 to 10. As a result, the first external electrode 3 is surrounded by a first insulating edge portion 14, which exposes the insulating portion on the first main surface 5 of the substrate 2, in a plan view. The first external electrode 3 is formed in a rectangular shape, with its longitudinal direction aligned with the first side surface 7, in a plan view. The first external electrode 3 has a first long side 15 close to the first side surface 7, a second long side 16 on the opposite side thereof, a first short side 17 close to the third side surface 9, and a second short side 18 on the opposite side thereof. The first long side 15, the second long side 16, the first short side 17, and the second short side 18 are sides that extend parallel to and spaced from the first side surface 7, the second side surface 8, the third side surface 9, and the fourth side surface 10 of the substrate 2, respectively. The first external electrode 3 may overlap the first side surface 7, the third side surface 9 and the fourth side surface 10 of the substrate 2, thereby partially covering the side surfaces 7, 9 and 10 of the substrate 2.

[0014] The second external electrode 4 is formed in a region on the first main surface 5 of the substrate 2, spaced inward from the four side surfaces 7 to 10. As a result, the second external electrode 4 is surrounded by a second insulating edge portion 19, which exposes the insulating portion on the first main surface 5 of the substrate 2, in a plan view. The second external electrode 4 is formed in a rectangular shape with its longitudinal direction aligned with the second side surface 8 in a plan view. The second external electrode 4 has a third long side 20 close to the second side surface 8, a fourth long side 21 on the opposite side thereof, a third short side 22 close to the third side surface 9, and a fourth short side 23 on the opposite side thereof. The third long side 20, the fourth long side 21, the third short side 22, and the fourth short side 23 are sides that extend parallel to and spaced from the second side surface 8, the first side surface 7, the third side surface 9, and the fourth side surface 10 of the substrate 2, respectively. The second external electrode 4 may overlap the second side surface 8, the third side surface 9 and the fourth side surface 10 of the substrate 2, thereby partially covering the side surfaces 8, 9 and 10 of the substrate 2.

[0015] A concave-convex structure 26 is formed on the surface (first electrode surface 24) of the first external electrode 3 and the surface (second electrode surface 25) of the second external electrode 4. The concave-convex structure 26 includes recesses 27 recessed toward the first main surface 5 and protrusions 28 protruding from the recesses 27. The recesses 27 may be formed in a lattice, mesh, line, or dot pattern. In this embodiment, the recesses 27 are formed in a mesh pattern.

[0016] The protrusions 28 include a plurality of protrusions 28 defined by recesses 27. The plurality of protrusions 28 are formed at the center and peripheral edges of each electrode surface 24, 25. Each protrusion 28 preferably has a flat outer surface. The outer surface of each protrusion 28 is preferably formed parallel to the first main surface 5. The planar shape of each protrusion 28 is not limited to a specific shape. Each protrusion 28 may have a polygonal shape, such as a triangular, rectangular, pentagonal, or hexagonal shape, in plan view. Each protrusion 28 may also have a circular or elliptical shape. In this embodiment, each electrode surface 24, 25 has a test protrusion 29 having a relatively large planar area. The test protrusion 29 is preferably formed at the center of each electrode surface 24, 25. The central test protrusion 29 has a planar area greater than that of the peripheral protrusions 28. The test protrusion 29 is used as a contact portion against which the tip of a probe contacts when testing the electrical characteristics of the chip component 1. The inspection protrusions 29 may be formed on the periphery of each of the electrode surfaces 24, 25 instead of at the center of each of the electrode surfaces 24, 25. [Exploded view of chip part 1] Fig. 3 is a schematic exploded view of the chip component 1. Fig. 3 shows only the main elements that make up the chip component 1. Therefore, the chip component 1 may include elements other than the components shown in Fig. 3.

[0017] As shown in FIG. 3, the chip component 1 includes a substrate 2, a capacitor structure 30, an electrode film 31, a first external electrode 3, and a second external electrode 4.

[0018] A capacitor section 32 is formed on the first main surface 5 of the substrate 2. The capacitor section 32 is a region of the substrate 2 where the main part of the capacitor structure 30 (a portion having a three-layer structure of electrode-capacitive film-electrode that functions as a passive element) is formed, and may also be referred to as a capacitor region. In FIG. 3, the capacitor section 32 is shown as a closed region surrounded by a two-dot chain line, and is clearly distinguished from the portion of the first main surface 5 other than the capacitor section. However, the capacitor section 32 may also be defined as a portion that is not clearly defined on the first main surface 5 in a plan view, for example, and that can be visually recognized as the portion where the main part of the capacitor structure 30 is located.

[0019] The capacitor portion 32 is formed approximately in the center of the first main surface 5. For example, it may be formed in a region spaced a distance inward in the first direction X from each of the first end 11 and the second end 12 of the substrate 2. As shown in FIG. 3 , the capacitor portion 32 may be defined as a rectangular region having a longitudinal direction along the first direction X. The capacitor portion 32 may include a plurality of capacitor portions 32. The plurality of capacitor portions 32 may be arranged adjacent to each other. In this embodiment, the capacitor portion 32 includes a first capacitor portion 321 and a second capacitor portion 322 that are adjacent to each other in the first direction X.

[0020] In addition to the capacitor section 32, a functional element section 33 including functional elements other than capacitors is formed on the first main surface 5 of the substrate 2. The functional element section 33 is a region of the substrate 2 in which functional elements such as diodes, resistors, and inductors are formed, and may also be referred to as a functional element region. In this embodiment, since the functional element section 33 is a portion that mainly includes diodes, the functional element section 33 may also be referred to as a diode section 33. Hereinafter, the functional element section will be described as the diode section 33.

[0021] 3, the diode section 33 is shown as a closed region surrounded by a two-dot chain line, and is clearly distinguished from the portions of the first main surface 5 other than the diode section 33. However, the diode section 33 may also be defined as a portion that is not clearly defined on the first main surface 5 in a plan view, for example, and that can be visually recognized as a portion where a diode is arranged.

[0022] The diode section 33 is formed at both ends of the first main surface 5 so as to sandwich the capacitor section 32 in a plan view. As shown in FIG. 3 , the diode section 33 may be formed at the first end 11 and the second end 12 of the substrate 2, or at both ends of the substrate 2 in the second direction Y (ends close to the third side surface 9 and the fourth side surface 10, respectively). As shown in FIG. 3 , the diode section 33 may be defined as a rectangular region having a longitudinal direction along the second direction Y. The diode section 33 may include multiple diode sections 33. The multiple diode sections 33 may be arranged apart from each other via the capacitor section 32. In this embodiment, the diode section 33 includes a first diode section 331 (first functional element section) and a second diode section 332 (second functional element section). The first diode section 331 is formed in a region between the capacitor section 32 and the first side surface 7 of the substrate 2. The second diode section 332 is formed in a region between the capacitor section 32 and the second side surface 8 of the substrate 2. The first diode portion 331 and the second diode portion 332 extend along the first side surface 7 and the second side surface 8, respectively, and have, for example, approximately the same length as the length of the capacitor portion 32 in the second direction Y.

[0023] The capacitor structure 30 is formed on the first main surface 5 of the substrate 2 and covers the capacitor portion 32. The capacitor structure 30 includes a lower electrode 34, a capacitance film 35, and an upper electrode 36, and has a structure in which the capacitance film 35 is sandwiched between the upper electrode 36 and the lower electrode 34 in the vertical direction. The lower electrode 34, the capacitance film 35, and the upper electrode 36 may each be formed in a film or plate shape. The lower electrode 34 and the capacitance film 35 have a size (planar size) smaller than the substrate 2 and a size (planar size) larger than the upper electrode 36. A first capacitor contact hole 37 for contacting the lower electrode 34 is formed in the peripheral portion of the capacitance film 35. The electrode film 31 is formed on the capacitor structure 30 and covers the capacitor structure 30. The electrode film 31 may be formed in the shape of a conductive film. The electrode film 31 includes a first electrode film 38 and a second electrode film 39.

[0024] The first electrode film 38 has contact portions with the lower electrode 34 and the first diode portion 331. The first electrode film 38 electrically connects the first external electrode 3 to the lower electrode 34 and the first diode portion 331. In FIG. 3, a lower contact portion 40 and a first diode contact portion 41 are shown as the contact portions of the first electrode film 38 with the lower electrode 34 and the first diode portion 331, respectively. For clarity, in FIG. 3, the entire first electrode film 38 is painted gray, and the lower contact portion 40 and the first diode contact portion 41, which are contact portions of the first electrode film 38, are also shown as gray-painted areas.

[0025] The second electrode film 39 has contact portions with the upper electrode 36 and the second diode portion 332. The second electrode film 39 electrically connects the second external electrode 4 to the upper electrode 36 and the second diode portion 332. In FIG. 3, an upper contact portion 42 and a second diode contact portion 43 are shown as the contact portions of the second electrode film 39 with the upper electrode 36 and the second diode portion 332, respectively. For clarity, in FIG. 3, the entire second electrode film 39 is hatched, and the upper contact portion 42 and the second diode contact portion 43, which are contact portions of the second electrode film 39, are also shown by hatched areas.

[0026] The first electrode film 38 and the second electrode film 39 are formed, for example, by dividing the electrode film 31, which has approximately the same shape as the first main surface 5 of the substrate 2 in a plan view, along dividing lines 44 of a predetermined pattern. Therefore, by combining the first electrode film 38 and the second electrode film 39 so that they face each other via the dividing lines 44, the first electrode film 38 and the second electrode film 39 are formed as a whole in a generally rectangular shape in a plan view.

[0027] The first electrode film 38 integrally includes a first base portion 45 and a pair of first extension portions 46 .

[0028] The first base portion 45 is a portion of the first electrode film 38 to which the first external electrode 3 is connected. In Fig. 3, a first external contact portion 47 (an area surrounded by a two-dot chain line) is shown as a contact portion of the first external electrode 3 with the first electrode film 38. The first base portion 45 is formed in a substantially rectangular shape with its longitudinal direction aligned with the second direction Y.

[0029] The pair of first extension portions 46 may branch out and extend from the first base portion 45. For example, the pair of first extension portions 46 may extend from one end and the other end of the first base portion 45 in the longitudinal direction along the first direction X (along the third side surface 9 and the fourth side surface 10). The pair of first extension portions 46 may extend from the first base portion 45 in the same direction in the first direction X and may have strip or rectangular shapes that are parallel to each other. As a result, the first electrode film 38 is formed in a substantially U-shape. In this embodiment, both the first base portion 45 and the pair of first extension portions 46 form the lower contact portion 40. Therefore, like the first electrode film 38, the lower contact portion 40 is also formed in a substantially U-shape.

[0030] In the first electrode film 38, the region surrounded on three sides by the first base portion 45 and the pair of first extension portions 46 may be referred to as an accepting region 48 that accepts a part of the second electrode film 39 in the first direction X. Note that the first base portion 45 and the first extension portions 46 of the first electrode film 38 may also be referred to as a first portion and a second portion of the first electrode film 38 using their ordinal numbers.

[0031] The second electrode film 39 integrally includes a second base portion 49 and a second extension portion 50.

[0032] The second base portion 49 is a portion of the second electrode film 39 to which the second external electrode 4 is connected. In Fig. 3, a second external contact portion 51 (an area surrounded by a two-dot chain line) is shown as a contact portion of the second external electrode 4 with the second electrode film 39. The second base portion 49 is formed in a substantially rectangular shape with its longitudinal direction aligned with the second direction Y.

[0033] The second extension portion 50 has a step 53 with respect to a pair of peripheral edges 52 of the second base portion 49 along the first direction X, and extends from the second base portion 49 toward the first base portion 45 of the first electrode film 38. One step 53 is formed on each side of the second extension portion 50 in the second direction Y. The second extension portion 50 has, for example, a rectangular shape and fits within the receiving region 48 via the parting line 44. As a result, the second extension portion 50 is surrounded on three sides by the first base portion 45 of the first electrode film 38 and the pair of first extension portions 46. The second base portion 49 and second extension portion 50 of the second electrode film 39 may also be referred to as a third portion and a fourth portion of the second electrode film 39 using ordinal numbers, respectively.

[0034] Meanwhile, focusing on the pair of first extending portions 46, the pair of first extending portions 46 extend from the first base portion 45 into the pair of steps 53, sandwiching the second extending portion 50 at a distance in the second direction Y. The tip ends of the pair of first extending portions 46 face the second base portion 49 across the parting line 44.

[0035] The first external electrode 3 and the second external electrode 4 are formed on the electrode film 31. The first external electrode 3 has a first external contact portion 47 and is connected to the first electrode film 38 via the first external contact portion 47. The second external electrode 4 has a second external contact portion 51 and is connected to the second electrode film 39 via the second external contact portion 51. [Planar structure of chip component 1] 4 to 6, the planar structure of the substrate 2, capacitor section 32, diode section 33, lower electrode 34, capacitance film 35, upper electrode 36, first electrode film 38, second electrode film 39, lower contact section 40, first diode contact section 41, upper contact section 42, second diode contact section 43, first external electrode 3, and second external electrode 4 in Fig. 3 will be described. The planar structure of these components can be explained taking into account their relative positions, overlapping relationships, etc. in a planar view.

[0036] FIG. 4 is a schematic plan view of the chip component 1. First, referring to FIG. 4, the planar structures of the lower electrode 34, the capacitive film 35, and the upper electrode 36 will be described in detail. For clarity, the first external electrode 3 and the second external electrode 4 are shown in perspective with dashed lines in FIG. 4. Also, FIG. 4 shows extracted components necessary for the description and their reference numerals.

[0037] A capacitor portion 32 is formed at approximately the center of the first main surface 5 of the substrate 2. The portion of the substrate 2 other than the capacitor portion 32 may be defined as a substrate main body portion 54. In this embodiment, the substrate main body portion 54 is a substantially quadrangular ring-shaped (closed ring-shaped) portion that surrounds the capacitor portion 32 in a plan view. The substrate main body portion 54 is frame-shaped and surrounds the capacitor portion 32, and may also be referred to as a frame portion of the substrate 2.

[0038] The capacitor portion 32 may include a first overlapping portion 55 overlapping the first external electrode 3, a second overlapping portion 56 overlapping the second external electrode 4, and an intermediate portion 57 between the first external electrode 3 and the second external electrode 4. For example, if the first external electrode 3 has a first outer peripheral edge 58 along the first long side 15 and a first inner peripheral edge 59 along the second long side 16, the first overlapping portion 55 may overlap the first inner peripheral edge 59. The first overlapping portion 55 has an edge in the first direction X below the first inner peripheral edge 59. Therefore, the first overlapping portion 55 may also be referred to as a first peripheral edge of the capacitor portion 32 in the first direction X.

[0039] For example, when the second external electrode 4 has a second outer peripheral edge 60 along the third long side 20 and a second inner peripheral edge 61 along the fourth long side 21, the second overlapping portion 56 may overlap the second inner peripheral edge 61. The second overlapping portion 56 has an edge in the first direction X below the second inner peripheral edge 61. Therefore, the second overlapping portion 56 may also be referred to as a second peripheral edge of the capacitor portion 32 in the first direction X.

[0040] The diode section 33 is formed at each of the first end 11 and the second end 12 of the substrate main body section 54. The diode section 33 may be formed at a position away from the capacitor section 32 in the opposing direction of the first external electrode 3 and the second external electrode 4 (first direction X in this embodiment). More specifically, the first diode section 331 is formed so as to overlap the first outer peripheral edge section 58 of the first external electrode 3, and the second diode section 332 is formed so as to overlap the second outer peripheral edge section 60 of the second external electrode 4. The first diode section 331 and the second diode section 332 are formed in strip shapes extending along the first outer peripheral edge section 58 and the second outer peripheral edge section 60, respectively.

[0041] The lower electrode 34 and the capacitive film 35 have the same shape in a plan view. In FIG. 4, the hatched rectangular area that covers the capacitor portion 32 and includes a portion surrounding the capacitor portion 32 is the lower electrode 34 and the capacitive film 35. In FIG. 4, the layered structure of the lower electrode 34 and the capacitive film 35 is shown as a single hatched area. Therefore, in FIG. 4, the portion where the reference symbols of the components of the lower electrode 34 and the capacitive film 35 are shown together is the portion where the components of the capacitive film 35 are layered on the components of the lower electrode 34.

[0042] The lower electrode 34 includes a first main body portion 62 and a first peripheral portion 63. The first main body portion 62 is formed within the capacitor portion 32. The first peripheral portion 63 is formed integrally with the first main body portion 62 on the substrate main body portion 54 (frame portion of the substrate 2) around the capacitor portion 32. The first peripheral portion 63 is a portion that is drawn out from the first main body portion 62 to the periphery of the capacitor portion 32, and may also be referred to as a drawn-out portion of the lower electrode 34.

[0043] The first surrounding portion 63 may further include multiple portions separately defined based on a relative positional relationship with the capacitor portion 32. For example, the first surrounding portion 63 may include a first portion 64 drawn from the first body portion 62 to both sides in the second direction Y with respect to the capacitor portion 32 and formed in a region between the first external electrode 3 and the second external electrode 4. The first surrounding portion 63 may include a second portion 65 drawn from the first body portion 62 to the first external electrode 3 side in the first direction X with respect to the capacitor portion 32 and formed in a region below the first external electrode 3 (region overlapping with the first external electrode 3). The first surrounding portion 63 may include a third portion 66 drawn from the first body portion 62 to the second external electrode 4 side in the first direction X with respect to the capacitor portion 32 and formed in a region below the second external electrode 4 (region overlapping with the second external electrode 4). The capacitor portion 32 is sandwiched between a pair of first portions 64 in the second direction Y, and between a second portion 65 and a third portion 66 in the first direction X. The pair of first portions 64, second portion 65, and third portion 66 are continuous with each other along the circumferential direction of the capacitor portion 32. As a result, the capacitor portion 32 is surrounded by the first surrounding portion 63 as a closed region.

[0044] The capacitive film 35 includes a second body portion 67 and a second peripheral portion 68. The second body portion 67 is formed within the capacitor portion 32. The second peripheral portion 68 is integrally formed with the second body portion 67 on the first peripheral portion 63 around the capacitor portion 32. The second peripheral portion 68 is a portion extending from the second body portion 67 to the periphery of the capacitor portion 32, and may also be referred to as an extended portion of the capacitive film 35. The second peripheral portion 68 of the capacitive film 35 entirely covers the pair of first portions 64, second portions 65, and third portions 66 of the first peripheral portion 63 of the lower electrode 34. Therefore, the second peripheral portion 68 of the capacitive film 35 may include a pair of first portions, second portions, and third portions corresponding to the pair of first portions 64, second portions 65, and third portions 66 of the first peripheral portion 63 of the lower electrode 34, respectively. Furthermore, the second peripheral portion 68 of the capacitive film 35 covers the first peripheral portion 63 of the lower electrode 34 around the capacitor portion 32, and therefore may be simply referred to as a covering portion.

[0045] The upper electrode 36 is formed in a shape that covers the capacitor portion 32. In this embodiment, the upper electrode 36 is formed in a rectangular shape that covers the entire capacitor portion 32. The upper electrode 36 integrally includes a main body portion 69 and a peripheral edge portion 70. The main body portion 69 may be a portion that faces the capacitor portion 32 in the third direction Z.

[0046] The peripheral edge portion 70 may be a portion that extends from the main body portion 69 to the periphery of the capacitor portion 32 and surrounds the capacitor portion 32. In this embodiment, the first peripheral portion 63 and the second peripheral portion 68 are formed outside the peripheral edge portion 70 of the upper electrode 36 in a plan view and have a shape that further surrounds the peripheral edge portion 70 that surrounds the capacitor portion 32. As a result, the lower electrode 34 and the capacitive film 35 have a common edge 71 that is located outside an edge 72 of the upper electrode 36. As shown in FIG. 4 , the edge 72 is the outer edge of the peripheral edge portion 70 of the upper electrode 36 and is formed in a rectangular ring shape. The edge 71 is the outer edge of the first peripheral portion 63 of the lower electrode 34 and the second peripheral portion 68 of the capacitive film 35 and is formed in a rectangular ring shape that surrounds the edge 72. The edge 71 and the edge 72 may also be referred to as the end face of the lower electrode 34 (capacitive film 35) and the end face of the upper electrode 36, respectively.

[0047] Fig. 5 is a schematic plan view of the chip component 1. Next, the planar structures of the lower contact portion 40, the first diode contact portion 41, the upper contact portion 42, and the second diode contact portion 43 will be described in detail with reference to Fig. 5. For clarity, Fig. 5 shows only the components necessary for the description and their reference numerals.

[0048] The lower contact portion 40 is a contact portion of the first electrode film 38 with the lower electrode 34 and is formed in the first peripheral portion 63 of the lower electrode 34. The lower contact portion 40 may be formed in an open ring shape, with one side of the capacitor portion 32 open and the other side closed in the first direction X, surrounding the capacitor portion 32. Here, the "shape surrounding the capacitor portion 32" may be a closed ring shape having a closed region therein that accommodates the entire capacitor portion 32, or an open ring shape that defines a housing region 73 that accommodates most of the capacitor portion 32 (e.g., more than 50% in terms of area ratio) and has a partially open ring shape, as shown in FIG. 5. In this embodiment, the lower contact portion 40 is formed in a substantially U-shape in the first direction X, with the second external electrode 4 side open relative to the capacitor portion 32. Furthermore, when the object to be surrounded (the capacitor portion 32 in FIG. 5) is rectangular in plan view, the lower contact portion 40 may be defined as surrounding the capacitor portion 32 if the lower contact portion 40 is formed adjacent to at least three sides of the object. This definition may be applied generally to the term "surrounded" in this disclosure.

[0049] The lower contact portion 40 may include a first lower contact portion 74 and a second lower contact portion 75 in FIG.

[0050] The first lower contact portions 74 are formed one by one in the pair of first portions 64 of the first peripheral portion 63. The pair of first lower contact portions 74 are each formed in a strip shape extending parallel to the third side surface 9 and the fourth side surface 10 of the substrate 2 in the first direction X. The pair of first lower contact portions 74 sandwich the capacitor portion 32 in the second direction Y.

[0051] The second lower contact portion 75 is formed in the second portion 65 of the first peripheral portion 63 in the region below the first external electrode 3. The second lower contact portion 75 is formed in a strip shape extending parallel to the first side surface 7 of the substrate 2 in the second direction Y. In this embodiment, the pair of first lower contact portions 74 are formed integrally with the second lower contact portion 75 and extend continuously from one end portion 76 and the other end portion 77 in the longitudinal direction of the second lower contact portion 75 toward the second external electrode 4. As a result, the lower contact portion 40 in FIG. 5 is formed in a substantially U-shape as a whole. In this way, the first peripheral portion 63 of the lower electrode 34 is the portion where the lower contact portion 40 is formed, and therefore may be referred to as a first contact region (lower contact region) in the capacitor structure 30. The lower contact portion 40 may be referred to as a first capacitor contact portion connected to the first contact region.

[0052] The upper contact portion 42 is a contact portion of the second electrode film 39 with the upper electrode 36, and is formed in the main portion 69 of the upper electrode 36. As described above, the main portion 69 of the upper electrode 36 is the portion where the upper contact portion 42 is formed, and therefore may be referred to as a second contact region (upper contact region) in the capacitor structure 30. The upper contact portion 42 may also be referred to as a second capacitor contact portion connected to the second contact region. The upper contact portion 42 is sandwiched between a pair of first lower contact portions 74 in the second direction Y. The upper contact portion 42 is formed in a rectangular shape that covers almost the entire capacitor portion 32. Here, "covering almost the entire capacitor portion 32" may mean, for example, that the upper contact portion 42 is formed in a rectangular shape having four sides extending parallel to the four sides of the rectangular capacitor portion 32 in a plan view and having a planar size slightly smaller than that of the capacitor portion 32, so that most of the capacitor portion 32 (for example, approximately 70% or more in terms of area) is covered by the upper contact portion 42.

[0053] In this embodiment, like the capacitor portion 32, the upper contact portion 42 is formed in a rectangular shape with its longitudinal direction aligned with the first direction X. The upper contact portion 42 extends in the second direction Y so as to straddle the interior and exterior of the accommodation region 73 of the lower contact portion 40. The upper contact portion 42 covers the entire capacitor portion 32 exposed in the intermediate portion 57 and also covers the capacitor portion 32 in the second overlap portion 56. Meanwhile, the upper contact portion 42 is formed to avoid the capacitor portion 32 in the first overlap portion 55. As a result, the upper contact portion 42 faces the second inner peripheral portion 61 of the second external electrode 4 in the third direction Z, but does not face the first external electrode 3. The upper contact portion 42 also has a first end portion 78 on the first external electrode 3 side and a second end portion 79 on the second external electrode 4 side in the first direction X, with the second end portion 79 overlapping the second external electrode 4. The first end 78 of the upper contact portion 42 is formed at a position away from the first external electrode 3 towards the second external electrode 4 in the first direction X.

[0054] The first diode contact portion 41 is a contact portion of the first electrode film 38 with the first diode portion 331. The first diode contact portion 41 overlaps the first external electrode 3. The first diode contact portion 41 may be formed in a region below the first external electrode 3 (in this embodiment, the first outer peripheral edge portion 58). The first diode contact portion 41 extends along the first side surface 7 of the substrate 2 in the first direction X and is formed in a strip shape parallel to the first side surface 7.

[0055] The second diode contact portion 43 is a contact portion of the second electrode film 39 with the second diode portion 332. The second diode contact portion 43 overlaps the second external electrode 4. The second diode contact portion 43 may be formed in a region below the second external electrode 4 (in this embodiment, the second outer peripheral edge portion 60). The second diode contact portion 43 extends along the second side surface 8 of the substrate 2 in the first direction X and is formed in a strip shape parallel to the second side surface 8.

[0056] Fig. 6 is a schematic plan view of the chip component 1. Next, the planar structures of the first electrode film 38 and the second electrode film 39 will be mainly described in detail with reference to Fig. 6. For clarity, Fig. 6 shows only extracted components necessary for the description and their reference numerals.

[0057] The first electrode film 38 surrounds the capacitor portion 32 and is formed in an open ring shape with a portion open on the side of the second external electrode 4. As described above, the first electrode film 38 integrally includes the first base portion 45 and a pair of first extension portions 46.

[0058] The first base portion 45 is formed in a substantially rectangular shape with its longitudinal direction aligned with the second direction Y, and is formed below the first external electrode 3. As a result, the first base portion 45 overlaps the first external electrode 3. The first base portion 45 is formed outward of the first external electrode 3, and has a first peripheral edge portion 80 that surrounds the first external electrode 3 in a plan view. In this embodiment, the first peripheral edge portion 80 is formed adjacent to the outside of the first long side 15, the first short side 17, and the second short side 18 of the first external electrode 3. The first base portion 45 forms the second lower contact portion 75 and the first diode contact portion 41.

[0059] The pair of first extending portions 46 extend from the first base portion 45 along the third side surface 9 and the fourth side surface 10 of the substrate 2. The pair of first extending portions 46 form first lower contact portions 74.

[0060] As described above, the second electrode film 39 integrally includes the second base portion 49 and the second extension portion 50.

[0061] The second base portion 49 is formed in a substantially rectangular shape with its longitudinal direction aligned with the second direction Y, and is formed below the second external electrode 4. As a result, the second base portion 49 overlaps the second external electrode 4. The second base portion 49 is formed outward of the second external electrode 4, and has a second peripheral edge portion 81 that surrounds the second external electrode 4 in a plan view. In this embodiment, the second peripheral edge portion 81 is formed adjacent to the outside of the third long side 20, the third short side 22, and the fourth short side 23 of the second external electrode 4. The second base portion 49 forms the second end portion 79 of the upper contact portion 42 and the second diode contact portion 43.

[0062] The second extension portion 50 is formed in a rectangular shape extending from the second base portion 49 toward the first base portion 45 of the first electrode film 38. The second extension portion 50 forms a majority of the upper contact portion 42. The second extension portion 50 is formed outward of the upper contact portion 42 and has a peripheral edge portion 82 that surrounds the upper contact portion 42 in a plan view. The peripheral edge portion 82 of the second extension portion 50 may include a pair of first peripheral edge portions 83 that extend along the pair of first lower contact portions 74 in the first direction X, and a second peripheral edge portion 84 that extends along the second lower contact portion 75 in the second direction Y. The first peripheral edge portion 83 and the second peripheral edge portion 84 may each be formed in a band shape whose longitudinal directions are along the first direction X and the second direction Y. The first peripheral edge portion 83 may be formed in the region between the first external electrode 3 and the second external electrode 4, and the second peripheral edge portion 84 may be formed in the region below the first external electrode 3. Therefore, the second peripheral edge portion 84 may overlap the first external electrode 3. Furthermore, when the width W2 of the first peripheral edge portion 83 is compared with the width W3 of the second peripheral edge portion 84, the width W3 may be greater than the width W2. [Structure of capacitor section 32] FIG. 7 is a schematic plan view of the chip component 1. FIG. 8 is an enlarged view of a main portion of the chip component 1 of FIG. 7. FIGS. 9 and 10 are schematic cross-sectional views of the chip component 1. For clarity, in FIG. 7, the trench 107 is hatched, and the first external electrode 3 and the second external electrode 4 are shown in perspective with dashed lines. Also, in FIG. 7, components necessary for explanation and their reference numerals are extracted and shown. Also, FIGS. 9 and 10 are diagrams that schematically show the layer structure on the first main surface 5 of the chip component 1, and do not show a cross section taken along a specific cutting line in FIG. 7. However, FIG. 9 is a diagram for explaining the cross-sectional structure of the capacitor section 32 of FIG. 7, and FIG. 10 is a diagram for explaining the cross-sectional structure of the periphery of the capacitor section 32.

[0063] 7, chip component 1 is a composite element in which capacitor section 32 and diode section 33 are mounted on a common substrate 2. Substrate 2 may be a semiconductor substrate such as a silicon plate, or may be an insulating substrate such as a ceramic substrate or a glass substrate. The thickness of substrate 2 may be, for example, 200 μm or more and 600 μm or less.

[0064] In the capacitor section 32, a portion of the substrate 2 on the first main surface 5 side is selectively removed, thereby forming a plurality of wall sections 85 using a portion of the substrate 2. Each of the plurality of wall sections 85 has a longitudinal direction and is formed in a striped pattern in plan view. The plurality of wall sections 85 are formed over the entire capacitor section 32. As a result, the plurality of wall sections 85 overlap the first external electrode 3 and the second external electrode 4 in plan view.

[0065] In this embodiment, the capacitor section 32 includes a plurality of capacitor sections whose wall sections 85 have different longitudinal directions. In FIG. 7 , the capacitor section 32 includes a first capacitor section 321 whose wall sections 85 have a first longitudinal direction D1 and a second capacitor section 322 whose wall sections 85 have a second longitudinal direction D2. In this embodiment, the first longitudinal direction D1 and the second longitudinal direction D2 are perpendicular to each other. The first longitudinal direction D1 may be parallel to the second direction Y, and the second longitudinal direction D2 may be parallel to the first direction X. Furthermore, the first longitudinal direction D1 may be parallel to one pair of side surfaces of the substrate 2 (in this embodiment, the first side surface 7 and the second side surface 8), and the second longitudinal direction D2 may be parallel to the other pair of side surfaces of the substrate 2 (in this embodiment, the third side surface 9 and the fourth side surface 10).

[0066] The first capacitor portion 321 and the second capacitor portion 322 are formed one by one and are formed adjacent to each other. In this embodiment, the first capacitor portion 321 and the second capacitor portion 322 are formed adjacent to each other in the first direction X. More specifically, the first capacitor portion 321 is formed across the first overlap portion 55 and the intermediate portion 57, and the second capacitor portion 322 is formed across the second overlap portion 56 and the intermediate portion 57. A boundary portion 86 between the first capacitor portion 321 and the second capacitor portion 322 is formed in the intermediate portion 57.

[0067] In the first capacitor portion 321, the multiple wall portions 85 are arranged at intervals from one another in a direction intersecting the first longitudinal direction D1. In the second capacitor portion 322, the multiple wall portions 85 are arranged at intervals from one another in a direction intersecting the second longitudinal direction D2. As a result, in each of the first capacitor portion 321 and the second capacitor portion 322, the multiple wall portions 85 are formed in a striped pattern in plan view.

[0068] As described above, the substrate main body portion 54 surrounds the capacitor portion 32. The substrate main body portion 54 may surround the first capacitor portion 321 and the second capacitor portion 322 individually. Therefore, the substrate main body portion 54 may include a boundary portion 86 between the first capacitor portion 321 and the second capacitor portion 322. One end portion 100 and the other end portion 101 of each wall portion 85 in the longitudinal directions D1, D2 are connected to the substrate main body portion 54, including the boundary portion 86. As a result, the wall portions 85 are supported at both ends by the substrate main body portion 54 from the sides. A portion of the substrate main body portion 54 near the connection portion with the wall portions 85 may be defined as a support portion 87.

[0069] The first diode section 331 includes a plurality of first diodes 88. The plurality of first diodes 88 are arranged in a row at intervals along the first side surface 7 of the substrate 2. The second diode section 332 includes a plurality of second diodes 89. The plurality of second diodes 89 are arranged in a row at intervals along the second side surface 8 of the substrate 2.

[0070] 8 to 10, the structure of the wall portion 85, the structures of the first diode 88 and the second diode 89, and the cross-sectional structure of the chip component 1 will be specifically described. Note that the structure of the first capacitor portion 321 will be described with reference to Fig. 8, but the structure of the first capacitor portion 321 can be applied as the structure of the second capacitor portion 322, except that the longitudinal direction of the wall portion 85 is different.

[0071] Referring to FIG. 8, the wall portion 85 is formed of a plurality of pillar units 90. Here, "the wall portion 85 is formed of a plurality of pillar units 90" may mean, for example, that pillar-like objects (pillar units 90 in this embodiment) having the same shape are connected to form a line-shaped wall portion 85 in a plan view. In other words, the wall portion 85 itself is not formed in a pillar shape, but as shown by the dashed lines in FIG. 8, the wall portion 85 can be divided into pillar units 90 having the same shape by imaginary lines. Therefore, at the boundary between the protrusions 92 of the pillar units 90 adjacent to each other, the material portion of the substrate 2 (semiconductor portion in this embodiment) is continuous. As a result, the adjacent protrusions 92 are integrally connected to each other via the material portion of the substrate 2.

[0072] Each pillar unit 90 includes, in a plan view, a central portion 91 and three protruding portions 92 extending in three different directions from the central portion 91. The wall portion 85 is formed by connecting the protruding portions 92 of adjacent pillar units 90. More specifically, in each pillar unit 90, each protruding portion 92 forms angles θ1, θ2, θ3 of 120° with the adjacent protruding portion 92, and intersects with the adjacent protruding portion 92 at the central portion 91.

[0073] In this embodiment, the angles θ1, θ2, and θ3 are all equal at 120°, but they may be different from one another. For example, the angle θ3 between a second convex portion 98 and a third convex portion 99 (described later) may be 160°, and the angle θ1 between the first convex portion 97 and the second convex portion 98 and the angle θ2 between the first convex portion 97 and the third convex portion 99 may both be 100°.

[0074] In this embodiment, among the plurality of wall portions 85, a pair of adjacent wall portions 85 may be referred to as a first wall portion 93 and a second wall portion 94.

[0075] The first wall portion 93 includes a first main portion 95 extending in the second direction Y and connected to the support portion 87, and first branch portions 96 extending in the first direction X and arranged in a comb-teeth shape along the second direction Y. Each first branch portion 96 is formed by a first convex portion 97 of the convex portions 92 of each column unit 90 of the first wall portion 93.

[0076] On the other hand, the convex portion 92 of each pillar unit 90 of the first wall portion 93 includes a second convex portion 98 and a third convex portion 99 in addition to the first convex portion 97. The first main portion 95 is formed by connecting the second convex portions 98 and the third convex portions 99 of adjacent pillar units 90. That is, in this embodiment, the second convex portions 98 and the third convex portions 99 are alternately arranged along the second direction Y, and as a whole, a first main portion 95 having a wavy (zigzag) shape in a plan view is formed.

[0077] The protrusions 92 forming one end 100 and the other end 101 (not shown in FIG. 8) of the first main portion 95 are connected to the support portion 87. More specifically, the material portion of the substrate 2 (in this embodiment, the semiconductor portion) is continuous at the boundary between the support portion 87 and the first main portion 95. As a result, the support portion 87 and the first main portion 95 are integrally connected via the material portion of the substrate 2.

[0078] The second wall portion 94 includes a second main portion 102 extending in the second direction Y and connected to the support portion 87, and comb-tooth-shaped second branch portions 103 extending toward the first main portion 95 and engaging with comb-tooth-shaped first branch portions 96. Each second branch portion 103 is formed by a fourth convex portion 104 among the convex portions 92 of each pillar unit 90 of the second wall portion 94.

[0079] On the other hand, the convex portion 92 of each pillar unit 90 of the second wall portion 94 includes a fifth convex portion 105 and a sixth convex portion 106 in addition to the fourth convex portion 104. The second main portion 102 is formed by connecting the fifth convex portions 105 and the sixth convex portions 106 of adjacent pillar units 90. That is, in this embodiment, the fifth convex portions 105 and the sixth convex portions 106 are alternately arranged along the second direction Y, and as a whole, a wave-shaped (zigzag) second main portion 102 is formed in a plan view.

[0080] The protrusions 92 that form one end 100 and the other end 101 (not shown in FIG. 8) of the second main portion 102 are connected to the support portion 87. More specifically, the material portion of the substrate 2 (in this embodiment, the semiconductor portion) is continuous at the boundary between the support portion 87 and the second main portion 102. As a result, the support portion 87 and the second main portion 102 are integrally connected via the material portion of the substrate 2.

[0081] In this embodiment, a pair of walls 85, each made up of a first wall 93 and a second wall 94 that interlock with each other like comb teeth, is formed in sequence along the first direction X. That is, the first wall 93 and the second wall 94 are alternately arranged along the first direction X. A trench 107 is formed between the first wall 93 and the second wall 94. The trench 107 is a portion where material of the substrate 2 has been removed, and is a portion surrounded by the wall 85 and the support portion 87. A width W4 of the trench 107 may be, for example, not less than 2 μm and not more than 8 μm.

[0082] In this embodiment, the trench 107 may include a first trench 108 and a second trench 109. The first trench 108 may be formed between a first wall portion 93 and a second wall portion 94 that interlock with each other like comb teeth, and may be formed in a zigzag shape. The second trench 109 may be formed between the first wall portion 93 and the second wall portion 94 that face each other across a surface opposite to the comb teeth, and may be formed in a wave (zigzag) shape.

[0083] In this embodiment, as shown in FIG. 9, the ratio (W5 / H) of the width W5 of the protrusion 92 of the pillar unit 90 to the height H of the wall portion 85 (depth of the trench 107) may be 2 / 50 or more and 2 / 100 or less. As shown in FIG. 8, the width W5 of the protrusion 92 may be defined as the width in a direction perpendicular to the extension direction from the central portion 91 of each protrusion 92. Specifically, the width W5 of the protrusion 92 of the pillar unit 90 may be, for example, 2 μm or more and 8 μm or less. On the other hand, the height H of the wall portion 85 may be 50 μm or more and 400 μm or less.

[0084] 9 and 10 , a p-type base region 110 is formed in the substrate 2 so as to be exposed from the first main surface 5 of the substrate 2. In this embodiment, p-type impurities are introduced into the entire thickness of the substrate 2, from the first main surface 5 to the second main surface 6 of the substrate 2. As a result, the base region 110 is formed throughout the entire substrate 2, and the substrate 2 can be considered a p-type substrate. The introduction of the p-type impurities may set the resistivity of the substrate 2 to approximately 5 mΩ·cm. This base region 110 is not selectively formed in the diode portion 33, but is formed throughout the entire substrate 2, including the capacitor portion 32. Therefore, the wall portion 85 of the capacitor portion 32 and the substrate main body portion 54 are formed of the p-type base region 110.

[0085] 7 to 9, in the first diode portion 331, a plurality of first impurity regions 111 (six in FIG. 7) are formed in a surface portion of the base region 110. The first impurity regions 111 are n-type impurity regions. As shown in FIG. 7, the plurality of first impurity regions 111 are arranged at intervals in the second direction Y (direction along the first side surface 7 of the substrate 2). In the second diode portion 332, a plurality of second impurity regions 112 (six in FIG. 7) are formed in a surface portion of the base region 110. The second impurity regions 112 are n-type impurity regions. As shown in FIG. 7, the plurality of second impurity regions 112 are arranged at intervals in the second direction Y (direction along the second side surface 8 of the substrate 2).

[0086] The first impurity region 111 and the second impurity region 112 may be formed to the same depth and with the same n-type impurity concentration. The n-type impurity concentration of each of the first impurity region 111 and the second impurity region 112 may be, for example, 1.0×10 19 cm -3 Over 1.0 x 10 21 cm -3The first impurity region 111 and the second impurity region 112 are both formed to have the same shape and the same area in the plan view shown in Fig. 7. The first impurity region 111 and the second impurity region 112 extend in the second direction Y in the plan view and are formed in a rectangular shape with the four corners removed (rectangle with rounded corners).

[0087] The first impurity region 111 forms a pn junction with the base region 110. The pn junction between the first impurity region 111 and the base region 110 forms a first Zener diode Di1 (first diode 88). On the other hand, the second impurity region 112 forms a pn junction with the base region 110. The pn junction between the second impurity region 112 and the base region 110 forms a second Zener diode Di2 (second diode 89). The first Zener diode Di1 and the second Zener diode Di2 are connected in anti-series via the base region 110. The first impurity region 111 and the second impurity region 112 are formed below the first external electrode 3 and the second external electrode 4, respectively, so as to overlap with the first external electrode 3 and the second external electrode 4 in a plan view. As a result, a depletion layer extending from the pn junction between the first impurity region 111 and the base region 110 does not overlap with a depletion layer extending from the pn junction between the second impurity region 112 and the base region 110. Therefore, a bidirectional Zener diode consisting of the first Zener diode Di1 and the second Zener diode Di2 is formed on the substrate 2.

[0088] 9 and 10, an insulating film 113 is formed on first main surface 5 of substrate 2 so as to cover the entire first main surface 5 of substrate 2. In addition to first main surface 5, which is a flat surface of substrate 2, insulating film 113 is also formed on the entire surfaces (top surface 114 and side surface 115) of wall portion 85. Insulating film 113 has end faces that coincide with side surfaces 7 to 10 of substrate 2. Insulating film 113 may be, for example, a SiO2 film or a SiN film. The thickness of insulating film 113 may be, for example, 20,000 Å or more and 40,000 Å or less (2 μm or more and 4 μm or less).

[0089] In the capacitor section 32, a capacitor structure 30 is formed on this insulating film 113. The capacitor structure 30 is formed to conform to the upper surface 114 and side surface 115 of the wall portion 85. In other words, the capacitor structure 30 has at least a lower electrode 34 that matches the uneven shape of the wall portion 85 in each of the width direction and height direction. In this embodiment, the lower electrode 34 is formed on the insulating film 113 and is formed as an electrode film having one surface in contact with the upper surface 114 and side surface 115 of the wall portion 85 and the other surface equidistant from the upper surface 114 and side surface 115 of the wall portion 85. In other words, the lower electrode 34 has a constant thickness along the upper surface 114 and side surface 115 of the wall portion 85.

[0090] A capacitance film 35 is formed on the lower electrode 34, and an upper electrode 36 is formed on the capacitance film 35. A first main body portion 62 of the lower electrode 34 faces the upper surface 114 and the side surface 115 of the wall portion 85 and includes a counter electrode for the upper electrode 36. A first peripheral portion 63 of the lower electrode 34 extends from the first main body portion 62 onto the first main surface 5 of the substrate 2 and includes a contact portion for the first external electrode 3. The lower electrode 34 may be made of a semiconductor material such as polysilicon, or a metal material containing Cu or Al. In the case of a metal material, it may be made of, for example, Cu, Al, AlSi, or AlCu. The thickness of the lower electrode 34 may be, for example, 1000 Å or more and 3000 Å or less (100 nm or more and 300 nm or less).

[0091] The capacitance film 35 is formed following the shape of the lower electrode 34 and matches the uneven shape of the wall portion 85 in both the width direction and the height direction. The capacitance film 35 includes a second main portion 67 covering the first main portion 62 of the lower electrode 34 and a second peripheral portion 68 covering the first peripheral portion 63 of the lower electrode 34. The first peripheral portion 63 and the second peripheral portion 68 have a common edge 71. The capacitance film 35 may be, for example, a SiO2 film or a SiN film, or a laminated film thereof. For example, it may be a SiO2 / SiN laminated film or a SiO2 / SiN / SiO2 laminated film. The capacitance film 35 may be an ON film or an ONO film, or a laminated film thereof. The capacitance film 35 may also be an insulating film made of a high-dielectric material (high-k material). Examples of high dielectric materials include aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), titanium pentoxide (Ti3O5), hafnium oxide (HfO2), strontium titanate (SrTiO3), barium strontium titanate (Ba x Sr 1-x Examples of the thickness of the capacitor film 35 include perovskite compounds such as TiO3. The thickness of the capacitor film 35 may be, for example, 100 Å to 1000 Å (10 nm to 100 nm).

[0092] The upper electrode 36 is embedded in the trench 107 and formed along the first main surface 5 of the substrate 2. The upper electrode 36 integrally includes a buried portion 116 embedded in the trench 107 and a flat portion 117 connected to the upper end of the buried portion 116 and formed flat along the first main surface 5 of the substrate 2. The flat portion 117 forms a peripheral portion 70 of the upper electrode 36 extending outward from the capacitor portion 32. The flat portion 117 has an edge 72 located inside edges 71 of the lower electrode 34 and the capacitive film 35. The upper electrode 36 may be made of a semiconductor material such as polysilicon, or a metal material containing Cu or Al. In the case of a metal material, it may be made of, for example, Cu, Al, AlSi, or AlCu. The thickness of the upper electrode 36 (flat portion 117) may be, for example, 4,000 Å to 10,000 Å (400 nm to 1,000 nm).

[0093] A first insulating film 118 and a second insulating film 119 are further formed on the substrate 2. The first insulating film 118 covers the insulating film 113, the lower electrode 34, the capacitive film 35, and the upper electrode 36 and is stacked thereon. The second insulating film 119 is stacked on the first insulating film 118. The first insulating film 118 and the second insulating film 119 have end faces that coincide with the side surfaces 7 to 10 of the substrate 2. Therefore, the insulating film 113, the first insulating film 118, and the second insulating film 119 may have stacking interfaces that are exposed on extensions of the side surfaces 7 to 10 of the substrate 2 in the cross-sectional views shown in FIGS. 9 and 10 .

[0094] The first insulating film 118 and the second insulating film 119 are formed with a first capacitor contact hole 37 exposing the first peripheral portion 63 of the lower electrode 34 and a second capacitor contact hole 120 exposing the flat portion 117 in the main body portion 69 of the upper electrode 36. The first capacitor contact hole 37 is also formed in the capacitive film 35.

[0095] Furthermore, a first diode contact hole 121 exposing the first diode portion 331 and a second diode contact hole 122 exposing the second diode portion 332 are formed in the insulating film 113, the first insulating film 118, and the second insulating film 119. Referring to Fig. 7, the first diode contact hole 121 is formed in a strip shape with its longitudinal direction aligned along the second direction Y, and collectively exposes the multiple first diodes 88. The second diode contact hole 122 is formed in a strip shape with its longitudinal direction aligned along the second direction Y, and collectively exposes the multiple second diodes 89.

[0096] 9 and 10, a first electrode film 38 and a second electrode film 39 are formed on the second insulating film 119 with a gap between them.

[0097] 9, a part of the first base portion 45 of the first electrode film 38 is formed in the first diode contact hole 121 as the first diode contact portion 41, and is also formed in the first capacitor contact hole 37 as the second lower contact portion 75 (lower contact portion 40). Referring to Fig. 10, a part of the first extension portion 46 of the first electrode film 38 is formed in the first capacitor contact hole 37 as the first lower contact portion 74 (lower contact portion 40).

[0098] 9, a part of the second base portion 49 of the second electrode film 39 is formed in the second diode contact hole 122 as the second diode contact portion 43. In addition, a part of the second extension portion 50 of the second electrode film 39 is formed in the second capacitor contact hole 120 as the upper contact portion 42.

[0099] Furthermore, a material containing Al may be used as the electrode material for the first electrode film 38 and the second electrode film 39. Examples of such a material include AlCu and AlSiCu, with AlCu being preferred.

[0100] A surface insulating film 123 is further formed on the substrate 2. The surface insulating film 123 covers the first electrode film 38 and the second electrode film 39. The surface insulating film 123 may be, for example, an SiO2 film or an SiN film. The thickness of the surface insulating film 123 may be, for example, 10,000 Å or more and 15,000 Å or less (1 μm or more and 1.5 μm or less). The surface insulating film 123 integrally includes a first portion 124 that covers an area on the first main surface 5 of the substrate 2, and a second portion 125 that covers the side surfaces 7 to 10 of the substrate 2. As a result, the second main surface 6 of the substrate 2 is exposed, while the other surfaces are entirely covered by the surface insulating film 123.

[0101] A surface protection film 126 is formed on the first portion 124 of the surface insulating film 123. The surface protection film 126 may be, for example, a resin film such as a polyimide film. The thickness of the surface protection film 126 may be, for example, 20,000 Å or more and 100,000 Å or less (2 μm or more and 10 μm or less). The surface protection film 126 is exposed between the first external electrode 3 and the second external electrode 4 as an insulating space 13.

[0102] The surface insulating film 123 and the surface protective film 126 have first pad openings 129 formed therein that expose the first base portions 45 of the first electrode film 38 as first pads 127. The surface insulating film 123 and the surface protective film 126 have second pad openings 130 formed therein that expose the second base portions 49 of the second electrode film 39 as second pads 128.

[0103] A first covering portion 131 that selectively covers the first pad 127 is formed on the first pad 127. A second covering portion 132 that selectively covers the second pad 128 is formed on the second pad 128. The first covering portion 131 and the second covering portion 132 may be made of the same material as the surface insulating film 123. The first covering portion 131 and the second covering portion 132 may be formed in the same pattern as the recesses 27 that are formed on the first electrode surface 24 of the first external electrode 3 and the second electrode surface 25 of the second external electrode 4.

[0104] A first external electrode 3 is formed in the first pad opening 129. The first external electrode 3 is connected to the first pad 127 as a first external contact portion 47 in the first pad opening 129. As a result, the first external electrode 3 is electrically connected to the lower electrode 34 and the first impurity region 111 via the first electrode film 38.

[0105] A second external electrode 4 is formed in the second pad opening 130. The second external electrode 4 is connected to the second pad 128 as a second external contact portion 51 in the second pad opening 130. As a result, the second external electrode 4 is electrically connected to the upper electrode 36 and the second impurity region 112 via the second electrode film 39.

[0106] The first external electrode 3 and the second external electrode 4 may also be, for example, a Ni / Pd / Au laminated film including a Ni film, a Pd film, and an Au film laminated in this order from the substrate 2 side. These laminated films may also be plated layers formed by plating growth. [Method of manufacturing chip component 1] 11A to 11Q are views showing the manufacturing process of the chip part 1 in the order of steps, and correspond to the cross section of FIG. 9 described above.

[0107] 11A, a wafer 133 that will become the substrate 2 is first prepared. Then, n-type impurities (e.g., phosphorus) are selectively introduced into the first main surface 5 of the wafer 133. Thereafter, the n-type impurities are diffused into the surface portion of the first main surface 5 of the wafer 133 by annealing at, for example, 900°C to 1000°C, and a first impurity region 111 and a second impurity region 112 are formed.

[0108] 11B, the first main surface 5 of the wafer 133 is thermally oxidized to form a hard mask (not shown) made of SiO. Next, openings are formed in the hard mask, and the wafer 133 is selectively etched from the first main surface 5 side through the hard mask. As a result, trenches 107 are formed in the removed portions of the wafer 133, and wall portions 85 and support portions 87 (substrate main body portion 54) are formed in the portions excluding the trenches 107. Dry etching is preferably used as the etching method.

[0109] Next, referring to FIG. 11C, first main surface 5 of wafer 133 and upper surface 114 and side surface 115 of wall portion 85 are thermally oxidized, for example, to form insulating film 113 made of SiO 2 .

[0110] 11D , a first conductive film 134, which will be the source of the lower electrode 34, is formed on the insulating film 113 by, for example, a CVD method. The first conductive film 134 is formed so as to cover the upper surface 114 and the side surface 115 of the wall portion 85, and the entire first main surface 5 of the wafer 133.

[0111] 11E, an intermediate insulating film 135, which will be the source of the capacitive film 35, is formed on the first conductive film 134 by, for example, a CVD method. The intermediate insulating film 135 is formed so as to cover the upper surface 114 and the side surface 115 of the wall portion 85, and the entire first main surface 5 of the wafer 133.

[0112] 11F, a second conductive film 136, which will be the source of the upper electrode 36, is formed on the intermediate insulating film 135 by, for example, a CVD method. The second conductive film 136 is formed to fill the trench 107 and to cover the entire first main surface 5 of the wafer 133.

[0113] 11G, the second conductive film 136 is selectively etched to form the upper electrode 36. As the etching gas, a gas having sufficient selectivity with respect to the material of the intermediate insulating film 135 is used so that the intermediate insulating film 135 is not etched.

[0114] 11H, the intermediate insulating film 135 is selectively etched to form the capacitance film 35. Subsequently, the first conductive film 134 is selectively etched using the same mask as used to form the capacitance film 35 to form the lower electrode 34. Because the capacitance film 35 and the lower electrode 34 are formed by etching using the same etching mask, the capacitance film 35 and the lower electrode 34 share a common edge 71. In this case, the shape of the opening pattern of the etching mask may be appropriately determined so that the edge 71 is positioned outside the edge 72 of the upper electrode 36. In this way, the capacitor structure 30 is formed.

[0115] Next, referring to FIG. 11I, a first insulating film 118 and a second insulating film 119 are formed in this order by, for example, a CVD method.

[0116] Next, referring to FIG. 11J, the second insulating film 119, the first insulating film 118, the capacitance film 35 and the insulating film 113 are selectively etched to form the first capacitor contact hole 37, the second capacitor contact hole 120, the first diode contact hole 121 and the second diode contact hole 122.

[0117] Next, referring to FIG. 11K, the materials for the first electrode film 38 and the second electrode film 39 are deposited by, for example, sputtering, and then patterned to form the first electrode film 38 and the second electrode film 39.

[0118] 11L, a material for the surface insulating film 123 (first portion 124) is formed over the entire first main surface 5 of the wafer 133, for example, by a CVD method. Subsequently, a material for the surface protective film 126 (for example, a photosensitive resin liquid made of polyimide) is spray-coated onto the wafer 133 from above the surface insulating film 123, thereby forming the photosensitive resin surface protective film 126. Alternatively, instead of spray-coating the photosensitive resin liquid, the surface protective film 126 may be formed by spin-coating the liquid or by attaching a sheet made of photosensitive resin to the first main surface 5 of the wafer 133. Next, a heat treatment (cure treatment) is performed on the surface protective film 126. As a result, the thickness of the surface protective film 126 is thermally shrunk, and the surface protective film 126 is hardened, stabilizing the film quality.

[0119] 11M, for example, a photolithography process is used to selectively remove and pattern surface protective film 126 and surface insulating film 123 by dry etching such as RIE (Reactive Ion Etching). As a result, first pad opening 129 and second pad opening 130 are simultaneously formed. At this time, surface insulating film 123 is patterned so that portions thereof remain as first covering portion 131 and second covering portion 132 on first pad 127 and second pad 128, respectively.

[0120] Next, referring to FIG. 11N, the wafer 133 is selectively removed by plasma etching using a mask (not shown). This removes material from the wafer 133 in boundary regions between adjacent element regions (regions where individual chip components 1 are formed). As a result, trenches 137 are formed with a predetermined depth that extends from the first main surface 5 of the wafer 133 to partway through the thickness of the wafer 133. The trenches 137 are defined by a pair of opposing side surfaces 138 and a bottom surface 139 that connects the lower ends of the pair of side surfaces 138 (ends on the second main surface 6 side of the wafer 133). For example, the depth of the trench 137 relative to the first main surface 5 of the wafer 133 may be approximately 100 μm, and the width of the trench 137 may be approximately 20 μm, and may be constant throughout the depth direction.

[0121] Next, referring to FIG. 11O, surface insulating film 123 (second portion 125) is formed over the entire inner surface (side surface 138 and bottom surface 139) of trench 137 by, for example, CVD.

[0122] 11P, the first external electrode 3 and the second external electrode 4 are simultaneously formed by stacking Ni, Pd, and Au by, for example, electroless plating. During this process, the plating progresses relatively slowly in the areas on the first covering portion 131 and the second covering portion 132. As a result, recesses 27 having the same pattern as the first covering portion 131 and the second covering portion 132 are formed on the electrode surfaces 24, 25 of the first external electrode 3 and the second external electrode 4.

[0123] 11Q, the wafer 133 is ground from the second main surface 6. Specifically, after the trenches 137 are formed, a thin support tape (not shown) made of, for example, PET (polyethylene terephthalate) and having an adhesive surface is attached to the side of the first external electrode 3 and the second external electrode 4 (i.e., the first main surface 5). Then, with the wafer 133 supported by the support tape, the wafer 133 is ground from the second main surface 6. When the wafer 133 is thinned by grinding to reach the bottom surfaces 139 of the trenches 137, there is nothing connecting adjacent chip components 1, so the wafer 133 is divided at the trenches 137 as boundaries, resulting in finished chip components 1. In other words, the wafer 133 is cut (divided) at the trenches 137 (in other words, the boundary regions), and individual chip components 1 are cut out. The chip component 1 may be cut out by etching the wafer 133 from the second main surface 6 side to the bottom surface 139 of the trench 137. The second main surface 6 of the substrate 2 in the completed chip component 1 may be polished or etched to have a mirror finish, thereby making the second main surface 6 clean.

[0124] Next, among the many features included in the embodiments of the present disclosure, Features 1 to 3 will be extracted and described in more detail. Note that Features 1 to 3 are merely examples of the features of the present disclosure, and the content of the claims should not be construed as being limited thereby. [Feature 1 of the embodiment of the present disclosure] (1) Effects of the capacitor section 32 of the present disclosure According to this chip component 1, as shown in FIG. 8 , the wall portion 85 formed on the substrate 2 is composed of multiple pillar units 90. Each pillar unit 90 includes a central portion 91 and three protrusions 92 extending from the central portion 91 in three different directions in a plan view. This allows the wall portion 85 to have a larger surface area than when the wall portion 85 is formed by connecting pillar units such as rectangular pillars. Furthermore, as shown in FIG. 9 , the lower electrode 34, the capacitive film 35, and the upper electrode 36 are formed following the top surface 114 and side surface 115 of the wall portion 85. This means that the capacitance of the capacitor structure 30 is not limited by the planar size of the substrate 2, and a large capacitance can be achieved by increasing the height H of the wall portion 85. In other words, even if the planar size of the substrate 2 is small, a large capacitance can be ensured for the capacitor structure 30. This allows for both a small element size and a large capacitance for the capacitor structure 30. Furthermore, the inclusion of the diode portion 33 also provides the chip component 1 with ESD protection functionality.

[0125] Furthermore, a wall portion 85 formed by connecting multiple pillar units 90 is more stable than pillar units 90 that are independent of each other. Furthermore, as shown in FIG. 7 , one end portion 100 and one end portion 101 of the wall portion 85 are connected to support portions 87 around the wall portion 85. This allows the wall portion 85 to be supported from both sides, thereby reinforcing the wall portion 85 against lateral forces applied thereto. As a result, the stability of the wall portion 85 can be maintained even when the height H of the wall portion 85 is increased, thereby improving the reliability of the element. Furthermore, in each pillar unit 90, each protrusion 92 forms angles θ1, θ2, and θ3 of 120° with adjacent protrusions 92 and intersects with adjacent protrusions 92 at the center 91. Therefore, regardless of the direction of force applied to the wall portion 85, at least one of the three protrusions 92 can act as a buttress to prevent the wall portion 85 from collapsing. As a result, the stability of the wall portion 85 can be further improved.

[0126] Furthermore, the capacitor portion 32 includes a first capacitor portion 321 and a second capacitor portion 322, whose wall portions 85 have different longitudinal directions. This allows the direction of stress generated in the substrate 2 (wafer 133) due to the formation of the wall portions 85 to be dispersed in multiple directions. As a result, warping of the substrate 2 (wafer 133) can be suppressed, improving its strength. In particular, in this embodiment, the first longitudinal direction D1 of the wall portions 85 of the first capacitor portion 321 and the second longitudinal direction D2 of the wall portions 85 of the second capacitor portion 322 are perpendicular to each other. This allows the stresses in the first capacitor portion 321 and the second capacitor portion 322 to be applied in directions that cancel each other out, further suppressing warping of the substrate 2 (wafer 133). As a result, a chip component 1 having a capacitor structure 30 with excellent mechanical reliability can be provided.

[0127] Furthermore, in the chip component 1, the edge 71 of the lower electrode 34 is spaced apart from the edge 72 of the upper electrode 36. In addition, the lower electrode 34 between the edge 72 of the upper electrode 36 and the edge 71 of the lower electrode 34 is covered with the capacitive film 35. This prevents short circuits between the lower electrode 34 and the upper electrode 36, making it possible to provide a chip component 1 with excellent insulation reliability. (2) Modifications of the capacitor section 32 12 to 17 are diagrams illustrating modified examples of the chip component 1. FIG. 12 and FIGS. 15 to 17 are plan views corresponding to the above-mentioned FIG. 7. FIGS. 13 and 14 are plan views further schematically illustrating the plan view of FIG. 7. More specifically, FIGS. 12 to 14 show modified examples of the number of capacitor sections included in the capacitor section 32. FIGS. 15 and 16 show modified examples of the first longitudinal direction D1 of the first capacitor section 321 and the second longitudinal direction D2 of the second capacitor section 322. FIG. 17 shows a modified example in which the diode section 33 may be omitted. Also, FIGS. 12 to 17 show extracted components necessary for the description and their reference numerals.

[0128] 12 , capacitor section 32 may include a pair of first capacitor sections 321 and a pair of second capacitor sections 322. In this case, the pair of first capacitor sections 321 and the pair of second capacitor sections 322 may be arranged alternately in a planar view. In other words, for example, in capacitor section 32 having a rectangular shape in a planar view, the pair of first capacitor sections 321 may be arranged diagonally opposite each other at a pair of first diagonal corners 140, and the pair of second capacitor sections 322 may be arranged diagonally opposite each other at a pair of second diagonal corners 141.

[0129] 13, the capacitor section 32 may include a total of six capacitor sections: three first capacitor sections 321 and three second capacitor sections 322. In this case, the three first capacitor sections 321 and the three second capacitor sections 322 may be arranged alternately in a plan view. In other words, when the second direction Y on the paper surface is the up-down direction, the first capacitor sections 321 and the second capacitor sections 322 may be arranged so that they alternate up and down.

[0130] 14, the capacitor section 32 may include a total of eight capacitor sections, including four first capacitor sections 321 and four second capacitor sections 322. In this case, the four first capacitor sections 321 and the four second capacitor sections 322 may be arranged alternately in a plan view. In other words, when the second direction Y on the paper surface is the up-down direction, the first capacitor sections 321 and the second capacitor sections 322 may be arranged so that they alternate up and down.

[0131] 15, the first longitudinal direction D1 of the first capacitor portion 321 and the second longitudinal direction D2 of the second capacitor portion 322 do not have to be perpendicular to each other. For example, the first longitudinal direction D1 may be a direction along the second direction Y (the width direction of the substrate 2), and the second longitudinal direction D2 may be a direction inclined to both the first direction X and the second direction Y (for example, a direction inclined at θ4=45° with respect to the second direction Y).

[0132] 16, the first longitudinal direction D1 of the first capacitor section 321 and the second longitudinal direction D2 of the second capacitor section 322 are perpendicular to each other but do not have to be perpendicular to the first direction X (the length direction of the substrate 2) and the second direction Y (the width direction of the substrate 2). For example, the first longitudinal direction D1 and the second longitudinal direction D2 may be inclined to both the first direction X and the second direction Y. In FIG. 16, the first longitudinal direction D1 is inclined counterclockwise with respect to the second direction Y at θ5=45°, and the second longitudinal direction D2 is inclined clockwise with respect to the second direction Y at θ6=45°.

[0133] Next, referring to FIG. 17, chip part 1 does not need to be a composite element in which both capacitor section 32 and diode section 33 are mounted on substrate 2, and may be a chip capacitor in which diode section 33 is omitted. [Feature 2 of the embodiment of the present disclosure] (1) Effects of the lower contact portion 40 and the upper contact portion 42 of the present disclosure 5, in this chip component 1, the lower contact portion 40 includes not only the second lower contact portion 75 in the region below the first external electrode 3, but also the first lower contact portion 74 formed on the lower electrode 34 (first portion 64) between the first external electrode 3 and the second external electrode 4. The upper contact portion 42 is formed between the first external electrode 3 and the second external electrode 4 so as to cover almost the entire capacitor portion 32. This increases the contact area of ​​the lower contact portion 40 and the upper contact portion 42, thereby providing a chip component 1 with excellent electrical characteristics. Below, the Q values ​​(Quality Factor) and Rs (series resistance) of chip components S1 to S3 according to samples 1 to 3 are compared as an example of the evaluation results of the electrical characteristics.

[0134] 18 to 20 are schematic plan views of chip parts S1 to S3, respectively, according to samples 1 to 3. Of the components of the chip part 1 described above, Fig. 18 to 20 mainly show the patterns of the lower contact portion 40 and the upper contact portion 42, which are necessary for explaining the evaluation results of the electrical characteristics.

[0135] 18, the chip component S1 of sample 1 differs from the aforementioned chip component 1 in that the lower contact portion 40 is formed only in the region below the first external electrode 3. The chip component S1 also differs from the aforementioned chip component 1 in that the upper contact portion 42 is formed only in the region below the second external electrode 4. In short, the lower contact portion 40 and the upper contact portion 42 of the chip component S1 are formed in strip shapes extending along the second direction Y in the regions below the first external electrode 3 and the second external electrode 4, respectively.

[0136] 19, the chip component S2 of sample 2 differs from the aforementioned chip component 1 in that the lower contact portion 40 is formed only in the region below the first external electrode 3. In short, the lower contact portion 40 of the chip component S2 is formed in a strip shape extending along the second direction Y in the region below the first external electrode 3. On the other hand, the shape (pattern) of the upper contact portion 42 of the chip component S2 is the same as that of the chip component 1, and is formed in a region that covers almost the entire capacitor portion 32.

[0137] 20, the shapes (patterns) of the lower contact portion 40 and the upper contact portion 42 of the chip part S3 of sample 3 are the same as those of the chip part 1. That is, the lower contact portion 40 is formed in a substantially U-shape surrounding the capacitor portion 32, and the upper contact portion 42 is formed in a region covering almost the entire capacitor portion 32.

[0138] Then, the Q values ​​and capacitance values ​​of the chip parts S1 to S3 were calculated by simulation, and the results shown in FIGS. 21 to 23 were obtained.

[0139] 21 to 23 are diagrams showing evaluation results of the Q-factors and capacitance values ​​of chip components S1 to S3 (samples 1 to 3), respectively. In FIGS. 21 to 23, the horizontal axis represents frequency [Hz], the vertical axis (right side) represents the Q-factor, and the vertical axis (left side) represents capacitance [pF]. FIGS. 21 to 23 show curves A1 to A3 and B1 to B3, respectively. Curves A1 to A3 represent the Q-factors of chip components S1 to S3 when the frequency of the current flowing through chip components S1 to S3 is increased from 0 Hz to approximately 1 GHz. Curves B1 to B3 represent the capacitance values ​​of chip components S1 to S3 when the frequency of the current flowing through chip components S1 to S3 is increased from 0 Hz to approximately 1 GHz.

[0140] Comparing the curves A1 to A3 in FIGS. 21 to 23, it can be seen that the Q values ​​of the chip components S2 and S3 are improved compared to the chip component S1. For example, when the frequency is 10 MHz (1×10 7 Hz), the Q value of chip component S2 (curve A2) was about 1.5 times that of chip component S1 (curve A1), and the Q value of chip component S3 (curve A3) was about 14 times. This shows that the Q value of chip component S3 (curve A3) is particularly excellent.

[0141] Comparing the curves B1 to B3 in FIGS. 21 to 23, it can be seen that the capacitance values ​​of the chip components S2 and S3 are relatively stable compared to the chip component S1. For example, when the frequency is 10 MHz (1×10 7 Hz) to 100MHz (1×10 8 When comparing the capacitance values ​​in the 10 MHz (1×10 Hz) band, the fluctuation range of the capacitance value of chip component S2 (curve B2) and the fluctuation range of the capacitance value of chip component S3 (curve B3) were smaller than the fluctuation range of the capacitance value of chip component S1 (curve B1). In particular, the capacitance value of chip component S3 (curve B3) 7 Hz) to 100MHz (1×10 8 Hz) frequency band, it was almost constant with no attenuation.

[0142] Next, the series resistance of the chip parts S1 to S3 was calculated by simulation, and the results shown in FIGS. 24 to 26 were obtained.

[0143] 24 to 26 are diagrams showing evaluation results of the series resistance (Rs) of chip parts S1 to S3 (samples 1 to 3), respectively. In FIGS. 24 to 26, the horizontal axis represents frequency [Hz], and the vertical axis represents series resistance value [Ω]. Curves C1 to C3 are shown in FIGS. 24 to 26, respectively. Curves C1 to C3 represent the series resistance of chip parts S1 to S3 when the frequency of the current flowing through chip parts S1 to S3 is increased from 0 Hz to approximately 1 GHz.

[0144] Comparing the curves C1 to C3 in FIGS. 24 to 26, it is clear that the series resistance of the chip components S2 and S3 is reduced compared to the chip component S1. For example, when the frequency is 10 MHz (1×10 7 Hz) to 100MHz (1×10 8 Comparing the series resistance values ​​in the 500 Hz band, the series resistance value of chip component S2 (curve C2) was about half of the series resistance value of chip component S1 (curve C1), and the series resistance value of chip component S3 (curve C3) was about 1 / 21. This shows that the series resistance value of chip component S3 (curve C3) is particularly low. (2) Modifications of the lower contact portion 40 27 to 31 are diagrams illustrating modified examples of the chip part 1. FIGS. 27 to 29 are plan views corresponding to the aforementioned FIG. 5. FIG. 30 is a cross-sectional view corresponding to the aforementioned FIG. 9. FIG. 31 is a plan view corresponding to the aforementioned FIG. 5. More specifically, FIGS. 27 to 31 show modified examples of the shape (pattern) of the lower contact portion 40. Also, FIGS. 27 to 31 show extracted components necessary for the explanation and their reference numerals.

[0145] 27, in the lower contact portion 40, the first lower contact portion 74 and the second lower contact portion 75 do not have to be formed integrally with each other. For example, they may be separated in a region below the first external electrode 3. Furthermore, the upper contact portion 42 may be divided into a first upper contact portion 142 and a second upper contact portion 143 in a region overlapping the capacitor portion 32. It is sufficient that the first upper contact portion 142 and the second upper contact portion 143 as a whole cover the entire capacitor portion 32.

[0146] 28 , the substrate main body 54 may further include a straight portion 144 extending linearly from a region below the first external electrode 3 toward the second external electrode 4. The capacitor portion 32 may be separated in the second direction Y into a first portion 145 on one side of the first lower contact portion 74 and a second portion 146 on the other side of the straight portion 144. The first portion 145 and the second portion 146 may be connected in the region below the second external electrode 4. As a result, the capacitor portion 32 may be formed in a generally U-shape in plan view.

[0147] The lower electrode 34 may include a fourth portion 147 drawn out from the capacitor portion 32 onto the linear portion 144. The fourth portion 147 may be covered with the capacitive film 35. The lower contact portion 40 includes a linear contact portion 148 connected to the fourth portion 147. The linear contact portion 148 extends integrally from the second lower contact portion 75 in the first direction X. As a result, the lower contact portion 40 includes a pair of first lower contact portions 74 and linear contact portion 148 that are integrally connected perpendicularly to the second lower contact portion 75, and is formed in a generally E-shape in plan view.

[0148] On the other hand, the upper contact portion 42 is formed in a pattern corresponding to the substantially U-shaped capacitor portion 32, and has a substantially U-shape in plan view.

[0149] 29, the lower contact portion 40 includes a third lower contact portion 149 connected to the third portion 66 of the lower electrode 34. The third lower contact portion 149 connects the tip ends (the ends opposite the second lower contact portion 75) of the pair of first lower contact portions 74 to each other. The third lower contact portion 149 may be formed in a region below the second external electrode 4. As a result, the first lower contact portion 74, the second lower contact portion 75, and the third lower contact portion 149 are integrally formed in the lower contact portion 40, thereby forming a closed-loop contact portion that surrounds the capacitor portion 32 as a whole.

[0150] 30 , a third insulating film 150 that covers the first electrode film 38 is formed on the second insulating film 119, and the second electrode film 39 is formed on the third insulating film 150. As a result, the first electrode film 38 and the second electrode film 39 are insulated from each other by the third insulating film 150, and the second electrode film 39 is made to overlap above the first electrode film 38 (third lower contact portion 149), and the second extension portion 50 can be extended to the region above the capacitor portion 32.

[0151] 31 , substrate main body 54 may further include a lattice portion 151 that divides capacitor portion 32 into a plurality of portions. Capacitor portion 32 may be separated by lattice portion 151 into a first portion 152, a second portion 153, a third portion 154, and a fourth portion 155. In other words, capacitor portion 32 may be formed in each of the window portions of the lattice divided by lattice portion 151.

[0152] The lower electrode 34 may include a fifth portion 156 that is drawn out from the capacitor portion 32 onto the lattice portion 151. The fifth portion 156 may be covered with the capacitive film 35. The lower contact portion 40 includes a lattice contact portion 157 that is connected to the fifth portion 156. The lattice contact portion 157 is integrally connected to a pair of the first lower contact portion 74, the second lower contact portion 75, and the third lower contact portion 149.

[0153] On the other hand, the upper contact portion 42 may be formed so as to cover the first portion 152, the second portion 153, the third portion 154, and the fourth portion 155 of the capacitor portion 32, respectively.

[0154] 32 to 35 are diagrams illustrating modified examples of the chip component 1. More specifically, FIGS. 32 to 35 show modified examples of the shape (pattern) of the lower contact portion 40 shown in FIGS. 27 to 31, as well as modified examples of the number of capacitor portions included in the capacitor portion 32. FIGS. 32 to 35 are all plan views corresponding to the above-mentioned FIG. 7. The shapes of the lower contact portions 40 in FIGS. 32 to 35 are the same as those of the lower contact portions 40 in FIGS. 7, 28, 29, and 31, respectively. In addition, FIGS. 32 to 35 show extracted components necessary for the explanation and their reference numerals.

[0155] 32 to 35, capacitor section 32 is formed by an assembly of wall sections 85 having a longitudinal direction in one specific direction. In FIGS. 32 to 35, the longitudinal directions of wall sections 85 constituting capacitor section 32 are all first longitudinal direction D1. In other words, capacitor section 32 in FIGS. 32 to 35 differs from capacitor section 32 in FIG. 7 in that it does not include a plurality of capacitor sections whose wall sections 85 have longitudinal directions that differ from one another. [Feature 3 of the embodiment of the present disclosure] (1) Effects of the diode section 33 of the present disclosure 7, the capacitor section 32 and the diode section 33 are mounted on a common substrate 2, thereby providing the chip component 1 with ESD protection capabilities. Furthermore, the diode section 33 is disposed in a region below the first external electrode 3 and the second external electrode 4. This improves the ESD protection capabilities compared to when the diode section 33 is formed in a region that avoids the first external electrode 3 and the second external electrode 4 in plan view. Below, the breakdown voltages [kV] of chip components S4 to S10 according to samples 4 to 10 are compared as an example of the results of evaluating the ESD protection characteristics.

[0156] 36 to 42 are schematic plan views of chip parts S4 to S10 according to samples 4 to 10, respectively. In Fig. 36 to 42, the position of the diode portion 33, which is necessary for explaining the evaluation results of the ESD protection characteristics, is mainly extracted and shown from among the components of the chip part 1 described above.

[0157] 36, the chip component S4 of sample 4 differs from the aforementioned chip component 1 in that the diode portion 33 is formed in a region 158 between the first external electrode 3 and the second external electrode 4. More specifically, in the region 158, the capacitor portions 32 separated from each other include a pair of capacitor portions 32. The pair of capacitor portions 32 are adjacent to each other in the second direction Y, sandwiching a diode region 159 therebetween. A pair of diode portions 33 is formed in the diode region 159. Each diode portion 33 is formed in a strip shape extending along the first direction X.

[0158] 37, the chip component S5 of sample 5 differs from the aforementioned chip component 1 in that the diode section 33 is formed in a region 158 between the first external electrode 3 and the second external electrode 4. More specifically, in the region 158, a pair of diode regions 160 are formed outside the capacitor section 32. The capacitor section 32 is sandwiched between the pair of diode regions 160 in the second direction Y. A diode section 33 is formed in each diode region 160. The diode sections 33 are formed in a strip shape extending along the first direction X.

[0159] 38, the positions of the diode portions 33 of the chip part S6 of sample 6 are the same as those of the chip part 1. That is, the pair of diode portions 33 are formed in the regions below the first external electrode 3 and the second external electrode 4, respectively.

[0160] 39, the chip part S7 of sample 7 differs from the above-described chip part 1 in that it does not include a diode portion 33. In short, the chip part S7 is a discrete capacitor element that includes only a capacitor portion 32 as an element.

[0161] 40 to 42, chip parts S8 to S10 according to samples 8 to 10 differ from the aforementioned chip part 1 in that none of them includes a capacitor part 32. Simply put, chip parts S8 to S10 are discrete diode elements that include only diode parts 33 as elements. The difference between chip parts S8 to S10 is the area of ​​the diode parts 33 (the number of diode elements). Chip part S8 has the largest area of ​​the diode parts 33 (the largest number of diode elements), followed by chip part S9. The area of ​​the diode parts 33 of chip part S9 is the same as the area of ​​the diode parts 33 of chip part S6. Meanwhile, the area of ​​the diode parts 33 of chip part S10 is smaller than the areas of the diode parts 33 of chip parts S8 and S9.

[0162] The breakdown voltages [kV] of the chip components S4 to S10 were calculated by simulation. The breakdown voltages of the chip components S4 to S10 were as follows:

[0163] Chip component S4 (interelectrode diode) = 3.5 kV Chip component S5 (interelectrode diode) = 4kV Chip component S6 (diode under electrode) = 4.5kV Chip component S7 (without diode) = 0.2 kV Chip component S8 (no capacitor, large diode) = 10.5kV Chip component S9 (no capacitor, diode inside) = 7.5kV Chip component S10 (no capacitor, small diode) = 5.5kV Comparing chip components S4 to S6 with chip component S7, it is clear that the breakdown voltage is increased and the ESD protection characteristics are improved by incorporating the diode section 33. Furthermore, it is clear that the ESD protection characteristics are further improved by arranging the diode section 33 in the region below the first external electrode 3 and the second external electrode 4, as in chip component S6.

[0164] On the other hand, when chip component S6 is compared with chip components S8 to S10, chip components S8 to S10, which are discrete diode elements, have superior ESD protection characteristics. However, as is clear from the comparison of chip components S8 to S10, the ESD protection characteristics can be improved by increasing the area of ​​the diode portion 33. The simulation results above also show that the breakdown voltage increases as the area of ​​the diode portion 33 increases in the order of chip component S10, chip component S9, and chip component S8. Therefore, chip component S6 can also be expected to exhibit ESD protection characteristics equivalent to those of a discrete diode element by adjusting the area of ​​the diode portion 33. [External appearance of chip part 201 (vertical type)] Fig. 43 is a schematic perspective view of a chip component 201 according to an embodiment of the present disclosure. Fig. 44 is a schematic plan view of the chip component 201. Fig. 45 is a schematic bottom view of the chip component 201. Hereinafter, structures corresponding to those described with reference to Figs. 1 to 42 will be denoted by the same reference numerals, and descriptions thereof will be omitted. In Figs. 43 to 45, the longitudinal direction of the rectangular parallelepiped chip component 201 is defined as a first direction X, the width direction of the chip component 201 is defined as a second direction Y, and the thickness direction of the chip component 201 is defined as a third direction Z.

[0165] The chip component 201 is formed in a rectangular parallelepiped shape and has a length L6 along the first direction X, a width W6 along the second direction Y, and a thickness T6 along the third direction Z. The length L6 may be, for example, 0.4 mm or more and 2 mm or less. The width W6 may be, for example, 0.2 mm or more and 2 mm or less. The thickness T6 may be, for example, 0.1 mm or more and 0.5 mm or less.

[0166] The chip component 201 may be a small electronic component designated by its size (length L1 (mm) x width W1 (mm)), such as a 1608 (1.6 mm x 0.8 mm) chip, a 1005 (1.0 mm x 0.5 mm) chip, a 0603 (0.6 mm x 0.3 mm) chip, a 0402 (0.4 mm x 0.2 mm) chip, or a 03015 (0.3 mm x 0.15 mm) chip.

[0167] The chip component 201 includes a substrate 202 , a first external electrode 203 , and a second external electrode 204 .

[0168] The substrate 202 forms the base of the chip component 201. The chip component 201 is configured by supporting a plurality of insulating films, metal films, etc. stacked on top of each other on the substrate 202. The substrate 202 has a rectangular parallelepiped shape and is approximately the same size as the chip component 201. The substrate 202 has a first main surface 205, a second main surface 206, and four side surfaces 207 to 210. The first main surface 205 is what is known as the front surface of the chip component 201, and the second main surface 206 is the back surface of the chip component 201. The four side surfaces 207 to 210 surround the first main surface 205 in a plan view seen from the normal direction n of the first main surface 205 (hereinafter simply referred to as "plan view"). The four side surfaces 207 to 210 may include a pair of first side surfaces 207 and second side surfaces 208 that face each other in the first direction X, and a pair of third side surfaces 209 and fourth side surfaces 210 that face each other in the second direction Y. In other words, the side surfaces that extend parallel to each other along the second direction Y may be the first side surfaces 207 and the second side surfaces 208, and the side surfaces that extend parallel to each other along the first direction X may be the third side surfaces 209 and the fourth side surfaces 210. The first side surface 207, the second side surface 208, the third side surface 209, and the fourth side surface 210 may also be referred to as a first end surface, a second end surface, a third end surface, and a fourth end surface, respectively.

[0169] The first external electrode 203 is formed on the second main surface 206. The first external electrode 203 is formed so as to cover the entire second main surface 206. The second external electrode 204 is formed on the first main surface 205. The second external electrode 204 is formed so as to cover almost the entire first main surface 205. The second external electrode 204 has an edge 211 formed at a distance inward from the side surfaces 207 to 210. The region between the edge 211 of the second external electrode 204 and the side surfaces 207 to 210 may be an insulating space 212 in which an insulating portion on the first main surface 205 of the substrate 202 is exposed. The edge 211 of the second external electrode 204 may also be referred to as an end face of the second external electrode 204.

[0170] In this embodiment, the first external electrode 203 and the second external electrode 204 form both terminals of the chip component 201. The chip component 201 is a vertical chip component 201 in which a capacitor structure 220 is formed, having a stacked structure of an upper electrode 215, a capacitive film 214, and a lower electrode 219, in the vertical direction along the thickness direction of the substrate 2. The vertical chip component 201 can be used, for example, by bonding to a mounting substrate via the first external electrode 203 and by wire bonding to the second external electrode 204. Therefore, the chip component 201 may also be referred to as a vertical chip component. The first external electrode 203 and the second external electrode 204 may also be referred to as a first terminal electrode and a second terminal electrode, or as a first external terminal and a second external terminal, respectively. [Structure of capacitor section 213] FIG. 46 is a schematic plan view of the chip component 201. FIG. 47 is a schematic cross-sectional view of the chip component 201. For clarity, in FIG. 46, the trench 107 is hatched, and the second external electrode 204 is shown in perspective with a dashed line. Also, in FIG. 46, components necessary for explanation and their reference numerals are extracted and shown. Also, FIG. 47 is a diagram schematically showing the layer structure of the first main surface 205 and the second main surface 206 of the chip component 201, and does not show a cross-section along a specific cutting line in FIG. 46.

[0171] The substrate 202 is a semiconductor substrate such as a silicon plate. In this embodiment, the substrate 202 is an n-type substrate. The thickness of the substrate 202 may be, for example, 200 μm or more and 600 μm or less. The resistivity of the substrate 202 may be set to about 5 mΩ·cm by introducing n-type impurities.

[0172] A capacitor portion 213 is formed on the first main surface 205 of the substrate 202. The capacitor portion 213 is formed in the center of the first main surface 205, and is entirely covered by the second external electrode 204. In the capacitor portion 213, a portion of the substrate 202 on the first main surface 205 side is selectively removed, thereby forming a plurality of wall portions 85 using a part of the substrate 202. The shape of the wall portions 85 of the capacitor portion 213 and the fact that the capacitor portion 213 includes a plurality of capacitor portions (for example, a first capacitor portion 321 and a second capacitor portion 322) whose wall portions 85 have different longitudinal directions are the same as those described above, and therefore will not be described again.

[0173] 47, a capacitive film 214 is formed on a first main surface 205 of a substrate 202 so as to cover the entire first main surface 205 of the substrate 202. The capacitive film 214 is formed not only on the first main surface 205, which is a flat surface of the substrate 202, but also on the entire surfaces (top surface 114 and side surface 115) of the wall portions 85. The capacitive film 214 has end surfaces that coincide with the side surfaces 207 to 210 of the substrate 202. The capacitive film 214 may be, for example, a SiO2 film or a SiN film, or a laminated film thereof. For example, it may be a SiO2 / SiN laminated film or a SiO2 / SiN / SiO2 laminated film. The capacitive film 214 may also be an ON film or an ONO film, or a laminated film thereof. Furthermore, the capacitive film 214 may be an insulating film made of a high-dielectric material (high-k material). Examples of high dielectric materials include aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), titanium pentoxide (Ti3O5), hafnium oxide (HfO2), strontium titanate (SrTiO3), barium strontium titanate (Ba x Sr 1-xExamples of the thickness of the capacitor film 214 include perovskite compounds such as TiO3. The thickness of the capacitor film 214 may be, for example, 100 Å to 1000 Å (10 nm to 100 nm).

[0174] The upper electrode 215 is embedded in the trench 107 and formed along the first main surface 205 of the substrate 202. The upper electrode 215 integrally includes a buried portion 216 embedded in the trench 107 and a flat portion 217 connected to the upper end of the buried portion 216 and formed flat along the first main surface 205 of the substrate 202. The flat portion 217 forms a peripheral portion 218 of the upper electrode 215 that extends outward from the capacitor portion 213. The upper electrode 215 may be made of a semiconductor material such as polysilicon, or a metal material containing Cu or Al. If the upper electrode 215 is made of a metal material, it may be made of Cu, Al, AlSi, or AlCu. The thickness of the upper electrode 215 (flat portion 217) may be, for example, 4000 Å or more and 10000 Å or less (400 nm or more and 1000 nm or less).

[0175] In the chip component 201, a substrate 202 made of a semiconductor substrate containing impurities forms a lower electrode 219 in a capacitor section 213. As a result, a capacitance film 214 is sandwiched between the lower electrode 219 (substrate 202) and the upper electrode 215, thereby forming a capacitor structure 220.

[0176] A surface insulating film 221 is formed on the substrate 202. The surface insulating film 221 covers the upper electrode 215. The surface insulating film 221 may be, for example, an SiO2 film or an SiN film. The thickness of the surface insulating film 221 may be, for example, 10,000 Å or more and 15,000 Å or less (1 μm or more and 1.5 μm or less). A capacitor contact hole 222 that exposes a portion of the upper electrode 215 is formed in the surface insulating film 221.

[0177] The first external electrode 203 is connected to the second main surface 206 of the substrate 202. The first external electrode 203 is electrically connected to the lower electrode 219. The first external electrode 203 may be, for example, a Ni / Pd / Au laminated film including a Ni film, a Pd film, and an Au film laminated in this order from the substrate 202 side.

[0178] The second external electrode 204 is formed on the surface insulating film 221. The second external electrode 204 is electrically connected to the upper electrode 215 within the capacitor contact hole 222. The second external electrode 204 may be a laminated film including multiple conductive layers. For example, the second external electrode 204 may include a first layer 223, a second layer 224, and a third layer 225, which are stacked in this order from the substrate 202 side. The first layer 223 may be referred to as a barrier layer containing Ti, for example. The second layer 224 may be referred to as a sputtered layer containing Au, and the third layer 225 may be referred to as a plated layer containing Au. When the second layer 224 and the third layer 225 are formed of the same material, there may be no boundary between them. The third layer 225 may be thicker than the first layer 223 and the second layer 224. [Manufacturing method of chip component 201] 48A to 48G are diagrams showing the manufacturing process of the chip part 201 in the order of steps, and correspond to the cross section of the above-mentioned FIG.

[0179] To manufacture chip component 201, first, referring to FIG. 48A, a wafer 226, which is the base of substrate 202, is prepared. Then, a first main surface 205 of wafer 226 is thermally oxidized, for example, to form a hard mask (not shown) made of SiO. Next, openings are formed in the hard mask, and then wafer 226 is selectively etched from the first main surface 205 side through the hard mask. As a result, trenches 107 are formed in the removed portions of wafer 226, and wall portions 85 and support portions 87 (substrate main body portion 54) are formed in the portions excluding trenches 107. As an etching method, dry etching is preferably used.

[0180] 48B, a capacitive film 214 is formed on the first main surface 205 of the wafer 226 and the upper surface 114 and side surface 115 of the wall portion 85. The capacitive film 214 may be formed by, for example, a thermal oxidation method, a CVD method, or a combination thereof.

[0181] 48C, a conductive film (not shown) that will become the upper electrode 215 is formed on the capacitance film 214, for example, by a CVD method. The conductive film is formed to fill the trench 107 and cover the entire first main surface 205 of the wafer 226. The conductive film is then patterned to form the upper electrode 215. This forms a capacitor structure 220 that includes the lower electrode 219 (substrate 202), the capacitance film 214, and the upper electrode 215.

[0182] 48D, a surface insulating film 221 is formed by, for example, a CVD method. Thereafter, the surface insulating film 221 is patterned to form capacitor contact holes 222.

[0183] 48E, second external electrode 204 is formed. For example, first layer 223 and second layer 224 are formed in this order by sputtering, and then third layer 225 is formed by plating growth from second layer 224.

[0184] Next, referring to FIG. 48F, first external electrode 203 is formed on second main surface 206 of substrate 202 by, for example, sputtering.

[0185] 48G, a dicing blade is inserted into the wafer 226 from the side of the second main surface 206, thereby cutting (dividing) the wafer 226. As a result, the individual chip parts 201 are cut out.

[0186] According to this chip component 201, as in the chip component 1, as shown in FIG. 8, the wall portion 85 formed on the substrate 2 is formed of a plurality of pillar units 90. Each pillar unit 90 includes a central portion 91 and three protrusions 92 extending from the central portion 91 in three different directions in a plan view. This allows the surface area of ​​the wall portion 85 to be larger than when the wall portion 85 is formed by connecting pillar units such as square pillars. As a result, even if the planar size of the substrate 202 is small, a large capacitance of the capacitor structure 220 can be ensured, and therefore, both a miniaturized element and an increased capacitance of the capacitor structure 220 can be achieved.

[0187] Furthermore, the capacitor portion 213 includes a first capacitor portion 321 and a second capacitor portion 322, whose wall portions 85 have different longitudinal directions. This allows the direction of stress generated in the substrate 202 (wafer 226) due to the formation of the wall portions 85 to be dispersed in multiple directions. As a result, warping of the substrate 202 (wafer 226) can be suppressed, improving its strength. In particular, in this embodiment, the first longitudinal direction D1 of the wall portions 85 of the first capacitor portion 321 and the second longitudinal direction D2 of the wall portions 85 of the second capacitor portion 322 are perpendicular to each other. This allows the stresses in the first capacitor portion 321 and the second capacitor portion 322 to be applied in directions that cancel each other out, further suppressing warping of the substrate 202 (wafer 226). As a result, a chip component 201 having a capacitor structure 220 with excellent mechanical reliability can be provided.

[0188] The chip part 201 can employ the same modified examples as those of the chip part 1. For example, an example of a modified capacitor part 213 will be given. Referring to FIG. 49, the capacitor part 213 may include a pair of first capacitor parts 321 and a pair of second capacitor parts 322. In this case, the pair of first capacitor parts 321 and the pair of second capacitor parts 322 may be arranged alternately in a plan view.

[0189] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0190] For example, in the above-described embodiment, the capacitor structure 30, 220 had a structure consisting of a lower electrode 34, 219 and an upper electrode 36, 215 sandwiching one layer of capacitance film 35, 214, but it may also have a structure including two or more layers of capacitance film and electrodes sandwiching each of the capacitance films.

[0191] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects.

[0192] The following characteristics can be extracted from the description of this specification and the drawings.

[0193] [Appendix 1-1] a substrate (2) having a first main surface (5) and a second main surface (6) opposite to the first main surface; a capacitor portion (32) formed on the first main surface (5) of the substrate (2) in a plan view seen from a normal direction (n) of the first main surface (5), the capacitor portion (32) having a plurality of wall portions (85) having a longitudinal direction separated from each other by trenches (107) formed in the first main surface (5); a substrate body portion (54) formed around the capacitor portion (32) using a part of the substrate (2) and connected to at least one of one end portion (100) and the other end portion (101) in the longitudinal direction of the wall portion (85); a lower electrode (34) formed along the upper surface (114) and side surface (115) of the wall portion (85); a capacitance film (35) formed on the lower electrode (34) along the upper surface (114) and side surface (115) of the wall portion (85); an upper electrode (36) formed on the capacitance film (35); The wall portion (85) is formed by a plurality of pillar units (90), and each of the pillar units (90) includes, in the plan view, a central portion (91) and three protruding portions (92) extending from the central portion (91) in three different directions, and the wall portion (85) is formed by connecting the protruding portions (92) of adjacent pillar units (90), The capacitor portion (32) includes, in the plan view, a first capacitor portion (321) including the wall portion (85) whose longitudinal direction is a first longitudinal direction (D1), and a second capacitor portion (322) including the wall portion (85) whose longitudinal direction is a second longitudinal direction (D2) that intersects the first longitudinal direction (D1), a chip component (1).

[0194] According to this configuration, the wall portion (85) formed on the substrate (2) is formed of a plurality of pillar units (90). Each pillar unit (90) includes, in a plan view, a central portion (91) and three protrusions (92) extending from the central portion (91) in three different directions. This allows the surface area of ​​the wall portion (85) to be larger than when the wall portion (85) is formed by connecting pillar units such as rectangular pillars. Furthermore, because the capacitor portion (32) is formed following the surface of the wall portion (85), the capacitance of the capacitor portion (32) is not limited by the planar size of the substrate (2). Therefore, a large capacitance can be achieved by increasing the height of the wall portion (85). In other words, even if the planar size of the substrate (2) is small, a large capacitance of the capacitor portion (32) can be ensured.

[0195] Furthermore, a wall portion (85) formed by connecting multiple pillar units (90) is more stable than pillar units that are independent of each other. Furthermore, at least one of the one end (100) and the other end (101) of the wall portion (85) is connected to the substrate main body portion (54) around the wall portion (85). This allows at least the wall portion (85) to be cantilevered laterally, thereby reinforcing the wall portion (85) against lateral forces. As a result, the stability of the wall portion (85) can be maintained even when the height of the wall portion (85) is increased, thereby improving the reliability of the device.

[0196] Furthermore, the capacitor section (32) includes a first capacitor section (321) and a second capacitor section (322) whose wall sections (85) have different longitudinal directions. This allows the direction of stress generated in the substrate (2) by the formation of the wall sections (85) to be dispersed in multiple directions. As a result, warping of the substrate (2) can be suppressed, and strength can be improved. As a result, a chip component (1) having a capacitor structure with excellent mechanical strength reliability can be provided.

[0197] [Appendix 1-2] a first external electrode (3) formed on the first main surface (5) of the substrate (2) and electrically connected to the lower electrode (34); A chip component (1) according to Appendix 1-1, including a second external electrode (4) formed on the first main surface (5) of the substrate (2) at a distance from the first external electrode (3) and electrically connected to the upper electrode (36).

[0198] This configuration makes it possible to provide a chip component (1) that can be used by flip-chip bonding.

[0199] [Appendix 1-3] The chip component (1) described in Appendix 1-2, wherein the capacitor portion (32) includes, in the planar view, a first overlap portion (55) overlapping the first external electrode (3), a second overlap portion (56) overlapping the second external electrode (4), and an intermediate portion (57) between the first external electrode (3) and the second external electrode (4).

[0200] According to this configuration, by arranging the capacitor section (32) in the region below the first external electrode (3) and the second external electrode (4), the capacitance of the capacitor section (32) can be increased.

[0201] [Appendix 1-4] The chip part (1) according to appendix 1-3, wherein the capacitor section (32) includes one each of the first capacitor section (321) and the second capacitor section (322) formed adjacent to each other.

[0202] [Appendix 1-5] The first capacitor portion (321) is formed across the first overlap portion (55) and the middle portion (57), The chip part (1) according to appendix 1-4, wherein the second capacitor portion (322) is formed across the second overlap portion (56) and the intermediate portion (57).

[0203] [Appendix 1-6] The capacitor unit (32) includes a pair of the first capacitor units (321) and a pair of the second capacitor units (322), The chip part (1) according to Supplementary Note 1-2 or Supplementary Note 1-3, wherein the pair of first capacitor portions (321) and the pair of second capacitor portions (322) are arranged alternately in the plan view.

[0204] [Appendix 1-7] The chip part (1) according to any one of Supplementary Notes 1-1 to 1-6, wherein the first longitudinal direction (D1) and the second longitudinal direction (D2) are directions perpendicular to each other.

[0205] With this configuration, the first longitudinal direction (D1) of the wall portion (85) of the first capacitor portion (321) and the second longitudinal direction (D2) of the wall portion (85) of the second capacitor portion (322) are perpendicular to each other, so that the stresses in the first capacitor portion (321) and the second capacitor portion (322) are applied in directions that cancel each other out, thereby further suppressing warping of the substrate (2).

[0206] [Appendix 1-8] The lower electrode (34) is formed outside the capacitor portion (32) and includes a first contact region (63) surrounding the capacitor portion (32); the upper electrode (36) includes a second contact region (69) that overlaps with the capacitor portion (32) in the plan view; a first electrode film (38) formed on the first main surface (5) of the substrate (2) and electrically connecting the first contact region (63) and the first external electrode (3); A chip component (1) according to any one of Appendices 1-2 to 1-7, further including a second electrode film (39) formed on the first main surface (5) of the substrate (2) and electrically connecting the second contact region (69) and the second external electrode (4).

[0207] According to this configuration, the first electrode film (38) is connected to the first contact region (63) surrounding the capacitor section (32), and the second electrode film (39) is connected to the second contact region (69) overlapping the capacitor section (32). This allows the first contact region (63) and the second contact region (69) to be effectively arranged on the first main surface (5) of the substrate (2). As a result, the contact area between the first electrode film (38) and the first contact region (63) and the contact area between the second electrode film (39) and the second contact region (69) can each be increased, thereby providing a chip component (1) with excellent electrical characteristics.

[0208] [Appendix 1-9] The substrate (2) is formed in a quadrangular shape in the plan view, surrounding the first main surface (5), and having a pair of first side surfaces (7) and second side surfaces (8) facing each other, and a pair of third side surfaces (9) and fourth side surfaces (10) facing each other, the first external electrode (3) being arranged on the first side surface (7) side, and the second external electrode (4) being arranged on the second side surface (8) side, the first electrode film (38) includes a first portion (45) that overlaps the first external electrode (3) in the plan view and extends along the first side surface (7) of the substrate (2), and a pair of second portions (46) that extend from one end and the other end of the first portion (45) of the first electrode film (38) along the third side surface (9) and the fourth side surface (10) of the substrate (2), respectively; The chip component (1) described in Appendix 1-8, wherein the second electrode film (39) includes a third portion (49) that overlaps the second external electrode (4) in the planar view, and a fourth portion (50) that extends from the third portion (49) of the second electrode film (39) toward the first external electrode (3) and is arranged in a region sandwiched between the pair of second portions (46) of the first electrode film (38).

[0209] [Appendix 1-10] The chip component (1) described in Appendix 1-9, wherein the first electrode film (38) includes a first capacitor contact portion (40) that is continuously formed along the first portion (45) of the first electrode film (38) and the pair of second portions (46) of the first electrode film (38) and is connected to the first contact region (63).

[0210] [Appendix 1-11] A chip component (1) according to Appendix 1-9 or Appendix 1-10, wherein the second electrode film (39) is formed in a shape that covers almost the entire capacitor portion (32) in the planar view and includes a second capacitor contact portion (42) connected to the second contact region (69).

[0211] [Appendix 1-12] The substrate (2) includes a semiconductor substrate (2), a first conductivity type base region (110) is formed on the first main surface (5) of the semiconductor substrate (2) so as to overlap the first external electrode (3) and the second external electrode (4) in the plan view; a first diode (88) including a second conductivity type impurity region (111) formed in the base region (110) below the first external electrode (3), and connected to the first electrode film (38); A chip component (1) according to any one of Appendices 1-9 to 1-11, further including a second conductivity type impurity region (112) formed in the base region (110) below the second external electrode (4), and a second diode (89) connected to the second electrode film (39).

[0212] According to this configuration, the formation of the first diode (88) and the second diode (89) can provide the chip component (1) with an ESD protection function.

[0213] [Appendix 1-13] the first diode (88) includes a plurality of diodes (88) arranged along the first side surface (7) of the substrate (2) in the plan view, The chip component (1) described in Appendix 1-12, wherein the second diode (89) includes a plurality of diodes (89) arranged along the second side surface (8) of the substrate (2) in the plan view.

[0214] [Appendix 1-14] the capacitive film (35) includes a covering portion (68) that is drawn outward from the capacitor portion (32), covers the first contact region (63), and surrounds the capacitor portion (32); A chip component (1) according to any one of Appendices 1-8 to 1-13, wherein the first contact region (63) and the covering portion (68) are extended outward from an edge (72) of the upper electrode (36) in the planar view, and have a common edge (71) positioned outward from the edge (72) of the upper electrode (36).

[0215] With this configuration, the edge 71 of the lower electrode 34 can be spaced apart from the edge 72 of the upper electrode 36, and the lower electrode 34 between the edge 72 of the upper electrode 36 and the edge 71 of the lower electrode 34 is covered with the capacitive film 35 (covering portion 68). This prevents short circuits between the lower electrode 34 and the upper electrode 36, thereby providing a chip component 1 with excellent insulation reliability.

[0216] [Appendix 1-15] a semiconductor substrate (202) having a first main surface (205) and a second main surface (206) opposite thereto; a capacitor portion (213) formed on the first main surface (205) of the semiconductor substrate (202) in a plan view seen from a normal direction (n) of the first main surface (205), the capacitor portion (213) having a plurality of wall portions (85) having a longitudinal direction separated from each other by trenches (107) formed in the first main surface (205); a substrate body portion (54) formed around the capacitor portion (213) using a part of the semiconductor substrate (202) and connected to at least one of one end portion (100) and the other end portion (101) in the longitudinal direction of the wall portion (85); a lower electrode (219) formed using at least a part of the semiconductor substrate (202) including the wall portion (85); a capacitive film (214) formed along the upper surface (114) and the side surface (115) of the wall portion (85); an upper electrode (215) formed on the capacitance film (214); The wall portion (85) is formed by a plurality of pillar units (90), and each of the pillar units (90) includes, in the plan view, a central portion (91) and three protruding portions (92) extending from the central portion (91) in three different directions, and the wall portion (85) is formed by connecting the protruding portions (92) of adjacent pillar units (90), The capacitor portion (213) includes, in the planar view, a first capacitor portion (321) including the wall portion (85) whose longitudinal direction is a first longitudinal direction (D1), and a second capacitor portion (322) including the wall portion (85) whose longitudinal direction is a second longitudinal direction (D2) that intersects the first longitudinal direction (D1), in a chip component (201).

[0217] According to this configuration, the wall portion (85) formed on the semiconductor substrate (202) is composed of a plurality of pillar units (90). Each pillar unit (90) includes, in a plan view, a central portion (91) and three protrusions (92) extending from the central portion (91) in three different directions. This allows the surface area of ​​the wall portion (85) to be larger than when the wall portion (85) is formed by connecting pillar units such as rectangular pillars. Furthermore, because the capacitor portion (213) is formed following the surface of the wall portion (85), the capacitance of the capacitor portion (213) is not limited by the planar size of the semiconductor substrate (202). Therefore, a large capacitance can be achieved by increasing the height of the wall portion (85). In other words, even if the planar size of the semiconductor substrate (202) is small, the capacitance of the capacitor portion (213) can be ensured to be large.

[0218] Furthermore, a wall portion (85) formed by connecting multiple pillar units (90) is more stable than pillar units that are independent of each other. Furthermore, at least one of the one end (100) and the other end (101) of the wall portion (85) is connected to the substrate main body portion (54) around the wall portion (85). This allows at least the wall portion (85) to be cantilevered laterally, thereby reinforcing the wall portion (85) against lateral forces. As a result, the stability of the wall portion (85) can be maintained even when the height of the wall portion (85) is increased, thereby improving the reliability of the device.

[0219] Furthermore, the capacitor section (213) includes a first capacitor section (321) and a second capacitor section (322) whose wall sections (85) have different longitudinal directions. This allows the direction of stress generated in the semiconductor substrate (202) by the formation of the wall sections (85) to be dispersed in multiple directions. As a result, warping of the semiconductor substrate (202) can be suppressed, and strength can be improved. As a result, a chip component (201) having a capacitor structure with excellent mechanical strength reliability can be provided.

[0220] [Appendix 1-16] a first external electrode (203) formed on the second main surface (206) of the semiconductor substrate (202) and electrically connected to the lower electrode (219); A chip component (201) according to Appendix 1-15, including a second external electrode (204) formed on the first main surface (205) of the semiconductor substrate (202) and electrically connected to the upper electrode (215).

[0221] According to this configuration, for example, the chip component (201) can be bonded to the mounting substrate (202) via the first external electrode (203) and wire-bonded to the second external electrode (204).

[0222] [Appendix 1-17] The chip part (201) according to Appendix 1-16, wherein the second external electrode (204) is formed in a shape that covers the entire capacitor portion (213) in the plan view.

[0223] [Appendix 1-18] The chip component (201) according to Appendix 1-16 or Appendix 1-17, wherein the capacitor portion (213) includes one each of the first capacitor portion (321) and the second capacitor portion (322) formed adjacent to each other.

[0224] [Appendix 1-19] The capacitor unit (213) includes a pair of the first capacitor units (321) and a pair of the second capacitor units (322), The chip part (201) according to Supplementary Note 1-16 or Supplementary Note 1-17, wherein the pair of first capacitor portions (321) and the pair of second capacitor portions (322) are arranged alternately in the plan view.

[0225] [Appendix 1-20] The chip part (201) according to any one of Supplementary Notes 1-15 to 1-19, wherein the first longitudinal direction (D1) and the second longitudinal direction (D2) are directions perpendicular to each other.

[0226] According to this configuration, the first longitudinal direction (D1) of the wall portion (85) of the first capacitor portion (321) and the second longitudinal direction (D2) of the wall portion (85) of the second capacitor portion (322) are perpendicular to each other. As a result, the stresses in the first capacitor portion (321) and the second capacitor portion (322) are applied in directions that cancel each other out, thereby further suppressing warping of the substrate (202).

[0227] [Appendix 2-1] a substrate (2) having a first main surface (5) and a second main surface (6) opposite to the first main surface; a first external electrode (3) and a second external electrode (4) formed on the first main surface (5) of the substrate (2) and spaced apart from each other; a capacitor portion (32) formed on the first main surface (5) of the substrate (2) in a plan view seen from a normal direction (n) of the first main surface (5), the capacitor portion (32) having a plurality of wall portions (85) having a longitudinal direction separated from one another by trenches (107) formed in the first main surface (5), and formed at least between the first external electrode (3) and the second external electrode (4); a frame portion (54) formed around the capacitor portion (32) using a part of the substrate (2) and surrounding the capacitor portion (32); a lower electrode (34) formed along an upper surface (114) and a side surface (115) of the wall portion (85) and including an extraction portion (63) extracted to the first main surface (5) in the frame portion (54); a capacitance film (35) formed on the lower electrode (34) along the upper surface (114) and side surface (115) of the wall portion (85); an upper electrode (36) formed on the capacitance film (35); a first electrode film (38) that electrically connects the first external electrode (3) and the lower electrode (34); a second electrode film (39) that electrically connects the second external electrode (4) and the upper electrode (36); The lead portion (63) includes a first portion (64) formed in a region between the first external electrode (3) and the second external electrode (4), the first electrode film (38) includes a first lower contact portion (74) connected to the first portion (64); The wall portion (85) is formed of a plurality of pillar units (90), and each of the pillar units (90) includes, in the plan view, a central portion (91) and three protrusions (92) extending from the central portion (91) in three different directions, and the wall portion (85) is formed by connecting the protrusions (92) of adjacent pillar units (90).

[0228] According to this configuration, the wall portion (85) formed on the substrate (2) is formed of a plurality of pillar units (90). Each pillar unit (90) includes, in a plan view, a central portion (91) and three protrusions (92) extending from the central portion (91) in three different directions. This allows the surface area of ​​the wall portion (85) to be larger than when the wall portion (85) is formed by connecting pillar units such as rectangular pillars. Furthermore, because the capacitor portion (32) is formed following the surface of the wall portion (85), the capacitance of the capacitor portion (32) is not limited by the planar size of the substrate (2). Therefore, a large capacitance can be achieved by increasing the height of the wall portion (85). In other words, even if the planar size of the substrate (2) is small, a large capacitance of the capacitor portion (32) can be ensured.

[0229] In addition, the first electrode film (38) is connected to the first portion (64) of the lower electrode (34) that is drawn out to the region between the first external electrode (3) and the second external electrode (4). This allows the first lower contact portion (74) to be effectively disposed using the region between the first external electrode (3) and the second external electrode (4). As a result, the contact area between the first electrode film (38) and the lower electrode (34) can be increased, thereby providing a chip component (1) with excellent electrical characteristics.

[0230] [Appendix 2-2] The lead portion (63) includes a second portion (65) formed in a region below the first external electrode (3), The chip part (1) according to Appendix 2-1, wherein the first electrode film (38) includes a second lower contact portion (75) connected to the second portion (65).

[0231] According to this configuration, the first electrode film (38) and the lower electrode (34) can also be connected via the second lower contact portion (75), thereby further increasing the contact area.

[0232] [Appendix 2-3] The substrate (2) is formed in a quadrangular shape in the plan view, surrounding the first main surface (5), and having a pair of first side surfaces (7) and second side surfaces (8) facing each other, and a pair of third side surfaces (9) and fourth side surfaces (10) facing each other, the first external electrode (3) being arranged on the first side surface (7) side, and the second external electrode (4) being arranged on the second side surface (8) side, The first portion (64) includes a pair of first portions (64) drawn out on both sides from the capacitor portion (32) toward the third side surface (9) and the fourth side surface (10), the first lower contact portions (74) are formed in the pair of first portions (64), respectively, and include a pair of strip-shaped first lower contact portions (74) extending along the third side surface (9) and the fourth side surface (10); The chip part (1) according to Appendix 2-2, wherein the second lower contact portion (75) includes a strip-shaped second lower contact portion (75) extending along the first side surface (7).

[0233] According to this configuration, the first electrode film (38) and the lower electrode (34) can be connected on at least three sides around the periphery of the capacitor section (32).

[0234] [Appendix 2-4] The chip component (1) described in Appendix 2-3, wherein the pair of first lower contact portions (74) are formed integrally with the second lower contact portion (75) and extend continuously from one end (76) and the other end (77) in the longitudinal direction of the second lower contact portion (75) toward the second external electrode (4).

[0235] [Appendix 2-5] the second electrode film (39) includes a second base portion (49) that overlaps the second external electrode (4) in the plan view and is connected to the second external electrode (4), and a second extension portion (50) that has a step (53) with respect to a peripheral edge (52) of the second base portion (49) and extends from the second base portion (49) toward the first external electrode (3), The chip component (1) according to any one of Appendices 2-2 to 2-4, wherein the first electrode film (38) includes a first base portion (45) that overlaps the first external electrode (3) in the planar view and is connected to the first external electrode (3) and the second lower contact portion (75), and a first extension portion (46) that extends from the first base portion (45) into the step (53) and is connected to the first lower contact portion (74).

[0236] [Appendix 2-6] The lead portion (63) includes a third portion (66) formed on the opposite side to the first external electrode (3), the first electrode film (38) includes a third lower contact portion (149) connected to the third portion (66); The chip component (1) according to any one of Appendices 2-2 to 2-5, wherein the first electrode film (38) is connected to the lower electrode (34) by an annular contact portion (74) that surrounds the capacitor portion (32) as a whole, by integrally forming the first lower contact portion (74), the second lower contact portion (75), and the third lower contact portion (149).

[0237] According to this configuration, the first electrode film (38) and the lower electrode (34) can be connected over the entire periphery of the capacitor section (32).

[0238] [Appendix 2-7] The capacitor unit (32) further includes a lattice portion (151) that divides the capacitor unit (32) into a plurality of portions in an inner region of the frame portion (54) in the plan view, the lower electrode (34) further includes a second lead portion (156) that is led out to the first main surface (5) in the lattice portion (151), The chip component (1) described in Appendix 2-6, wherein the first electrode film (38) further includes a lattice-shaped contact portion (157) connected to the second lead portion (156) and formed integrally with the annular contact portion (40).

[0239] According to this configuration, the first electrode film (38) and the lower electrode (34) can be connected not only around the entire periphery of the capacitor portion (32) but also in the lattice portion (151).

[0240] [Appendix 2-8] further including a linear portion (144) extending linearly from the lower region of the first external electrode (3) toward the second external electrode (4) in the plan view, the lower electrode (34) further includes a third lead portion (147) that is led out to the first main surface (5) in the linear portion (144), The chip component (1) according to any one of Appendix 2-2 to Appendix 2-5, wherein the first electrode film (38) further includes a linear contact portion (148) connected to the third extraction portion (147) and integrally formed with the second lower contact portion (75).

[0241] According to this configuration, the first electrode film (38) and the lower electrode (34) can be connected not only on at least three sides around the capacitor portion (32) but also at the linear portion (144).

[0242] [Appendix 2-9] the upper electrode (36) includes a flat portion (117) formed along the first main surface (5) of the substrate (2) outside the trench (107), the flat portion (117) having a shape that covers the capacitor portion (32) in the plan view; The chip component (1) according to any one of Supplementary Notes 2-1 to 2-8, wherein the second electrode film (39) includes an upper contact portion (42) connected to the flat portion (117).

[0243] [Appendix 2-10] The chip part (1) according to Appendix 2-9, wherein the upper contact portion (42) is formed in a shape that covers almost the entire capacitor portion (32) in the plan view.

[0244] According to this configuration, the upper contact portion (42) covers almost the entire capacitor portion (32), so that the contact area between the second electrode film (39) and the upper electrode (36) can be increased.

[0245] [Appendix 2-11] a substrate (2) formed in a quadrangular shape having a first main surface (5), a second main surface (6) opposite to the first main surface (5), a pair of first side surfaces (7) and second side surfaces (8) surrounding the first main surface (5) and facing each other in a first direction (X) in a plan view seen from a normal direction (n) of the first main surface (5), and a pair of third side surfaces (9) and fourth side surfaces (10) facing each other in a second direction (Y) intersecting the first direction (X); a first external electrode (3) and a second external electrode (4) formed on the first main surface (5) of the substrate (2) and spaced apart from each other in the first direction (X); a capacitor portion (32) formed on the first main surface (5) in the plan view, the capacitor portion (32) having a plurality of wall portions (85) having a longitudinal direction separated from each other by trenches (107) formed in the first main surface (5), and formed at least between the first external electrode (3) and the second external electrode (4); a lower electrode (34) including a first main body portion (62) formed along an upper surface (114) and a side surface (115) of the wall portion (85), and a first peripheral portion (63) integrally drawn from the first main body portion (62) to a periphery of the capacitor portion (32); a capacitance film (35) formed on the lower electrode (34) along the upper surface (114) and side surface (115) of the wall portion (85); an upper electrode (36) formed on the capacitance film (35); a first electrode film (38) including a first base portion (45) formed below the first external electrode (3) and a pair of first extension portions (46) branching and extending from the first base portion (45) on both sides of the capacitor portion (32) in the first direction (X), the first base portion (45) and the pair of first extension portions (46) being connected to the first surrounding portion (63); a second electrode film (39) including a second base portion (49) formed below the second external electrode (4) and a second extension portion (50) extending from the second base portion (49) to a region (48) between the pair of first extension portions (46), and at least the second extension portion (50) is connected to the upper electrode (36); The wall portion (85) is formed of a plurality of pillar units (90), and each of the pillar units (90) includes, in the plan view, a central portion (91) and three protrusions (92) extending from the central portion (91) in three different directions, and the wall portion (85) is formed by connecting the protrusions (92) of adjacent pillar units (90).

[0246] According to this configuration, the wall portion (85) formed on the substrate (2) is formed of a plurality of pillar units (90). Each pillar unit (90) includes, in a plan view, a central portion (91) and three protrusions (92) extending from the central portion (91) in three different directions. This allows the surface area of ​​the wall portion (85) to be larger than when the wall portion (85) is formed by connecting pillar units such as rectangular pillars. Furthermore, because the capacitor portion (32) is formed following the surface of the wall portion (85), the capacitance of the capacitor portion (32) is not limited by the planar size of the substrate (2). Therefore, a large capacitance can be achieved by increasing the height of the wall portion (85). In other words, even if the planar size of the substrate (2) is small, a large capacitance of the capacitor portion (32) can be ensured.

[0247] In addition, the first electrode film (38) is connected to the first peripheral portion (63) of the lower electrode (34). This allows the first lower contact portion (74) to be effectively arranged around the periphery of the capacitor portion (32), and the first electrode film (38) and the lower electrode (34) can be connected on at least three sides around the periphery of the capacitor portion (32). As a result, the contact area between the first electrode film (38) and the lower electrode (34) can be increased, making it possible to provide a chip component (1) with excellent electrical characteristics.

[0248] [Appendix 2-12] the upper electrode (36) includes a flat portion (117) formed along the first main surface (5) of the substrate (2) outside the trench (107), the flat portion (117) having a shape that covers the capacitor portion (32) in the plan view; The chip part (1) according to Appendix 2-11, wherein the second extension portion (50) of the second electrode film (39) is connected to the flat portion (117).

[0249] [Appendix 2-13] A chip component (1) described in Appendix 2-12, wherein the second extension portion (50) of the second electrode film (39) is formed over substantially the entire region (48) between the pair of first extension portions (46) in the plan view.

[0250] According to this configuration, the second electrode film (39) and the upper electrode (36) can be connected in an area that covers almost the entire capacitor portion (32), thereby increasing the contact area between the second electrode film (39) and the upper electrode (36).

[0251] [Appendix 2-14] the capacitive film (35) includes a second main body portion (67) in the capacitor portion (32) and a second peripheral portion (68) integrally drawn from the second main body portion (67) onto the first peripheral portion (63), A chip component (1) according to any one of Appendices 2-11 to 2-13, wherein a first capacitor contact hole (37) for connecting the first electrode film (38) and the lower electrode (34) is formed in the second peripheral portion (68).

[0252] [Appendix 2-15] A chip component (1) described in Appendix 2-14, wherein the first peripheral portion (63) of the lower electrode (34) and the second peripheral portion (68) of the capacitive film (35) are pulled outward from an edge (72) of the upper electrode (36) in the planar view, and have a common edge (71) located outward from the edge (72) of the upper electrode (36).

[0253] With this configuration, the edge 71 of the lower electrode 34 can be spaced apart from the edge 72 of the upper electrode 36, and the lower electrode 34 between the edge 72 of the upper electrode 36 and the edge 71 of the lower electrode 34 is covered with the capacitive film 35. This prevents short circuits between the lower electrode 34 and the upper electrode 36, thereby providing a chip component 1 with excellent insulation reliability.

[0254] [Appendix 2-16] A chip component (1) according to any one of Appendices 2-11 to 2-15, wherein the capacitor portion (32) includes, in the plan view, a first overlap portion (55) overlapping the first external electrode (3), a second overlap portion (56) overlapping the second external electrode (4), and an intermediate portion (57) between the first external electrode (3) and the second external electrode (4).

[0255] According to this configuration, by arranging the capacitor section (32) in the region below the first external electrode (3) and the second external electrode (4), the capacitance of the capacitor section (32) can be increased.

[0256] [Appendix 2-17] The substrate (2) includes a semiconductor substrate (2), a first conductivity type base region (110) is formed on the first main surface (5) of the semiconductor substrate (2) so as to overlap the first external electrode (3) and the second external electrode (4) in the plan view; a first diode (88) including a second conductivity type impurity region (111) formed in the base region (110) below the first external electrode (3), and connected to the first electrode film (38); A chip component (1) according to any one of Appendices 2-11 to 2-16, further including a second conductivity type impurity region (112) formed in the base region (110) below the second external electrode (4), and a second diode (89) connected to the second electrode film (39).

[0257] According to this configuration, the formation of the first diode (88) and the second diode (89) can provide the chip component (1) with an ESD protection function.

[0258] [Appendix 2-18] the first diode (88) includes a plurality of diodes (88) arranged along the second direction (Y) in the plan view, The chip part (1) according to Appendix 2-17, wherein the second diode (89) includes a plurality of diodes (89) arranged along the second direction (Y) in the plan view.

[0259] [Appendix 2-19] The chip component (1) according to any one of Appendices 2-1 to 2-18, wherein the capacitor portion (32) includes, in the plan view, a first capacitor portion (321) including the wall portion (85) whose longitudinal direction is a first longitudinal direction (D1), and a second capacitor portion (322) including the wall portion (85) whose longitudinal direction is a second longitudinal direction (D2) that intersects with the first longitudinal direction (D1).

[0260] According to this configuration, the capacitor section (32) includes a first capacitor section (321) and a second capacitor section (322) whose wall sections (85) have different longitudinal directions. This allows the direction of stress generated in the substrate (2) due to the formation of the wall sections (85) to be dispersed in multiple directions. As a result, warping of the substrate (2) can be suppressed, and strength can be improved. As a result, a chip component (1) having a capacitor structure with excellent mechanical strength reliability can be provided.

[0261] [Appendix 2-20] the first longitudinal direction (D1) and the second longitudinal direction (D2) are directions perpendicular to each other, A chip part (1) according to appendix 2-19, including one each of the first capacitor portion (321) and the second capacitor portion (322) formed adjacent to each other.

[0262] With this configuration, the first longitudinal direction (D1) of the wall portion (85) of the first capacitor portion (321) and the second longitudinal direction (D2) of the wall portion (85) of the second capacitor portion (322) are perpendicular to each other, so that the stresses in the first capacitor portion (321) and the second capacitor portion (322) are applied in directions that cancel each other out, thereby further suppressing warping of the substrate (2).

[0263] [Appendix 3-1] a substrate (2) having a first main surface (5) and a second main surface (6) opposite to the first main surface; a first external electrode (3) and a second external electrode (4) formed on the first main surface (5) of the substrate (2) and spaced apart from each other; a capacitor portion (32) formed on the first main surface (5) of the substrate (2) in a plan view seen from a normal direction (n) of the first main surface (5), the capacitor portion (32) having a plurality of wall portions (85) having a longitudinal direction separated from one another by trenches (107) formed in the first main surface (5), and formed at least between the first external electrode (3) and the second external electrode (4); a lower electrode (34) including a first main body portion (62) formed along an upper surface (114) and a side surface (115) of the wall portion (85), and a first peripheral portion (63) integrally drawn from the first main body portion (62) to a periphery of the capacitor portion (32); a capacitive film (35) formed on the lower electrode (34) along an upper surface (114) and a side surface (115) of the wall portion (85), the capacitive film including a second main body portion (67) in the capacitor portion (32) and a second peripheral portion (68) integrally drawn from the second main body portion (67) onto the first peripheral portion (63); an upper electrode (36) formed on the capacitance film (35); a first electrode film (38) that electrically connects the first external electrode (3) and the lower electrode (34); a second electrode film (39) that electrically connects the second external electrode (4) and the upper electrode (36); the first peripheral portion (63) and the second peripheral portion (68) are drawn outward from an edge (72) of the upper electrode (36) in the plan view, and have a common edge (71) positioned outward from the edge (72) of the upper electrode (36); The wall portion (85) is formed of a plurality of pillar units (90), and each of the pillar units (90) includes, in the plan view, a central portion (91) and three protrusions (92) extending from the central portion (91) in three different directions, and the wall portion (85) is formed by connecting the protrusions (92) of adjacent pillar units (90).

[0264] According to this configuration, the wall portion (85) formed on the substrate (2) is formed of a plurality of pillar units (90). Each pillar unit (90) includes, in a plan view, a central portion (91) and three protrusions (92) extending from the central portion (91) in three different directions. This allows the surface area of ​​the wall portion (85) to be larger than when the wall portion (85) is formed by connecting pillar units such as rectangular pillars. Furthermore, because the capacitor portion (32) is formed following the surface of the wall portion (85), the capacitance of the capacitor portion (32) is not limited by the planar size of the substrate (2). Therefore, a large capacitance can be achieved by increasing the height of the wall portion (85). In other words, even if the planar size of the substrate (2) is small, a large capacitance of the capacitor portion (32) can be ensured.

[0265] In addition, the edge 71 of the lower electrode 34 can be spaced apart from the edge 72 of the upper electrode 36, and the lower electrode 34 between the edge 72 of the upper electrode 36 and the edge 71 of the lower electrode 34 is covered with the capacitive film 35. This prevents short circuits between the lower electrode 34 and the upper electrode 36, thereby providing a chip component 1 with excellent insulation reliability.

[0266] [Appendix 3-2] The chip part (1) according to Appendix 3-1, wherein the second peripheral portion (68) of the capacitive film (35) is formed in a ring shape surrounding the capacitor portion (32) in the plan view.

[0267] [Appendix 3-3] the first electrode film (38) surrounds the capacitor portion (32) in the plan view, is formed in an open ring shape with a portion on the second external electrode (4) side being open, and includes a lower contact portion (40) connected to the first peripheral portion (63) of the lower electrode (34); The chip component (1) described in Appendix 3-1 or Appendix 3-2, wherein the second electrode film (39) includes an upper contact portion (42) connected to the upper electrode (36) in an inner region of the lower contact portion (40).

[0268] According to this configuration, the first electrode film (38) has a lower contact portion (40) around the capacitor portion (32), and the second electrode film (39) has an upper contact portion (42) in an area inside the lower contact portion (40). This allows the lower contact portion (40) and the upper contact portion (42) to be effectively arranged on the first main surface (5) of the substrate (2). As a result, the area of ​​the lower contact portion (40) and the area of ​​the upper contact portion (42) can each be increased, thereby providing a chip component (1) with excellent electrical characteristics.

[0269] [Appendix 3-4] functional elements (88, 89) other than capacitors are formed on the first main surface (5) of the semiconductor substrate (2) in a region overlapping with at least one of the first external electrode (3) and the second external electrode (4) in the plan view; The chip component (1) according to any one of Supplementary Notes 3-1 to 3-3, wherein the first external electrode (3) and the second external electrode (4) are electrically connected to the functional element (88, 89) as both terminals.

[0270] [Appendix 3-5] The substrate (2) includes a semiconductor substrate (2), The chip component (1) described in Appendix 3-4, wherein the functional element (88, 89) includes a diode (88, 89) having a base region (110) of a first conductivity type formed on the first main surface (5) of the semiconductor substrate (2) and an impurity region of a second conductivity type formed in the base region (110).

[0271] According to this configuration, the formation of the diodes (88, 89) can provide the chip components (1) with an ESD protection function.

[0272] [Appendix 3-6] the diodes (88, 89) include a first diode (88) overlapping the first external electrode (3) in the plan view and a second diode (89) overlapping the second external electrode (4) in the plan view, The chip component (1) according to appendix 3-5, wherein the first diode (88) and the second diode (89) form a bidirectional diode connected via the common base region (110).

[0273] [Appendix 3-7] The capacitor section (32) includes, in the plan view, a first overlapping section (55) overlapping the first external electrode (3), a second overlapping section (56) overlapping the second external electrode (4), and an intermediate section (57) between the first external electrode (3) and the second external electrode (4), The chip component (1) according to any one of Supplementary Notes 3-4 to 3-6, wherein the functional elements (88, 89) are arranged at a position away from the capacitor section (32) in the opposing direction of the first external electrode (3) and the second external electrode (4).

[0274] According to this configuration, the capacitance of the capacitor section (32) can be increased by disposing the capacitor section (32) in the region below the first external electrode (3) and the second external electrode (4). In addition, by separating the capacitor section (32) from the functional elements (88, 89), electrical and mechanical influences between the capacitor section (32) and the functional elements (88, 89) can be reduced.

[0275] [Appendix 3-8] The substrate (2) is a semiconductor substrate (2) of a first conductivity type formed in a quadrangular shape, in the plan view, surrounding the first main surface (5) and having a pair of first side surfaces (7) and second side surfaces (8) opposing each other, and a pair of third side surfaces (9) and fourth side surfaces (10) opposing each other, and the first external electrode (3) is arranged on the first side surface (7) side, and the second external electrode (4) is arranged on the second side surface (8) side, the first electrode film (38) includes a lower contact portion (40) connected to the first peripheral portion (63) in a region below the first external electrode (3); the second electrode film (39) includes an upper contact portion (42) connected to the upper electrode (36); a first diode (88) including a second conductivity type impurity region (111) formed in the semiconductor substrate (2) between the lower contact portion (40) and the first side surface (7) in the plan view; a second diode (89) including a second conductivity type impurity region (112) formed in the semiconductor substrate (2) between the upper contact portion (42) and the second side surface (8) in the plan view, the first electrode film (38) includes a first diode contact portion (41) connected to the first diode (88); The chip component (1) according to any one of Supplementary Notes 3-1 to 3-3, wherein the second electrode film (39) includes a second diode contact portion (43) connected to the second diode (89).

[0276] [Appendix 3-9] The chip component (1) described in Appendix 3-8, wherein the first diode (88) includes a plurality of first diodes (88) arranged along the first side surface (7) of the semiconductor substrate (2).

[0277] [Appendix 3-10] The chip component (1) described in Appendix 3-8 or Appendix 3-9, wherein the second diode (89) includes a plurality of second diodes (89) arranged along the second side surface (8) of the semiconductor substrate (2).

[0278] [Appendix 3-11] The first external electrode (3) is formed in a rectangular shape having a first long side (15), a second long side (16), a first short side (17), and a second short side (18) whose longitudinal direction is along the first side surface (7) in the plan view, the first long side (15) is the long side closest to the first side surface (7), and the long side opposite thereto is the second long side (16), The chip component (1) according to any one of Appendices 3-8 to 3-10, wherein the first diode (88) is formed so as to overlap a first outer peripheral edge (58) along the first long side (15) of the first external electrode (3).

[0279] [Appendix 3-12] The second external electrode (4) is formed in a rectangular shape having a third long side (20), a fourth long side (21), a third short side (22) and a fourth short side (23) whose longitudinal direction is along the second side surface (8) of the semiconductor substrate (2) in the plan view, the third long side (20) is the long side closest to the second side surface (8) and the long side opposite thereto is the fourth long side (21); A chip component (1) described in Appendix 3-11, wherein the second diode (89) is formed so as to overlap a second outer peripheral edge (60) along the third long side (20) of the second external electrode (4).

[0280] [Appendix 3-13] The first external electrode (3) includes a first inner peripheral edge (59) along the second long side (16) and opposite the first outer peripheral edge (58), The second external electrode (4) includes a second inner peripheral portion (61) along the fourth long side (21) and opposite to the second outer peripheral portion (60), The chip component (1) described in Appendix 3-12, wherein the capacitor portion (32) includes, in the plan view, a first peripheral portion (55) that overlaps the first inner peripheral portion (59) and a second peripheral portion (56) that overlaps the second inner peripheral portion (61).

[0281] [Appendix 3-14] A chip component (1) according to any one of Appendices 3-8 to 3-13, wherein the first electrode film (38) includes a first base portion (45) formed below the first external electrode (3) and having the first diode contact portion (41), and a pair of first extension portions (46) branching and extending from the first base portion (45) on both sides of the capacitor portion (32) in a direction along the third side surface (9) and the fourth side surface (10).

[0282] According to this configuration, the first electrode film (38) and the lower electrode (34) can be connected on at least three sides around the periphery of the capacitor section (32).

[0283] [Appendix 3-15] The chip component (1) described in Appendix 3-14, wherein the second electrode film (39) includes a second base portion (49) formed below the second external electrode (4) and having the second diode contact portion (43), and a second extension portion (50) extending from the second base portion (49) to a region (48) between the pair of first extension portions (46) and having the upper contact portion (42).

[0284] [Appendix 3-16] A chip component (1) described in Appendix 3-14 or Appendix 3-15, wherein the lower contact portion (40) includes a pair of strip-shaped first lower contact portions (74) formed on each of the pair of first extension portions (46) and extending along the third side surface (9) and the fourth side surface (10), and a strip-shaped second lower contact portion (75) extending along the first side surface (7) in the first base portion (45).

[0285] [Appendix 3-17] A chip component (1) described in Appendix 3-16, wherein the pair of first lower contact portions (74) are formed integrally with the second lower contact portion (75) and extend continuously from one end (76) and the other end (77) in the longitudinal direction of the second lower contact portion (75) toward the second external electrode (4).

[0286] [Appendix 3-18] The chip component (1) according to any one of Supplementary Notes 3-8 to 3-17, wherein the upper contact portion (42) is formed so as to avoid an area that overlaps with the first external electrode (3) in the plan view.

[0287] [Appendix 3-19] The chip component (1) according to any one of Appendices 3-1 to 3-18, wherein the capacitor portion (32) includes, in the plan view, a first capacitor portion (321) including the wall portion (85) whose longitudinal direction is a first longitudinal direction (D1), and a second capacitor portion (322) including the wall portion (85) whose longitudinal direction is a second longitudinal direction (D2) that intersects with the first longitudinal direction (D1).

[0288] According to this configuration, the capacitor section (32) includes a first capacitor section (321) and a second capacitor section (322) whose wall sections (85) have different longitudinal directions. This allows the direction of stress generated in the substrate (2) due to the formation of the wall sections (85) to be dispersed in multiple directions. As a result, warping of the substrate (2) can be suppressed, and strength can be improved. As a result, a chip component (1) having a capacitor structure with excellent mechanical strength reliability can be provided.

[0289] [Appendix 3-20] the first longitudinal direction (D1) and the second longitudinal direction (D2) are directions perpendicular to each other, A chip part (1) according to appendix 3-19, including one each of the first capacitor portion (321) and the second capacitor portion (322) formed adjacent to each other.

[0290] With this configuration, the first longitudinal direction (D1) of the wall portion (85) of the first capacitor portion (321) and the second longitudinal direction (D2) of the wall portion (85) of the second capacitor portion (322) are perpendicular to each other, so that the stresses in the first capacitor portion (321) and the second capacitor portion (322) are applied in directions that cancel each other out, thereby further suppressing warping of the substrate (2). [Explanation of symbols]

[0291] 1: Chip parts 2: Circuit board 3 :1st external electrode 4: 2nd external electrode 5: First main surface 6: Second main surface 7 :1st side 8:Second side 9:Third side 10: 4th side 11:First end 12:Second end 13: Insulating space 14: First insulating edge 15: First long side 16: Second long side 17: First short side 18: Second short side 19: Second insulating edge 20: Third long side 21: Fourth long side 22: Third short side 23: Fourth short side 24: 1st electrode surface 25: 2nd electrode surface 26: Concave and convex structure 27: Recess 28:Protrusion 29: Inspection protrusion 30: Capacitor structure 31: Electrode membrane 32: Capacitor section 33: Diode section (functional element section) 34: Lower electrode 35: Capacitive membrane 36: Upper electrode 37: First capacitor contact hole 38:First electrode film 39:Second electrode film 40: Lower contact part 41: First diode contact portion 42: Upper contact part 43: Second diode contact portion 44: Dividing line 45: First base part 46: 1st extension part 47: First external contact part 48: Acceptance area 49: Second base part 50:Second extension part 51: Second external contact part 52: Periphery 53: Step 54: Main board part 55: First overlap section 56: Second overlap section 57: Middle part 58: First outer periphery 59: First inner periphery 60: Second outer periphery 61: Second inner periphery 62: First main body part 63: First peripheral part 64 :1st part 65:Second part 66: 3rd part 67: Second main body part 68: Second peripheral part 69: Main body 70: Periphery 71: Edge 72: Edge 73: Containment Area 74: First lower contact part 75: Second lower contact part 76:One end 77:Other end 78: First end 79:Second end 80: First peripheral portion 81: Second peripheral part 82: Periphery 83: First peripheral part 84: Second peripheral part 85: Wall 86: Boundary 87: Support part 88: First diode 89: Second diode 90: Column unit 91: Central part 92: Convex part 93: 1st wall part 94:Second wall 95: First subject 96: First branch 97: First convex part 98: Second convex part 99: Third convex part 100: One end 101:Other end 102: Second subject 103: Second branch 104: 4th convex part 105: 5th convex part 106: 6th convex part 107: Trench 108: First trench 109: Second trench 110: Base area 111: First impurity region 112:Second impurity region 113: insulating film 114:Top surface 115: Side 116: Embedded part 117: Flat part 118: First insulating film 119: Second insulating film 120: Second capacitor contact hole 121: First diode contact hole 122: Second diode contact hole 123: Surface insulating film 124 :1st part 125 :Second part 126: Surface protective film 127: First pad 128: Second pad 129: First pad opening 130: Second pad opening 131: First covering part 132: Second coating part 133: Wafer 134: First conductive film 135: Intermediate insulating film 136: Second conductive film 137: Trench 138: Side 139: Bottom 140: 1st diagonal 141: 2nd diagonal 142: First upper contact part 143: Second upper contact part 144: Straight section 145 :1st part 146:Second part 147: 4th part 148: Linear contact part 149: Third lower contact part 150: Third insulating film 151: Lattice part 152 :1st part 153:Second part 154: 3rd part 155: 4th part 156: 5th part 157: Lattice contact part 158 :Area 159: Diode region 160: Diode region 201: Chip parts 202: Substrate 203: 1st external electrode 204: 2nd external electrode 205: First main surface 206: Second main surface 207 :1st side 208:Second side 209:Third side 210: 4th side 211: Edge 212: Insulating space 213: Capacitor section 214: Capacitive membrane 215: Upper electrode 216: Embedded part 217: Flat part 218: Periphery 219: Lower electrode 220: Capacitor structure 221: Surface insulating film 222: Capacitor contact hole 223 :1st layer 224: 2nd layer 225: 3rd layer 226: Wafer 321: First capacitor section 322: Second capacitor section 331: First diode section 332: Second diode section D1: First longitudinal direction D2: Second longitudinal direction Di1: First Zener diode Di2: Second Zener diode S1: Chip parts S10: Chip parts S2: Chip parts S3: Chip parts S4: Chip parts S5: Chip parts S6: Chip parts S7: Chip parts S8: Chip parts S9: Chip parts T1: Thickness T6: Thickness W1: Width W2: Width W3:Width W4: Width W5:Width W6:Width X: 1st direction Y: Second direction Z: 3rd direction n:Normal direction θ1 :Angle θ2 :Angle θ3: Angle

Claims

1. a substrate having a first major surface and an opposite second major surface; a capacitor section formed on the first main surface in a plan view seen from a normal direction of the first main surface of the substrate, the capacitor section having a plurality of wall sections having a longitudinal direction separated from one another by trenches formed in the first main surface; a substrate body portion formed around the capacitor portion using a part of the substrate and connected to at least one of one end and the other end of the wall portion in the longitudinal direction; a lower electrode formed along an upper surface and a side surface of the wall portion and including a first contact region extended to the first main surface in the substrate body portion; a capacitance film formed on the lower electrode along the upper surface and side surface of the wall portion; an upper electrode formed on the capacitance film, The wall portion is formed by a plurality of pillar units, and each pillar unit includes, in the plan view, a central portion and three protruding portions extending from the central portion in three different directions, and the wall portion is formed by connecting the protruding portions of adjacent pillar units, the capacitor section includes, in the plan view, a first capacitor section including the wall section whose longitudinal direction is a first longitudinal direction, and a second capacitor section including the wall section whose longitudinal direction is a second longitudinal direction intersecting the first longitudinal direction, a first external electrode formed on the first main surface of the substrate and electrically connected to the lower electrode; a second external electrode formed on the first main surface of the substrate at a distance from the first external electrode and electrically connected to the upper electrode, the first external electrode is electrically connected to the first contact region at least in a region that avoids a region below the second external electrode; the first contact region surrounds the capacitor portion, the upper electrode includes a second contact region that overlaps with the capacitor portion in the plan view; a first electrode film formed on the first main surface of the substrate and electrically connecting the first contact region and the first external electrode; a second electrode film formed on the first main surface of the substrate and electrically connecting the second contact region and the second external electrode;

2. 2. The chip component according to claim 1, wherein the capacitor portion includes, in the planar view, a first overlap portion overlapping the first external electrode, a second overlap portion overlapping the second external electrode, and an intermediate portion between the first external electrode and the second external electrode.

3. The chip part according to claim 2 , wherein the capacitor section includes one each of the first capacitor section and the second capacitor section formed adjacent to each other.

4. the first capacitor portion is formed across the first overlap portion and the intermediate portion, The chip component according to claim 3 , wherein the second capacitor portion is formed across the second overlap portion and the intermediate portion.

5. the capacitor unit includes a pair of the first capacitor units and a pair of the second capacitor units, The chip part according to claim 1 , wherein the pair of first capacitor portions and the pair of second capacitor portions are arranged alternately in the plan view.

6. 6. The chip part according to claim 1, wherein the first longitudinal direction and the second longitudinal direction are perpendicular to each other.

7. the substrate is formed in a quadrangular shape in the plan view, surrounding the first main surface, and having a pair of first and second side surfaces opposed to each other, and a pair of third and fourth side surfaces opposed to each other, the first external electrode being disposed on the first side surface side, and the second external electrode being disposed on the second side surface side, the first electrode film includes a first portion that overlaps the first external electrode in the plan view and extends along the first side surface of the substrate, and a pair of second portions that extend from one end and the other end of the first portion of the first electrode film along the third side surface and the fourth side surface of the substrate, A chip component according to any one of claims 1 to 6, wherein the second electrode film includes a third portion that overlaps the second external electrode in the planar view, and a fourth portion that extends from the third portion of the second electrode film toward the first external electrode and is positioned in a region sandwiched between the pair of second portions of the first electrode film.

8. 8. The chip component of claim 7, wherein the first electrode film is formed continuously along the first portion of the first electrode film and the pair of second portions of the first electrode film, is connected to the first contact area, and includes a first capacitor contact portion formed in an approximately U-shape with the second external electrode side open relative to the capacitor portion.

9. 9. The chip component of claim 8, wherein the first capacitor contact portion is formed in a region between the first external electrode and the second external electrode, is strip-shaped extending parallel to the third side surface and the fourth side surface of the substrate, and includes a pair of first lower contact portions sandwiching the capacitor portion, and a strip-shaped second lower contact portion extending parallel to the first side surface of the substrate in a region below the first external electrode.

10. the first contact region surrounds the capacitor portion as a closed region, and includes a first portion formed in a region between the first external electrode and the second external electrode, a second portion formed in a region below the first external electrode, and a third portion formed in a region below the second external electrode; the pair of first lower contact portions are formed in the first portion, and the second lower contact portion is formed in the second portion; 10. The chip part according to claim 9, wherein the third portion does not have a contact portion with the first electrode film.

11. A chip component described in any one of claims 7 to 10, wherein the second electrode film is formed in a shape that covers almost the entire capacitor portion in the planar view and includes a second capacitor contact portion connected to the second contact region.

12. the substrate includes a semiconductor substrate; a first conductivity type base region overlapping the first external electrode and the second external electrode in the plan view is formed on the first main surface of the semiconductor substrate; a first diode including a second conductivity type impurity region formed in the base region below the first external electrode and connected to the first electrode film; A chip component according to any one of claims 7 to 11, further comprising a second diode connected to the second electrode film and including a second conductivity type impurity region formed in the base region below the second external electrode.

13. the first diode includes a plurality of diodes arranged along the first side surface of the substrate in the plan view; The chip part according to claim 12 , wherein the second diode includes a plurality of diodes arranged along the second side surface of the substrate in the plan view.

14. the capacitive film includes a covering portion that is drawn outward from the capacitor portion, covers the first contact region, and surrounds the capacitor portion; A chip component described in any one of claims 6 to 13, wherein the first contact region and the covering portion, when viewed in the plane, are extended outward from the edge of the upper electrode and have a common edge located outward from the edge of the upper electrode.

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