Integrated assembly and method of forming an integrated assembly - Patent Application 20070122997

Abstract

To provide improved methods of forming interconnects in a staircase region of an integrated assembly.SOLUTION: Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels contain conductive material, and the second levels contain insulative material. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels over an associated one of the first levels. A layer is over the steps and is separated from the stack by an intervening insulative region. Insulative material is over the layer. Conductive interconnects extend through the insulative material, through the layer, through the intervening insulative region and to the conductive material within the first levels of the steps. Some embodiments include methods of forming integrated assemblies.SELECTED DRAWING: Figure 15

Description

[Technical Field]

[0001] [Related patent data] This application is related to U.S. patent application Ser. No. 16 / 872,598, filed May 12, 2020, entitled "Integrated Assemblies and Methods of Forming Integrated Assemblies," which is hereby incorporated by reference in its entirety.

[0002] [Technical field] Integrated assemblies (eg, memory arrays) and methods of forming integrated assemblies. [Background technology]

[0003] Memory provides data storage for electronic systems. Flash memory is a type of memory that has many uses in modern computers and devices. As an illustration, modern personal computers may have their BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid-state drives to replace traditional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it allows manufacturers to support new communication protocols as they become standardized and provides the ability to remotely upgrade devices for enhanced features.

[0004] NAND may be the basic architecture of flash memory and may be configured to include vertically stacked memory cells.

[0005] Before describing NAND specifically, it may be helpful to more generally describe the relationship of memory arrays within an integrated array. FIG. 1 shows a block diagram of a prior art device 1000 including a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns, along with access lines 1004 (e.g., word lines WL0-WLm for conducting signals) and first data lines 1006 (e.g., bit lines BL0-BLn for conducting signals). The access lines 1004 and first data lines 1006 can be used to transfer information to and from the memory cells 1003. Row decoder 1007 and column decoder 1008 decode address signals A0-AX on address lines 1009 to determine which one of the memory cells 1003 is being accessed. Sense amplifier circuitry 1015 operates to determine the value of information read from the memory cells 1003. I / O circuitry 1017 transfers information values ​​between the memory array 1002 and input / output (I / O) lines 1005. Signals DQ0-DQN on I / O lines 1005 may represent information values ​​to be read from or written into memory cells 1003. Other devices may communicate with device 1000 through I / O lines 1005, address lines 1009, or control lines 1020. Memory control unit 1018 is used to control memory operations performed on memory cells 1003 and utilizes signals on control line 1020. Device 1000 may receive supply voltage signals Vcc and Vss on first supply line 1030 and second supply line 1032, respectively. Device 1000 includes selection circuitry 1040 and input / output (I / O) circuitry 1017. Selection circuitry 1040 may respond to signals CSEL1-CSELn via I / O circuitry 1017 to select signals on first data lines 1006 and second data lines 1013, which may represent information values ​​to be read from or programmed into memory cells 1003. Column decoder 1008 may selectively activate the CSEL1-CSELn signals based on address signals A0-AX on address lines 1009.Selection circuitry 1040 can select signals on first data line 1006 and second data line 1013 to provide communication between memory array 1002 and I / O circuitry 1017 during read and programming operations.

[0006] The memory array 1002 of FIG. 1 may be a NAND memory array, and FIG. 2 shows a schematic diagram of a three-dimensional NAND memory device 200 that may be utilized in the memory array 1002 of FIG. 1. The device 200 includes multiple strings of charge storage devices. In a first direction (ZZ'), each string of charge storage devices may include, for example, 32 charge storage devices stacked on top of each other, with each charge storage device corresponding to, for example, one of 32 tiers (tier 0 through tier 31). The charge storage devices of individual strings may share a common channel region, such as those formed within individual pillars of semiconductor material (e.g., polysilicon) near which the strings of charge storage devices are formed. In a second direction (XX'), for example, each of 16 first groups of multiple strings may include, for example, eight strings that share multiple (e.g., 32) access lines (i.e., "global control gate (CG) lines," also known as word lines, WL). Each of the access lines may couple the charge storage devices within a tier. Charge storage devices coupled by the same access line (and therefore corresponding to the same tier) may be logically grouped into two pages, such as P0 / P32, P1 / P33, and P2 / P34, for example, when each charge storage device includes a cell capable of storing two bits of information. In the third direction (YY'), for example, each of eight second groups of strings may include 16 strings coupled by a corresponding one of eight data lines. The size of a memory block may include 1,024 pages and a total of approximately 16 MB (e.g., 16 WL × 32 tiers × 2 bits = 1,024 pages / block, block size = 1,024 pages × 16 KB / page = 16 MB). The number of strings, tiers, access lines, data lines, first groups, second groups, and / or pages may be greater or less than those shown in FIG. 2 .

[0007] 3 illustrates a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of FIG. 2 in the XX′ direction, including 15 strings of charge storage devices in one of the 16 first groups of strings described with respect to FIG. 2. The multiple strings of memory block 300 are arranged in tile columns. I , tile column J , and tile columns KThe memory blocks 300 may be grouped into multiple subsets 310, 320, 330 (e.g., tile columns), such as 310, 320, 330, etc., with each subset (e.g., tile column) including a "partial block" of the memory block 300. A global drain-side select gate (SGD) line 340 may be coupled to the SGDs of multiple strings. For example, the global SGD line 340 may be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via a corresponding one of multiple (e.g., three) sub-SGD drivers 332, 334, 336, with each sub-SGD line corresponding to a separate subset (e.g., tile column). Each of the sub-SGD drivers 332, 334, 336 may simultaneously couple or decouple the SGDs of the strings in the corresponding partial block (e.g., tile column), independently of those of the other partial blocks. A global source-side select gate (SGS) line 360 ​​may be coupled to the SGSs of multiple strings. For example, a global SGS line 360 ​​may be coupled to multiple sub-SGS lines 362, 364, and 366, each corresponding to a separate subset (e.g., a tile column), via a corresponding one of multiple sub-SGS drivers 322, 324, and 326. Each of the sub-SGS drivers 322, 324, and 326 may simultaneously couple or disconnect the SGS of the strings of the corresponding partial block (e.g., a tile column) independently of those of the other partial blocks. A global access line (e.g., global CG line) 350 may couple charge storage devices corresponding to separate tiers of each of the multiple strings. Each global CG line (e.g., global CG line 350) may be coupled to multiple sub-access lines (e.g., sub-CG lines) 352, 354, and 356 via a corresponding one of multiple sub-string drivers 312, 314, and 316. Each of the substring drivers can simultaneously couple or decouple the charge storage devices corresponding to individual partial blocks and / or tiers independently of those of other partial blocks and / or other tiers. The charge storage devices corresponding to individual subsets (e.g., partial blocks) and individual tiers can comprise a "partial tier" (e.g., a single "tile") of charge storage devices.Strings corresponding to individual subsets (e.g., partial blocks) may be coupled to corresponding ones of sub-sources 372, 374, and 376 (e.g., "tile sources"), with each sub-source coupled to a separate power supply.

[0008] The NAND memory device 200 is alternatively described with reference to the schematic diagram of FIG.

[0009] The memory array 200 includes word lines 2021 to 2022. N , and bit lines 2281 to 228 M Includes:

[0010] The memory array 200 also includes NAND strings 2061-2066. M Each NAND string includes charge storage transistors 2081 to 2088. N Charge storage transistors may use a floating gate material (e.g., polysilicon) to store charge, or may use a charge trapping material (e.g., silicon nitride, metal nanodots, etc.) to store charge.

[0011] Charge storage transistors 208 are located at the intersections of word lines 202 and strings 206. The charge storage transistors 208 represent non-volatile memory cells for data storage. The charge storage transistors 208 of each NAND string 206 are connected in series from source to drain between a source select device (e.g., source side select gate, SGS) 210 and a drain select device (e.g., drain side select gate, SGD) 212. Each source select device 210 is located at the intersection of a string 206 and a source select line 214, while each drain select device 212 is located at the intersection of a string 206 and a drain select line 215. The select devices 210 and 212 may be any suitable access devices and are generally described using boxes in FIG. 4 .

[0012] The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the drain of the source select device 2101 is connected to the source of the charge storage transistor 2081 of the corresponding NAND string 2061. The source select devices 210 are connected to a source select line 214.

[0013] The drain of each drain select device 212 is connected at its drain contact to a bit line (i.e., digit line) 228. For example, the drain of drain select device 2121 is connected to bit line 2281. The source of each drain select device 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain select device 2121 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. N is connected to the drain of the

[0014] The charge storage transistors 208 include a source 230, a drain 232, a charge storage region 234, and a control gate 236. The charge storage transistors 208 have their control gates 236 coupled to a word line 202. A column of charge storage transistors 208 is those transistors in the NAND string 206 that are coupled to a given bit line 228. A row of charge storage transistors 208 is those transistors that are commonly coupled to a given word line 202.

[0015] 5 and 6 illustrate the general layout of a conventional integrated assembly, with FIG. 5 showing a top view of an area of ​​the assembly and FIG. 6 showing a cross-sectional side view of an area of ​​the assembly.

[0016] Referring to FIG. 5, assembly 10 includes a memory array region 12 (memory array) adjacent to a staircase region 14 (staircase).

[0017] The memory array region 12 includes channel material pillars 16 arranged in a dense pattern (e.g., a hexagonal packed pattern). The channel material pillars extend through the conductive tiers (described below with reference to FIG. 6). The staircase region 14 includes interconnect regions 18 through which electrical contact is made to individual tiers. Each of the interconnect regions may be utilized to establish interconnections to a particular set of tiers. By way of illustration, FIG. 5 shows that each of the interconnect regions is utilized to establish interconnections to eight tiers, with one of the regions utilized to couple with tiers 1-8 and another of the regions utilized to couple with tiers 9-16. Any suitable number of interconnect regions 18 may be utilized, and such interconnect regions may be utilized to couple with any suitable number of conductive tiers.

[0018] 6 shows a cross-sectional side view of regions 12 and 14. A stack 20 of alternating first and second levels 22 and 24 extends into regions 12 and 14. Level 22 includes a conductive material 26, and level 24 includes an insulating material 28. In the illustrated embodiment, a dielectric barrier material 30 extends along the conductive material 26 of level 22.

[0019] The levels 22 may be considered to include conductive tiers, which correspond to the conductive material 26 within those levels. Any suitable number of conductive tiers may be utilized, for example, 8, 16, 32, 64, 128, 256, 512, 1024, etc.

[0020] Channel material pillar 16 extends through stack 20 in memory array region 12. The channel material pillar includes channel material 32 (indicated by stippled lines). The channel material is separated from stack 20 by intervening regions 34. These regions include charge blocking material 36, charge trapping material 38, and gate dielectric material 40.

[0021] In the described embodiment, the channel material pillar 16 is configured as an annular ring surrounding the insulating material 33. This may be considered a hollow channel configuration, with the insulating material 33 within the "hollow" of the channel material pillar 16. In other applications, the channel material pillar 16 may be solid rather than hollow.

[0022] The stepped region 14 includes conductive interconnects 42 that extend into the conductive material 26 of the individual tiers 22. The conductive interconnects extend through an insulating filler material 44.

[0023] The source structure 46 is shown as being below the stacks 20 in the memory array region 12. The source structure may or may not extend below the stacks 20 in the staircase region 14.

[0024] The channel material 32 is shown electrically coupled to the source structure 46 .

[0025] Memory cells 48 are located along conductive level 22 in memory array region 12, and each memory cell includes a channel material 32, a gate dielectric material 40, a charge trapping material 38, a charge blocking material 36, and portions of dielectric barrier material 30. The memory cells also include a region of conductive material 26 in conductive tier 22. The region of conductive material 26 in memory cell 48 may be considered a gate region 50. Other regions of conductive material 26 may be considered routing regions (wordline regions) 52 that couple the gate region with other regions. Routing regions 52 extend to interconnects 42 in staircase region 14.

[0026] A source side select gate (SGS) 54 may be between the memory cell 48 and the source structure 46 .

[0027] The channel material 32 may be coupled to a bit line 54 through a drain side select gate (SGD) 56 .

[0028] The base 58 supports the structures of the memory array region 12 and the staircase region 14. The base 58 may be part of a semiconductor die. The base 58 may include a semiconductor material, for example, may include, consist essentially of, or consist of monocrystalline silicon. The base 58 may be referred to as a semiconductor substrate. The term "semiconductor substrate" refers to any structure including semiconductor material, including, but not limited to, bulk semiconductor material such as a semiconductor wafer (either alone or in an assembly with other materials) and a semiconductor material layer (either alone or in an assembly with other materials). The term "substrate" refers to any support structure, including, but not limited to, the semiconductor substrates described above. In some applications, the base 58 may correspond to a semiconductor substrate including one or more materials associated with the fabrication of integrated circuits. Such materials may include, for example, one or more of a refractory metal material, a barrier material, a diffusion material, an insulator material, etc.

[0029] Logic circuits 60 and 62 are shown supported by bases. Such logic circuits may include, for example, CMOS. In the illustrated application, logic circuit 60 includes sense amplifier circuitry (sense amp) and is electrically coupled to bit lines 54, and logic circuit 62 includes word line driver circuitry (word line driver) and is electrically coupled to word line level (access level) 22 through interconnects 42. Summary of the Invention [Problem to be solved by the invention]

[0030] Forming interconnects 42 within staircase region 14 can be difficult. Forming interconnects 42 in very deep tiers can be particularly difficult due to the high aspect ratio of the deep openings used to reach the deep tiers. It would be desirable to develop improved methods for forming interconnects 42. [Means for solving the problem]

[0031] An embodiment of an integrated assembly includes a stack of alternating first and second levels, the first level including a conductive material and the second level including an insulating material, at least some of the first and second levels configured as steps, each of the steps including one of the second levels above an associated one of the first levels; a layer above the step and separated from the stack by an intervening insulating region; insulating material above the layer; and a conductive interconnect extending through the insulating material, through the layer, through the intervening insulating region, to the conductive material in the first level of the step. [Brief explanation of the drawings]

[0032] [Figure 1] 1 shows a block diagram of a prior art memory device having a memory array with memory cells; [Figure 2] 2 shows a schematic diagram of the prior art memory array of FIG. 1 in the form of a 3D NAND memory device. [Figure 3] 3 shows a cross-sectional view of the prior art 3D NAND memory device of FIG. 2 in the direction XX′. [Figure 4] FIG. 1 is a schematic diagram of a prior art NAND memory array. [Figure 5] 1 is a schematic top view of an area of ​​a prior art integrated assembly. [Figure 6] FIG. 6 is a schematic cross-sectional side view of a region of the prior art assembly of FIG. 5. [Figure 7] 1A-1C are schematic cross-sectional side views of regions of an exemplary structure at exemplary process stages of an exemplary method. [Figure 7A] 8 is a schematic cross-sectional side view of another region of the exemplary structure of FIG. 7 at the same processing stage as FIG. [Figure 8] 8A-8C are schematic cross-sectional side views of a region of the example structure of FIG. 7 at successive process stages of an example method. The process stage of FIG. 8 may follow the process stage of FIG. [Figure 9]8A-8C are schematic cross-sectional side views of a region of the example structure of FIG. 7 at successive process stages of an example method. [Figure 10] 8A-8C are schematic cross-sectional side views of a region of the example structure of FIG. 7 at successive process stages of an example method. [Figure 11] 8A-8C are schematic cross-sectional side views of a region of the example structure of FIG. 7 at successive process stages of an example method. [Figure 11A] 12 is a schematic cross-sectional side view of the region of FIG. 7A at an exemplary process stage similar to the process stage of FIG. 11. [Figure 12] 12 is a schematic cross-sectional side view of a region of the exemplary structure of FIG. 7 at a process stage of an exemplary method. The process stage of FIG. 12 may follow the process stage of FIG. [Figure 12A] 13 is a schematic cross-sectional side view of the region of FIG. 7A at an exemplary process stage similar to the process stage of FIG. 12. [Figure 13] 13 is a schematic cross-sectional side view of a region of the exemplary structure of FIG. 7 at successive process stages of an exemplary method. The process stage of FIG. 13 may follow the process stage of FIG. [Figure 14] 8A-8C are schematic cross-sectional side views of a region of the exemplary structure of FIG. 7 at successive process stages of an exemplary method. [Figure 15] 8A-8C are schematic cross-sectional side views of a region of the exemplary structure of FIG. 7 at successive process stages of an exemplary method. [Figure 16] 16 is a schematic cross-sectional side view of a region of the exemplary structure of FIG. 7 at successive process stages of an exemplary method. The process stage of FIG. 16 may follow the process stage of FIG. [Figure 17] 8A-8C are schematic cross-sectional side views of a region of the exemplary structure of FIG. 7 at successive process stages of an exemplary method. [Figure 18] 8A-8C are schematic cross-sectional side views of a region of the exemplary structure of FIG. 7 at successive process stages of an exemplary method. [Figure 19] 8A-8C are schematic cross-sectional side views of a region of the exemplary structure of FIG. 7 at successive process stages of an exemplary method. DETAILED DESCRIPTION OF THE INVENTION

[0033] Some embodiments include methods of forming interconnects to specific steps in a staircase region of an integrated assembly. Some embodiments include an integrated assembly having interconnects electrically coupled to steps in the staircase region of the integrated assembly. Exemplary embodiments are described with reference to Figures 7-19.

[0034] 7, the staircase region 14 of the integrated assembly 10 is illustrated in exemplary process stages. The staircase region includes a stack 20 of alternating first and second levels 22 and 24. The first level 22 includes a sacrificial material 64, and the second level 24 includes an insulating material 28.

[0035] Sacrificial material 64 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of silicon nitride.

[0036] Insulating material 28 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

[0037] Some of the first and second levels 22 / 24 are configured as steps 66. Each of the steps includes one of the second levels 24 above an associated one of the first levels 22 (i.e., includes insulating material 28 above sacrificial material 64) and has an upper surface 67.

[0038] Levels 22 and 24 may be of any suitable thickness, may be the same thickness as one another, or may be different thicknesses from one another, hi some embodiments, levels 22 and 24 may have a vertical thickness in the range of about 10 nanometers (nm) to about 400 nm.

[0039] The stack 20 may have any suitable number of first and second levels 22 and 24. By way of example, in some embodiments, the stack 20 may have 8 first levels, 16 first levels, 32 first levels, 64 first levels, 512 first levels, 1024 first levels, etc., which ultimately result in conductive tiers similar to those described above with reference to FIG.

[0040] Only the bottom region of stack 20 is patterned during the illustrated step 66 of the illustrated interconnect region of Figure 7. Other portions of stack 20 may be patterned during steps in other interconnect regions (similar to interconnect region 18 of Figure 5).

[0041] Figure 7A shows memory array region 12 adjacent to staircase region 14 of Figure 7, at the same process stage as staircase region 14 of Figure 7. Stack 20 extends across memory array region 12.

[0042] The portion of the stack 20 within the memory array region 12 may be referred to as a first portion (or first region) of the stack, and the portion of the stack 20 within the staircase region 14 may be referred to as a second portion (or second region) of the stack.

[0043] Source structure 46 (FIG. 6) and base 58 (FIG. 6) are not shown in FIGS. 7 and 7A to simplify the drawings, but it should be understood that such structures may be present below stack 20 in FIGS. 7 and 7A.

[0044] 8 , a protective liner 68 is formed above stack 20 in staircase region 14. Protective liner 68 includes liner material 70. Such liner material may include any suitable composition and, in some embodiments, may include, consist essentially of, or consist of one or more insulating oxides. Illustratively, liner material 70 may include, consist essentially of, or consist of one or more of SiO, AlO, HfO, ZrO, and TaO, where the chemical formula indicates the major components rather than a specific stoichiometry.

[0045] Liner 68 can have any suitable thickness, and in some embodiments, can have a thickness in the range of about 10 nm to about 100 nm, such as in the range of about 20 nm to about 50 nm.

[0046] 9, an etch stop material 72 is formed over protective liner 68. The etch stop material forms an etch stop layer (structure) 74.

[0047] The etch stop material 72 may comprise any suitable composition and may be insulating, semiconductive, or conductive. In some embodiments, the etch stop material may comprise, consist essentially of, or consist of one or more of aluminum oxide, carbon-doped silicon nitride, silicon, and tungsten. When the etch stop material comprises carbon-doped silicon nitride, the carbon concentration may be in the range of about 5 atomic percent (at %) to about 20 at %, in the range of about 10 at % to about 15 at %, etc. When the etch stop material comprises silicon, the silicon may be substantially undoped (i.e., there are about 10 at % to about 15 at % therein). 15 atoms / cm 3 (which may include the conductivity-enhancing dopants described below). The silicon may be in any suitable crystalline form, and in some embodiments may be polycrystalline and / or amorphous.

[0048] Etch stop layer 74 can have any suitable thickness, and in some embodiments, can have a thickness in the range of about 50 nm to about 250 nm, in the range of about 20 nm to about 100 nm, in the range of about 40 nm to about 60 nm, etc.

[0049] 10, material 76 is formed above etch stop material 72. Material 76 may be referred to as a fill material. Material 76 is above step 66.

[0050] Material 76 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide and / or doped silicate glass (e.g., borophosphosilicate glass, phosphosilicate glass, fluorosilicate glass, etc.). In some embodiments, filler material 76 may comprise the same composition as protective material 70, while in other embodiments, filler material 76 may comprise a different composition than protective material 70.

[0051] 11 , planarized surface 77 is formed extending across the top surface of liner 68 and across materials 70, 72, and 76. Planarized surface 77 may be formed using any suitable process, including, for example, chemical mechanical polishing (CMP). Planarized surface 77 may be formed at any suitable level. In some embodiments, planarized surface 77 may be along the top level 24 of stack 20 (i.e., along the top surface of material 28 of upper level 24) rather than along the top surface of liner 68.

[0052] Figure 11A shows memory array region 12 at a similar (and in some embodiments, the same) process stage as Figure 11. Openings 90 are formed through stack 20, and materials 32, 33, 36, 38, and 40 are then formed within those openings. Material 68 in Figure 11 may or may not extend across memory array region 12 in Figure 11A, and in the illustrated embodiment, is not shown across the illustrated portion of the memory array region.

[0053] Channel material 32 includes a semiconductor material and may include any suitable composition or combination of compositions. Illustratively, channel material 32 may include one or more of silicon, germanium, a III / V semiconductor material (e.g., gallium phosphide), a semiconductor oxide, etc., where the term III / V semiconductor material refers to a semiconductor material that includes elements selected from Groups III and V of the periodic table (Groups III and V are older nomenclature, now referred to as Groups 13 and 15). In some embodiments, channel material 32 may include, consist essentially of, or consist of silicon.

[0054] The tunnel material (gate dielectric material) 40 may comprise any suitable composition, in some embodiments, the tunnel material 40 may comprise, for example, one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, etc.

[0055] Charge blocking material 36 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide and / or one or more high-k materials (e.g., aluminum oxide, zirconium oxide, hafnium oxide, etc.), where the term "high-k" means a dielectric constant greater than that of silicon dioxide.

[0056] Material 38 may be referred to as a charge storage material and may include any suitable composition. In some embodiments, charge storage material 38 may include a charge trapping material, such as silicon nitride, silicon oxynitride, conductive nanodots, etc. Illustratively, in some embodiments, charge storage material 38 may include, consist essentially of, or consist of silicon nitride.

[0057] Insulating material 33 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

[0058] The channel material 82 is configured as channel material pillars 16 of the type described above with reference to Figures 5 and 6. The illustrated channel material pillars 16 of Figure 11A may represent multiple channel material pillars formed across the memory array region 12.

[0059] 12 and 12A, sacrificial material 64 (FIGS. 11 and 11A) is removed and conductive material 26 is formed within level 22. Also, in the illustrated embodiment, dielectric barrier material 30 is formed along the periphery of conductive material 26.

[0060] The sacrificial material 64 (FIGS. 11 and 11A) may be removed using an etch utilizing hot phosphoric acid. The protective liner 68 may protect the etch stop material 72 from exposure to such an etch. If the etch stop material 72 is resistant to the etch utilized to remove the sacrificial material 64, the protective liner 68 may be omitted.

[0061] Conductive material 26 may include any suitable conductive composition, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, conductive material 26 may include a tungsten core surrounded by a liner comprising titanium nitride.

[0062] Dielectric barrier material 30 may comprise any suitable composition. In some embodiments, dielectric barrier material 30 may comprise a high-k material (illustratively one or more of aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, etc.). In some embodiments, dielectric barrier material 30 may comprise, consist essentially of, or consist of aluminum oxide.

[0063] The conductive material 26 within the steps 66 may be considered to be configured as conductive layers 92 , each of which has an upper surface 93 .

[0064] The configuration shown in memory array region 12 of Figure 12A may include memory cells 48 similar to those described above with reference to Figure 6. Conductive level 22 may include gate regions 50 and routing regions 52 similar to those described above with reference to Figure 6. In some embodiments, conductive layer 92 may be referred to as the gate / routing layer of the memory array, and such layer extends into both memory array region 12 and staircase region 14.

[0065] The process step of Figure 12A may, in some embodiments, be the same as the process step of Figure 12. In such embodiments, protective liner 68 may or may not extend along the top surface of memory array region 12 of Figure 12A.

[0066] 13, openings 78 are formed through the fill material 76 to extend into the etch stop material 72. In the described embodiment, the openings 78 extend partially through the etch stop material. In other embodiments, the openings 78 may stop at the top surface of the etch stop material. Each of the openings 78 is aligned with one of the steps 66.

[0067] 14 , opening 78 is extended through etch stop material 72, protective material 70, insulating material 28, and dielectric barrier material 30 to top surface 93 of conductive layer 92 in step 66. In the described embodiment, opening 78 is extended using one or more anisotropic etches through each of materials 72, 70, 28, and 30 so that the opening has relatively straight vertical sidewalls through materials 72, 70, 28, and 30. In some embodiments, etching through layer 74 to protective liner 68 may be considered to comprise first etching conditions, and etching through materials 70, 28, and 30 may be considered to comprise additional etching conditions. The additional etching conditions may or may not be the same as the first etching conditions. The first etching conditions may be selected for the particular material 74. In some embodiments, the first etching conditions may utilize one or both of hydrofluoric acid (HF) and tetramethylammonium hydroxide (TMAH), and layer 70 may include silicon and / or carbon-doped silicon nitride. In some embodiments, additional etching conditions may utilize HF to penetrate the oxide-containing materials 70 , 28 , and 30 .

[0068] In some embodiments, openings 78 may extend all the way through conductive material 52 of layer 92 rather than stopping at top surface 93 .

[0069] It should be understood that although the replacement of sacrificial material 64 (FIG. 11) is shown as occurring at the process step of FIG. 12, in other embodiments, such replacement may occur at any process step prior to the process step of FIG. 14. Desirably, conductive layer 92 is present at the process step of FIG. 14 so that opening 78 may stop on (or, in some embodiments, extend into) such conductive material.

[0070] Referring to FIG. 15, a conductive material 96 is formed within the opening 78 to form an interconnect 42 similar to that described above with reference to FIG.

[0071] Conductive material 96 may include any suitable conductive composition, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, conductive material 96 may be a metal-containing material and may include one or more of tungsten, titanium nitride, tungsten nitride, etc.

[0072] The conductive interconnect 42 of FIG. 15 may be coupled to a driver circuit 62 similar to that shown in FIG.

[0073] Planarized surface 97 is shown extending over interconnects 42 and fill material 76. Planarized surface 97 may be formed using any suitable method, including, for example, CMP.

[0074] As discussed above, in some embodiments, etch stop material 72 may be electrically conductive (e.g., may include tungsten). In such embodiments, it may be advantageous to electrically insulate etch stop material 72 from interconnects 42. Figures 16-19 illustrate exemplary process stages of an exemplary method for electrically insulating etch stop material from interconnects 42.

[0075] 16, staircase region 14 is shown at a process stage that may follow that of FIG. 13. An isotropic etch is utilized to remove regions of material 72 and form cavities 99 that extend below fill material 76. The isotropic etch of FIG. 16 may utilize any suitable etchant and conditions. Illustratively, in some embodiments, the isotropic etch may utilize one or more of HF, TMAH, and hot phosphoric acid when material 72 includes silicon and / or carbon-doped silicon nitride.

[0076] 17, insulating spacer material 102 is formed within cavity 99 (FIG. 16) to form insulating spacer 100. Insulating spacer material 102 may include any suitable insulating composition, and in some embodiments may include, consist essentially of, or consist of one or more of silicon dioxide, silicon nitride, aluminum oxide, etc.

[0077] Spacers 100 may be formed using any suitable process. Illustratively, a liner of spacer material 102 may be formed within openings 78 and cavities 99, and then excess spacer material may be removed using an etch, leaving spacers 100 in cavities 99 (FIG. 16).

[0078] 18, opening 78 is extended through protective material 70, insulating material 28, and dielectric barrier material 30 to upper surface 93 of conductive layer 92 in step 66. This can be accomplished using an etch similar to that described above with reference to FIG.

[0079] 19, a conductive material 96 is formed in opening 78 (FIG. 18) to form interconnect 42 similar to that described above with reference to FIG. 6. Conductive interconnect 42 is laterally separated from layer 74 by insulating spacers 100 (which may be, for example, a conductive material such as tungsten).

[0080] The conductive interconnect 42 of FIG. 19 may be coupled to a driver circuit 62 similar to that shown in FIG.

[0081] In the illustrated embodiment of FIGS. 15 and 19, layer 74 is above step 66 and along the bottom of stack 20 , separated from stack 20 by an intervening insulating region corresponding to liner material 70 .

[0082] The processes described herein may advantageously improve the formation of conductive interconnects (42) into deep steps in staircase regions by utilizing an etch-stop material (72) as a landing pad for openings (78) punched through a fill material (76). The etch-stop material may be tailored to fully stop both low-aspect ratio and high-aspect ratio openings (78) by adjusting the thickness and / or composition of the etch-stop. In some applications, the tunability of the etch-stop material is enhanced by floating (forming above) the protective material (70).

[0083] In some embodiments, the etch stop material (74) can be selected to be selectively removable relative to the insulating material (28) of the insulating tier (24) and relative to the conductive material (26) of the conductive tier (22).

[0084] In some embodiments, the processes described herein may advantageously provide scalability and location flexibility for stepped contact structures (interconnects).

[0085] The assemblies and structures discussed above may be utilized in integrated circuits (the term "integrated circuit" refers to an electronic circuit supported by a semiconductor substrate) and incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communications modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic systems may be any of a wide range of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0086] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed using any suitable methodology, whether currently known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0087] The terms "dielectric" and "insulating" may be used to describe materials that have insulating electrical properties. In this disclosure, the terms are considered synonymous. The use of the term "dielectric" in some instances and the term "insulating" (or "electrically insulating") in other instances may provide language variation within this disclosure to simplify the antecedents in the claims that follow, and is not used to indicate any significant chemical or electrical differences.

[0088] The terms "electrically connected" and "electrically coupled" may both be used in this disclosure. The terms are considered synonymous. The use of one term in some instances and the other term in other instances may provide for language variations within this disclosure to simplify the antecedents in the claims that follow.

[0089] The particular orientations of the various embodiments in the figures are for illustrative purposes only, and in some applications the embodiments may be rotated relative to the orientation shown. The description provided herein and the claims that follow relate to any structure having the described relationships between the various features, regardless of whether the structure is in the particular orientation of the figures or rotated relative to such orientation.

[0090] The cross-sectional views of the accompanying examples show only features within the plane of the cross section and, to simplify the drawings, do not show material behind the plane of the cross section unless otherwise specified.

[0091] When a structure is referred to above as being "on," "adjacent," or "against" another structure, it may be directly on the other structure, or there may be intervening structures. In contrast, when a structure is referred to as being "directly on," "directly adjacent," or "directly against" another structure, there are no intervening structures. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless otherwise specified), but rather indicate upright alignment.

[0092] A structure (e.g., a layer, a material, etc.) may be referred to as "vertically extending" to indicate that the structure generally extends upward from an underlying base (e.g., substrate). A vertically extending structure may or may not extend substantially perpendicular to the top surface of the base.

[0093] Some embodiments include a method of forming an integrated assembly. A stack of alternating first and second levels is formed. The first level includes a sacrificial material and the second level includes an insulating material. At least some of the first and second levels are configured as steps. Each of the steps includes one of the second levels above an associated one of the first levels and has a top surface corresponding to a top surface of the one of the second levels. An etch-stop material is formed above the stack. A fill material is formed above the etch-stop material. The sacrificial material is removed, and a conductive layer is formed in the first level. The conductive layer in the step has a top surface. An opening is formed through the fill material to extend to the etch-stop material. The opening is extended through the etch-stop material to the top surface of the conductive layer in the step. A conductive interconnect is formed in the extended opening.

[0094] Some embodiments include a method for forming an integrated assembly. A stack of alternating first and second levels is formed. The stack has a first region in a memory array region and a second region in a staircase region adjacent to the memory array region. The first level includes a sacrificial material and the second level includes an insulating material. At least some of the first and second levels are configured as steps in the staircase region. Each of the steps includes one of the second levels above an associated one of the first levels and has a top surface corresponding to a top surface of the one of the second levels. A protective liner is formed above the second region of the stack. An etch stop material is formed above the second region of the stack and above the protective liner. A fill material is formed above the steps. The fill material is above the etch stop material. The sacrificial material is removed, and a conductive material is formed in the first level. The conductive material in the steps is configured as a conductive layer having a top surface. An opening is formed extending through the fill material to the etch stop material. The opening is extended through the etch stop material to the protective liner using first etching conditions. The opening is extended through the protective liner to the top surface of the conductive layer within the step using additional etching conditions, and a conductive interconnect is formed within the extended opening.

[0095] Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first level includes a conductive material and the second level includes an insulating material. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels above an associated one of the first levels. A layer is above the step and is separated from the stack by an intervening insulating region. An insulating material is above the layer. A conductive interconnect extends through the insulating material, through the layer, through the intervening insulating region, and to the conductive material in the first level of the step.

[0096] In accordance with the statute, the subject matter disclosed herein has been described in language that is more or less specific in terms of structural and systematic features. However, because the means disclosed herein include exemplary embodiments, it should be understood that the scope of the claims is not limited to the specific features shown and described. The claims should therefore be given full scope in literal terms and appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. forming a stack of alternating first and second levels, the first levels comprising a conductive material and the second levels comprising an insulating material, at least some of the first and second levels configured as steps, each of the steps comprising one of the second levels above an associated one of the first levels; forming a layer above the step and separated from the stack by an intervening insulating region, the layer including an etch stop material; forming an insulating material over the layer; forming an opening through the insulating material to extend to the layer; removing a portion of the layer from beneath the insulating material to form a recess; forming an insulating spacer within the recess; extending the opening through the insulating material, through the layer, through the intervening insulating region, and to the conductive material in the first level of the step; forming a conductive interconnect within the enlarged opening; A method of forming an integrated assembly comprising:

2. The method for forming an integrated assembly of claim 1 , wherein said layer is insulating.

3. The method for forming an integrated assembly of claim 1 , wherein the layer is electrically conductive.

4. 4. The method for forming an integrated assembly of claim 3, wherein said insulating spacers are formed laterally between said layers and said conductive interconnects.

5. The method for forming an integrated assembly of claim 1 , wherein the layer has a thickness in the range of about 50 nm to about 250 nm.

6. The method for forming an integrated assembly of claim 1 , wherein the layer has a thickness in the range of about 20 nm to about 100 nm.

7. The method for forming an integrated assembly of claim 1 , wherein the layer has a thickness in the range of about 40 nm to about 60 nm.

8. The method for forming an integrated assembly of claim 1 , wherein the layer comprises aluminum oxide.

9. The method for forming an integrated assembly of claim 1 , wherein the layer comprises carbon-doped silicon nitride.

10. 10. The method for forming an integrated assembly of claim 9, wherein the carbon-doped silicon nitride comprises a carbon concentration in the range of about 5 at% to about 20 at%.

11. 10. The method for forming an integrated assembly of claim 9, wherein the carbon-doped silicon nitride comprises a carbon concentration in the range of about 10 at% to about 15 at%.

12. The method for forming an integrated assembly of claim 1 , wherein the layer comprises tungsten.

13. The method for forming an integrated assembly of claim 1 , wherein said layer comprises silicon.

14. 10. The method for forming an integrated assembly of claim 1, wherein said layer comprises silicon having less than about 10<15> atoms / cm<3> of a conductivity-enhancing dopant therein.

15. 10. The method of forming an integrated assembly of claim 1, wherein the first level includes a dielectric barrier material in addition to the conductive material, and the conductive interconnects extend through the dielectric barrier material.

16. 16. The method for forming an integrated assembly of claim 15, wherein the dielectric barrier material comprises aluminum oxide.

17. 10. The method of forming an integrated assembly of claim 1, wherein the intervening insulating regions comprise one or more of SiO, AlO, HfO, ZrO, and TaO, wherein the chemical formula indicates a major component rather than a specific stoichiometry.

18. The method of forming an integrated assembly of claim 1 , wherein the insulating material comprises the same composition as the intervening insulating regions.

19. The method of forming an integrated assembly of claim 1 , wherein the insulating material comprises a different composition than the intervening insulating regions.

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