Data storage method, storage device and readable storage device

Abstract

The present application discloses a data storage method, which includes: writing data to a first buffer area and a second buffer area of ​​a page buffer; writing data to a third buffer area of ​​the page buffer, in which the data written to the third buffer area is obtained from the data of the first buffer area and the data of the second buffer area through a logical operation using the computing resources of the page buffer, and first data information is determined by the data of the first buffer area, the second buffer area and the third buffer area; and writing the first data information buffered in the page buffer to a storage unit. The present application further discloses a storage device and a computer-readable storage device. The present application can improve the data reliability of a TLC / QLC storage device without consuming the computing resources of the system.

Description

[Technical Field]

[0001] The present application relates to the technical field of storage, and in particular to data storage methods, storage devices and computer-readable storage devices. [Background technology]

[0002] As the use of storage devices continues to grow, storage technologies for such devices are also constantly evolving. Taking the widely used TLC / QLC memory as an example, TLC can store three bits of data per storage unit, while QLC can store four bits of data per storage unit. To distinguish between multiple types of data within a single storage unit, corresponding voltage intervals must be defined to distinguish them. TLC requires eight voltage intervals, while QLC requires 16 voltage intervals. However, because the number of voltage intervals within a storage unit is limited, the more voltage intervals there are, the smaller the interval spacing becomes. When the interval spacing becomes smaller, if a voltage offset occurs to the left or right of the voltage data due to various factors, the voltage may exceed the critical voltage value. If data is read according to the critical voltage value of the original interval, data errors may occur, resulting in reduced reliability of the stored data. Summary of the Invention [Problem to be solved by the invention]

[0003] A main object of the present application is to provide a data storage method, a storage device, and a computer-readable storage device that can solve the problem of improving data reliability of storage devices. [Means for solving the problem]

[0004] To solve the above problems, a first technical aspect of the present application provides a data storage method, the method including: writing data to a first buffer area and a second buffer area of ​​a page buffer; writing data to a third buffer area of ​​the page buffer, wherein the data written to the third buffer area is obtained from the data in the first buffer area and the data in the second buffer area through a logical operation using the computing resources of the page buffer, and first data information is determined by the data in the first buffer area, the second buffer area, and the third buffer area; and writing the first data information buffered in the page buffer to a storage unit.

[0005] In order to solve the above problem, a second technical aspect adopted by the present application is to provide a storage device including a memory and a processor, the memory being for storing program data, the program data being executable by the processor to implement the method according to the first technical aspect.

[0006] To solve the above problems, a third technical aspect of the present application provides a computer-readable storage device that stores program data that can be executed by a processor to implement the method described in the first technical aspect. [Effects of the Invention]

[0007] The present invention has the following advantageous effects. Unlike the prior art, the data in the first and second buffer areas is not determined first and then determined using a threshold voltage value. Instead, the data in the third buffer area is obtained by performing a logical operation on the data in the first and second buffer areas. Because the buffer data has two types, 0 and 1, and each buffer area stores one bit of data information, the prior art obtains eight types of data information by determining the first, second, and third buffer data using a threshold voltage value. In contrast, the present invention obtains data in the third buffer area by performing an operation on the already-determined data in the first and second buffer areas. That is, by making the data status in the third buffer area correspond to four types of status data in the first and second buffer areas, the data information ultimately obtained based on the data in the first, second, and third buffer areas is only four types, not eight. Because the number of types of data information is reduced, larger voltage ranges can be defined for the four types of data information within the same maximum voltage range, thereby increasing the degree of error tolerance against the data voltage offset and improving the reliability of stored data. Furthermore, the present invention realizes the logical operation process by using the logical operation function of the page buffer, which does not require the master's computing resources to be occupied, thereby saving the system's computing power. [Brief explanation of the drawings]

[0008] In order to more clearly explain the technical aspects of the embodiments of the present invention, the following briefly introduces the drawings that need to be used in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can also obtain other drawings from these drawings without paying creative labor. [Figure 1] FIG. 1 is a schematic diagram of writing and reading voltages in a TLC NAND FLASH memory according to the present application. [Figure 2] FIG. 2 is a schematic diagram showing the occurrence of a left-right offset in the voltage stored in the storage unit of the TLC according to the present invention. [Figure 3] FIG. 3 is a flow diagram of a first embodiment of the data storage method according to the present application. [Figure 4] FIG. 4 is a flow diagram of a second embodiment of the data storage method according to the present invention. [Figure 5] FIG. 5 is a flow diagram of a third embodiment of the data storage method according to the present application. [Figure 6] FIG. 6 is a flow diagram of a fourth embodiment of the data storage method according to the present application. [Figure 7] FIG. 7 is a flow diagram of a fifth embodiment of the data storage method according to the present invention. [Figure 8] FIG. 8 is a schematic diagram showing the determination of the voltage reading section after the logical operation according to the present invention. [Figure 9] FIG. 9 is a flow diagram of a sixth embodiment of the data storage method according to the present application. [Figure 10] FIG. 10 is a flow diagram of a seventh embodiment of the data storage method according to the present application. [Figure 11] FIG. 11 is a flow diagram of an eighth embodiment of the data storage method according to the present application. [Figure 12] FIG. 12 is a flow diagram of a ninth embodiment of the data storage method according to the present application. [Figure 13] FIG. 13 is a flow diagram of a tenth embodiment of the data storage method according to the present application. [Figure 14] FIG. 14 is a flow diagram of an eleventh embodiment of the data storage method according to the present application. [Figure 15] FIG. 15 is a flow diagram of a twelfth embodiment of the data storage method according to the present application. [Figure 16] FIG. 16 is a schematic flow diagram of a thirteenth embodiment of the data storage method according to the present application. [Figure 17] FIG. 17 is a flow diagram of a fourteenth embodiment of the data storage method according to the present application. [Figure 18] FIG. 18 is a structural schematic diagram of an embodiment of a storage device according to the present invention. [Figure 19]FIG. 19 is a structural schematic diagram of one embodiment of a computer-readable storage device according to the present application. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, the technical aspects of the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, but it should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. Based on the embodiments of the present application, other embodiments obtained by those skilled in the art without paying creative labor shall all be within the scope of protection of the present application.

[0010] As used herein, terms such as "first," "second," etc. are used to distinguish between different objects and are not intended to describe a particular order. Furthermore, the terms "comprise" and "have," and any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not limited to the listed steps or units, but may optionally further include unlisted steps or units, or may optionally further include other steps or units inherent to the process, method, product, or apparatus.

[0011] References to "an embodiment" herein mean that a particular feature, structure, or characteristic described with respect to an embodiment may be included in at least one embodiment of the present application. Appearances of the term in various places in the specification do not necessarily refer to the same embodiment, nor are they mutually exclusive, independent, or alternative embodiments of other embodiments. Those skilled in the art will understand, both explicitly and implicitly, that the embodiments described herein can be combined with other embodiments.

[0012] Before introducing the technical aspects of the present application, a brief introduction to related art will be given.

[0013] Please refer to FIG. 1, which is a schematic diagram of writing and reading voltages in a TLC NAND FLASH memory.

[0014] Currently, TLC NAND FLASH memory and QLC NAND FLASH memory are widely used in practical applications. Of these two types of memory, TLC can store 3 bits of information per memory unit, while QLC can store 4 bits of information per memory unit. On the other hand, MLC can only store 2 bits of information per memory unit, making the production costs of both types lower than MLC. However, the maximum voltage range of each memory unit is the same. Storing more information under the same maximum voltage range means dividing the voltage range into more sub-ranges and identifying the stored voltages and reading the data according to the range thresholds. In the case of TLC, as shown in the figure, one memory unit can store 3 bits of information, which requires eight voltage states and eight ranges, which are distinguished using different read levels.

[0015] The information stored in the TLC has 3 bits. When storing, each bit of data is first stored in a different page buffer. After all bits of data are stored in the buffer, the data is written to the memory die. In this figure, the write mode of the memory unit is 2-3-2 mode. First, writing is performed using read level 1 and read level 5, and the written data is stored in the lower page buffer, and the state of the data written thereto from left to right is 101, and the data written thereto is the least significant bit of data; next, writing is performed using read level 2, read level 4, and read level 6, and the written data is stored in the middle page buffer, and the state of the data written thereto from left to right is 1010, and the data written thereto is the middle bit of data; finally, writing is performed using read level 3 and read level 7, and the written data is stored in the upper page buffer, and the data written thereto is the most significant bit of data; following this order, the resulting data is 111, 110, 100, 000, 010, 011, 001, 101, in that order; and finally, all the data is stored together on the memory die.

[0016] When writing data, various interference factors can cause left and right offsets and spreads in the voltage distribution of each state, making it difficult for the read level to properly distinguish between the eight voltage states during reading. Figure 2 shows a schematic diagram of left and right offsets in the voltages stored in a TLC memory unit. If a certain number of error bits is exceeded, the data will fail to be read and will be lost. The larger the small voltage interval for data storage, the easier it is to distinguish between left and right offsets caused by interference during reading using the read level, making it less likely for errors to occur in the data and increasing the reliability of data storage.

[0017] In some application scenarios, the requirements for data reliability are very high, while the requirements for its storage capacity are not so strict, so the reliability of TLC / QLC does not meet the actual needs of users. Therefore, this application provides the following examples to improve the data reliability of TLC / QLC products to meet the usage requirements.

[0018] 3, which is a flow diagram of a first embodiment of a data storage method according to the present invention, includes the following steps S11 to S13.

[0019] S11: Data is written to the first buffer area and the second buffer area of ​​the page buffer.

[0020] As per the original memory write flow, the first two bits of data are written to the buffer area according to the write read level. Taking the above TLC write 2-3-2 mode as an example, write is performed using read level 1 and read level 5, and the written data is stored in the lower page buffer. Next, write is performed using read level 2, read level 4, and read level 6, and the written data is stored in the middle page buffer. Here, the first buffer area is the lower page buffer and the second buffer area is the middle page buffer, but this is merely an illustrative example. In actual application, the first buffer area and the second buffer area may be any two of the configured buffer areas. The subsequent third buffer area is a buffer area different from the first buffer area and the second buffer area.

[0021] S12: Write data into the third buffer area of ​​the page buffer.

[0022] After data has been written to the first buffer area and the second buffer area, instead of writing data to the third buffer area according to the read level as per the original flow, the data to be written to the third buffer area is obtained through a logical operation using the computing resources of the page buffer from the data in the first buffer area and the data in the second buffer area. The storage device can achieve this logical operation process using logical operation functions within the buffer, such as logical sum (OR), logical product (AND), negative logical sum (NOR), negative logical product (NAND), exclusive logical sum (XNOR), and exclusive logical sum (XOR). Furthermore, first data information is determined by the data in the first buffer area, the second buffer area, and the third buffer area. The first data information is determined by the data written to the corresponding first buffer area, the second buffer area, and the third buffer area under the same voltage section.

[0023] S13: The first data information buffered in the page buffer is written to the storage unit.

[0024] After the data has been written into the buffer, the final data is written into the storage unit to complete the data storage.

[0025] In this embodiment, all logical operations can be realized by the logical operation capacity of the page buffer itself, and there is no need to occupy the master's computing resources, thereby saving the system's computing capacity.

[0026] According to this embodiment, instead of determining the data in the first and second buffer areas and then determining the data in the third buffer area using a threshold voltage value, a logical operation is performed on the data in the first and second buffer areas to obtain the data in the third buffer area. Since the buffer data has two types, 0 and 1, and each buffer area stores one bit of data information, in the prior art, determining the first, second, and third buffer data using the threshold voltage value results in eight types of data information. In contrast, in the present invention, the data in the third buffer area is obtained by performing an operation on the already determined data in the first and second buffer areas to obtain the data in the third buffer area. That is, the data status in the third buffer area corresponds to four types of status data in the first and second buffer areas. Therefore, the data information finally obtained based on the data in the first, second, and third buffer areas is only four types instead of the original eight types. Because the number of types of data information is reduced, a larger voltage range can be defined for the four types of data information within the same maximum voltage range, thereby increasing the degree of error tolerance against the data voltage offset and improving the reliability of the stored data.

[0027] 4, which is a flow diagram of a second embodiment of the data storage method according to the present application. This method is a further expansion of step S12, and includes the following steps S21 to S22.

[0028] S21: A first logical operation is performed on the data in the first buffer area and the data in the second buffer area to obtain intermediate data.

[0029] A first logical operation is first performed according to the data already written in the first buffer area and the second buffer area, and the logical operation may be an XNOR operation.

[0030] S22: Data obtained by performing a second logical operation on the intermediate data and the data in the first buffer area is written to the third buffer area, or data obtained by performing a second logical operation on the intermediate data and the data in the second buffer area is written to the third buffer area.

[0031] The obtained intermediate data is further subjected to a second logical operation with the data in the first buffer area to obtain data to be written to the third buffer area. The logical operation may be an OR operation. The obtained intermediate data may be further subjected to a second logical operation with the data in the second buffer area to obtain data to be written to the third buffer area.

[0032] Taking the TLC 2-3-2 mode as an example, if the data written to the first buffer area is 10000111 and the data written to the second buffer area is 11001100, then an XNOR operation on both data results in 10110100, which is then ORed with the data in the first buffer area to obtain 10110111, which is the data in the third buffer area. The resulting data voltages are then stored in four states: 111, 001, 010, and 101, respectively, out of the original eight states. Because the four voltage states are far apart, new data read voltages can be set for them. By distinguishing between the four voltage states using the new read voltage, the intervals between the new four voltage ranges are increased compared to before, increasing the tolerance for left and right offsets in the voltages, improving data reliability and reducing the probability of data errors.

[0033] Similarly, if an OR operation is performed on the intermediate data and the data in the second buffer area, the resulting data in the third buffer area will be 11111100. The data voltages stored therein will ultimately have four states, which are 111, 011, 001, and 100, respectively, out of the original eight states. Among them, the voltage section of 100 is far away from the other three voltage sections, while the other three sections are still close to each other. Therefore, after setting a new data read voltage, the interval between the new voltage sections corresponding to 100 will be increased, which will increase the tolerance for left and right offsets of the voltage, improving data reliability and reducing the probability of data errors. Meanwhile, the intervals between the other three voltage sections will likely not be significantly different, and the reliability of the data will not fluctuate significantly.

[0034] Therefore, in the process of performing logical operations, it is necessary to consider that the original voltage intervals of the four voltage states finally obtained are distributed relatively evenly throughout the entire maximum voltage interval. In this way, among the interval intervals of the four new voltage states, not only some of the interval intervals are increased obviously, but all of the interval intervals are increased to some extent, thereby improving the reliability of all of the stored data, not just some of the data.

[0035] 5, which is a flow diagram of a third embodiment of the data storage method according to the present application. This method is a further extension of the above embodiment, and includes the following steps S31 to S33.

[0036] S31: After writing data to the first buffer area, the data in the first buffer area is copied to the third buffer area.

[0037] The TLC page buffer has a three-layer page buffer structure, and each page buffer buffers one bit of data. During the logical operation, when the least significant bit of data is stored in the first buffer area corresponding to the lower page buffer, the data in the first buffer area is copied and written to the third buffer area.

[0038] S32: After writing the data to the second buffer area, perform a first logical operation on the data in the third buffer area and the data in the second buffer area to obtain intermediate data, and write the intermediate data to the third buffer area.

[0039] When the second bit of data is stored in the second buffer area, a logical operation is performed on the data from the first buffer area currently stored in the third buffer area and the data from the second buffer area. The logical operation may be an XNOR operation. After the operation, intermediate data is obtained, and the data from the first buffer area written to the third buffer area is updated with the intermediate data.

[0040] S33: Data obtained by performing a second logical operation on the data in the third buffer area and the data in the first buffer area is written to the third buffer area.

[0041] After the intermediate data is written to the third buffer area, a logical operation is again performed with the buffer data in the first buffer area. The logical operation may be an OR operation. The resulting data becomes the final data to be written to the third buffer area, and the intermediate data is updated with the resulting data and written to the third buffer area.

[0042] After all the data is written to the buffer area, it is written all together to the storage unit.

[0043] The logical operations can all be realized by the logical operation capabilities of the page buffer itself, without occupying the master's computing resources, thus saving the system's computing power.

[0044] 6, which is a flow diagram of a fourth embodiment of the data storage method according to the present application. This method is a further expansion of step S13, and includes the following steps S41 to S42.

[0045] S41: Determine a corresponding section voltage signal according to the first data information buffered in the page buffer.

[0046] After performing logical operations on the data in the first buffer area and the second buffer area to obtain data in the third buffer area, four types of voltage status data can be obtained correspondingly, and these four types of voltage status data become the data information currently stored in the buffer.

[0047] In the above embodiment, an XNOR operation is performed on the data in the first buffer area and the data in the second buffer area to obtain intermediate data, and then an OR operation is performed on the intermediate data and the data in the first buffer area to obtain data in the third buffer area. The four types of voltage state data finally obtained are 111, 100, 010, and 101. As shown in Figure 1, the voltage sections corresponding to the four types of voltage state data are, counted from left to right, the first section, the third section, the fifth section, and the eighth section. The corresponding voltage signals are read level 1, which defines the first section, read level 2 and read level 3, which define the third section, read level 4 and read level 5, which define the fifth section, and read level 7, which defines the eighth section.

[0048] S42: Write the first data information into the storage unit according to the corresponding section voltage signal.

[0049] After the data information of the buffer is determined, an interval voltage signal corresponding to the data information can be obtained, and the data can be written to the storage unit according to the corresponding voltage interval signal. The write voltage corresponding to 111 is stored in the storage unit at a value lower than read level 1 or is not written; the write voltage corresponding to 100 is stored in the storage unit at a value between read level 2 and read level 3; the write voltage corresponding to 010 is stored in the storage unit at a value between read level 4 and read level 5; and the write voltage corresponding to 101 is stored in the storage unit at a value higher than read level 7.

[0050] 7, which is a flow diagram of a fifth embodiment of the data storage method according to the present application. This method is a further extension of the above-described embodiment, and includes the following steps S51 to S52.

[0051] S51: Eight voltage sections corresponding to 3-bit data are determined.

[0052] In the TLC memory mode, one memory unit can store 3 bits corresponding to 8 types of state data, each occupying a voltage range, which can be easily distinguished according to the threshold voltage of the voltage range during reading. The 8 voltage ranges are determined by 7 threshold voltage values. In the above example, the 7 threshold voltages are read level 1 to read level 7.

[0053] S52: Determine four voltage sections defined by the first buffer area, the second buffer area, and the third buffer area.

[0054] Referring to FIG. 8, FIG. 8 is a schematic diagram of determining voltage read intervals after a logical operation according to the present invention. After performing the logical operation, only four of the eight types of state data remain. For example, after the logical operation of the above embodiment, only 111, 100, 010, and 101, corresponding to the first, third, fifth, and eighth voltage intervals, remain. Meanwhile, to increase the reliability of the data, a new read voltage must be determined for the data; that is, a new voltage interval must be defined for the data to distinguish between the four remaining voltage states. The four voltage intervals are determined by three critical voltage values.

[0055] Each of the three critical voltage values ​​is represented by one of seven critical voltage values ​​and a corresponding offset. After determining the voltage ranges corresponding to the remaining four types of status data, the respective critical voltages are determined accordingly. In the above embodiment, the first, third, fifth, and eighth voltage ranges correspond to six critical voltages: read levels 1, 2, 3, 4, 5, and 7. To effectively improve the reliability of each type of status data, the new critical voltages 111 and 100 are determined as midpoints between the first and third voltage ranges, i.e., midpoints between read level 1 and read level 2. These voltages are obtained by adding half the difference between read level 1 and read level 2 to read level 1, or by subtracting half the difference between read level 1 and read level 2 from read level 2. Similarly, the new critical voltages for 100 and 010 are determined to be midway between the third and fifth voltage sections, i.e., midway between read level 3 and read level 4. This voltage can be obtained by adding an offset value to read level 3 or subtracting an offset value from read level 4. The new critical voltages for 010 and 101 are determined to be midway between the fifth and eighth voltage sections, i.e., midway between read level 5 and read level 7. This voltage can be obtained by adding an offset value to read level 5 or subtracting an offset value from read level 7. The determined new critical voltages do not necessarily lie midway between the two base critical voltages and can be adjusted according to actual conditions. However, determining the new critical voltages midway between the two base voltages can maximize the reliability of each data.

[0056] 9, which is a flow diagram of a sixth embodiment of the data storage method according to the present invention, which is a further extension of the above embodiment, and includes the following step S61.

[0057] S61: Compare the voltage information in the storage unit with the four voltage intervals to read the first data information stored in the storage unit.

[0058] After the data in the buffer area is stored in the memory unit, when the data is read, it is read according to the new threshold voltage value determined in the above embodiment.

[0059] 10, which is a flow diagram of a seventh embodiment of the data storage method according to the present application. This method is a further extension of the first embodiment, and includes the following steps S71 to S72.

[0060] S71: Data is written to the fourth buffer area of ​​the page buffer.

[0061] The data to be written to the fourth buffer area is obtained by performing a logical operation using the computing resources of the page buffer from any two of the data in the first buffer area, the data in the second buffer area, and the data in the third buffer area, and the second data information is determined from the data in the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area. Based on the above embodiment, after writing data to the first buffer area and the second buffer area, a logical operation is performed on the data in the first buffer area and the second buffer area to obtain data in the third buffer area. Furthermore, a logical operation is again performed on the data in any two of the first buffer area, the second buffer area, and the third buffer area to obtain data in the fourth buffer area.

[0062] In QLC memory units, each memory unit can store 4 bits of data information. It corresponds to 16 different voltage states, has 16 voltage intervals, and is distinguished by 15 critical voltage values. Its page buffer has a four-layer structure, and each page buffer corresponds to 1 bit of data. When writing, data is written sequentially from the least significant bit.

[0063] The process of performing a logical operation to obtain data in the third buffer area can be described in the above embodiment. For example, after writing data to the first buffer area, the data in the first buffer area is copied to the third buffer area, and after writing data to the second buffer area, a logical operation is performed on the data in the third buffer area and the data in the second buffer area. The operation may be an XNOR operation. After the operation, intermediate data is obtained, and the data in the first buffer area written to the third buffer area is updated with the intermediate data. After writing the intermediate data to the third buffer area, a logical operation is again performed with the buffer data in the first buffer area. The logical operation may be an OR operation. The resulting data becomes the final data to be written to the third buffer area, and the intermediate data is updated with the data and written to the third buffer area.

[0064] After the logical operation to obtain the fourth buffer area, four corresponding voltage state data are left, which correspond to four of the original 16 voltage data. To enhance the reliability of the four voltage state data, it is necessary to determine new, larger voltage ranges for the four voltage states. To improve the reliability of all, not just a portion, of the four voltage state data, it is necessary to ensure that the voltage ranges originally corresponding to the finally obtained four voltage state data are distributed relatively evenly throughout the maximum voltage range, so that each new voltage range is significantly larger than the previous voltage range. For specific operation logic, the ideas provided in the above embodiments may be referred to and will not be repeated here.

[0065] The logical operations can all be realized by the logical operation capabilities of the page buffer itself, without occupying the master's computing resources, thereby saving the system's computing power.

[0066] In actual application, the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area may be any one of all the configured buffer areas, and the terms first, second, third, and fourth do not limit the locations of the buffer areas, but merely indicate that the locations of the buffer areas are different.

[0067] S72: The second data information buffered in the page buffer is written to the storage unit.

[0068] After the data is written to the buffer, second data information in the buffer is written to the storage unit, and the second data information is determined by the data written to the corresponding first buffer area, second buffer area, third buffer area, and fourth buffer area under the same voltage section. After the data is written to the storage unit, the storage of the data is completed.

[0069] 11, which is a flow diagram of an eighth embodiment of the data storage method according to the present application. This method is a further expansion of step S72, and includes the following steps S81 to S82.

[0070] S81: Determine a corresponding section voltage signal according to the second data information buffered in the page buffer.

[0071] A logical operation is performed on the data in the first buffer area and the second buffer area to obtain data in the third buffer area, and then a logical operation is performed again to obtain data in the fourth buffer area, and four types of voltage status data can be obtained correspondingly, and these four types of voltage status data become the data information currently stored in the buffer.

[0072] After determining the four kinds of voltage status data, the original voltage range and the critical voltage value of the voltage range can be further determined, the determination procedure can be referred to the above embodiment and will not be repeated here.

[0073] S82: Write second data information into the storage unit according to the corresponding section voltage signal.

[0074] According to the determined buffer data, the voltage interval and the threshold voltage value are determined. Data is written to the storage unit based on the interval voltage. The corresponding data information is written to the storage unit so that the voltage is within the corresponding voltage interval. For details, please refer to the description of step S42 in the above embodiment, and it will not be repeated here.

[0075] 12, which is a flow diagram of a ninth embodiment of the data storage method according to the present application. This method is a further extension of the above-described embodiment, and includes the following steps S91 to S92.

[0076] S91: Determine 16 voltage sections corresponding to 4-bit data.

[0077] In QLC memory mode, one memory unit can store 4 bits corresponding to 16 types of state data, each occupying a voltage range, which can be easily distinguished according to the critical voltage of the voltage range during reading. The 16 voltage ranges are determined by 15 critical voltage values, which are read level 1 to read level 15.

[0078] S92: Determine four voltage sections defined by a first buffer area, a second buffer area, a third buffer area and a fourth buffer area.

[0079] After the logical operation, only four of the 16 types of state data remain. For example, assume that the voltage intervals corresponding to the four remaining voltage state data after the logical operation are the first interval, the fifth interval, the tenth interval, and the sixteenth interval. Meanwhile, in order to increase the reliability of the data, a new read voltage must be determined for the data, i.e., a new voltage interval must be defined for the data to distinguish the remaining four voltage states. The four voltage intervals are determined by three critical voltage values.

[0080] Each of the three critical voltage values ​​is represented by one of 15 critical voltage values ​​and a corresponding offset. After determining the voltage intervals corresponding to the remaining four types of status data, the respective critical voltages are determined accordingly. Assume that the remaining voltage intervals are the first, fifth, tenth, and sixteenth voltage intervals, which correspond to six critical voltages: read levels 1, 4, 5, 9, 10, and 15. To effectively improve the reliability of each status data, the first new critical voltage is determined to be midway between the first and fifth voltage intervals, i.e., the midway voltage between read level 1 and read level 4. This voltage can be obtained by adding half the difference between read level 1 and read level 4 to read level 1, or by subtracting half the difference between read level 1 and read level 4 from read level 4. Similarly, a second new critical voltage is determined to be midway between the fifth and tenth voltage sections, i.e., the midway voltage between read level 5 and read level 9. This voltage can be obtained by adding an offset value to read level 5 or subtracting an offset value from read level 9. A third new critical voltage is determined to be midway between the tenth and sixteenth voltage sections, i.e., the midway voltage between read level 10 and read level 15. This voltage can be obtained by adding an offset value to read level 10 or subtracting an offset value from read level 15. The determined new critical voltage does not necessarily have to be midway between the two base critical voltages and can be adjusted according to actual conditions. However, determining the new critical voltage midway between the two base voltages can maximize the reliability of each data.

[0081] 13, which is a flow diagram of a tenth embodiment of the data storage method according to the present application. This method is a further extension of the above-mentioned embodiment, and includes the following step S101.

[0082] S101: To read the second data information stored in the storage unit, voltage information in the storage unit is compared with four voltage intervals.

[0083] After the data in the buffer area is stored in the memory unit, when reading, the data is read according to the determined new threshold voltage value.

[0084] Based on the above embodiment, it can be envisioned that in a QLC storage unit, data is written to the first, second, and third buffer areas according to the original threshold voltage values, and then eight voltage state data are obtained through logical operations so that the eight voltage state data are evenly distributed throughout the entire voltage range. Furthermore, eight new voltage ranges and seven corresponding threshold voltage values ​​are determined according to the original voltage ranges and threshold voltage values ​​corresponding to the eight voltage state data. The seven new threshold voltage values ​​may be obtained based on the threshold voltage values ​​corresponding to the eight voltage state data. After the data information stored in the buffer is written to the storage unit, the storage unit is read using the seven new threshold voltage values. Such an embodiment of the method is also within the scope of protection of the present application.

[0085] 14, which is a flow diagram of an eleventh embodiment of the data storage method according to the present application, includes the following steps S111 to S113.

[0086] S111: Data is written to the first buffer area, the second buffer area, and the third buffer area of ​​the page buffer.

[0087] In the QLC memory unit, data is written to the first buffer area, the second buffer area, and the third buffer area according to the original read level voltage value, in accordance with the original memory write flow.

[0088] S112: Write data into the fourth buffer area.

[0089] The data written to the fourth buffer area is obtained by performing a logical operation using the computing resources of the page buffer from any two of the data in the first buffer area, the data in the second buffer area, and the data in the third buffer area. The third data information is determined by the data in the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area.

[0090] S113: The third data information stored in the page buffer is written to the storage unit.

[0091] After the data has been written to the buffer, the final data is written to the storage unit to complete the data storage.

[0092] In actual application, the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area may be any one of all the configured buffer areas, and the terms first, second, third, and fourth do not limit the locations of the buffer areas, but merely indicate that the locations of the buffer areas are different.

[0093] 15, which is a schematic flow diagram of a twelfth embodiment of the data storage method according to the present application, which is a further expansion of step S113 and includes the following steps S121 to S122.

[0094] S121: Determine a corresponding section voltage signal according to the third data information buffered in the page buffer.

[0095] After writing data to the first buffer area, the second buffer area, and the third buffer area, data in the fourth buffer area is obtained through logical operations using the calculation resources of the page buffer, and eight types of voltage status data can finally be obtained, and these eight types of status data become the data information currently stored in the buffer.

[0096] After the eight kinds of voltage status data are determined, the original voltage range and the critical voltage value of the voltage range can be further determined. The determination procedure can be referred to the above embodiment and will not be repeated here.

[0097] S122: Write third data information into the storage unit according to the corresponding section voltage signal.

[0098] According to the determined buffer data, the voltage interval and the threshold voltage value are determined. Data is written to the storage unit based on the interval voltage. The corresponding data information is written to the storage unit at a voltage within the corresponding voltage interval. Please refer to the above embodiment, and the description will not be repeated here.

[0099] 16, which is a flow diagram illustrating a thirteenth embodiment of the data storage method according to the present application. This method is a further extension of the above-described embodiments, and includes the following steps S131 to S132.

[0100] S131: Determine 16 voltage intervals corresponding to 4-bit data.

[0101] In QLC memory mode, one memory unit can store 4 bits corresponding to 16 types of state data, each occupying a voltage range, which can be easily distinguished according to the critical voltage of the voltage range during reading. The 16 voltage ranges are determined by 15 critical voltage values, which are read level 1 to read level 15.

[0102] S132: Determine eight voltage sections defined by the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area.

[0103] After the logical operation, only eight of the 16 types of state data remain. For example, assume that the voltage intervals corresponding to the remaining eight types of voltage state data after the logical operation are interval 1, interval 3, interval 5, interval 7, interval 9, interval 11, interval 13, and interval 16. Meanwhile, to increase the reliability of the data, a new read voltage must be determined for it, i.e., a new voltage interval must be defined for it to distinguish the remaining eight voltage states. The eight voltage intervals are determined by seven critical voltage values.

[0104] Each of the seven critical voltage values ​​is represented by one of the 15 critical voltage values ​​and the corresponding offset. After determining the voltage ranges corresponding to the remaining eight types of status data, the respective critical voltages are determined accordingly. The remaining ranges are the first, third, and fifth ranges. Assume that the critical voltage corresponding to the third range is read level 2 and 3, the first range corresponds to read level 1, and the fifth range corresponds to read levels 4 and 5. The first new critical voltage is midway between the first and third ranges and may be the midpoint voltage between read level 1 and read level 2. This voltage can be obtained by adding half the difference between read level 1 and read level 2 to read level 1 or by subtracting half the difference between read level 1 and read level 2 from read level 4. The other new critical voltages are determined in accordance with the above description. The determined new critical voltage does not necessarily lie midway between the two basic critical voltages and can be adjusted according to actual conditions. However, if the new critical voltage is determined to be midway between the two base voltages, the reliability of each data can be improved to the maximum extent possible.

[0105] 17, which is a flow diagram of a fourteenth embodiment of the data storage method according to the present application. This method is a further extension of the above-mentioned embodiments, and includes the following step S141.

[0106] S141: To read the third data information stored in the storage unit, voltage comparison is performed between the voltage information in the storage unit and the eight voltage intervals.

[0107] After the data in the buffer area is stored in the memory unit, when reading, the data is read according to the eight new threshold voltage values ​​determined above.

[0108] Based on the above embodiment, furthermore, for a storage device capable of storing multiple bits of information in one storage unit, any technical aspect in which the bit information stored in one storage unit is reduced by logical operations in the above page buffer, but data reliability is increased, is within the scope of protection of the present application.

[0109] As shown in FIG. 18, FIG. 18 is a structural schematic diagram of an embodiment of a storage device according to the present invention.

[0110] The storage device includes a processor 110 and a memory 120 .

[0111] The processor 110 controls the operation of the storage device and may also be referred to as a CPU (Central Processing Unit). The processor 110 may be an integrated circuit chip capable of processing signal sequences. The processor 110 may also be a general-purpose processor, a digital signal sequence processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The general-purpose processor may be a microprocessor, any conventional processor, or the like.

[0112] The memory 120 stores instructions and program data necessary for the operation of the processor 110 .

[0113] The processor 110 is for executing instructions such that the method according to any one embodiment and possible combination of the above-mentioned data storage methods of the present application is implemented.

[0114] The storage device may be a TLC / QLC NAND FLASH memory.

[0115] As shown in FIG. 19, FIG. 19 is a structural schematic diagram of one embodiment of a computer-readable storage device according to the present application.

[0116] One embodiment of the readable storage device of the present application includes a memory 210, which stores program data, and when the program data is executed, realizes a method according to any one embodiment and possible combinations of the data storage method of the present application.

[0117] The memory 210 may be a medium capable of storing program instructions, such as a USB flash drive, a portable hard disk, a read-only memory (ROM), a random access memory (RAM), or a magnetic disk, or may be a server that stores the program instructions, and the server may transmit the stored program instructions to other devices to operate them, or may operate the stored program instructions itself.

[0118] In summary, the present invention does not determine the data in the first and second buffer areas and then determine the data in the third buffer area using a threshold voltage value, but rather performs a logical operation on the data in the first and second buffer areas to obtain the data in the third buffer area. Since the buffer data has two types, 0 and 1, and each buffer area stores one bit of data information, the prior art would obtain eight types of data information by determining the first, second, and third buffer data using a threshold voltage value. In contrast, the present invention obtains the data in the third buffer area by performing an operation on the already determined data in the first and second buffer areas, i.e., by making the data status of the third buffer area correspond to four types of status data in the first and second buffer areas, the data information finally obtained based on the data in the first, second, and third buffer areas is only four types instead of the original eight types. Because the number of types of data information is reduced, larger voltage ranges can be defined for the four types of data information within the same maximum voltage range, thereby increasing the degree of error tolerance against the data voltage offset and improving the reliability of the stored data. Furthermore, the logical operation process is realized by the logical operation function in the buffer, and there is no need to borrow the computation resources of the upper layer, which saves the computation power of the system.

[0119] It should be understood that in some embodiments of the present application, the disclosed methods and devices may be realized in other forms. For example, the device embodiments described above are merely exemplary. For example, the division of the modules or units is merely a division based on logical functions, and other division schemes may be used in actual implementation. For example, multiple units or components may be incorporated or integrated into another system, or some features may be omitted or not implemented.

[0120] The units described as separate components may or may not be physically separated, and the components listed as units may or may not be physical units, i.e., they may be co-located or distributed across multiple network units, and some or all of the units may be selected according to actual needs to achieve the objectives of the aspects of this embodiment.

[0121] Furthermore, the functional units in each embodiment of the present application may be integrated into a single processing unit, or each unit may be physically provided separately. Furthermore, two or more units may be integrated into a single unit. The integrated unit may be realized in the form of hardware, or may be realized by adding a software functional unit to hardware.

[0122] The integrated units in the above other embodiments may be realized in the form of a software functional unit and stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the essential part of the technical aspects of the present application, the part that contributes to the prior art, or all or part of the technical aspects may be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions that cause a computer device (which may be a personal computer, a server, or a network device) or a processor to execute all or part of the steps of the methods described in each embodiment of the present application. The above-mentioned storage medium includes various media that can store program code, such as a USB flash drive, a portable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0123] The above are merely examples of the present application and do not limit the scope of the claims of the present application. Any equivalent structure or equivalent flow transformation made by utilizing the contents of the specification and drawings of the present application, or direct or indirect application to other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. 1. A data storage method comprising: writing data into a first buffer area and a second buffer area of ​​a page buffer; writing data into a third buffer area of ​​the page buffer, wherein the data written into the third buffer area is obtained from the data of the first buffer area and the data of the second buffer area through a logical operation using the calculation resources of the page buffer, and first data information is determined by the data of the first buffer area, the second buffer area, and the third buffer area; writing the first data information buffered in the page buffer to a storage unit; Including, A data storage method comprising:

2. The writing of data into the third buffer area of ​​the page buffer includes: performing a first logical operation on the data in the first buffer area and the data in the second buffer area to obtain intermediate data; performing a second logical operation on the intermediate data and the data in the first buffer area, and writing the resulting data into the third buffer area; or writing data obtained by performing a second logical operation on the intermediate data and the data in the second buffer area into the third buffer area; Including, 2. The data storage method according to claim 1.

3. The above-mentioned first logical operation on the data in the first buffer area and the data in the second buffer area to obtain intermediate data includes: After writing data into the first buffer area, copying the data in the first buffer area to the third buffer area; After writing the data into the second buffer area, performing a first logical operation on the data in the third buffer area and the data in the second buffer area to obtain intermediate data, and writing the intermediate data into the third buffer area; Including, writing data obtained by performing a second logical operation on the intermediate data and the data in the first buffer area into the third buffer area, writing data obtained by performing a second logical operation on the data in the third buffer area and the data in the first buffer area into the third buffer area; Including, 3. The data storage method according to claim 2.

4. 3. The method of claim 2, wherein the first logical operation is an XNOR logical operation and the second logical operation is an OR logical operation.

5. The writing of the first data information buffered in the page buffer to the storage unit includes: determining a corresponding section voltage signal according to the first data information buffered in the page buffer; writing the first data information into a storage unit according to the corresponding section voltage signal; 2. The method of claim 1, further comprising:

6. determining eight voltage intervals corresponding to three bits of data, the eight voltage intervals being determined by seven threshold voltage values; determining four voltage sections defined by the first buffer region, the second buffer region, and the third buffer region, the four voltage sections being defined by three critical voltage values; Among them, the three critical voltage values ​​are represented by one of the seven critical voltage values ​​and a corresponding offset amount.

6. The data storage method according to claim 5.

7. 7. The data storage method of claim 6, further comprising: comparing voltage information in the storage unit with the four voltage intervals to read the first data information stored in the storage unit.

8. writing data into a fourth buffer area of ​​the page buffer, wherein the data written into the fourth buffer area is obtained from any two of the data in the first buffer area, the data in the second buffer area, and the data in the third buffer area through a logical operation using a calculation resource of the page buffer, and second data information is determined by the data in the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area; writing the second data information buffered in the page buffer to a storage unit; Further comprising:

2. The data storage method according to claim 1.

9. The writing of the second data information buffered in the page buffer to the storage unit includes: determining a corresponding section voltage signal according to the second data information buffered in the page buffer; writing the second data information into a storage unit according to the corresponding section voltage signal; Including, 9. The data storage method according to claim 8.

10. determining 16 voltage intervals corresponding to 4-bit data, the 16 voltage intervals being determined by 15 threshold voltage values; determining four voltage sections defined by the first buffer region, the second buffer region, the third buffer region, and the fourth buffer region, the four voltage sections being defined by three threshold voltage values; Further comprising: Among them, one of the 15 critical voltage values ​​and a corresponding offset amount are used to represent each of the three critical voltage values.

10. The data storage method according to claim 9.

11. voltage comparison between the voltage information in the storage unit and the four voltage intervals to read the second data information stored in the storage unit; Further comprising:

11. The data storage method according to claim 10.

12. After writing data into the first buffer area and the second buffer area of ​​the page buffer, writing data to the third buffer area of ​​the page buffer; writing data into a fourth buffer area, wherein the data written into the fourth buffer area is obtained from any two of the data in the first buffer area, the data in the second buffer area, and the data in the third buffer area through a logical operation using the calculation resources of the page buffer, and third data information is determined by the data in the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area; writing the third data information stored in the page buffer to a storage unit; Including, 2. The data storage method according to claim 1.

13. The writing of the third data information stored in the page buffer to the storage unit includes: determining a corresponding section voltage signal according to the third data information buffered in the page buffer; writing the third data information into a storage unit according to the corresponding section voltage signal; Including, 13. The method of claim 12.

14. determining 16 voltage intervals corresponding to 4-bit data, the 16 voltage intervals being determined by 15 threshold voltage values; determining eight voltage sections defined by the first buffer region, the second buffer region, the third buffer region, and the fourth buffer region, the eight voltage sections being defined by seven threshold voltage values; Further comprising: Among them, the seven critical voltage values ​​are represented by one of the fifteen critical voltage values ​​and a corresponding offset amount.

14. The method of claim 13.

15. Further comprising: comparing voltage information in the storage unit with the eight voltage intervals to read the third data information stored in the storage unit; 15. The method of claim 14.

16. A storage device comprising a memory and a processor, the memory being for storing program data, the program data being executable by the processor to implement the data storage method according to any one of claims 1 to 15.

1. A storage device comprising:

17. The storage device is a TLC / QLC NAND FLASH memory.

17. The storage device according to claim 16.

18. A computer-readable storage device, characterized in that it stores program data that can be executed by a processor to implement the data storage method according to any one of claims 1 to 15.

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