Information processing device and information processing method

Abstract

To provide an information processing device and an information processing method for suppressing a data transfer error in executing a change or the like in a configuration within a region while performing data transfer with which an area of a certain size can be displayed on a screen of a display device.SOLUTION: An information processing device 1 includes a control part (a microcomputer 11), an image processing part (a video IC 12), and a storage part (a flash memory 13) for storing data of a screen to be output to a display part (a display device 14) through the image processing part. The control part sets a transfer speed of transferring data from the storage part to the image processing part to a transfer speed lower than a transfer speed before switching the screen when the image processing part switches the screen to be output to the display part, starts to transfer the data from the storage part to the image processing part, and causes the image processing part to change the screen to be output during a blank period until an output is started to the display part of the switched screen.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an information processing device and an information processing method. [Background technology]

[0002] Some information processing devices have an On-Screen Display (OSD) function. The OSD function is a function to display an additional display area (OSD) on at least a part of the screen of the display device. The OSD is displayed superimposed on an image provided to the user from the information processing device, such as the processing result of the information processing device or an image from a camera, and is used for setting or operating the information processing device itself.

[0003] In some cases, the display and non-display of the OSD, changes to the configuration displayed on the OSD, etc. are performed during the blank period between the drawing period of one screen and the drawing period of the next screen. In addition, in order to display and non-display the OSD, changes to the configuration of the OSD, etc., data transfer from an image storage device that stores data to be displayed on the OSD to an image processing device that processes the OSD is performed using Direct Memory Access (DMA). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-301428 Summary of the Invention [Problem to be solved by the invention]

[0005] When display devices become high-resolution and the dimensions of the area displayed on the screen, such as an OSD, become large enough, problems can arise: for example, if the data transfer rate from the image storage device to the image processing device is not appropriate for the screen size, the area cannot be displayed in time.

[0006] On the other hand, if the data transfer rate from the image storage device to the image processing device becomes high in order to keep up with the display of the area, data transfer errors become a problem, especially when transferring part of the data to be displayed in the area from the image storage device to the image processing device due to a change in the configuration of the area displayed on the screen.

[0007] An aspect of the present disclosure is to perform data transfer that allows an area of ​​a certain size to be displayed on the screen of a display device, while suppressing data transfer errors when making changes to the configuration within the area. [Means for solving the problem]

[0008] An embodiment of the disclosure is exemplified by an information processing device. The information processing device includes a control unit, an image processing unit, and a storage unit that stores screen data to be output to a display unit via the image processing unit. When the image processing unit switches the screen to be output to the display unit, the control unit sets a transfer rate for transferring data from the storage unit to the image processing unit to a transfer rate that is slower than the transfer rate before the screen is switched. The control unit then starts transferring data from the storage unit to the image processing unit and causes the image processing unit to change the screen to be output during a blank period until the screen after the switch starts to be output to the display unit. [Effects of the Invention]

[0009] According to the present information processing device, a certain size of area can be displayed on the screen of the display device. While transferring data, it is possible to suppress data transfer errors when changing the configuration within the area. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating an information processing apparatus according to the first embodiment. [Figure 2] FIG. 2 is a diagram illustrating a detailed configuration of a video IC. [Figure 3] FIG. 3 is a flowchart illustrating the processing of the information processing device. [Figure 4] FIG. 4 is a flowchart illustrating the details of DMA transfer and screen switching processing by the video IC. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an information processing apparatus and an information processing method according to the present embodiment will be described with reference to the drawings.

[0012] First Embodiment (System Configuration) FIG. 1 is a diagram illustrating an information processing device 1 according to a first embodiment. FIG. 1 illustrates a head unit 2 together with the information processing device 1. The information processing device 1 is, for example, a device called a Rear Seat Entertainment system (RSE) that is installed in a vehicle. The RSE provides content such as television broadcasts and video and audio played from media such as Digital Versatile Discs (DVDs) to passengers in the rear seats of the vehicle. The head unit 2 is a device that provides video, audio, navigation functions, and the like to passengers in the front seats.

[0013] As shown in FIG. 1, the information processing device 1 includes a microcomputer 11, a video integrated circuit (hereinafter referred to as a video IC 12), and a flash memory with a serial peripheral interface (SPI) (hereinafter referred to as a flash memory , flash memory 13) and a display device 14.

[0014] The microcomputer 11 is also called a microcontroller or a microcomputer. The microcomputer 11 includes, for example, a central processing unit (CPU) and a main memory unit. The PU executes a computer program deployed in an executable manner in the main memory, providing the functions of the information processing device 1. The main memory stores the computer program executed by the CPU, the data processed by the CPU, etc. The CPU is also called a processor. However, the CPU is not limited to a single processor and may have a multi-processor configuration. Furthermore, the CPU may be a single processor connected via a single socket and have a multi-core configuration. Through these processes, the microcomputer 11 accepts operations from the user, who is an occupant, and provides the user with various functions in response to the user's operations. The microcomputer 11 is an example of a control unit.

[0015] The video IC 12 cooperates with the microcomputer 11 to provide the user with various contents via the RSE. The video IC 12 outputs, for example, television broadcasts received by the head unit 2 or video played by the head unit 2 to the display device 14. The video IC 12 also acquires OSD screen data from the flash memory 13, superimposes it on the received television broadcasts or the played video, and outputs it to the display device 14.

[0016] In this embodiment, the video IC 12 is, for example, a Low Voltage Differential Signal (LV A video signal is supplied to the display device 14 via a LVDS interface. However, the interface between the video IC 12 and the display device 14 is not limited to LVDS. The video IC 12 and the display device 14 may be connected via, for example, digital RGB, analog RGB, or a Digital Visual Interface (DVI). In other words, the type of interface connected between the video IC 12 and the display device 14 is not limited. As long as the data processed by the video IC 12 can be output to the display device 14, the video IC 12 and the display device 14 may be connected via any interface. The video IC 12 is an example of an image processing unit.

[0017] The flash memory 13 stores the OSD screen data to be provided to the video IC 12 and parameters for changing the configuration of the OSD screen data. In this embodiment, the flash memory 13 communicates with the video IC 12 via SPI and provides data such as the OSD screen data and parameters to the video IC 12. However, in this embodiment, the storage of the OSD screen data and parameters for changing the configuration of the screen data is not limited to the flash memory 13. The information processing device 1 may use a general nonvolatile memory called an Electrically Erasable Programmable Read-Only Memory (EEPROM) instead of the flash memory 13. A volatile memory may also be included. The flash memory 13 is an example of a storage unit.

[0018] Furthermore, in the information processing device 1 of this embodiment, the connection between the flash memory 13 and the video IC 12 is not limited to SPI. The connection between the flash memory 13 and the video IC 12 may be, for example, an Inter-Integrated Circuit (I2C) or a Peripheral Component Interconnect (PCI) Express. The connection between the flash memory 13 and the video IC 12 may also be a parallel bus. In other words, in this embodiment, the type of interface or bus connecting the flash memory 13 and the video IC 12 is not limited. As long as data stored in the flash memory 13 can be transferred to the video IC 12, the flash memory 13 and the video IC 12 may be connected by any interface or bus.

[0019] The display device 14 displays screen data output from the video IC 12. The display device 14 is, for example, an organic electroluminescent display (OLED), a liquid crystal display (LCD), etc. The display device 14 is an application specific display (ADS) for display. The ASIC 141 has a video integrated circuit (ASIC 141). 2 and outputs drive signals to drive OLEDs, LCDs, etc.

[0020] In this embodiment, the head unit 2 is not an essential component, and the head unit 2 may be omitted. Furthermore, in this embodiment, the information processing device 1 is not limited to an RSE, and may be a television device, a video playback device, an audio playback device, a personal computer, or the like installed in a home. In this case, a playback device for a DVD, a Blu-ray disc, or the like may be connected to the information processing device instead of the head unit 2. The information processing device 1 may be one that superimposes an OSD on screen data from a device that supplies content, such as the head unit 2, and outputs the data to a display, such as an OELD or LCD.

[0021] FIG. 2 is a diagram illustrating a detailed configuration of the video IC 12. Also illustrated in FIG. 2 are a microcomputer 11, a flash memory 13, and a display device 14. As shown in FIG. 2, the video IC 12 includes an SPI circuit 121, a readout unit 122, an I2C circuit 123, a register group 124, a content output unit 125, a composition circuit 126, and a display driver circuit 127. Each unit in FIG. 2 is essentially formed by a hardware circuit. However, at least a portion of the configuration in FIG. 2 may be provided by a program loaded in memory and a processor.

[0022] The SPI circuit 121 communicates with the SPI circuit built in the flash memory 13 in accordance with instructions from the reading unit 122, and acquires OSD screen data and the like from the flash memory 13. The SPI circuit 121 passes the data acquired from the flash memory 13 to the reading unit 122.

[0023] The reading unit 122 acquires data from the flash memory 13 through the SPI circuit 121. The reading unit 122 supplies the acquired OSD screen data and the like to the synthesis circuit 126. do.

[0024] The content output unit 125 acquires, for example, video data from television broadcasting from the head unit 2, video data played back from a DVD or the like (also referred to as content data), and supplies it to the synthesis circuit 126.

[0025] I The 2C circuit 123 communicates with the microcomputer 11 and stores setting values ​​from the microcomputer 11 in the register group 124. The register group 124 includes registers that store various control parameters. For example, the register group 124 includes a register that causes the microcomputer 11 to start processing by the video IC, a register that specifies the clock frequency when the SPI circuit 121 receives data transferred from the flash memory 13, and a register that specifies the OSD configuration. The register that specifies the OSD configuration holds setting values ​​such as the positions or colors of knobs, switches, volume controls, indicators, etc. on the OSD.

[0026] The flash memory 13 and the SPI circuit 121 transfer data via SPI at a clock frequency according to a parameter specified in a register specifying the clock frequency in the register group 124. The synthesis circuit 126 changes the configuration of the OSD screen obtained from the readout unit 122 in accordance with the parameter or command in the register group 124.

[0027] Among the registers of the register group 124, data is set in at least some of the registers that specify the OSD configuration by Direct Memory Access (DMA) transfer between the video IC 12 and the flash memory 13. In the DMA transfer, data obtained from the flash memory 13 is taken into the registers of the register group 124 without the intervention of the microcomputer 11. Note that the process of transferring data from the flash memory 13 to the readout unit 122 via the SPI circuit is also a type of process that uses DMA transfer.

[0028] However, the data handed over to the readout unit 122 is different from the process of reading data (control parameters) into the registers of the register group 124 in that the data is read in in blocks of OSD screen data. Therefore, even if the data transfer rate from the flash memory 13 is high enough, data transfer errors (also called communication errors) are unlikely to occur in the data transfer via the readout unit 122. On the other hand, data transfer errors are likely to occur when setting data (control parameters) into the registers of the register group 124. For example, if the display device 14 is a full high-definition (FHD) display, the data transfer rate from the flash memory 13 will be higher than for formats other than FHD, and data transfer errors are likely to occur.

[0029] The process of taking data into the register of register group 124 that specifies the OSD configuration and changing the OSD screen configuration in synthesis circuit 126 is executed during a blank period when no data is output from a display such as an OLED in display device 14. Here, the blank period is the period between a refresh period in which each pixel on the screen is drawn and the next refresh period, during which the elements that make up each pixel on the screen are not driven.

[0030] The blank period of the display can be detected by a vertical synchronization signal (V-Sync) among the signals transmitted from the display drive circuit 127 to the display device 14. Therefore, a part of the vertical synchronization signal (V-Sync) from the display drive circuit 127 is branched off and supplied to the register group 124. More specifically, the vertical synchronization signal (V-Sync) is supplied to a control circuit that sets data in the register group 124. The register group 124 is instructed to start and end the blank period detected by the vertical synchronization signal (V-Sync). Then, during this blank period, the synthesis circuit 12 switches the OSD screen, that is, changes the OSD screen configuration. Execute.

[0031] The composition circuit 126 combines the content data from the content output unit 125 with the OSD screen data and the like supplied from the readout unit 122. More specifically, among the pixels of the screen occupied by the content data, the composition circuit 126 replaces the pixels in the area occupied by the OSD screen data with the OSD screen data. Also, during the blank period, the composition circuit 126 changes the position or configuration of each part on the OSD in accordance with parameters specifying each part of the OSD contained in the register group 124. The position or configuration of each part on the OSD refers to the operating status of knobs, buttons, volume controls, etc. displayed on the OSD, the display status of indicators, etc.

[0032] The combining circuit 12 outputs the combined data to the display driver circuit 127. The display driver circuit 127 converts the screen data combined by the combining circuit 126 into data that conforms to an LVDS interface, for example, and outputs it to the display device 14.

[0033] (Processing flow) 3 is a flowchart illustrating the processing of the information processing device 1 according to this embodiment. These processing steps are executed by the microcomputer 11 and the video IC 12. The processing of the video IC 12 is executed by a hardware circuit. However, the processing of the video IC 12 may also be executed by a processor according to a program stored in memory.

[0034] In this process, the microcomputer 11 first sets a clock frequency slower than the current clock frequency in the SPI CLK setting register of the register group 124 via the I2C circuit 123. Then, the microcomputer 11 activates DMA transfer by the video IC 12 (S31). The current clock frequency is a clock frequency fast enough for the video IC 12 to acquire OSD screen data from the flash memory 13 and display it on the display device 14. This current clock frequency is an appropriate value determined based on the size of the OSD screen, such as the horizontal length and the amount of data per line. This current clock frequency is also the clock frequency used for normal rendering of the OSD screen. The data transfer rate between the flash memory 13 and the video IC 12 is determined based on this clock frequency setting. The process of S31 is an example of a process for setting the transfer rate for transferring data from the flash memory 13 (storage unit) to the video IC 12 (image processing unit) slower than the transfer rate before switching screens. The process of S31 is also an example of starting the transfer of data from the flash memory 13 (storage unit) to the video IC 12 (image processing unit).

[0035] On the other hand, a clock frequency slower than the optimum value set in S31 reduces the occurrence of communication errors when the video IC 12 acquires data from the flash memory 13 via DMA and sets the acquired data in the registers of the register group. The clock frequency slower than the optimum value set in S31 is also a clock frequency at which the video IC can properly refresh the OSD screen on the display device 14. That is, a clock frequency slower than the optimum value is also a frequency at which the video IC can acquire OSD screen data from the flash memory 13 and cause the display device 14 to draw the OSD screen during the screen refresh period, which is a non-blank period. This clock frequency slower than the optimum value allows data transfer at a transfer speed slower than the optimum value. Even at this transfer speed slower than the optimum value, the video IC 12 acquires OSD screen data from the flash memory 13 and properly draws it on the display device 14. That is, a transfer speed slower than the optimum value can be said to be a transfer speed at which distortion of the screen output to the display device 14, which is the display unit, is suppressed after the slow transfer speed is set. In other words, a clock frequency slower than this optimum value can be said to be a slow value within the range in which the OSD screen can be drawn, which is determined by the size of the OSD screen, for example, the horizontal length, the amount of data per line, etc.

[0036] The clock frequency that is the optimum value for normal operation and the optimum value set by S31 are different. Any slower clock frequency may be determined experimentally or empirically. For example, this clock frequency may be adjusted and determined experimentally or empirically based on the specifications of the information processing device 1 or the occurrence of DMA transfer errors in the information processing device 1. A screen that displays content from the head unit 2 or the like on the display device 14 is defined as a first screen. The OSD screen can be considered a second screen that is formed by superimposing it on at least a partial area of ​​the first screen. It can be said that a transfer speed slower than the appropriate value is set according to the OSD screen, i.e., the second screen.

[0037] By setting S31, the video IC 12 draws the OSD screen at a clock frequency slower than the appropriate value, executes DMA, and switches the screen during the blank period between screen refreshes on the display device 14 (S32). The processing of S32 is an example of the microcomputer 11 (controller) causing the video IC 12 (image processor) to change the screen to be output during the blank period until the microcomputer 11 (controller) starts outputting the switched screen to the display device 14 (display unit).

[0038] Then, when the video IC 12 has completed switching the screen, the microcomputer 11 sets the original clock frequency, i.e., a faster clock frequency of an appropriate value, in the SPI CLK setting register (S33). The microcomputer 11 determines the completion of the video IC's screen switching from the value of a register that indicates the completion of processing, which is included in the register group 124, etc. The microcomputer 11 may also determine the completion of the video IC's screen switching from the vertical synchronization signal (V-Sync) in the display device 14. As described above, the information processing device 1 sets the SPI CLK setting register to the original clock frequency, i.e., a faster clock frequency of an appropriate value (S33). The SPI CLK is set to be slower than the normal value. After the information processing device 1 executes the DMA transfer, it returns the SPI CLK to the normal value. This allows the normal SPI CLK to be used at times other than during the DMA transfer. That is, data transfer is carried out between the flash memory 13 and the video IC 12 at the normal data transfer rate.

[0039] Figure 4 is a flowchart illustrating the details of the DMA transfer and screen switching process (S32 in Figure 3) by the video IC. As described in Figure 3, these processes are performed by hardware circuits. However, the processes of the video IC 12 may also be performed by a processor according to a program in memory.

[0040] The process in FIG. 4 is initiated by an instruction from the microcomputer 11. At this time, the SPI clock frequency is set to a slow clock frequency by the setting of the microcomputer 11. When the process in FIG. 4 is initiated, the video IC 12 determines whether or not a blank period has begun based on the vertical synchronization signal that drives the display device 14 (S41). If the determination in S41 is that the period is not a blank period (determination of NO), the video IC 12 displays a normal OSD screen (S42). The normal OSD screen is a screen obtained from the flash memory 13, and is a screen in which the configuration on the OSD screen has not been changed. The process in S43 can be considered normal processing that is executed when there has been no change in the OSD screen.

[0041] If the determination in S41 is that the display device 14 is in a blank period (determination of YES), the video IC 12 obtains a register value specifying a change to the OSD screen through DMA transfer (S43). The video IC 12 changes the configuration of the OSD screen in accordance with the register value and outputs the changed configuration to the display driver circuit 127 (S44). That is, the video IC 12 switches the OSD screen to the changed screen in accordance with the register setting during the blank period of the display device 14. This process can also be called a process of changing to the changed screen.

[0042] (Effects of the embodiment) As described above, in the information processing device 1 of this embodiment, the configuration of the OSD screen is determined in the process of S32. When changing and switching the configuration of the OSD screen, the microcomputer 11 sets the SPI clock frequency slower than the normal optimum value (normal value). Therefore, the DMA transfer from the flash memory 13 is performed at a data transfer rate slower than the normal value. As a result, data transfer errors are reduced when data is set in the registers of the register group 124. That is, when changing the configuration of the OSD screen in accordance with a user operation, for example, the information processing device 1 can reduce communication errors during data transfer, change the screen during the display blank period, and switch to the changed OSD screen.

[0043] Furthermore, in the information processing device 1 of this embodiment, a clock frequency slower than the normal value can be said to be a slow value within a range determined by the size of the OSD screen, which is the second screen, for example, the horizontal length, the amount of data per line, etc. Therefore, in this embodiment, it is possible to set an appropriate clock frequency (normal value) according to the OSD screen and a clock frequency slower than the normal value. Also, in this embodiment, it is possible to set an appropriate SPI data transfer rate (normal value) according to the OSD screen and a data transfer rate slower than the normal value. In this embodiment, the information processing device 1 can reduce data transfer errors by setting a slow clock frequency as described above.

[0044] Furthermore, in the information processing device 1 of this embodiment, even at a clock frequency slower than the normal value, the video IC can obtain OSD screen data from the flash memory 13 during the screen refresh period, which is a non-blank period, and display it on the display device 14. Therefore, the information processing device 1 of this embodiment reduces data transfer errors when register settings are made in association with changes to the OSD screen, and suppresses distortion of the OSD screen, enabling normal rendering. [Explanation of symbols]

[0045] 1. Information processing equipment 2 head units 11 Microcomputer 12 Video IC 13. Flash Memory 14 Display device 121 SPI circuit 122 Readout section 123 I2C circuit 124 registers 125 Content Output Unit 126 Synthesis circuit 127 Display driver circuit

Claims

1. A control unit; an image processing unit; a storage unit that stores data of an on-screen display screen to be output to a display unit via the image processing unit and parameters for switching settings of the on-screen display screen; the control unit sets the transfer speed at which the parameters are DMA transferred from the memory unit to the image processing unit to a second transfer speed that is slower than the first transfer speed at which data of the on-screen display screen is transferred from the memory unit to the image processing unit during a blank period in which pixels of the display unit are not updated, in order for the image processing unit to switch the on-screen display screen that is output to the display unit.

2. 2. The information processing device according to claim 1, wherein the first transfer rate is determined according to the size of the on-screen display screen, and is a transfer rate that is sufficiently high to display the on-screen display screen on the display unit without causing any screen distortion.

3. The information processing apparatus according to claim 1 , wherein the control unit sets the data transfer rate from the storage unit to the image processing unit to the first transfer rate after the on-screen display screen has been switched.

4. An information processing method in which a computer sets a transfer rate at which parameters for switching settings of an on-screen display screen are DMA transferred from a storage unit to an image processing unit during a blank period in which pixels of the display unit are not updated, in order to switch an on-screen display screen output by an image processing unit to a second transfer rate that is slower than a first transfer rate at which data of the on-screen display screen is transferred from the storage unit to the image processing unit.

Images