Trans chip, signal transmission device

Abstract

This transformer chip, which forms a signal-transmitting device, has, for example, a first wiring layer, a second wiring layer different from the first wiring layer, a primary winding formed on the first wiring layer, a secondary winding formed on the second wiring layer to be magnetically coupled with the primary winding, and a shield electrode formed as to be disposed between the primary winding and the secondary winding.

Description

[Technical Field]

[0001] The invention disclosed herein relates to a transformer chip and a signal transmission device. [Background technology]

[0002] BACKGROUND ART Signal transmission devices that transmit pulse signals while insulating input and output have been used in a variety of applications (such as power supply devices or motor drive devices).

[0003] An example of the prior art related to the above is Patent Document 1 by the applicant of the present application. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-011108 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in conventional signal transmission devices, there is room for further improvement in the process of reducing instantaneous transient in-phase noise (so-called common mode noise) that is superimposed on each of the received pulse signals input in parallel to the secondary-side pulse receiving circuit.

[0006] In view of the above-mentioned problems discovered by the inventors of the present application, the invention disclosed in this specification aims to provide a signal transmission device that is less susceptible to the effects of common mode noise, and a transformer chip used therein. [Means for solving the problem]

[0007] The transformer chip disclosed in this specification has, for example, a first wiring layer, a second wiring layer different from the first wiring layer, a primary winding formed on the first wiring layer, a secondary winding formed on the second wiring layer so as to be magnetically coupled to the primary winding, and a shield electrode formed so as to be interposed between the primary winding and the secondary winding.

[0008] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto. [Effects of the Invention]

[0009] According to the invention disclosed in this specification, it is possible to provide a signal transmission device that is less susceptible to the effects of common mode noise. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. [Figure 2] FIG. 2 is a diagram showing how potential fluctuations occur between GND1 and GND2. [Figure 3] FIG. 3 is a diagram showing an example of a malfunction caused by common mode noise. [Figure 4] Figure 4 shows the principle behind the occurrence of signal transmission abnormalities (ideal transformer, normal signal input). [Figure 5] Figure 5 shows the principle behind the occurrence of signal transmission abnormalities (with an ideal transformer and CM noise input). [Figure 6] FIG. 6 shows the principle behind the occurrence of signal transmission abnormalities (when a normal signal is input to an actual transformer). [Figure 7] Figure 7 shows the principle behind the occurrence of signal transmission abnormalities (when an actual transformer is subjected to CM noise input). [Figure 8] FIG. 8 is a diagram showing an example of the introduction of a noise canceller. [Figure 9] FIG. 9 is a diagram illustrating an example of a noise cancellation operation. [Figure 10] FIG. 10 is a diagram showing the basic structure of a transformer chip. [Figure 11] FIG. 11 is a perspective view of a semiconductor device used as a two-channel transformer chip. [Figure 12] FIG. 12 is a plan view of the semiconductor device shown in FIG. [Figure 13] FIG. 13 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 14] FIG. 14 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 15] FIG. 15 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 16] FIG. 16 is a cross-sectional view taken along line IX-IX shown in FIG. [Figure 17] FIG. 17 is an enlarged view of the region X shown in FIG. [Figure 18] FIG. 18 is an enlarged view of region XI shown in FIG. [Figure 19] FIG. 19 is an enlarged view of region XII shown in FIG. [Figure 20] FIG. 20 is an enlarged view of region XIII shown in FIG. 15, showing the isolation structure. [Figure 21] FIG. 21 is a diagram schematically illustrating an example of the layout of a transformer chip. [Figure 22] FIG. 22 is a diagram showing an example of introducing a shield electrode. [Figure 23] FIG. 23 is a diagram showing the vertical structure of a transformer chip equipped with a shield electrode. [Figure 24] FIG. 24 is a diagram showing the noise reduction effect achieved by introducing a shield electrode. [Figure 25] FIG. 25 is a diagram (full surface) showing the relationship between the layout of the shield electrode and the signal transmission capacity. [Figure 26] FIG. 26 is a diagram (O type) showing the relationship between the shield electrode layout and signal transmission capability. [Figure 27]FIG. 27 is a diagram (type C) showing the relationship between the shield electrode layout and signal transmission capability. [Figure 28] FIG. 28 is a diagram showing a first planar layout example (C type) of the shield electrode. [Figure 29] FIG. 29 is a diagram showing a second planar layout example of the shield electrode (size change of the C-shape). [Figure 30] FIG. 30 is a diagram showing a third planar layout example (O-type) of the shield electrode. [Figure 31] FIG. 31 is a diagram showing a fourth planar layout example (single stroke type) of the shield electrode. [Figure 32] FIG. 32 is a diagram showing a first example of the cross-sectional structure of the primary winding, secondary winding, and shield electrode. [Figure 33] FIG. 33 is a diagram showing a second cross-sectional structure example of the primary winding, secondary winding, and shield electrode. [Figure 34] FIG. 34 is a diagram showing a third example of the cross-sectional structure of the primary winding, secondary winding, and shield electrode. [Figure 35] FIG. 35 is a diagram showing a fourth example of the cross-sectional structure of the primary winding, secondary winding, and shield electrode. [Figure 36] FIG. 36 is a diagram showing a fifth example of the cross-sectional structure of the primary winding, secondary winding, and shield electrode. [Figure 37] FIG. 37 is a diagram showing the relationship between the presence or absence and shape of the shield electrode and the inter-coil capacitance. [Figure 38] FIG. 38 is a diagram showing a planar layout of pads and coils. [Figure 39] FIG. 39 is a diagram showing a first planar layout of the shield electrode overlapping the coil of FIG. [Figure 40] FIG. 40 is a diagram in which FIG. 38 and FIG. 39 are superimposed. [Figure 41] FIG. 41 is a diagram showing a second planar layout of the shield electrode overlapping the coil of FIG. [Figure 42] FIG. 42 is a diagram in which FIG. 38 and FIG. 41 are superimposed. DETAILED DESCRIPTION OF THE INVENTION

[0011] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0012] The controller chip 210 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC1 (for example, up to 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0013] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signals S11 or S21 in response to the logic level of the input pulse signal IN.

[0014] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0015] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0016] The driver chip 220 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC2 (for example, up to 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0017] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0018] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0019] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0020] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0021] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0022] More specifically, the transformer 231 outputs a reception pulse signal S12 from the secondary coil 231s in response to a transmission pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s in response to a transmission pulse signal S21 input to the primary coil 232p.

[0023] In this way, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0024] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0025] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0026] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs) / plug-in hybrid vehicles (PHVs), or xEVs such as fuel cell electric vehicles (FCEVs) / FCVs (fuel cell electric vehicles)).

[0027] Furthermore, the controller chip 210 and the driver chip 220 can both be manufactured using existing processes with a proven track record, and there is no need to conduct new reliability tests, which contributes to shortening development time and reducing development costs.

[0028] Furthermore, even when a DC isolation element other than a transformer (for example, a photocoupler) is used, it can be easily accommodated by simply replacing the transformer chip 230, which eliminates the need to redevelop the controller chip 210 and the driver chip 220, thereby contributing to shortening the development period and reducing development costs.

[0029] <Considerations regarding common mode noise> 2 is a diagram showing how potential fluctuations occur between GND1 and GND2. As shown in the figure, when a potential fluctuation ΔV / Δt (i.e., noise) occurs between the ground potential GND1 of the primary circuit system 200p and the ground potential GND2 of the secondary circuit system 200s, noise appears on the secondary side of the transformer chip 230, which may cause problems in signal transmission.

[0030] FIG. 3 is a diagram showing an example of a malfunction caused by common mode noise, and depicts, from top to bottom, an input pulse signal IN, received pulse signals S12 and S22, and an output pulse signal OUT.

[0031] First, a brief description of the normal pulse signal transmission operation will be given. At time t11, when the input pulse signal IN rises to high level, the transformer 231 is pulse-driven, causing a normal pulse to rise in the received pulse signal S12. As a result, the output pulse signal OUT rises to high level. Also, at time t12, when the input pulse signal IN falls to low level, the transformer 232 is pulse-driven, causing a normal pulse to rise in the received pulse signal S22. As a result, the output pulse signal OUT falls to low level.

[0032] On the other hand, an erroneous signal due to common-mode noise is generated simultaneously in both transformers 231 and 232. When such an erroneous signal occurs, the output pulse signal OUT switches to an unintended logic level. In this diagram, the output pulse signal OUT rises to a high level even though the input pulse signal IN is maintained at a low level.

[0033] 4 to 7 are diagrams each showing the principle of occurrence of abnormal signal transmission due to the common mode noise.

[0034] First, let us consider signal transmission using an ideal transformer (i.e., a transformer with no inter-coil capacitance between the primary and secondary windings) with reference to Figures 4 and 5. As shown in Figure 4, when a normal transmission pulse signal (excitation voltage VL1) is input to the primary winding (equivalent to the primary coil) of the transformer, an induced voltage VL2 is generated in the secondary winding (equivalent to the secondary coil). If this induced voltage VL2 exceeds the buffer threshold voltage Vth, a normal reception pulse signal (output voltage Vout) is generated. On the other hand, as shown in Figure 5, even if common-mode noise VCM occurs between the primary and secondary circuit systems, no erroneous signal is transmitted to the secondary circuit system.

[0035] Next, let's consider signal transmission using an actual transformer (i.e., a transformer with an inter-coil capacitance C between the primary and secondary windings) with reference to Figures 6 and 7. As shown in Figure 6, even when an actual transformer is used, when a normal transmission pulse signal (excitation voltage VL1) is input to the primary winding of the transformer, an induced voltage VL2 is generated in the secondary winding. If this induced voltage VL2 exceeds the buffer threshold voltage Vth, a normal reception pulse signal (output voltage Vout) is generated. In other words, the normal signal transmission operation is not particularly different from when an ideal transformer is used. On the other hand, as shown in Figure 7, when common-mode noise VCM occurs between the primary and secondary circuit systems, an erroneous signal is transmitted to the secondary circuit system via the inter-coil capacitance C, unlike when an ideal transformer is used.

[0036] Note that, if a signal transmission abnormality occurs due to common mode noise, it may lead to malfunction or failure of the application, so the signal transmission device 200 is required to have high common mode transient immunity (CMTI).

[0037] <General noise countermeasures (introduction of noise cancellers)> 8 is a diagram showing an example of introducing a noise canceller (noise mask circuit) into the signal transmission device 200. In the signal transmission device 200 of this configuration example, a noise canceller 225 is introduced in the driver chip 220 before the pulse receiving circuit 223.

[0038] The noise canceller 225 of this configuration example includes buffers BUF1 to BUF4, delay units DLY1 to DLY4, and AND gates AND1 and AND2.

[0039] The buffer BUF1 raises its output signal to a high level when the received pulse signal S12 becomes higher than the threshold voltage Vth1, and lowers its output signal to a low level when the received pulse signal S12 becomes lower than the threshold voltage Vth.

[0040] Buffer BUF2 raises the output signal to the high level when the received pulse signal S12 becomes higher than the threshold voltage Vth2 (<Vth1), and lowers the output signal to the low level when the received pulse signal S12 becomes lower than the threshold voltage Vth2.

[0041] Buffer BUF3 raises the output signal to the high level when the received pulse signal S22 becomes higher than the threshold voltage Vth1, and lowers the output signal to the low level when the received pulse signal S22 becomes lower than the threshold voltage Vth.

[0042] Buffer BUF4 raises the output signal to the high level when the received pulse signal S22 becomes higher than the threshold voltage Vth2 (<Vth1), and lowers the output signal to the low level when the received pulse signal S22 becomes lower than the threshold voltage Vth2.

[0043] Delay unit DLY1 generates the main signal A1 by applying a predetermined delay to the output signal of buffer BUF1.

[0044] Delay unit DLY2 generates the mask signal B2 by applying a predetermined delay to the output signal of buffer BUF2. For example, the mask signal B2 falls to the low level without delay when the output signal of buffer BUF2 rises to the high level, and rises to the high level when a predetermined mask period has elapsed.

[0045] Delay unit DLY3 generates the main signal B1 by applying a predetermined delay to the output signal of buffer BUF3.

[0046] Delay unit DLY4 generates the mask signal A2 by applying a predetermined delay to the output signal of buffer BUF4. For example, the mask signal A2 falls to the low level without delay when the output signal of buffer BUF4 rises to the high level, and rises to the high level when a predetermined mask period has elapsed.

[0047] The AND gate AND1 performs a logical AND operation between the signal A1 and the mask signal A2 to generate a set signal A for the pulse receiving circuit 223 (for example, an RS flip-flop). Therefore, if A2=L (logical level when masked), A=L (fixed value), and if A2=H (logical level when masked), A=A1.

[0048] The AND gate AND2 performs a logical AND operation between the signal B1 and the mask signal B2 to generate a reset signal B for the pulse receiving circuit 223 (for example, an RS flip-flop). Therefore, if B2=L (logical level when masked), then B=L (fixed value), and if B2=H (logical level when masked), then B=B1.

[0049] For example, the pulse receiving circuit 223 sets the output pulse signal OUT to a high level when the set signal A rises to a high level, and resets the output pulse signal OUT to a low level when the reset signal B rises to a high level.

[0050] FIG. 9 is a diagram showing an example of noise cancellation operation, depicting, from top to bottom, an input pulse signal IN, a received pulse signal S12, a main signal A1, a mask signal A2, a set signal A, a received pulse signal S22, a main signal B1, a mask signal B2, a reset signal B, and an output pulse signal OUT.

[0051] First, consider the rising edge of the input pulse signal IN. At time t21, when the input pulse signal IN rises to high level, a normal pulse is generated in the received pulse signal S12, and at the following time t22, a pulse is generated in the main signal A1. On the other hand, even when the input pulse signal IN rises to high level, no pulse is generated in the received pulse signal S22, so the mask signal A2 remains at high level. As a result, the main signal A1 is output as the set signal A, and the output pulse signal OUT is set to high level.

[0052] At time t21, when a normal pulse is generated in the received pulse signal S12, the mask signal B2 falls to low level, and the reset signal B is fixed to low level. However, at the rising edge of the input pulse signal IN, the reset signal B should originally be maintained at low level, so no mismatch occurs.

[0053] Next, consider the falling edge of the input pulse signal IN. When the input pulse signal IN falls to low level at time t23, a normal pulse is generated in the received pulse signal S22, and at the following time t24, a pulse is generated in the main signal B1. On the other hand, even when the input pulse signal IN falls to low level, no pulse is generated in the received pulse signal S12, so the mask signal B2 remains at high level. As a result, the main signal B1 is output as the reset signal B, and the output pulse signal OUT is reset to low level.

[0054] At time t23, when a normal pulse is generated in the received pulse signal S22, the mask signal A2 falls to low level, and the set signal A is fixed to low level. However, at the falling edge of the input pulse signal IN, the set signal A should originally be maintained at low level, so no mismatch occurs.

[0055] Next, consider the case where common mode noise is superimposed on both the received pulse signals S12 and S22. At time t25, a noise pulse rises in both the received pulse signals S12 and S22, and when the noise pulses exceed the threshold voltages Vth1 and Vth2 of the buffers BUF1 to BUF4, pulses are generated in the main signals A1 and B1 and the mask signals A2 and B2.

[0056] When the mask signal A2 is at a low level, the set signal A is fixed at a low level regardless of the logic level of the main signal A1. Similarly, when the mask signal B2 is at a low level, the reset signal B is fixed at a low level regardless of the logic level of the main signal B1. Therefore, common mode noise superimposed on both the received pulse signals S12 and S22 can be appropriately removed, making it possible to suppress malfunction of the output pulse signal OUT.

[0057] However, as shown at time t26, for example, if common mode noise is superimposed while the received pulse signal S12 is being pulsed (=while a normal pulse is being received), the normal pulse of this signal A1 may be masked by the mask signal A2, and the output pulse signal OUT may not be raised to a high level correctly.

[0058] Furthermore, although not shown in the figure, if common mode noise is superimposed during pulse driving of the received pulse signal S22, the normal pulse of the signal B1 may be masked by the mask signal B2, and the output pulse signal OUT may not be properly lowered to a low level.

[0059] In the following, a new structure of the transformer chip 230 that can effectively suppress the occurrence of common mode noise itself without relying on the noise canceller 225 will be proposed.

[0060] <Trans chip (basic structure)> First, the basic structure of transformer chip 230 will be described. Fig. 10 is a diagram showing the basic structure of transformer chip 230. In transformer chip 230 in this figure, transformer 231 includes primary coil 231p and secondary coil 231s that face each other in the vertical direction. Transformer 232 includes primary coil 232p and secondary coil 232s that face each other in the vertical direction.

[0061] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0062] The primary coil 231p is laid in a spiral shape starting from a first end connected to the internal terminal X21, surrounding the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. Meanwhile, the primary coil 232p is laid in a spiral shape starting from a first end connected to the internal terminal X23, surrounding the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are arranged linearly in the order shown in the figure.

[0063] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged linearly and are used for wire bonding with the controller chip 210.

[0064] The secondary coil 231s is laid in a spiral shape, starting from a first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with a second end corresponding to the end point connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape, starting from a first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with a second end corresponding to the end point connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0065] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0066] <Transformer chip (2-channel type)> FIG. 11 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 12 is a plan view of the semiconductor device 5 shown in FIG. 11. FIG. 13 is a plan view showing a layer in which a low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 11. FIG. 14 is a plan view showing a layer in which a high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 11. FIG. 15 is a cross-sectional view taken along line VIII-VIII shown in FIG. 14. FIG. 16 is a cross-sectional view taken along line IX-IX shown in FIG. 14. FIG. 17 is an enlarged view of region X shown in FIG. 14. FIG. 18 is an enlarged view of region XI shown in FIG. 14. FIG. 19 is an enlarged view of region XII shown in FIG. 14. FIG. 20 is an enlarged view of region XIII shown in FIG. 15, illustrating an isolation structure 130.

[0067] 11 to 15, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. Semiconductor chip 41 includes at least one of silicon, a wide band gap semiconductor, and a compound semiconductor.

[0068] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0069] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0070] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0071] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0072] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0073] The insulating side walls 53A to 53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A to 44D. Specifically, the insulating side walls 53A to 53D are formed flush with the chip side walls 44A to 44D. The insulating side walls 53A to 53D form ground surfaces that are flush with the chip side walls 44A to 44D.

[0074] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0075] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0076] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0077] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0078] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inside the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0079] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0080] 13 to 16, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0081] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0082] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0083] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0084] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0085] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the form shown in Fig. 13 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0086] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The body layer is embedded in the recess space defined by the barrier layer. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0087] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a planar view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a planar view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0088] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0089] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0090] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0091] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 14 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0092] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0093] 12, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0094] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0095] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0096] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.

[0097] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0098] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0099] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0100] The multiple high potential terminals 12 are each formed in an area close to the corresponding transformer 21A to 21D in a plan view. The high potential terminals 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0101] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0102] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0103] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0104] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0105] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0106] 13 to 16, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0107] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0108] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0109] The plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The plurality of first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first low potential wirings 31, and will not be repeated here.

[0110] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0111] The through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0112] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0113] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0114] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0115] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0116] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0117] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0118] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0119] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0120] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0121] 16, the plurality of second low potential wirings 32 are electrically connected to the corresponding low potential terminals 11E, 11F and the first outer ends 25 of the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of second low potential wirings 32 each have a similar structure. In the following, the structure of the second low potential wiring 32 connected to the fifth low potential terminal 11E and the first transformer 21A (second transformer 21B) will be described as an example. The structure of the other second low potential wirings 32 will be omitted, as the description of the structure of the second low potential wiring 32 connected to the first transformer 21A (second transformer 21B) applies mutatis mutandis.

[0122] Like the first low potential wiring 31, the second low potential wiring 32 includes a through wiring 71, a low potential connecting wiring 72, a lead wiring 73, a first connecting plug electrode 74, a second connecting plug electrode 75, a pad plug electrode 76, and a substrate plug electrode 77. The second low potential wiring 32 has a similar structure to the first low potential wiring 31, except that the low potential connecting wiring 72 is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22).

[0123] The low potential connection wiring 72 of the second low potential wiring 32 is formed around the low potential coil 22 in the same interlayer insulating layer 57 as the low potential coil 22. Specifically, the low potential connection wiring 72 is formed in a region between two adjacent low potential coils 22 in a plan view. The pad plug electrode 76 is formed in a region between the low potential terminal 11 (fifth low potential terminal 11E) and the low potential connection wiring 72 in the uppermost insulating layer 56, and is electrically connected to the low potential terminal 11 and the low potential connection wiring 72.

[0124] 15, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. In the following, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0125] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (multiple in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0126] The high-potential connecting wire 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wire 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wire 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wire 81 is formed spaced apart from the low-potential connecting wire 72 in a plan view and does not face the low-potential connecting wire 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wire 72 and the high-potential connecting wire 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0127] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. The plurality of pad plug electrodes 82 each have a plane area smaller than the plane area of ​​the high potential connecting wiring 81 in a plan view.

[0128] 16, the plurality of second high-potential wirings 34 are electrically connected to the corresponding high-potential terminals 12E, 12F and the second outer ends 28 of the corresponding transformers 21A-21D (high-potential coils 23), respectively. The plurality of second high-potential wirings 34 each have a similar structure. In the following, the structure of the second high-potential wiring 34 connected to the fifth high-potential terminal 12E and the first transformer 21A (second transformer 21B) will be described as an example. The structure of the other second high-potential wirings 34 will be omitted, as the description of the structure of the second high-potential wiring 34 connected to the first transformer 21A (second transformer 21B) applies mutatis mutandis.

[0129] Like the first high potential wiring 33, the second high potential wiring 34 includes a high potential connecting wiring 81 and a pad plug electrode 82. The second high potential wiring 34 has a similar structure to the first high potential wiring 33, except that the high potential connecting wiring 81 is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23).

[0130] The high-potential connection wiring 81 of the second high-potential wiring 34 is formed around the high-potential coil 23 in the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in a region between two adjacent high-potential coils 23 in plan view, and faces the high-potential terminal 12 (fifth high-potential terminal 12E) in the normal direction Z. The high-potential connection wiring 81 is formed spaced apart from the low-potential connection wiring 72 in plan view, and does not face the low-potential connection wiring 72 in the normal direction Z.

[0131] A plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (fifth high potential terminal 12E) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81, respectively.

[0132] Referring to FIGS. 15 and 16, it is preferable that the distance D1 between the low potential terminal 11 and the high potential terminal 12 exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the insulation withstand voltage to be achieved.

[0133] Referring to FIGS. 14 to 19, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view. In FIGS. 17 to 19, the dummy pattern 85 is shown by hatching. The dummy pattern 85 includes a conductor. The dummy pattern 85 is preferably formed of the same conductive material as the low potential coil 22 or the like. That is, the dummy pattern 85 preferably includes a barrier layer and a main body layer, similar to the low potential coil 22 or the like.

[0134] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high potential coil 23 and the low potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low potential coil 22 and the high potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high potential coil 23.

[0135] In this embodiment, the dummy pattern 85 is routed in dense lines so as to partially cover and partially expose the area surrounding one or more high-potential coils 23 in a plan view. In this embodiment, the dummy pattern 85 is routed at a line density per unit area equal to the line density of the high-potential coils 23. The line density of the dummy pattern 85 being equal to the line density of the high-potential coils 23 means that the line density of the dummy pattern 85 falls within a range of ±20% of the line density of the high-potential coils 23.

[0136] The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than the low-potential terminal 11 in a plan view. The dummy pattern 85 being closer to the high-potential coil 23 in a plan view means that the distance between the dummy pattern 85 and the high-potential coil 23 is less than the distance between the dummy pattern 85 and the low-potential terminal 11.

[0137] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0138] In this case, it is possible to appropriately suppress electric field concentration on the high-potential coil 23. The shorter the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more effectively electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, it is possible to even more appropriately suppress electric field concentration on the high-potential coil 23.

[0139] The dummy patterns 85 are preferably formed around the plurality of high-potential coils 23 so as to be located in the region between the plurality of adjacent high-potential coils 23 in a plan view. In this case, the region between the plurality of adjacent high-potential coils 23 can be utilized to suppress undesired electric field concentration on the plurality of high-potential coils 23.

[0140] The dummy pattern 85 is preferably located in the region between the low potential terminal 11 and the high potential coil 23 in a plan view. In this case, undesired conduction between the low potential terminal 11 and the high potential coil 23 due to electric field concentration in the high potential coil 23 can be suppressed. The dummy pattern 85 is preferably located in the region between the low potential terminal 11 and the high potential terminal 12 in a plan view. In this case, undesired conduction between the low potential terminal 11 and the high potential terminal 12 due to electric field concentration in the high potential coil 23 can be suppressed.

[0141] In this embodiment, the dummy pattern 85 is formed along the multiple high-potential coils 23 in a plan view and is interposed in the region between adjacent multiple high-potential coils 23. In addition, the dummy pattern 85 collectively surrounds the region including the multiple high-potential coils 23 and the multiple high-potential terminals 12 in a plan view. In addition, the dummy pattern 85 is interposed in the region between the multiple low-potential terminals 11A-11F and the multiple high-potential coils 23 in a plan view. In addition, the dummy pattern 85 is interposed in the region between the multiple low-potential terminals 11A-11F and the multiple high-potential terminals 12A-12F in a plan view.

[0142] 14 to 19, dummy pattern 85 includes a plurality of dummy patterns having different electrical states. Dummy pattern 85 includes high-potential dummy pattern 86. High-potential dummy pattern 86 is formed in insulating layer 51 so as to be located around transformers 21A to 21D in a plan view. High-potential dummy pattern 86 is formed in a pattern (discontinuous pattern) different from high-potential coil 23 and low-potential coil 22, and is independent of transformers 21A to 21D. In other words, high-potential dummy pattern 86 does not function as transformers 21A to 21D.

[0143] In this embodiment, the high-potential dummy pattern 86 is routed in dense lines so as to partially cover and partially expose the area surrounding the high-potential coil 23 in a plan view. In this embodiment, the high-potential dummy pattern 86 is routed at a line density per unit area equal to the line density of the high-potential coil 23. The line density of the high-potential dummy pattern 86 being equal to the line density of the high-potential coil 23 means that the line density of the high-potential dummy pattern 86 falls within a range of ±20% of the line density of the high-potential coil 23.

[0144] The high-potential dummy pattern 86 shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D, thereby suppressing electric field concentration on the high-potential coil 23. Specifically, the high-potential dummy pattern 86 shields the electric field between the low-potential coil 22 and the high-potential coil 23, thereby moving the electric field leaking above the high-potential coil 23 away from the high-potential coil 23. This suppresses electric field concentration on the high-potential coil 23 caused by the electric field leaking above the high-potential coil 23.

[0145] A voltage that exceeds the voltage applied to the low-potential coil 22 is applied to the high-potential dummy pattern 86. This makes it possible to suppress the voltage drop between the high-potential coil 23 and the high-potential dummy pattern 86, thereby suppressing electric field concentration on the high-potential coil 23. It is preferable that the voltage applied to the high-potential coil 23 is applied to the high-potential dummy pattern 86. In other words, it is preferable that the high-potential dummy pattern 86 is fixed to the same potential as the high-potential coil 23. This makes it possible to reliably suppress the voltage drop between the high-potential coil 23 and the high-potential dummy pattern 86, thereby appropriately suppressing electric field concentration on the high-potential coil 23.

[0146] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0147] In this case, it is possible to appropriately suppress electric field concentration on the high-potential coil 23. The shorter the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z, the more effectively electric field concentration on the high-potential coil 23 can be suppressed. The high-potential dummy pattern 86 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, it is possible to even more appropriately suppress electric field concentration on the high-potential coil 23.

[0148] The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential terminal 11 in a plan view. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in a plan view means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential terminal 11.

[0149] The high-potential dummy pattern 86 is preferably formed around the plurality of high-potential coils 23 so as to be located in the region between the plurality of adjacent high-potential coils 23 in a plan view. In this case, the region between the plurality of adjacent high-potential coils 23 can be utilized to suppress undesired electric field concentration on the plurality of high-potential coils 23.

[0150] The high-potential dummy pattern 86 is preferably located in the region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. In this case, undesired conduction between the low-potential terminal 11 and the high-potential coil 23 due to electric field concentration in the high-potential coil 23 can be suppressed. The high-potential dummy pattern 86 is preferably located in the region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view. In this case, undesired conduction between the low-potential terminal 11 and the high-potential terminal 12 due to electric field concentration in the high-potential coil 23 can be suppressed.

[0151] In this embodiment, the high-potential dummy pattern 86 is formed along the multiple high-potential coils 23 in a plan view and is interposed in the region between adjacent multiple high-potential coils 23. Furthermore, the high-potential dummy pattern 86 collectively surrounds the region including the multiple high-potential coils 23 and the multiple high-potential terminals 12 in a plan view. Furthermore, the high-potential dummy pattern 86 is interposed in the region between the multiple low-potential terminals 11A-11F and the multiple high-potential coils 23 in a plan view. Furthermore, the high-potential dummy pattern 86 is interposed in the region between the multiple low-potential terminals 11A-11F and the multiple high-potential terminals 12A-12F in a plan view.

[0152] The high-potential dummy pattern 86 is routed around the high-potential terminals 12E and 12F in the region between adjacent high-potential coils 23 in a plan view, exposing the region directly below the high-potential terminals 12E and 12F. A portion of the high-potential dummy pattern 86 may face the high-potential terminals 12A to 12F in the normal direction Z. In this case, the high-potential terminals 12E and 12F, like the high-potential dummy pattern 86, shield the electric field, thereby suppressing the electric field leaking above the high-potential coil 23. In other words, the high-potential terminals 12E and 12F, together with the high-potential dummy pattern 86, are formed as a shield conductor layer that suppresses electric field concentration on the high-potential coil 23.

[0153] It is preferable that the high-potential dummy pattern 86 be formed in a terminated shape. In this case, it is possible to prevent a current loop circuit (closed circuit) from being formed in the high-potential dummy pattern 86. This suppresses noise caused by the current flowing through the high-potential dummy pattern 86. As a result, it is possible to suppress undesired electric field concentration caused by noise, and at the same time, it is possible to suppress fluctuations in the electrical characteristics of the transformers 21A to 21D.

[0154] The high-potential dummy pattern 86 specifically includes a first high-potential dummy pattern 87 and a second high-potential dummy pattern 88. The first high-potential dummy pattern 87 is formed in a region between the plurality of adjacent transformers 21A to 21D (the plurality of high-potential coils 23) in a planar view. The second high-potential dummy pattern 88 is formed in a region outside the region between the plurality of adjacent transformers 21A to 21D (the plurality of high-potential coils 23) in a planar view.

[0155] Hereinafter, the region between the adjacent first transformer 21A (high-potential coil 23) and second transformer 21B (high-potential coil 23) will be referred to as a first region 89. The region between the second transformer 21B (high-potential coil 23) and third transformer 21C (high-potential coil 23) will be referred to as a second region 90. The region between the third transformer 21C (high-potential coil 23) and fourth transformer 21D (high-potential coil 23) will be referred to as a third region 91.

[0156] In this embodiment, the first high potential dummy pattern 87 is electrically connected to the high potential terminal 12 (fifth high potential terminal 12E) via the first high potential wiring 33. Specifically, the first high potential dummy pattern 87 includes a first connection portion 92 connected to the first high potential wiring 33. The position of the first connection portion 92 is arbitrary. As a result, the first high potential dummy pattern 87 is fixed to the same potential as the multiple high potential coils 23.

[0157] Specifically, the first high-potential dummy pattern 87 includes a first pattern 93 formed in a first region 89, a second pattern 94 formed in a second region 90, and a third pattern 95 formed in a third region 91. As a result, the first high-potential dummy pattern 87 suppresses the electric field leaking above the high-potential coil 23 in the first region 89, the second region 90, and the third region 91, and suppresses electric field concentration on the adjacent high-potential coils 23.

[0158] In this embodiment, the first pattern 93, the second pattern 94, and the third pattern 95 are integrally formed and fixed to the same potential. The first pattern 93, the second pattern 94, and the third pattern 95 may be separated as long as they are fixed to the same potential.

[0159] 14 and 17, the first pattern 93 is connected to the first high-potential wiring 33 via a first connection portion 92. The first pattern 93 is routed in a dense line shape so as to cover a part of the first region 89 in a plan view. The first pattern 93 is formed in the first region 89 at a distance from the high-potential terminal 12 (fifth high-potential terminal 12E) in a plan view and does not face the high-potential terminal 12 in the normal direction Z. Furthermore, the first pattern 93 is formed at a distance from the low-potential connecting wiring 72 in a plan view and does not face the low-potential connecting wiring 72 in the normal direction Z. This increases the insulation distance between the first pattern 93 and the low-potential connecting wiring 72, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0160] The first pattern 93 includes a first circumferential line 96, a second circumferential line 97, and a plurality of first intermediate lines 98. The first circumferential line 96 extends in a band shape along the periphery of the high-potential coil 23 of the first transformer 21A. In this embodiment, the first circumferential line 96 is formed in a ring shape having an open end in the first region 89 in a plan view. The width of the open end of the first circumferential line 96 is less than the width of the high-potential coil 23 along the second direction Y.

[0161] The width of the first circumferential line 96 may be 0.1 μm or more and 5 μm or less. The width of the first circumferential line 96 is preferably 1 μm or more and 3 μm or less. The width of the first circumferential line 96 is defined by the width in a direction perpendicular to the direction in which the first circumferential line 96 extends. The width of the first circumferential line 96 is preferably equal to the width of the high-potential coil 23. The width of the first circumferential line 96 being equal to the width of the high-potential coil 23 means that the width of the first circumferential line 96 falls within a range of ±20% of the width of the high-potential coil 23.

[0162] The first pitch between the first outer circumferential line 96 and the high-potential coil 23 (first transformer 21A) may be 0.1 μm or more and 5 μm or less. The first pitch is preferably 1 μm or more and 3 μm or less. The first pitch is preferably equal to the second winding pitch of the high-potential coil 23. The first pitch being equal to the first winding pitch means that the first pitch falls within a range of ±20% of the first winding pitch.

[0163] The second circumferential line 97 extends in a band shape along the periphery of the high-potential coil 23 of the second transformer 21B. In this embodiment, the second circumferential line 97 is formed in a ring shape having an open end in the first region 89 in a plan view. The width of the open end of the second circumferential line 97 is less than the width of the high-potential coil 23 along the second direction Y. The open end of the second circumferential line 97 faces the open end of the first circumferential line 96 along the first direction X.

[0164] The width of the second circumferential line 97 may be 0.1 μm or more and 5 μm or less. The width of the second circumferential line 97 is preferably 1 μm or more and 3 μm or less. The width of the second circumferential line 97 is defined by the width in a direction perpendicular to the direction in which the second circumferential line 97 extends. The width of the second circumferential line 97 is preferably equal to the width of the high-potential coil 23. The width of the second circumferential line 97 being equal to the width of the high-potential coil 23 means that the width of the second circumferential line 97 falls within a range of ±20% of the width of the high-potential coil 23.

[0165] The second pitch between the second outer circumferential line 97 and the high-potential coil 23 (second transformer 21B) may be 0.1 μm or more and 5 μm or less. The second pitch is preferably 1 μm or more and 3 μm or less. The second pitch is preferably equal to the second winding pitch of the high-potential coil 23. The second pitch being equal to the second winding pitch means that the second pitch falls within a range of ±20% of the second winding pitch.

[0166] The plurality of first intermediate lines 98 extend in a band shape in the region between the first circumferential line 96 and the second circumferential line 97 in the first region 89. The plurality of first intermediate lines 98 include at least one (one in this embodiment) first connecting line 99 that electrically connects the first circumferential line 96 and the second circumferential line 97.

[0167] From the viewpoint of preventing the formation of a current loop circuit, it is preferable that the multiple first intermediate lines 98 include only one first connecting line 99. The position of the first connecting line 99 is arbitrary. At least one of the multiple first intermediate lines 98 has a slit 100 formed therein to interrupt the current loop circuit. The position of the slit 100 is adjusted as appropriate depending on the design of the multiple first intermediate lines 98.

[0168] The multiple first intermediate lines 98 are preferably formed in a band shape extending along the opposing direction of the multiple high-potential coils 23. In this embodiment, the multiple first intermediate lines 98 are each formed in a band shape extending in the first direction X and are formed at intervals in the second direction Y. The multiple first intermediate lines 98 are formed in a stripe shape extending in the first direction X as a whole in a plan view.

[0169] The plurality of first intermediate lines 98 specifically includes a plurality of first lead-out portions 101 and a plurality of second lead-out portions 102. The plurality of first lead-out portions 101 are drawn out in stripes from the first circumferential line 96 toward the second circumferential line 97. The tip ends of the plurality of first lead-out portions 101 are formed at intervals from the first circumferential line 96 toward the second circumferential line 97.

[0170] The multiple second lead portions 102 are drawn out in a striped pattern from the second outer periphery line 97 toward the first outer periphery line 96. The tip ends of the multiple second lead portions 102 are formed at intervals from the second outer periphery line 97 toward the first outer periphery line 96. In this embodiment, the multiple second lead portions 102 are formed alternately with the multiple first lead portions 101 at intervals in the second direction Y, with one first lead portion 101 sandwiched between them.

[0171] The plurality of second lead portions 102 may sandwich the plurality of first lead portions 101. Also, a group including the plurality of second lead portions 102 may be formed adjacent to a group including the plurality of first lead portions 101. The slit 100, the plurality of first lead portions 101, and the plurality of second lead portions 102 suppress the formation of a current loop circuit in the first pattern 93.

[0172] The width of the first intermediate line 98 in the second direction Y may be 0.1 μm or more and 5 μm or less. The width of the first intermediate line 98 is preferably 1 μm or more and 3 μm or less. The width of the first intermediate line 98 is preferably equal to the width of the high-potential coil 23. The width of the first intermediate line 98 being equal to the width of the high-potential coil 23 means that the width of the first intermediate line 98 falls within a range of ±20% of the width of the high-potential coil 23.

[0173] The third pitch between two adjacent first intermediate lines 98 may be 0.1 μm or more and 5 μm or less. The third pitch is preferably 1 μm or more and 3 μm or less. The third pitch is defined by the distance between adjacent first intermediate lines 98 in the second direction Y. The third pitches are preferably equal to each other. "The third pitches are equal to each other" means that the third pitch falls within a range of ±20% of the third pitch. The third pitch is preferably equal to the second winding pitch of the high-potential coil 23. "The third pitch is equal to the second winding pitch" means that the third pitch falls within a range of ±20% of the second winding pitch.

[0174] 14 and 18, the second pattern 94 is electrically connected to the high potential terminal 12 via the first high potential wiring 33. In this embodiment, the second pattern 94 is electrically connected to the first high potential wiring 33 (the fifth high potential terminal 12E) via a second peripheral line 97 of the first pattern 93. The second pattern 94 is routed in a dense line shape so as to cover the second region 90.

[0175] The second pattern 94 includes the aforementioned second circumferential line 97, third circumferential line 103, and multiple second intermediate lines 104. The third circumferential line 103 extends in a strip shape along the periphery of the high-potential coil 23 of the third transformer 21C. In this embodiment, the third circumferential line 103 is formed in a ring shape with an open end in the third region 91 in plan view. The width of the open end of the third circumferential line 103 is less than the width of the high-potential coil 23 of the third transformer 21C along the second direction Y.

[0176] The width of the third circumferential line 103 may be 0.1 μm or more and 5 μm or less. The width of the third circumferential line 103 is preferably 1 μm or more and 3 μm or less. The width of the third circumferential line 103 is defined by the width in a direction perpendicular to the direction in which the third circumferential line 103 extends. The width of the third circumferential line 103 is preferably equal to the width of the high-potential coil 23. The width of the third circumferential line 103 being equal to the width of the high-potential coil 23 means that the width of the third circumferential line 103 falls within a range of ±20% of the width of the high-potential coil 23.

[0177] The fourth pitch between the third outer peripheral line 103 and the high-potential coil 23 (third transformer 21C) may be 0.1 μm or more and 5 μm or less. The fourth pitch is preferably 1 μm or more and 3 μm or less. The fourth pitch is preferably equal to the second winding pitch of the high-potential coil 23. The fourth pitch being equal to the second winding pitch means that the fourth pitch falls within a range of ±20% of the second winding pitch.

[0178] The plurality of second intermediate lines 104 extend in a band shape in the region between the second circumferential line 97 and the third circumferential line 103 in the second region 90. The plurality of second intermediate lines 104 include at least one (one in this embodiment) second connection line 105 that electrically connects the second circumferential line 97 and the third circumferential line 103.

[0179] From the viewpoint of preventing the formation of a current loop circuit, it is preferable that the multiple second intermediate lines 104 include only one second connection line 105. The second connection line 105 may have a width greater than the width of the other second intermediate lines 104. The position of the second connection line 105 is arbitrary. At least one of the multiple second intermediate lines 104 has a slit 106 formed therein to interrupt the current loop circuit. The position of the slit 106 is adjusted as appropriate depending on the design of the multiple second intermediate lines 104.

[0180] The second intermediate lines 104 are preferably formed in a strip shape extending along the opposing direction of the high-potential coils 23. In this embodiment, the second intermediate lines 104 are each formed in a strip shape extending in the first direction X and spaced apart in the second direction Y. The second intermediate lines 104 are formed in a strip shape extending in the first direction X as a whole in a plan view.

[0181] Specifically, the plurality of second intermediate lines 104 includes a plurality of third lead-out portions 107 and a plurality of fourth lead-out portions 108. The plurality of third lead-out portions 107 are drawn out in stripes from the second periphery line 97 toward the third periphery line 103. The tip ends of the plurality of third lead-out portions 107 are formed at intervals from the third periphery line 103 toward the second periphery line 97.

[0182] The multiple fourth lead portions 108 are drawn out in stripes from the third periphery line 103 toward the second periphery line 97. The tip ends of the multiple fourth lead portions 108 are formed at intervals from the second periphery line 97 toward the third periphery line 103. In this embodiment, the multiple fourth lead portions 108 are formed alternately with the multiple third lead portions 107 at intervals in the second direction Y, with one third lead portion 107 sandwiched between them.

[0183] The plurality of fourth lead portions 108 may sandwich the plurality of third lead portions 107. Furthermore, a group including the plurality of fourth lead portions 108 may be formed adjacent to a group including the plurality of third lead portions 107. The slits 106, the plurality of third lead portions 107, and the plurality of fourth lead portions 108 suppress the formation of a current loop circuit in the second pattern 94.

[0184] The width of the second intermediate line 104 in the second direction Y may be 0.1 μm or more and 5 μm or less. The width of the second intermediate line 104 is preferably 1 μm or more and 3 μm or less. The width of the second intermediate line 104 is preferably equal to the width of the high-potential coil 23. The width of the second intermediate line 104 being equal to the width of the high-potential coil 23 means that the width of the second intermediate line 104 falls within a range of ±20% of the width of the high-potential coil 23.

[0185] The fifth pitch between two adjacent second intermediate lines 104 may be 0.1 μm or more and 5 μm or less. The fifth pitch is preferably 1 μm or more and 3 μm or less. The fifth pitch is defined by the distance between adjacent second intermediate lines 104 in the second direction Y. The fifth pitches are preferably equal to each other. "The fifth pitches are equal to each other" means that the fifth pitch falls within a range of ±20% of the fifth pitch. The fifth pitch is preferably equal to the second winding pitch of the high-potential coil 23. "The fifth pitch is equal to the second winding pitch" means that the fifth pitch falls within a range of ±20% of the second winding pitch.

[0186] 14 and 19, the third pattern 95 is electrically connected to the first high-potential wiring 33. In this embodiment, the third pattern 95 is electrically connected to the first high-potential wiring 33 via the second pattern 94 and the first pattern 93. The third pattern 95 is routed in a dense line shape so as to cover a part of the third region 91. The third pattern 95 is formed in the third region 91 at a distance from the high-potential terminal 12 (sixth high-potential terminal 12F) in a plan view, and does not face the high-potential terminal 12 in the normal direction Z.

[0187] The third pattern 95 is formed at a distance from the low potential connecting wiring 72 in plan view, and does not face the low potential connecting wiring 72 in the normal direction Z. This increases the insulation distance between the third pattern 95 and the low potential connecting wiring 72 in the normal direction Z, and increases the dielectric strength of the insulating layer 51.

[0188] The third pattern 95 includes the aforementioned third periphery line 103, fourth periphery line 109, and a plurality of third intermediate lines 110. The fourth periphery line 109 extends in a band shape along the periphery of the high-potential coil 23 of the fourth transformer 21D. In this embodiment, the fourth periphery line 109 is formed in a ring shape having an open end in the third region 91 in a plan view. The width of the open end of the fourth periphery line 109 is less than the width of the high-potential coil 23 of the fourth transformer 21D along the second direction Y. The open end of the fourth periphery line 109 faces the open end of the third periphery line 103 along the first direction X.

[0189] The width of the fourth circumferential line 109 may be 0.1 μm or more and 5 μm or less. The width of the fourth circumferential line 109 is preferably 1 μm or more and 3 μm or less. The width of the fourth circumferential line 109 is defined by the width in a direction perpendicular to the direction in which the fourth circumferential line 109 extends. The width of the fourth circumferential line 109 is preferably equal to the width of the high potential coil 23. The width of the fourth circumferential line 109 being equal to the width of the high potential coil 23 means that the width of the fourth circumferential line 109 falls within a range of ±20% of the width of the high potential coil 23.

[0190] The sixth pitch between the fourth outer peripheral line 109 and the high-potential coil 23 (fourth transformer 21D) may be 0.1 μm or more and 5 μm or less. The sixth pitch is preferably 1 μm or more and 3 μm or less. The sixth pitch is equal to the second winding pitch of the high-potential coil 23. The sixth pitch being equal to the second winding pitch means that the sixth pitch falls within a range of ±20% of the second winding pitch.

[0191] The plurality of third intermediate lines 110 extend in a band shape in the region between the third circumferential line 103 and the fourth circumferential line 109 in the third region 91. The plurality of third intermediate lines 110 include at least one (one in this embodiment) third connection line 111 that electrically connects the third circumferential line 103 and the fourth circumferential line 109.

[0192] From the viewpoint of preventing the formation of a current loop circuit, it is preferable that the multiple third intermediate lines 110 include only one third connection line 111. The position of the third connection line 111 is arbitrary. At least one of the multiple third intermediate lines 110 has a slit 112 formed therein to interrupt the current loop circuit. The position of the slit 112 is adjusted as appropriate depending on the design of the multiple third intermediate lines 110.

[0193] The third intermediate lines 110 are preferably formed in a strip shape extending along the opposing direction of the high-potential coils 23. In this embodiment, the third intermediate lines 110 are each formed in a strip shape extending in the first direction X and spaced apart in the second direction Y. The third intermediate lines 110 are formed in a stripe shape as a whole in a plan view.

[0194] In this embodiment, the plurality of third intermediate lines 110 includes a plurality of fifth lead-out portions 113 and a plurality of sixth lead-out portions 114. The plurality of fifth lead-out portions 113 are drawn out in stripes from the third circumferential line 103 toward the fourth circumferential line 109. The tip ends of the plurality of fifth lead-out portions 113 are formed at intervals from the fourth circumferential line 109 toward the third circumferential line 103.

[0195] The plurality of sixth lead portions 114 are drawn out in stripes from the fourth periphery line 109 toward the third periphery line 103. The tip ends of the plurality of sixth lead portions 114 are formed at intervals from the third periphery line 103 toward the fourth periphery line 109. In this embodiment, the plurality of sixth lead portions 114 are formed alternately with the plurality of fifth lead portions 113 at intervals in the second direction Y, with one fifth lead portion 113 sandwiched between them.

[0196] The plurality of sixth lead portions 114 may sandwich the plurality of fifth lead portions 113. Furthermore, a group including the plurality of sixth lead portions 114 may be formed adjacent to a group including the plurality of fifth lead portions 113. The slits 112, the plurality of fifth lead portions 113, and the plurality of sixth lead portions 114 suppress the formation of a current loop circuit in the third pattern 95.

[0197] The width of the third intermediate line 110 in the second direction Y may be 0.1 μm or more and 5 μm or less. The width of the third intermediate line 110 is preferably 1 μm or more and 3 μm or less. The width of the third intermediate line 110 is preferably equal to the width of the high-potential coil 23. The width of the third intermediate line 110 being equal to the width of the high-potential coil 23 means that the width of the third intermediate line 110 falls within a range of ±20% of the width of the high-potential coil 23.

[0198] The seventh pitch between two adjacent third intermediate lines 110 may be 0.1 μm or more and 5 μm or less. The seventh pitch is preferably 1 μm or more and 3 μm or less. The seventh pitch is defined by the distance between adjacent third intermediate lines 110 in the second direction Y. The seventh pitches are preferably equal to each other. The seventh pitches being equal to each other means that the seventh pitch falls within a range of ±20% of the seventh pitch. The seventh pitch is preferably equal to the second winding pitch of the high-potential coil 23. The seventh pitch being equal to the second winding pitch means that the seventh pitch falls within a range of ±20% of the second winding pitch.

[0199] 14 to 19, in this embodiment, the second high-potential dummy pattern 88 is electrically connected to the high-potential terminal 12 via the first high-potential dummy pattern 87. Specifically, the second high-potential dummy pattern 88 includes a second connection portion 115 connected to the first high-potential dummy pattern 87. The position of the second connection portion 115 is arbitrary. As a result, the second high-potential dummy pattern 88 is fixed to the same potential as the multiple high-potential coils 23.

[0200] The second high-potential dummy pattern 88 suppresses the electric field leaking above the high-potential coil 23 in areas outside the first area 89, the second area 90, and the third area 91, and suppresses electric field concentration on the multiple high-potential coils 23. In this embodiment, the second high-potential dummy pattern 88 collectively surrounds the area including the multiple high-potential coils 23 and the multiple high-potential terminals 12A to 12F in plan view. In this embodiment, the second high-potential dummy pattern 88 is formed in the shape of an oval ring in plan view.

[0201] As a result, the second high potential dummy pattern 88 is located in a region between the plurality of low potential terminals 11A to 11F and the plurality of high potential coils 23 in a plan view. The second high potential dummy pattern 88 is also located in a region between the plurality of low potential terminals 11A to 11F and the plurality of high potential terminals 12A to 12F in a plan view.

[0202] The second high potential dummy pattern 88 includes multiple (six in this embodiment) high potential lines 116A, 116B, 116C, 116D, 116E, and 116F. The number of high potential lines is adjusted depending on the electric field to be relaxed. The multiple high potential lines 116A to 116F are formed in this order at intervals in a direction away from the multiple high potential coils 23.

[0203] The multiple high potential lines 116A to 116F collectively surround the multiple high potential coils 23 in a planar view. Specifically, the multiple high potential lines 116A to 116F collectively surround an area including the multiple high potential coils 23 and the multiple high potential terminals 12A to 12F in a planar view. In this embodiment, the multiple high potential lines 116A to 116F are formed in an oval ring shape in a planar view.

[0204] Each of the plurality of high potential lines 116A to 116F includes a slit 117 that interrupts the current loop circuit. The position of the slit 117 is adjusted appropriately depending on the design of the plurality of high potential lines 116A to 116F.

[0205] The width of the high potential lines 116A to 116F may be 0.1 μm or more and 5 μm or less. The width of the high potential lines 116A to 116F is preferably 1 μm or more and 3 μm or less. The width of the high potential lines 116A to 116F is defined by the width in a direction perpendicular to the direction in which the high potential lines 116A to 116F extend. The width of the high potential lines 116A to 116F is preferably equal to the width of the high potential coil 23. The width of the high potential lines 116A to 116F being equal to the width of the high potential coil 23 means that the width of the high potential lines 116A to 116F falls within a range of ±20% of the width of the high potential coil 23.

[0206] The eighth pitch between two adjacent high potential lines 116A to 116F may be 0.1 μm or more and 5 μm or less. The eighth pitch is preferably 1 μm or more and 3 μm or less. The eighth pitches are preferably equal to each other. The eighth pitches being equal to each other means that the eighth pitches fall within a range of ±20% of the eighth pitch.

[0207] The ninth pitch between adjacent first high potential dummy patterns 87 and second high potential dummy patterns 88 may be 0.1 μm or more and 5 μm or less. The ninth pitch is preferably 1 μm or more and 3 μm or less. The ninth pitch is preferably equal to the second winding pitch of the high potential coil 23. The ninth pitch being equal to the second winding pitch means that the ninth pitch falls within a range of ±20% of the second winding pitch. The number, width, pitch, etc. of the multiple high potential lines 116A to 116F are arbitrary and are adjusted according to the electric field to be relaxed.

[0208] 14 to 19, dummy pattern 85 includes floating dummy pattern 121 formed in an electrically floating state in insulating layer 51 so as to be located around transformers 21A to 21D in a plan view. Floating dummy pattern 121 is formed in a pattern (discontinuous pattern) different from high potential coil 23 and low potential coil 22, and is independent from transformers 21A to 21D. In other words, floating dummy pattern 121 does not function as transformers 21A to 21D.

[0209] In this embodiment, the floating dummy pattern 121 is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern 121 may be formed to have ends or to have no ends.

[0210] The floating dummy pattern 121 is routed at a line density per unit area equal to that of the high-potential coil 23. The line density of the floating dummy pattern 121 being equal to that of the high-potential coil 23 means that the line density of the floating dummy pattern 121 is within a range of ±20% of the line density of the high-potential coil 23.

[0211] Furthermore, the floating dummy patterns 121 are routed at a line density per unit area equal to that of the high-potential dummy patterns 86. The line density of the floating dummy patterns 121 being equal to that of the high-potential dummy patterns 86 means that the line density of the floating dummy patterns 121 is within a range of ±20% of the line density of the high-potential dummy patterns 86.

[0212] Floating dummy pattern 121 shields the electric field between low-potential coil 22 and high-potential coil 23 in transformers 21A to 21D, and suppresses electric field concentration on high-potential coil 23. Specifically, floating dummy pattern 121 disperses the electric field leaking above high-potential coil 23 in a direction away from high-potential coil 23. This makes it possible to suppress electric field concentration on high-potential coil 23.

[0213] Furthermore, the floating dummy pattern 121 disperses the electric field leaking above the high-potential dummy pattern 86 around the high-potential dummy pattern 86 in a direction away from the high-potential coil 23 and the high-potential dummy pattern 86. This makes it possible to suppress electric field concentration on the high-potential dummy pattern 86, and at the same time, to appropriately suppress electric field concentration on the high-potential coil 23.

[0214] The depth position of the floating dummy pattern 121 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The floating dummy pattern 121 is preferably formed in a region closer to the high potential coil 23 than to the low potential coil 22 in the normal direction Z. The floating dummy pattern 121 being closer to the high potential coil 23 in the normal direction Z means that the distance between the floating dummy pattern 121 and the high potential coil 23 in the normal direction Z is less than the distance between the floating dummy pattern 121 and the low potential coil 22.

[0215] In this case, it is possible to appropriately suppress electric field concentration on the high-potential coil 23. The shorter the distance between the floating dummy pattern 121 and the high-potential coil 23 in the normal direction Z, the more it is possible to suppress electric field concentration on the high-potential coil 23. It is preferable that the floating dummy pattern 121 is formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, it is possible to further appropriately suppress electric field concentration on the high-potential coil 23.

[0216] The floating dummy pattern 121 is preferably located in a region between the low potential terminal 11 and the high potential coil 23 in a plan view. In this case, undesired conduction between the low potential terminal 11 and the high potential coil 23 due to electric field concentration in the high potential coil 23 can be suppressed. The floating dummy pattern 121 is preferably located in a region between the low potential terminal 11 and the high potential terminal 12 in a plan view. In this case, undesired conduction between the low potential terminal 11 and the high potential terminal 12 due to electric field concentration in the high potential coil 23 can be suppressed.

[0217] In this embodiment, the floating dummy pattern 121 is formed along the plurality of high-potential coils 23 in a planar view. Specifically, the floating dummy pattern 121 collectively surrounds an area including the plurality of high-potential coils 23 and the plurality of high-potential terminals 12 in a planar view. In this embodiment, the floating dummy pattern 121 collectively surrounds an area including the plurality of high-potential coils 23 and the plurality of high-potential terminals 12 across the high-potential dummy pattern 86 (second high-potential dummy pattern 88) in a planar view.

[0218] As a result, the floating dummy pattern 121 is located in a region between the plurality of low potential terminals 11A to 11F and the plurality of high potential coils 23 in a plan view. The floating dummy pattern 121 is also located in a region between the plurality of low potential terminals 11A to 11F and the plurality of high potential terminals 12A to 12F in a plan view.

[0219] The number of floating lines is arbitrary and is adjusted according to the electric field to be relaxed. In this embodiment, the floating dummy pattern 121 includes a plurality of (six in this figure) floating lines 122A, 122B, 122C, 122D, 122E, and 122F. The plurality of floating lines 122A to 122F are formed in this order at intervals in a direction away from the plurality of high potential coils 23.

[0220] The plurality of floating lines 122A to 122F collectively surround the plurality of high-potential coils 23 in plan view. Specifically, the plurality of floating lines 122A to 122F collectively surround an area including the plurality of high-potential coils 23 and the plurality of high-potential terminals 12A to 12F across the high-potential dummy pattern 86 in plan view. In this embodiment, the plurality of floating lines 122A to 122F are formed in an oval ring shape in plan view.

[0221] The width of the floating lines 122A to 122F may be 0.1 μm or more and 5 μm or less. The width of the floating lines 122A to 122F is preferably 1 μm or more and 3 μm or less. The width of the floating lines 122A to 122F is defined by the width in a direction perpendicular to the direction in which the floating lines 122A to 122F extend.

[0222] The tenth pitch between two adjacent floating lines 122A-122F may be 0.1 μm or more and 5 μm or less. The tenth pitch is preferably 1 μm or more and 3 μm or less. The width of the floating lines 122A-122F is preferably equal to the width of the high-potential coil 23. The width of the floating lines 122A-122F being equal to the width of the high-potential coil 23 means that the width of the floating lines 122A-122F falls within a range of ±20% of the width of the high-potential coil 23.

[0223] The 11th pitch between the floating dummy patterns 121 and the high potential dummy patterns 86 (second high potential dummy patterns 88) may be 0.1 μm or more and 5 μm or less. The 11th pitch is preferably 1 μm or more and 3 μm or less. The 11th pitches are preferably equal to each other. The 11th pitches being equal to each other means that the 11th pitches fall within a range of ±20% of the 11th pitch.

[0224] The 11th pitch is preferably equal to the second winding pitch of the high-potential coil 23. The 11th pitch between the floating lines 122A to 122F being equal to the second winding pitch means that the 11th pitch falls within a range of ±20% of the second winding pitch. For clarity, Figs. 12 to 14 show an example in which the 11th pitch exceeds the second winding pitch.

[0225] The 12th pitch between the floating dummy pattern 121 and the high-potential dummy pattern 86 is preferably equal to the second winding pitch. The 12th pitch being equal to the second winding pitch means that the 12th pitch is within a range of ±20% of the second winding pitch. The number, width, pitch, etc. of the multiple floating lines 122A-122F are adjusted according to the electric field to be relaxed, and are not limited to specific values.

[0226] 15 and 16, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 11, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0227] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0228] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The passive device may include a circuit network in which any two or more of the passive device, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0229] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0230] 15 and 16, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0231] The device region 62 is a region including the first functional device 45 (plurality of transformers 21), the second functional device 60, plural low potential terminals 11, plural high potential terminals 12, first low potential wiring 31, second low potential wiring 32, first high potential wiring 33, second high potential wiring 34, and dummy patterns 85. The outer region 63 is a region outside the device region 62.

[0232] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0233] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in plan view.

[0234] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0235] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0236] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, a plurality) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0237] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0238] As long as a single annular seal conductor 61 is formed by an assembly of multiple seal plug conductors 64, it is not necessary for all of the multiple seal plug conductors 64 to be formed in an annular shape. For example, at least one of the multiple seal plug conductors 64 may be formed in an end shape. Also, at least one of the multiple seal plug conductors 64 may be divided into multiple strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the multiple seal plug conductors 64 be formed in an endless (annular) shape.

[0239] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0240] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined as the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0241] 15, 16 and 20, the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the seal conductor 61 to electrically isolate the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0242] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0243] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a strip shape along the seal conductor 61 in plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 bites in toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0244] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0245] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0246] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0247] 15 and 16 , the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0248] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high-potential coil 23 can be increased.

[0249] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0250] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0251] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the low potential terminals 11. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the high potential terminals 12.

[0252] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0253] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0254] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0255] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0256] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0257] If the organic insulating layer 145 is not formed, the filler contained in the package body (mold resin) may cause damage to the multiple high-potential coils 23, the multiple high-potential terminals 12, the seal conductor 61, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121. This type of damage is called a filler attack.

[0258] The organic insulating layer 145 protects the multiple high-potential coils 23, the multiple high-potential terminals 12, the seal conductor 61, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121 from the filler contained in the package body (mold resin). The slit between the first portion 146 and the second portion 147 functions as an anchor portion for the package body (mold resin).

[0259] A part of the package body (molding resin) enters the slit between the first portion 146 and the second portion 147 and is connected to the inorganic insulating layer 140. This increases the adhesion of the package body (molding resin) to the semiconductor device 5. Of course, the first portion 146 and the second portion 147 may be integrally formed. Alternatively, the organic insulating layer 145 may include only either the first portion 146 or the second portion 147. In this case, however, attention must be paid to filler attack.

[0260] The embodiments of the present invention can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0261] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0262] In the above embodiment, an example was described in which the second functional device 60 was formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0263] In the above embodiment, an example was described in which the dummy pattern 85 was formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0264] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes multiple transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0265] <Transformer arrangement> 21 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0266] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s that forms a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s that forms a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0267] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0268] Note that the primary coil L1p forming the first transformer 301, the primary coil L2p forming the second transformer 302, the primary coil L3p forming the third transformer 303, and the primary coil L4p forming the fourth transformer 304 are not shown in the figure. However, the primary coils L1p to L4p basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s, respectively.

[0269] That is, pads a5 and b5 are connected to one end of a primary coil L1p that forms the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil L1p. Also, pads a6 and b6 are connected to one end of a primary coil L2p that forms the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil L2p.

[0270] Pads a7 and b7 are connected to one end of a primary coil L3p that forms the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil L3p. Pads a8 and b8 are connected to one end of a primary coil L4p that forms the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil L4p.

[0271] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0272] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0273] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break occurs in each coil, but also to appropriately reject defective products in which an abnormal resistance value occurs in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0274] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0275] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0276] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminal of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0277] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner that couples them in the respective signal transmission directions, as shown in Fig. 13. Referring to this figure, for example, the first transformer 301 and the second transformer 302 that transmit signals from the primary-side chip to the secondary-side chip are connected as a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 that transmit signals from the secondary-side chip to the primary-side chip are connected as a second pair by a second guard ring 306.

[0278] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0279] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0280] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between the primary coil L3p and the primary coil L4p. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0281] 21, it is desirable that the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are wound so as to form a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. With this configuration, the area where the primary coil and the secondary coil overlap each other increases, making it possible to improve the transmission efficiency of the transformer.

[0282] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0283] <Introduction of a shield electrode> Next, a new structure of the transformer chip 230 that can effectively suppress the occurrence of common mode noise itself without relying on the noise canceller 225 (FIG. 8) will be described.

[0284] Figure 22 shows an example of the introduction of shield electrodes in a transformer chip 230. For comparison, the left side of the figure shows a transformer chip 230 with a conventional structure in which no shield electrodes are introduced. On the other hand, the right side of the figure shows a transformer chip 230 with a new structure in which shield electrodes SLD1 and SLD2 are introduced. Note that only one of the shield electrodes SLD1 and SLD2 may be introduced.

[0285] In the following description, the primary coils 231p and 232p and the secondary coils 231s and 232s may be referred to as primary windings 231p and 232p and secondary windings 231s and 232s, respectively.

[0286] As shown in FIG. 10, the transformer chip 230 has six external terminals T21 to T26. The external terminal T21 is connected to a first end of the primary winding 231p. The external terminal T22 is connected to a second end of the primary winding 231p and a second end of the primary winding 232p. The external terminal T23 is connected to a second end of the primary winding 232p. On the other hand, the external terminal T24 is connected to a first end of the secondary winding 231s. The external terminal T25 is connected to a second end of the secondary winding 231s and a second end of the secondary winding 232s. The external terminal T26 is connected to a second end of the secondary winding 232s.

[0287] Furthermore, due to their structure, the transformers 231 and 232 are provided with inter-coil capacitances C1 and C2 between the primary winding 231p and the secondary winding 231s, and between the primary winding 232p and the secondary winding 232s, respectively.

[0288] Here, the transformer chip 230 of the new structure (on the right side of the figure) has shield electrodes SLD1 and SLD2 formed so as to be interposed between the primary windings 231p and 232p and the secondary windings 231s and 232s.

[0289] FIG. 23 is a diagram showing the vertical structure of a transformer chip 230 equipped with shield electrodes SLD1 and SLD2. As shown in this figure, the transformer chip 230 with the novel structure is formed by stacking, from bottom to top, metal layers (wiring layers) 1MT, 2MT, and 3MT. The metal layers 1MT and 2MT are electrically connected via a single via 1VIA. The metal layers 2MT and 3MT are electrically connected via a three-stage via 2VIA. The top surface of the transformer chip 230 is covered with a passivation layer PSV, except for the exposed pad portions.

[0290] The primary winding 231p is formed on the intermediate metal layer 2MT. Meanwhile, the secondary winding 231s is formed on the uppermost metal layer 3MT so as to be magnetically coupled to the primary winding 231p. The same applies to the primary winding 232p and secondary winding 232s (not shown).

[0291] Here, the shield electrodes SLD1 and SLD2 are both formed in the area sandwiched between the metal layer 2MT and the metal layer 3MT so as to be interposed between the primary winding 231p and the secondary winding 231s (or between the primary winding 232p and the secondary winding 232s).

[0292] 22 and 23, the shield electrode SLD1 is connected to the ground terminal α (=external terminal T22 to which the ground potential GND1 of the primary circuit system 200p is applied) of each of the primary windings 231p and 232p, while the shield electrode SLD2 is connected to the ground terminal β (=external terminal T25 to which the ground potential GND2 of the secondary circuit system 200s is applied) of each of the secondary windings 231s and 232s.

[0293] 23, for example, the shield electrodes SLD1 and SLD2 are formed extending in the left-right direction of the page, directly above the primary winding 231p and directly below the secondary winding 231s, and are connected at their right ends to ground terminals α and β. The ground terminal β is electrically connected to the pad TMT (corresponding to the external terminal T25) through a via TVIA. Meanwhile, the ground terminal α is connected to the external terminal T22 (not shown) through metal layers 1MT to 3MT and vias 1VIA and 2VIA.

[0294] Returning to Figure 22, we continue to compare the conventional and new structures. The transformer chip 230 of the conventional structure (left side of the figure) transmits out-of-phase signals via the inter-coil capacitances C1 and C2 when common-mode noise is superimposed. This requires noise countermeasures (such as the introduction of a noise canceller 225) in the driver chip 220.

[0295] However, even if noise canceller 225 (FIG. 8) is introduced, if a noise pulse is superimposed at the same timing as a regular pulse, the regular pulse may be mistakenly masked, resulting in a delay of one pulse (see time t26 in FIG. 9). Furthermore, noise canceller 225 includes delay units DLY1 to DLY4, which causes the problem of band limitation.

[0296] In contrast, in the transformer chip 230 with the new structure (right side of the figure), the current that flows through the inter-coil capacitances C1 and C2 when common mode noise is superimposed is released to the ground terminals α and β via the shield electrodes SLD1 and SLD2. In other words, the common mode noise itself that is transmitted through the inter-coil capacitances C1 and C2 can be effectively reduced, making it possible to suppress malfunctions without relying on the noise canceller 225.

[0297] FIG. 24 is a diagram showing the noise reduction effect achieved by introducing shield electrodes SLD1 and SLD2, and like FIG. 3, it depicts, from top to bottom, the input pulse signal IN, the received pulse signals S12 and S22, and the output pulse signal OUT.

[0298] First, a brief description of the normal pulse signal transmission operation will be given. At time t31, when the input pulse signal IN rises to high level, the transformer 231 is pulse-driven, causing a normal pulse to rise in the received pulse signal S12. As a result, the output pulse signal OUT rises to high level. Also, at time t32, when the input pulse signal IN falls to low level, the transformer 232 is pulse-driven, causing a normal pulse to rise in the received pulse signal S22. As a result, the output pulse signal OUT falls to low level. In this respect, there is no change from the previous system.

[0299] On the other hand, erroneous signals due to common-mode noise are generated simultaneously in both transformers 231 and 232. However, the shield electrodes SLD1 and SLD2 function to significantly reduce the common-mode noise itself superimposed on the received pulse signals S12 and S22. As a result, the common-mode noise is less likely to exceed the threshold voltage Vth of the buffers 221 and 222, making it possible to suppress malfunction of the output pulse signal OUT.

[0300] <Shield electrode layout and signal transmission capability> 25 to 27 are diagrams showing the relationship between the layout of the shield electrode SLD (corresponding to the above-mentioned shield electrodes SLD1 and SLD2) and the signal transmission capability. In each diagram, the solid arrows indicate current, and the dashed arrows indicate magnetic fields.

[0301] 25, the shield electrode SLD is formed in a solid pattern on one surface so as to be interposed between the primary winding 231p and the secondary winding 231s (or between the primary winding 232p and the secondary winding 232s). When such a layout is adopted, countless eddy currents are generated on the shield electrode SLD, which is thought to significantly impede transmission due to the demagnetizing field.

[0302] 26, multiple shield electrodes SLD are formed in a concentric circle or ring shape in a plan view (comb-like shape in a cross section) so as to be interposed between the primary winding 231p and the secondary winding 231s (or between the primary winding 232p and the secondary winding 232s). When such a layout is adopted, the generation of eddy currents can be suppressed compared to the previously mentioned one-sided solid pattern (FIG. 25), and therefore transmission obstruction due to the demagnetizing field is thought to be reduced. However, since eddy currents are generated within the loop of the shield electrode SLD, it is difficult to completely eliminate transmission obstruction due to the demagnetizing field.

[0303] 27, a plurality of shield electrodes SLD are formed in a concentric circle or ring shape (comb-like in cross section) in plan view so as to be interposed between the primary winding 231p and the secondary winding 231s (or between the primary winding 232p and the secondary winding 232s), as in the case of Fig. 26, and are formed in an open ring shape in plan view. That is, the shield electrode SLD does not have a loop that can serve as a path for eddy currents, and therefore it is possible to minimize transmission obstruction due to a demagnetizing field.

[0304] In this way, by devising the layout of the shield electrode SLD, it is possible to suppress a decrease in the signal transmission capability.

[0305] <Plane layout of shield electrode> 28 is a diagram showing a first planar layout example of the shield electrode SLD. In this diagram, a plurality of shield electrodes SLD are formed in the shape of concentric circles or concentric open rings in plan view. This planar layout corresponds to the C-shaped pattern shown in FIG. 27.

[0306] Fig. 29 is a diagram showing a second planar layout example of the shield electrode SLD. The shield electrode SLD in this diagram is similar to the C-shaped pattern in Fig. 27, but the white arrows indicate that its size (radius) and line width / line spacing ratio (L / S [line / space]) can be changed as desired.

[0307] 30 is a diagram showing a third planar layout example of the shield electrode SLD. In this diagram, a plurality of shield electrodes SLD are formed in a concentric circle or annular shape in plan view. This planar layout corresponds to the above-mentioned FIG. 26 (O-shaped pattern). Note that, as a planar layout similar to the O-shaped pattern, the shield electrode SLD may have exactly the same shape as the primary winding and secondary winding.

[0308] Fig. 31 is a diagram showing a fourth example of a planar layout of the shield electrode SLD. The shield electrode SLD in this figure has a planar layout similar to that of Fig. 28 (C-shaped pattern), but is formed as a continuous unicursal pattern. Even when such a pattern is adopted, it is possible to suppress the generation of eddy currents (and thus transmission obstruction due to demagnetizing fields).

[0309] <Cross-sectional structure of the shield electrode> 32 is a diagram showing a first example of the cross-sectional structure of the primary winding 231p and secondary winding 231s (or the primary winding 232p and secondary winding 232s) and the shield electrodes SLD1 and SLD2. The shield electrodes SLD1 and SLD2 in this diagram are formed outward from the outermost peripheries of the primary winding 231p and secondary winding 231s, respectively, and are also formed inward from the innermost peripheries of the primary winding 231p and secondary winding 231s, respectively. In addition, the shield electrodes SLD1 and SLD2 are designed to have the same wire width / wire spacing ratio as the primary winding 231p and secondary winding 231s, respectively.

[0310] 33 is a diagram showing a second example of the cross-sectional structure of the primary winding 231p and the secondary winding 231s (or the primary winding 232p and the secondary winding 232s) and the shield electrodes SLD1 and SLD2. The shield electrodes SLD1 and SLD2 in this diagram are formed to the same position as the outermost periphery of the primary winding 231p and the secondary winding 231s, respectively, and are also formed to the same position as the innermost periphery of the primary winding 231p and the secondary winding 231s, respectively.

[0311] 34 is a diagram showing a third example of the cross-sectional structure of the primary winding 231p and the secondary winding 231s (or the primary winding 232p and the secondary winding 232s) and the shield electrodes SLD1 and SLD2. The shield electrodes SLD1 and SLD2 in this diagram are formed outward from the outermost peripheries of the primary winding 231p and the secondary winding 231s, respectively, and are formed to the same position as the innermost peripheries of the primary winding 231p and the secondary winding 231s, respectively.

[0312] 35 is a diagram showing a fourth example of the cross-sectional structure of the primary winding 231p and the secondary winding 231s (or the primary winding 232p and the secondary winding 232s) and the shield electrodes SLD1 and SLD2. The shield electrodes SLD1 and SLD2 in this diagram are formed only inward from the outermost peripheries of the primary winding 231p and the secondary winding 231s, respectively, and are also formed only outward from the innermost peripheries of the primary winding 231p and the secondary winding 231s, respectively.

[0313] 36 is a diagram showing a fifth cross-sectional structure example of the primary winding 231p and the secondary winding 231s (or the primary winding 232p and the secondary winding 232s) and the shield electrodes SLD1 and SLD2. As in the first cross-sectional structure example (FIG. 33), the shield electrodes SLD1 and SLD2 in this figure are formed outward from the outermost peripheries of the primary winding 231p and the secondary winding 231s, respectively, and are formed inward from the innermost peripheries of the primary winding 231p and the secondary winding 231s, respectively. However, the shield electrodes SLD1 and SLD2 are designed to have a smaller wire width / wire spacing ratio than the primary winding 231p and the secondary winding 231s, respectively.

[0314] In this way, the sizes and line width / line spacing ratios of the primary winding 231p, the secondary winding 231s, and the shield electrodes SLD1 and SLD2 can be adjusted as desired. For example, although not illustrated in the figure, it is also possible to make the upper structure (secondary winding 231s and shield electrode SLD2) larger than the lower structure (primary winding 231p and shield electrode SLD1), or to gradually increase the size from the lower structure to the upper structure.

[0315] <Effects of introducing a shield electrode> 37 is a diagram showing the relationship between the presence or absence and shape of a shield electrode and the inter-coil capacitance. As shown in this figure, by introducing a shield electrode, it is possible to reduce the inter-coil capacitance of the transformer chip.

[0316] Furthermore, as can be seen from this figure, there is no significant difference in the effect of reducing inter-coil capacitance whether a full-surface solid pattern (Fig. 25) or a C-shaped pattern (Fig. 27) is used for the planar layout of the shield electrode. In light of this, it can be said that it is more desirable to use a C-shaped pattern for the planar layout of the shield electrode, which has less transmission interference due to a demagnetizing field than a full-surface solid pattern.

[0317] Furthermore, it is thought that the smaller the wire width / wire spacing ratio of the shield electrode, the less likely it is to impede signal transmission, but the trade-off is that this impairs the effect of reducing the capacitance between the coils, so it is best to design it appropriately by taking into account the balance between these two.In accordance with this diagram, it can be said that it is desirable to design the shield electrode to have the same wire width / wire spacing ratio (same diameter) as the primary and secondary windings.

[0318] <Plane layout of coil and shield electrode> 38 is a diagram showing the planar layout of pads and coils formed on a transformer chip. Note that this diagram depicts pads 401 and 402 and a coil 403 formed on a transformer chip 400 (corresponding to the aforementioned transformer chip 230, etc.).

[0319] 10, the pad 401 corresponds to, for example, the external terminal T25 (GND pad of the secondary circuit system 200s), the pad 402 corresponds to, for example, the external terminal T24 or T26 (signal pad of the secondary circuit system 200s), and the coil 403 corresponds to, for example, the secondary winding 231s or 232s.

[0320] The coil 403 is laid in a spiral shape surrounding the pad 402. Specifically, in the plan view of the transformer chip 400, the coil 403 is laid so as to trace a rounded rectangle (= a planar shape like a track) around the pad 402, and a locus that moves away from the center as it goes around (or, conversely, a locus that moves closer to the center as it goes around). This planar layout is as clearly shown in the above-mentioned Figures 10 and 13.

[0321] Fig. 39 is a diagram showing a first planar layout of shield electrode 404 overlapping coil 403 in Fig. 38. Fig. 40 is a diagram in which Fig. 38 and Fig. 39 are superimposed.

[0322] The shield electrode 404 corresponds to, for example, the shield electrode SLD1 or SLD2 in Fig. 23 or the shield electrode SLD in Fig. 27 or 28. The shield electrode 404 is formed in a wiring layer different from that of the coil 403 (for example, the wiring layer one layer below the wiring layer on which the coil 403 is formed).

[0323] Furthermore, the shield electrode 404 is laid out in a manner that traces the coil 403 so that it overlaps partly or entirely (in this figure, the majority of 80% or more) with the coil 403 in a plan view of the transformer chip 400. Such a layout pattern can enhance the effect of reducing common-mode noise.

[0324] Specifically, with reference to this figure, shield electrode 404 is basically laid out in the same shape (spiral shape) as coil 403, but has open ends 404x to inhibit the generation of eddy currents. That is, shield electrode 404's spiral shape is interrupted at the portion where open ends 404x are provided. Therefore, shield electrode 404 does not have a loop that can serve as a path for eddy currents, making it possible to minimize transmission inhibition due to demagnetizing fields. This point is as described above in FIG. 27.

[0325] Note that each portion of the shield electrode 404 is electrically connected to the pad 401 via the connecting portion 404y. Therefore, the common-mode noise reduction effect is not impaired. This point is also self-evident from the above-mentioned Figure 28, but will be clarified again here.

[0326] Fig. 41 is a diagram showing a second planar layout of shield electrode 405 overlapping coil 403 in Fig. 38. Fig. 42 is a diagram in which Fig. 38 and Fig. 41 are superimposed.

[0327] Like the previously mentioned shield electrode 404, the shield electrode 405 is laid out so as to trace the coil 403 so as to overlap partly or entirely (almost 100% in this figure) with the coil 403 in a plan view of the transformer chip 400.

[0328] However, unlike the previously described shield electrode 404, shield electrode 405 has an open end 405x at the end rather than in the middle of a continuous spiral shape. This layout pattern increases the overlapping portion between coil 403 and shield electrode 405, further enhancing the effect of reducing common-mode noise.

[0329] <Shield electrode planar layout (summary)> As is clear from the explanation so far, as a means of reducing common mode noise, the shield electrodes provided between the coils (= between the primary winding and the secondary winding) may be formed in multiple concentric circles or concentric rings when viewed in a plane of the transformer chip, or may be formed in a spiral shape when viewed in a plane of the transformer chip.

[0330] Whichever layout pattern is adopted, increasing the area that overlaps with the coil when viewed from above on the transformer chip is important in terms of improving the common-mode noise reduction effect.

[0331] Furthermore, although the relationship between the secondary winding and the shield electrode has been mainly taken as an example in FIGS. 38 to 41, the relationship between the primary winding and the shield electrode is similar to that described above.

[0332] <Summary> The following will provide a general overview of the various embodiments described above.

[0333] The transformer chip disclosed in this specification has a configuration (first configuration) that includes, for example, a first wiring layer, a second wiring layer different from the first wiring layer, a primary winding formed on the first wiring layer, a secondary winding formed on the second wiring layer so as to be magnetically coupled to the primary winding, and a shield electrode formed so as to be interposed between the primary winding and the secondary winding.

[0334] In addition, in the transformer chip according to the above-mentioned first configuration, the shield electrode may be configured (second configuration) to include a first shield electrode connected to a first ground end of the primary winding and a second shield electrode connected to a second ground end of the secondary winding.

[0335] In addition, in the transformer chip having the above first or second configuration, the shield electrode may be configured so that multiple shield electrodes are formed in a concentric circle or concentric ring shape when viewed in a plane, or so that the shield electrode is formed in a spiral shape when viewed in a plane (third configuration).

[0336] In the transformer chip according to the third configuration, the shield electrode may be configured to be formed in an open ring shape in a plan view (fourth configuration).

[0337] In addition, in the transformer chip according to the third or fourth configuration, the shield electrode may be configured (fifth configuration) to have the same wire width / wire spacing ratio as the primary winding or the secondary winding.

[0338] In addition, in a transformer chip having any of the above-mentioned first to fifth configurations, the shield electrode may be configured (sixth configuration) to be formed outside the outermost periphery of the primary winding or the secondary winding.

[0339] In addition, in the transformer chip according to any one of the first to sixth configurations described above, the shield electrode may be configured to extend further inward than the innermost periphery of the primary winding or the secondary winding (seventh configuration).

[0340] Furthermore, in a transformer chip having any of the above configurations 1 to 7, the shield electrode may be configured (configuration 8) to be laid in a manner that traces the primary winding or the secondary winding so that it partially or completely overlaps the primary winding or the secondary winding in a planar view.

[0341] In the transformer chip according to the eighth configuration, the shield electrode may have an open end configured to inhibit the generation of eddy currents (ninth configuration).

[0342] Furthermore, the transformer chip disclosed in this specification has a configuration (tenth configuration) including, for example, a first wiring layer, a second wiring layer different from the first wiring layer, a primary winding of a first transformer and a primary winding of a second transformer formed on the first wiring layer, a secondary winding of the first transformer and a secondary winding of the second transformer formed on the second wiring layer so as to be magnetically coupled to the primary winding of the first transformer and the primary winding of the second transformer, respectively, and shield electrodes formed so as to be interposed between the primary winding of the first transformer and the secondary winding of the first transformer, and between the primary winding of the second transformer and the secondary winding of the second transformer, respectively.

[0343] In addition, the transformer chip according to the above-mentioned tenth configuration may also be configured (eleventh configuration) to have a first terminal to which the first end of the primary winding of the first transformer is connected, a second terminal to which the second end of the primary winding of the first transformer and the first end of the primary winding of the second transformer are connected, a third terminal to which the second end of the primary winding of the second transformer is connected, a fourth terminal to which the first end of the secondary winding of the first transformer is connected, a fifth terminal to which the second end of the secondary winding of the first transformer and the first end of the secondary winding of the second transformer are connected, and a sixth terminal to which the second end of the secondary winding of the second transformer is connected.

[0344] Furthermore, the signal transmission device disclosed in this specification is configured (12th configuration) to have, for example, a controller chip, a driver chip, and a transformer chip that has the above-mentioned first to eleventh configurations and transmits pulse signals while insulating between the controller chip and the driver chip.

[0345] <Other variations> Furthermore, in addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. For example, bipolar transistors can be substituted for MOS field-effect transistors, or the logic levels of various signals can be inverted. In other words, the above-described embodiments are illustrative in all respects and should not be considered limiting. The technical scope of the present invention is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope of the claims. [Industrial Applicability]

[0346] The invention disclosed in this specification can be used, for example, in general applications that require signal transmission while isolating input and output (e.g., insulated gate drivers, motor drivers, isolators, and other ICs that handle high voltages). [Explanation of symbols]

[0347] 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42 First main surface 43 Second main surface 44A~44D Chip sidewall 45 First Functional Device 51 Insulating layer 52 Main insulating surface 53A~53D Insulated sidewall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 PCB plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High-potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 Second Pattern 95 Third Pattern 96 First Outer Line 97 Second Outer Line 98 First Intermediate Line 99 First connecting line 100 slits 101 First drawer 102 Second drawer section 103 Third Outer Line 104 Second Intermediate Line 105 Second connecting line 106 Slit 107 Third drawer 108 4th drawer 109 4th Outer Line 110 3rd Intermediate Line 111 Third Connection Line 112 Slit 113 5th drawer 114 6th drawer 115 Second connection part 116A~116F High voltage line 117 Slit 121 Floating Dummy Pattern 122A~122F Floating line 130 Separation structure 130A inner end 130B Outer end 130C Main body 131 Field insulating film 132 Connection 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal Transmission Device 200p primary circuit system 200s secondary circuit system 210 Controller Chip (1st Chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 buffer 220 Driver Chip (Second Chip) 221, 222 buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 225 Noise Canceller 230 Transformer Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformer 231p, 232p Primary coil (primary winding) 231s, 232s Secondary coil (secondary winding) 300 Trans Chip 301 1st transformer 302 2nd transformer 303 Third Transformer 304 4th Transformer 305 1st Guard Ring 306 Second Guard Ring 400 Trans Chip 401, 402 pads 403 Coil 404, 405 Shield electrode 404x, 405x open end 404y connection part a1 to a8 pads (corresponding to the first current supply pads) b1~b8 pads (corresponding to the first voltage measurement pads) c1 to c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads AND1, AND2 logical AND gates BUF1~BUF4 buffers C, C1, C2 Inter-coil capacitance DLY1~DLY4 delay section L1p, L2p, L3p, L4p Primary coil L1s, L2s, L3s, L4s Secondary coil 1MT, 2MT, 3MT Metal layer (wiring layer) PSV passivation layer SLD, SLD1, SLD2 shield electrodes T21, T22, T23, T24, T25, T26 external terminals TMT Pad 1VIA, 2VIA, TVIA vias X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias α, β grounding end

Claims

1. a first wiring layer; a second wiring layer different from the first wiring layer; a primary winding formed on the first wiring layer; a secondary winding formed on the second wiring layer so as to be magnetically coupled to the primary winding; a shield electrode formed so as to be interposed between the primary winding and the secondary winding; and the shield electrode is formed in a plurality of concentric circles or concentric rings in a plan view, or in a spiral shape in a plan view, The shield electrode is designed to have the same line width / line spacing ratio as the primary winding or the secondary winding.

2. 2. The transformer chip according to claim 1, wherein the shield electrode includes a first shield electrode connected to a first ground end of the primary winding and a second shield electrode connected to a second ground end of the secondary winding.

3. The transformer chip according to claim 1 , wherein the shield electrode is formed in an open ring shape in a plan view.

4. 4. The transformer chip according to claim 1, wherein the shield electrode is formed to extend beyond the outermost periphery of the primary winding or the secondary winding.

5. 5. The transformer chip according to claim 1, wherein the shield electrode is formed to extend inside the innermost periphery of the primary winding or the secondary winding.

6. The transformer chip according to any one of claims 1 to 5, wherein the shield electrode is laid in a manner tracing the primary winding or the secondary winding so as to overlap partially or completely with the primary winding or the secondary winding in a planar view.

7. The transformer chip of claim 6 , wherein the shield electrode has an open end configured to inhibit the generation of eddy currents.

8. a first wiring layer; a second wiring layer different from the first wiring layer; a primary winding of a first transformer and a primary winding of a second transformer formed on the first wiring layer; a secondary winding of the first transformer and a secondary winding of the second transformer formed in the second wiring layer so as to be magnetically coupled to the primary winding of the first transformer and the primary winding of the second transformer, respectively; a shield electrode formed to be interposed between the primary winding of the first transformer and the secondary winding of the first transformer, and between the primary winding of the second transformer and the secondary winding of the second transformer, respectively; and the shield electrode is formed in a plurality of concentric circles or concentric rings in a plan view, or in a spiral shape in a plan view, The shield electrode is designed to have the same line width / line spacing ratio as the primary winding or the secondary winding.

9. a first terminal to which a first end of the primary winding of the first transformer is connected; a second terminal to which a second end of the primary winding of the first transformer and a first end of the primary winding of the second transformer are connected; a third terminal to which a second end of the primary winding of the second transformer is connected; a fourth terminal to which a first end of the secondary winding of the first transformer is connected; a fifth terminal to which a second end of the secondary winding of the first transformer and a first end of the secondary winding of the second transformer are connected; a sixth terminal to which a second end of the secondary winding of the second transformer is connected; The transformer chip according to claim 8, comprising:

10. A controller chip; A driver chip; a transformer chip according to any one of claims 1 to 9, which transmits pulse signals while insulating the controller chip from the driver chip; A signal transmission device having:

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