Semiconductor device and manufacturing method thereof

Abstract

To prevent increase in the on-resistance in a vertical type power MOSFET adopting a super junction structure.SOLUTION: In a manufacturing process of a vertical type power MOSFET of a super junction structure, an n-type column NC reaching a semiconductor layer SL is formed by introducing an n-type impurity to a bottom part of a trench GT by using a mask after forming the trench GT for embedding a gate electrode by means of an etching method on an upper surface of a semiconductor substrate SB having an n-type semiconductor layer SL and a p-type epitaxial layer EP on the semiconductor layer SL.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique that is effective when applied to a power semiconductor device. [Background technology]

[0002] In vertical power MOSFETs, which are power semiconductor devices, the adoption of a superjunction structure in which n-type columns and p-type columns are arranged alternately is being considered in order to maintain the breakdown voltage and suppress the on-resistance.

[0003] For example, Patent Document 1 (JP 2006-196518 A) describes that in a semiconductor device employing a superjunction structure, p-type columns are formed by ion implantation in a semiconductor substrate between multiple trenches in which gate electrodes are buried. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-196518 Summary of the Invention [Problem to be solved by the invention]

[0005] When forming p-type columns using photolithography and ion implantation, the trench (gate trench) formed by photolithography and dry etching and the p-type columns may become too close due to misalignment of the lithography. It is also possible that impurities in the p-type columns may diffuse excessively laterally. In such cases, the width of the n-type semiconductor region, which is the current path, becomes narrower, increasing the on-resistance of the semiconductor element and degrading the performance of the semiconductor device.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of a representative embodiment of the present invention will be given below.

[0008] In one embodiment of a method for manufacturing a semiconductor device, in a manufacturing process of a vertical power MOSFET with a superjunction structure, a gate trench is formed on an upper surface of a semiconductor substrate having an n-type semiconductor layer and a p-type semiconductor layer on the n-type semiconductor layer by an etching method using a mask, and then an n-type impurity is introduced into the bottom of the gate trench using the mask to form an n-type column that reaches the n-type semiconductor layer.

[0009] A semiconductor device according to one embodiment is a vertical power MOSFET with a superjunction structure, which includes a gate trench formed on an upper surface of a semiconductor substrate including an n-type semiconductor layer and a p-type semiconductor layer on the n-type layer, and in which a gate electrode is embedded, and an n-type column formed directly below the gate trench, adjacent to the p-type semiconductor layer, and in contact with the n-type semiconductor layer. [Effects of the Invention]

[0010] According to one embodiment disclosed in the present application, the performance of a semiconductor device can be improved. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view of the semiconductor device according to the first embodiment during the manufacturing process. [Figure 2] 2 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 1. [Figure 3] 3 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 2. [Figure 4] 4 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 3. [Figure 5] 5 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 4. [Figure 6] 6 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 5. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 6. [Figure 8] 8 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 7. [Figure 9] 9 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 8. [Figure 10] FIG. 10 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. [Figure 11] 11 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 11. [Figure 13] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 14] 10A and 10B are cross-sectional views of a semiconductor device according to a second embodiment during a manufacturing process. [Figure 15] FIG. 15 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. [Figure 16] FIG. 16 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. [Figure 17] FIG. 17 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. [Figure 18] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment. [Figure 19] FIG. 10 is a cross-sectional view showing a main part of a semiconductor device of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0012] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the mentioned number, and may be more or less than the mentioned number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0013] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0014] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0015] (Embodiment 1) <Method of manufacturing a semiconductor device> A method for manufacturing a semiconductor device according to this embodiment will be described below with reference to FIGS. 1 to 12. FIGS. 1 to 12 are cross-sectional views of the semiconductor device according to this embodiment during the manufacturing process. The semiconductor device (semiconductor element) according to this embodiment is a vertical power MOSFET (Metal Oxide Semiconductor Field Effect Transistor, a MOS type field effect transistor). A MOSFET is a type of MISFET (Metal Insulator Semiconductor Field Effect Transistor).

[0016] First, as shown in FIG. 1, an epitaxial layer EP made of a p-type semiconductor layer is formed on the main surface (upper surface). + A semiconductor substrate (semiconductor wafer) SB having a layered structure, i.e., a semiconductor layer SL, is prepared. That is, the epitaxial layer EP has an n-type epitaxial layer on the bottom side thereof. + The semiconductor substrate (laminated semiconductor substrate) SB has a semiconductor layer SL which is a semiconductor region. The semiconductor substrate (laminated semiconductor substrate) SB, which is made up of the epitaxial layer EP and the semiconductor layer SL, has a plurality of chip regions which will later be diced into individual semiconductor chips. In a plan view, a cell region CR in which elements are formed is located at the center of each chip region. The outer periphery of the chip region is the peripheral region PER. In Figure 1, the cell region CR is shown from the center to the left side of the figure, and the peripheral region PER is shown on the right side of the figure.

[0017] The semiconductor layer SL is formed by doping single crystal silicon with n-type impurities such as P (phosphorus). The resistance of the semiconductor layer SL is, for example, 1.5 mΩcm or less. The n-type impurity concentration of the semiconductor layer SL is, for example, 5.2×10 19 cm -3 The epitaxial layer EP is formed on the semiconductor layer SL by epitaxial growth. The epitaxial layer EP is mainly made of Si (silicon). A p-type impurity (e.g., B (boron)) is introduced into the epitaxial layer EP during epitaxial growth. The p-type impurity concentration of the epitaxial layer EP is, for example, 2.5×10 18 cm -3 is.

[0018] Subsequently, insulating films IF1, IF2, and IF3 are formed in this order on the epitaxial layer EP (on the semiconductor substrate (laminated semiconductor substrate)). The insulating film IF1 is made of, for example, silicon oxide and can be formed by, for example, an oxidation method. The insulating film IF2 is made of, for example, silicon nitride and can be formed by, for example, a CVD (Chemical Vapor Deposition) method. The insulating film IF3 is made of, for example, silicon oxide and can be formed by, for example, a CVD method.

[0019] Next, a photoresist film PR1 is formed on the insulating film IF3. The photoresist film PR1 is a resist pattern having openings that expose the insulating film IF3 in each of the cell region CR and the peripheral region PER. A plurality of such openings are arranged in the cell region CR in a plan view. Next, dry etching is performed using the photoresist film PR1 as a mask (etching prevention mask, etching mask). This removes parts of the insulating films IF1, IF2, and IF3, exposing the upper surfaces of the epitaxial layers.

[0020] Next, as shown in FIG. 2, dry etching is performed using the photoresist film PR1 and insulating films IF1, IF2, and IF3 as masks. This forms multiple trenches GT extending from the upper surface of the epitaxial layer EP to a depth intermediate the epitaxial layer EP. In the cell region CR, the trenches GT, each having a predetermined width and a predetermined depth, extend in the Y direction along the upper surface of the semiconductor layer SL and the upper surface of the semiconductor substrate SB, and are arranged in multiple rows in the X direction perpendicular to the Y direction in a planar view. However, the trenches GT may be formed as islands in a planar view, and may be arranged in multiple rows in a staggered pattern. The trenches GT extend to a depth intermediate the epitaxial layer EP but do not reach the interface between the epitaxial layer EP and the semiconductor layer SL. The distance between the trenches GT and the semiconductor layer SL in a direction perpendicular to the upper surface of the epitaxial layer EP (vertical direction, longitudinal direction, thickness direction) is, for example, 2 μm or less. The trenches GT are gate trenches into which gate electrodes will be embedded in a later process.

[0021] Here, the photoresist film PR1 is used as a mask for etching performed in the step of forming the trench GT. However, the photoresist film PR1 may be removed after the step described with reference to FIG. 1 and before the etching. In that case, only the insulating films IF1, IF2, and IF3 are used as a mask (hard mask) in the etching.

[0022] Next, as shown in FIG. 3, ion implantation is performed using the photoresist film PR1 and insulating films IF1, IF2, and IF3 as masks (ion implantation blocking mask, impurity introduction mask). That is, n-type impurities (e.g., P (phosphorus)) are introduced into the epitaxial layer EP at the bottom of the trench GT. Here, n-type impurities are implanted twice with different implantation energies into the epitaxial layer EP immediately below the trench GT. That is, multi-stage implantation is performed. By introducing n-type impurities into the epitaxial layer EP in this way, n-type columns NC are formed in the epitaxial layer EP immediately below each trench GT. The dose of this implantation process is, for example, 5.0×10 13 ~5.0×10 14 cm -2 The implantation energy in this implantation step is, for example, 1.5 MeV for the first time and 2.0 MeV for the second time. The length in the vertical direction of the n-type column NC is, for example, about 2 μm. The n-type impurity concentration of the n-type column NC is, for example, 1.0×10 19 cm -3 is.

[0023] The n-type columns NC directly below the adjacent trenches GT are spaced apart via the p-type epitaxial layer EP. The n-type columns NC are adjacent to the epitaxial layer EP in the direction along the upper surface of the epitaxial layer EP. In addition, a part (lower part) of the n-type columns NC is +The trench GT is in contact with the semiconductor layer SL, which is a type semiconductor region. One of the main features of this embodiment is that, by introducing n-type impurities directly below the trench GT using the mask used when forming the trench GT, the n-type columns NC are formed, reaching the semiconductor layer SL. In other words, the introduction of impurities in the process of forming the n-type columns NC is performed by ion implantation using the mask (etching mask) that defines the opening of the trench GT as a mask for introducing impurities.

[0024] In addition, when the photoresist film PR1 has already been removed in the process described with reference to FIG. 2, the ion implantation performed to form the n-type columns NC is performed using the insulating films IF1, IF2, and IF3 as a mask (ion implantation blocking mask).

[0025] Next, as shown in FIG. 4, the photoresist film PR1 and the insulating films IF1, IF2, and IF3 on the epitaxial layer EP are removed.

[0026] Next, as shown in FIG. 5, a silicon oxide film is formed, for example, by oxidation, to cover the side and bottom surfaces of the trench GT and the upper surface of the epitaxial layer EP outside the trench GT. Subsequently, a silicon film is formed on the silicon oxide film, for example, by CVD, to completely fill the trench GT. Subsequently, the silicon film on the upper surface of the epitaxial layer EP except for the inside of the trench GT is removed, for example, by etch-back. This forms a gate electrode GE made of the silicon film within the trench GT via an insulating film (gate insulating film) IF4 made of the silicon oxide film.

[0027] Next, as shown in FIG. 6, a photoresist film PR2 is formed on the epitaxial layer EP. The photoresist film PR2 is a resist pattern having openings that expose the upper surfaces of the epitaxial layer EP in the regions adjacent to the trenches GT in the cell region CR and the peripheral region PER. Next, using the photoresist film PR2 as a mask, ion implantation is performed to implant p-type impurities (e.g., B (boron)) into the upper surface of the epitaxial layer EP. By introducing the p-type impurities into the epitaxial layer EP in this manner, p-type body regions BR shallower than the trenches GT are formed between adjacent trenches GT. The body regions BR are in contact with and formed along the side surfaces of the trenches GT. The depth of the body regions BR is shallower than the depth of the gate electrodes GE.

[0028] The body region BR is formed by, for example, three ion implantations (multi-stage implantations) with different implantation energies. The dose of each implantation step is, for example, 3.3×10 12 cm -2 The p-type impurity concentration of the body region BR is, for example, 1.0×10 18 cm -3 is.

[0029] Next, as shown in FIG. 7, the photoresist film PR2 is removed. Thereafter, a photoresist film PR3 is formed on the epitaxial layer EP. The photoresist film PR3 is a resist pattern having openings that expose the upper surface of the epitaxial layer EP in the region adjacent to the trench GT in the cell region CR. Next, ion implantation is performed using the photoresist film PR3 as a mask to implant n-type impurities (e.g., As (arsenic)) into the upper surface of the epitaxial layer EP. By introducing the n-type impurities into the epitaxial layer EP in this manner, n-type impurities (e.g., As (arsenic)) are formed between adjacent trenches GT at a depth shallower than the body region BR. + The source region SR is formed along the side surface of the trench GT and in contact with the body region BR.

[0030] The dose of this implantation step is, for example, 1.0×10 16 cm-2 The n-type impurity concentration of the source region SR is, for example, 1.0×10 21 cm -3 is.

[0031] Next, as shown in FIG. 8, the photoresist film PR3 is removed. After that, an insulating film is formed on each of the epitaxial layer EP, the insulating film IF4, and the gate electrode GE, for example, by using a CVD method. The insulating film is made of, for example, silicon oxide. In FIG. 8, the insulating film and the insulating film IF4 are shown collectively as the insulating film IF4, assuming that they are integrated.

[0032] Next, an interlayer insulating film IL is formed on the insulating film IF4. The interlayer insulating film IL is made mainly of, for example, silicon oxide and can be formed by, for example, a CVD method. Next, the upper surface of the interlayer insulating film IL is polished and planarized by, for example, a CMP (Chemical Mechanical Polishing) method. Next, although not shown in the drawings, an insulating film made of silicon oxide is formed on the interlayer insulating film IL by, for example, a CVD method.

[0033] 9, the interlayer insulating film IL is patterned using photolithography and dry etching, thereby forming a contact hole (opening) that penetrates the interlayer insulating film IL and exposes the upper surface of the epitaxial layer EP in which the source region SR is formed in the cell region CR.

[0034] 10, etching is performed using the interlayer insulating film IL as a mask to recess the upper surface of the epitaxial layer EP exposed at the bottom of each of the plurality of contact holes. This forms a plurality of trenches that are deeper than the source region SR and shallower than the body region BR. The body region BR is exposed at the bottom of each trench.

[0035] Next, ion implantation is performed using the interlayer insulating film IL as a mask. Here, p-type impurities (e.g., BF2 (boron fluoride)) are implanted into the epitaxial layer EP directly below each of the plurality of contact holes in the cell region CR. By introducing the p-type impurities into the epitaxial layer EP in this manner, p-type impurities are implanted into the epitaxial layer EP from the top surface of the body region BR to the middle depth of the body region BR at positions spaced apart from the trenches GT. + A type diffusion region BC is formed, and then a heat treatment is performed on the semiconductor wafer, which causes the impurities in the source region SR and the diffusion region BC to diffuse.

[0036] In this way, a superjunction structure is formed in the cell region CR, in which n-type columns NC and p-type epitaxial layers EP are arranged alternately in the horizontal direction. In other words, the epitaxial layers EP between adjacent n-type columns NC form p-type columns. The n-type column junction structure, which is composed of the gate electrode GE, the source region SR, the body region BR, the n-type columns NC, the epitaxial layers EP, and the semiconductor layers SL, + The vertical semiconductor region constitutes a vertical power MOSFET. The structure formed in the peripheral region PER is a structure for ensuring the breakdown voltage of the periphery of the semiconductor chip.

[0037] 11, the interlayer insulating film IL is patterned using photolithography and dry etching, thereby forming a contact hole (opening) that penetrates the interlayer insulating film IL and exposes the upper surface of the gate electrode GE in the peripheral region PER.

[0038] Next, as shown in FIG. 12, metal films are formed on the interlayer insulating film IL. That is, for example, a TiN (titanium nitride) film, a Ti (titanium) film, and a W (tungsten) film are formed in this order by sputtering or the like. As a result, the insides of the connection holes are filled with these metal films. Subsequently, the metal films on the interlayer insulating film IL are removed by, for example, CMP, to expose the upper surface of the interlayer insulating film IL. As a result, contact plugs (conductive connection portions) CP made of the metal films remaining in the connection holes are formed. Note that in FIG. 12, the metal films constituting the contact plug CP are collectively shown as one contact plug CP.

[0039] Next, a metal film made of Al (aluminum) is formed on the interlayer insulating film IL and the contact plug CP by a method such as sputtering. The metal film is then patterned using photolithography and dry etching to form a source electrode SM and a gate lead electrode GM made of the metal film. Here, the gate lead electrode GM is formed in the peripheral region PER. The source electrode SM in the cell region CR is electrically connected to the source region SR and the diffusion region BC via the contact plug CP. The gate lead electrode GM is electrically connected to the gate electrode GE via the contact plug CP.

[0040] Next, a surface protective film CV is formed so as to cover the source electrode SM and the gate extraction electrode GM. That is, a silicon oxide film is deposited on each of the source electrode SM and the gate extraction electrode by, for example, a CVD method. Then, the silicon oxide film is patterned to expose a part of the upper surface of the source electrode SM and the upper surface of the gate extraction electrode GM. This exposed portion becomes an external connection region (e.g., a gate pad, a source pad). In this way, a surface protective film CV made of the silicon oxide film is formed.

[0041] Next, a drain electrode (not shown) is formed on the back surface of the semiconductor substrate SB opposite to the main surface. For example, a metal film is formed by sputtering or vapor deposition on the back surface of the semiconductor substrate SB. This allows the drain electrode made of the metal film to be formed.

[0042] The semiconductor wafer is then cut by a dicing process to separate each of the multiple chip regions of the semiconductor wafer. In other words, one semiconductor chip can be obtained from one chip region, and multiple semiconductor chips can be obtained from the semiconductor wafer. Through the above steps, the semiconductor device of this embodiment can be formed.

[0043] <Structure of semiconductor device> 13 is a cross-sectional view of a main part of the cell region of the semiconductor device of this embodiment. As shown in FIG. 13, the semiconductor device of this embodiment is an n-type semiconductor device having an epitaxial layer EP made of a p-type semiconductor layer formed on the main surface (upper surface). + The epitaxial layer EP has a n-type semiconductor layer SL, i.e., a semiconductor substrate (laminated semiconductor substrate) SB. + The semiconductor layer SL is in contact with the semiconductor region.

[0044] A plurality of trenches GT are formed in the upper surface of the epitaxial layer EP, reaching a depth of the epitaxial layer EP. The trenches GT extend, for example, in the Y direction, and a plurality of trenches GT are lined up in the X direction within the cell region. The X direction and Y direction referred to in this application are directions along the upper surfaces of the semiconductor layer SL and the epitaxial layer EP, and are directions (lateral directions) perpendicular to each other in a plan view.

[0045] A gate electrode GE is buried in each trench GT via an insulating film IF4. That is, the side and bottom surfaces of the trench GT are covered with the insulating film IF4 made of, for example, a silicon oxide film, and the epitaxial layer EP and the gate electrode GE are insulated by the insulating film IF4. The gate electrode GE is made of, for example, a polycrystalline silicon film.

[0046] In the epitaxial layer EP between the adjacent trenches GT, a body region (p-type semiconductor region) BR and an n-type semiconductor region (n-type semiconductor region) whose lower surface is in contact with the body region BR are formed on the side surface of each trench GT. + A source region SR, which is a diffusion region of a p-type, is formed in the epitaxial layer EP. In other words, a body region BR having a predetermined depth from the upper surface of the epitaxial layer EP is formed in the epitaxial layer EP, and the source region SR is formed on the upper surface of the body region BR. In addition, a p-type diffusion region SR is formed between adjacent trenches GT, which is spaced from the trenches GT and in contact with the body region BR. + A diffusion region BC, which is a type semiconductor region, is formed.

[0047] In the epitaxial layer EP directly below the trenches GT, n-type columns NC, which are n-type semiconductor regions, are formed. The n-type columns NC directly below the adjacent trenches GT are spaced apart via a p-type epitaxial layer EP. The n-type columns NC are adjacent to the epitaxial layer EP in the direction along the upper surface of the epitaxial layer EP. In addition, a part (lower part) of the n-type columns NC is n + The semiconductor layer SL is in contact with the semiconductor region.

[0048] The n-type impurity concentration of the source region SR is higher than the n-type impurity concentrations of the n-type column NC and the semiconductor layer SL, and the p-type impurity concentration of the diffusion region BC is higher than the p-type impurity concentration of the epitaxial layer EP.

[0049] An interlayer insulating film IL is formed on the epitaxial layer EP and the gate electrode GE, and a contact plug CP penetrating the interlayer insulating film IL is connected to the source region SR and the diffusion region BC.

[0050] The body region BR is formed across the opposing side surfaces of adjacent trenches GT. Also, below the body region BR, a portion of the epitaxial layer EP is formed across the opposing side surfaces of adjacent trenches GT.

[0051] <Superjunction structure> By placing a vertical power MOSFET on the main surface of a structure (superjunction structure) in which n-type columns NC and p-type columns (p-type epitaxial layers EP) are periodically arranged, as in the cell region CR, it is possible to reduce the on-resistance while ensuring a high breakdown voltage.

[0052] That is, in a superjunction structure in which p-type columns and n-type columns are periodically arranged, when the device is off, a depletion layer extends laterally within the n-column from the boundary region between the p-type columns and the n-type columns in the horizontal direction, i.e., the pn junction extending in the vertical direction.

[0053] Therefore, in a vertical power MOSFET with a superjunction structure, even if the impurity concentration of the n-type column, which serves as the current path, is increased to reduce on-resistance, the depletion layer that spreads laterally from the pn junction ensures a high breakdown voltage. This makes it possible to reduce on-resistance while maintaining a high breakdown voltage. In this way, the adoption of a superjunction structure and the periodic arrangement of p-type and n-type columns can alleviate the electric field between the drain and source.

[0054] In the semiconductor device of this embodiment shown in Fig. 13, the n-type column NC, which is the drift layer, is in contact with the bottom surface of the trench GT. When the vertical power MOSFET is in the on-state, an inversion layer is generated in the epitaxial layer EP and the body region BR at a portion where the epitaxial layer EP and the trench GT are in contact with each other, and a current flows between the source region SR and the semiconductor layer SL, which is the drain region, via the n-type column NC. Even if the n-type column NC and the trench GT are separated from each other via the epitaxial layer EP, if an inversion layer is generated between the n-type column NC and the trench GT, a current flows between the source and drain of the vertical power MOSFET via the n-type column NC.

[0055] <Effects of this embodiment> 19 shows a cross-sectional view of a main part of a superjunction structure of a semiconductor device as a comparative example. Unlike the semiconductor device of this embodiment, the semiconductor device of the comparative example does not have an n-type column NC, and an n-type epitaxial layer EN is formed instead of the p-type epitaxial layer EP. Also, unlike the semiconductor device of this embodiment, the semiconductor device of the comparative example has a p-type column PC in the epitaxial layer EN below the region between adjacent trenches GT. That is, the superjunction structure of the comparative example has a plurality of p-type columns PC and an n-type column that is the epitaxial layer EN between adjacent p-type columns PC.

[0056] In the semiconductor device of this comparative example, the trench GT is formed using photolithography and dry etching, as in the present embodiment. The p-type column PC is formed by implanting p-type impurities into the epitaxial layer EN using photolithography and ion implantation. The p-type column PC is formed by ion implantation using a mask different from the mask used to form the trench GT. In this case, there is a problem that misalignment of the lithography used to form these masks may occur.

[0057] Furthermore, it is considered that the p-type impurity in the p-type column PC may be excessively diffused in the lateral direction due to a heat treatment or the like performed after forming the source region SR and the diffusion region BC.

[0058] If the above-mentioned misalignment or excessive diffusion of p-type impurities occurs, the trench GT and the p-type column PC may become close to each other. In this case, the width of the n-type column, which is the current path of the vertical power MOSFET, becomes narrower. This increases the on-resistance of the vertical power MOSFET. Furthermore, if there is variation in the formation depth and spread of the p-type column PC in the vertical direction (depth direction), this may cause variation in the performance of the vertical power MOSFET. These problems become more pronounced as semiconductor devices become smaller and the spacing between the trenches GT becomes smaller.

[0059] Therefore, in this embodiment, as described with reference to FIGS. 1 to 13, n-type impurities are introduced directly below the trench GT using the mask used when forming the trench GT, thereby forming n-type columns NC that reach the semiconductor layer SL. This allows the n-type columns NC to be formed in a self-aligned manner with the trench GT. That is, it is possible to prevent deviations in the relative positions of the trench GT and the n-type columns NC. By forming the n-type columns NC in desired positions in this way, it is possible to prevent deviations in the relative positions of the trench GT and the p-type columns (epitaxial layer EP). That is, it is possible to control the extent of the p-type columns and the distance between the p-type columns and the trench.

[0060] Therefore, the area occupied by the p-type columns PC can be reduced, and the resistance of the n-type columns NC (drift layer) can be lowered. Even if the semiconductor device is miniaturized and the spacing between the trenches GT becomes smaller, the width of the n-type columns NC, which are the current paths, can be secured at a desired size. Therefore, it becomes easy to increase the number of columns arranged per unit area while securing the breakdown voltage of the vertical power MOSFET. This reduces the on-resistance of the vertical power MOSFET and improves the performance of the semiconductor device.

[0061] (Embodiment 2) In the first embodiment, the formation of n-type columns in a p-type epitaxial layer has been described, but p-type columns and n-type columns may be formed in an n-type epitaxial layer by ion implantation, respectively. A method for manufacturing a semiconductor device according to this embodiment will be described below with reference to FIGS.

[0062] First, as shown in Fig. 14, the steps described with reference to Figs. 1 to 7 are carried out. However, in the steps described with reference to Fig. 1, n + A semiconductor substrate (laminated semiconductor substrate) SB having an n-type epitaxial layer EN on an n-type semiconductor layer SL is prepared. The resistance of the epitaxial layer EN is, for example, 0.13 mΩcm or less. The n-type impurity concentration of the epitaxial layer EN is, for example, 6.0×10 16 cm -3 is.

[0063] Next, the photoresist film PR3 is removed. After that, an insulating film is formed on each of the epitaxial layer EP, the insulating film IF4, and the gate electrode GE, using, for example, a CVD method. The insulating film is made of, for example, silicon oxide. In FIG. 14, the insulating film and the insulating film IF4 are shown collectively as the insulating film IF4, assuming that they are integrated.

[0064] Next, insulating films IF5 and IF6 are formed in this order on insulating film IF4. Insulating film IF5 is made of, for example, silicon nitride. Insulating film IF6 is made of, for example, silicon oxide. The insulating films IF5 and IF6 can be formed by, for example, the CVD method. Subsequently, although not shown, a silicon oxide film is formed on insulating film IF6 by, for example, the CVD method.

[0065] 15, a photoresist film PR4 is formed on the insulating film IF6. The photoresist film PR4 is a resist pattern having openings that expose the insulating film IF6 in each of the cell region CR and the peripheral region PER. In the cell region CR, the openings are located directly above the regions between adjacent trenches GT.

[0066] Next, as shown in FIG. 16, dry etching is performed using the photoresist film PR4 as a mask to form a plurality of openings that penetrate the insulating film IF6 and expose the upper surface of the insulating film IF5. Subsequently, ion implantation is performed using the photoresist film PR4 as a mask. Here, p-type impurities (e.g., B (boron)) are implanted into the epitaxial layer EP. By introducing the p-type impurities into the epitaxial layer EP in this manner, p-type columns PC, which are p-type semiconductor regions, are formed between adjacent trenches GT. The p-type columns PC are spaced apart from the trenches GT in the X direction along the upper surface of the epitaxial layer EN. In other words, by introducing the p-type impurities into the epitaxial layer EN that is spaced apart from the trenches GT in the X direction, p-type columns PC adjacent to the n-type columns NC in the X direction are formed.

[0067] Here, the p-type column PC is formed in the epitaxial layer EN from the lower surface of the body region BR to a position deeper than the trench GT. The p-type column PC does not reach the semiconductor layer SL. In other words, the p-type column PC and the semiconductor layer SL are spaced apart from each other.

[0068] The p-type column PC is formed by, for example, two ion implantations (multi-stage implantations) with different implantation energies. The dose of each implantation step is, for example, 2.5×10 13 cm -2 The p-type impurity concentration of the p-type column PC is, for example, 2.5 × 10 18 cm -3 is.

[0069] Next, although not shown, the photoresist film PR4 and the insulating films IF6 and IF5 are removed. Subsequently, the step of forming the interlayer insulating film IL described with reference to FIG.

[0070] Next, as shown in FIG. 17, the steps described with reference to FIGS. 9 to 12 are carried out to complete the semiconductor device of this embodiment.

[0071] <Structure of semiconductor device> The semiconductor device of this embodiment is a vertical power MOSFET having a superjunction structure in which p-type columns PC and n-type columns each consisting of an n-type epitaxial layer EP and an n-type column NC are arranged alternately in the horizontal direction, as shown in Fig. 18. The semiconductor device shown in Fig. 18 differs from the first embodiment in that the epitaxial layer EN is n-type instead of p-type, and in that p-type columns PC are provided below regions between adjacent trenches GT. The p-type columns PC are formed in the epitaxial layer EN spaced apart from the trenches GT in the X direction along the upper surface of the epitaxial layer EN, and are adjacent to the n-type columns NC in the X direction.

[0072] <Effects of this embodiment> Even when the p-type columns PC and the n-type columns NC are formed in the n-type epitaxial layer EN by ion implantation as in this embodiment, the same effects as those in the first embodiment can be obtained.

[0073] That is, here, n-type impurities are introduced directly below the trench GT using the mask used when forming the trench GT, thereby forming n-type columns NC that reach the semiconductor layer SL. This prevents deviations in the relative positions of the trench GT and the n-type columns NC. By forming the n-type columns NC in desired positions in this way, deviations in the relative positions of the trench GT and the p-type columns PC can be prevented. In other words, even if the p-type impurities in the p-type columns PC diffuse significantly, or even if the formation position of the p-type columns PC becomes close to the trench GT due to lithography misalignment, the presence of the n-type columns NC ensures that the width of the current path is the desired size.

[0074] This makes it easy to increase the number of columns per unit area while ensuring the breakdown voltage of the vertical power MOSFET, thereby reducing the on-resistance of the vertical power MOSFET and improving the performance of the semiconductor device.

[0075] The invention made by the present inventors has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention.

[0076] In the above embodiment, the semiconductor device is described as having a substrate and an epitaxial layer made of Si (silicon), but the semiconductor device may be made of SiC (silicon carbide) instead of Si. That is, the semiconductor substrate may be made of SiC.

[0077] Although the above embodiment has been described with respect to the case where an n-channel MOSFET is formed, the MOSFET may be a p-channel MOSFET. In the case where a p-channel MOSFET is formed, each of the semiconductor regions constituting the semiconductor device described above may be formed with an opposite conductivity type. [Explanation of symbols]

[0078] BC diffusion region BR Body Region CP Contact Plug CR Cell Area CV surface protective film EN, EP epitaxial layer GE gate electrode GM gate extraction electrode GT Trench IF1~IF6 insulating film IL Interlayer insulating film NC n-type column PC p-type column PER Surrounding Area PR1~PR4 Photoresist film SB semiconductor substrate SL Semiconductor layer SM source electrode SR Source Region

Claims

1. (a) preparing a semiconductor substrate in which a second semiconductor layer of a second conductivity type different from the first conductivity type is formed on a first semiconductor layer of a first conductivity type; (b) forming a gate trench having a predetermined width and reaching a depth from the top surface of the second semiconductor layer using an etching mask having a predetermined opening width; (c) introducing impurities of the first conductivity type into the second semiconductor layer at the bottom of the gate trench to form first columns of the first conductivity type reaching the first semiconductor layer; (d) forming a body region of the second conductivity type and a source region of the first conductivity type in the second semiconductor layer on a side surface of the gate trench; Including, the introduction of impurities in the step (c) is performed by ion implantation using the etching mask that defines the opening of the gate trench as a mask for introducing impurities; A method for manufacturing a semiconductor device, wherein the first column is spaced apart from a bottom surface of the gate trench.

2. 2. The method of manufacturing a semiconductor device according to claim 1, In the step (b), a plurality of the gate trenches are formed; A method for manufacturing a semiconductor device, wherein a portion of the second semiconductor layer is formed across opposing side surfaces of two adjacent gate trenches.

3. (a) preparing a semiconductor substrate in which a second semiconductor layer of a first conductivity type is formed on a first semiconductor layer of the first conductivity type; (b) forming a gate trench having a predetermined width and reaching a depth from the top surface of the second semiconductor layer using an etching mask having a predetermined opening width; (c) introducing impurities of the first conductivity type into the second semiconductor layer at the bottom of the gate trench to form first columns of the first conductivity type reaching the first semiconductor layer; (d) forming a body region of a second conductivity type different from the first conductivity type and a source region of the first conductivity type in the second semiconductor layer on a side surface of the gate trench; (e) introducing the impurity of the second conductivity type into the second semiconductor layer spaced apart from the gate trench in a first direction along the top surface of the second semiconductor layer to form a second column of the second conductivity type adjacent to the first column in the first direction; Including, the introduction of impurities in the step (c) is performed by ion implantation using the etching mask that defines the opening of the gate trench as a mask for introducing impurities; A method for manufacturing a semiconductor device, wherein the first column is spaced apart from a bottom surface of the gate trench.

4. a semiconductor substrate in which a second semiconductor layer of a second conductivity type different from the first conductivity type is formed on a first semiconductor layer of a first conductivity type; a gate trench having a predetermined width and extending from the top surface of the second semiconductor layer to a certain depth; a gate electrode formed in the gate trench via an insulating film; a first column of the first conductivity type formed in the second semiconductor layer directly below the gate trench and reaching the first semiconductor layer; a body region of the second conductivity type and a source region of the first conductivity type formed in the second semiconductor layer on a side surface of the gate trench; and The first column is spaced apart from a bottom surface of the gate trench.

5. 5. The semiconductor device according to claim 4, The gate trenches are formed in a plurality of rows, A semiconductor device, wherein a portion of the second semiconductor layer is formed across opposing side surfaces of two adjacent gate trenches.

6. a semiconductor substrate in which a second semiconductor layer of the first conductivity type is formed on a first semiconductor layer of the first conductivity type; a gate trench having a predetermined width and extending from the top surface of the second semiconductor layer to a certain depth; a gate electrode formed in the gate trench via an insulating film; a first column of the first conductivity type formed in the second semiconductor layer directly below the gate trench and reaching the first semiconductor layer; a body region of a second conductivity type different from the first conductivity type and a source region of the first conductivity type formed in the second semiconductor layer on a side surface of the gate trench; a second column of the second conductivity type adjacent to the first column, the second column being formed in the second semiconductor layer and spaced apart from the gate trench in a first direction along the top surface of the second semiconductor layer; and The first column is spaced apart from a bottom surface of the gate trench.

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