Pulse Width Modulation (PWM) Waveform Generation and Synchronization for Radio Frequency (RF) Applications

Abstract

SOLUTION: To disclose a pulse width modulation (PWM) generation device having a phase shift element and a wave form combiner, in which the phase shift element contains: a pair of IQ modulators that is constructed so as to receive a reference signal synchronized by the PWM wave form; a digital-analog converter (DAC) that includes first and second outputs coupled to an I / Q input of one IQ modulator of the pair of IQ modulators, and third and fourth outputs and inputs that are coupled to the I / Q input of the other IQ modulator of the pair of IQ modulators; and a micro controller that is coupled to the reference signal by controlling the DAC so as to control a phase shift of a signal IQ1 and a signal IQ2 of each output of the pair of IQ modulators. A wave form combiner includes: a first input coupled to the output of the one of IQ modulator; and a second input coupled to the output of the other IQ modulator.SELECTED DRAWING: Figure 33

Description

[Technical Field]

[0001] The present invention relates to the generation and synchronization of pulse width modulated (PWM) waveforms for radio frequency (RF) applications. [Background technology]

[0002]

[0001] As is known in the art, impedance matching networks are commonly used to maximize power transfer in many radio frequency (RF) and microwave systems. For example, in an RF transmitter, an impedance matching network may be used to provide an impedance match from the output impedance of an RF power amplifier (PA) to the impedance of an RF load (e.g., an antenna). Such impedance matching increases transmitted power, reduces power losses, and reduces or eliminates the need for additional circuit elements (e.g., isolators, etc.).

[0003]

[0002] One category of impedance matching networks is called a tunable impedance matching network (TMN), which is sometimes referred to as an automatic antenna tuning unit. Conventional TMNs may be implemented as single-element or lumped-element reactive networks, where at least one of the reactive elements is a variable (e.g., tunable) component, so that the impedance of the variable component can be changed at a specific frequency or over a range of frequencies. The reactive elements in a TMN may be arranged in circuit topologies such as a ladder network, an L-network, a T-network, or a Pi-network.

[0004]

[0003] Conventional TMNs can be classified as either analog (continuously adjustable) or digital (adjustable between a set of discrete values). Analog TMNs utilize variable reactance elements with reactance values ​​(at some frequency or over a range of frequencies) that can be tuned in a continuous manner by adjusting bias conditions. Digital TMNs implement variable reactance elements as digitally switched arrays of fixed reactance elements. This approach allows for the adjustment of impedance reactance values ​​in finite, discrete steps.

[0005]

[0004] Analog TMNs are often implemented using varactor diodes (or varactor diode circuits) or microelectromechanical systems (MEMS) varactors. Analog TMNs enable fast and accurate impedance matching over a wide range of impedances, but require relatively high bias voltages to operate at high power levels.

[0006]

[0005] Digital TMNs are often implemented using CMOS switches, MEMS switches, PIN diodes, or discrete power transistors. MEMS switches have low on-resistance and can operate up to tens of GHz with low power consumption, but MEMS switches require large control voltages. PIN diode and CMOS switch-based digital TMNs exhibit low to moderate on-resistance and can therefore handle high power levels at the expense of some resistive power loss. PIN diode and CMOS switch-based digital TMNs are often implemented through on-die integration, e.g., software defined radio (SDR) integrated circuits (ICs) and other on-chip Digital TMNs are preferred. However, digital TMNs exhibit limited tuning resolution and therefore limit the precision with which impedance matching can be achieved. In some high-power applications where precise impedance matching is required over a very wide impedance range, such as RF plasma drivers, the use of digital TMNs may be impractical due to the large number of digital switches required to achieve the required fine tuning resolution. Summary of the Invention [Means for solving the problem]

[0007] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key or essential features or combinations of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0008] In general overview, the concepts, systems, and techniques described herein are directed to methods and apparatus for generating one or more pulse-width modulated (PWM) waveforms (signals) with the ability to dynamically control their pulse width and phase relative to a reference signal. The pulse width and phase (relative to a reference signal) of each PWM waveform can be independently adjusted over a range of 0° to 360° with arbitrarily fine resolution unaffected by the operating frequency. The generated PWM signals can maintain phase and frequency lock to a reference signal over a wide modulation range of the reference signal frequency. The concepts, systems, and techniques described herein are suitable for generating precise, dynamically adjustable PWM waveforms for HF and VHF applications. They are particularly valuable in applications where the reference signal is derived from a radio frequency (RF) input source, relative to which precise timing of the PWM must be maintained, such as phase-switched impedance modulation (PSIM)-based tunable matching networks (TMNs) and PSIM amplifiers. Such circuits find application, for example, in high power microwave plasma systems for use in connection with semiconductor processing and for cleaning semiconductor processing equipment.

[0009] In one aspect of the concepts, systems, and techniques described herein, a pulse width modulation (PWM) generator includes a phase shift circuit having at least one input and multiple outputs. The phase shift circuit is configured to receive a reference signal and, in response, provide a phase-shifted signal at each of the two or more outputs. Each phase-shifted signal may have a phase shift relative to the reference signal. The PWM generator may further include a waveform combiner. The waveform combiner may have multiple inputs, each coupled to a respective output of the phase shift circuit. The waveform combiner may be configured to receive the phase-shifted signals from the phase shift circuit and, in response, generate a PWM signal having a pulse width and a phase shift relative to the reference signal.

[0010]

[0009] In this configuration, a PWM generator is provided for generating a PWM signal having a pulse width and a phase shift relative to a reference signal. In an embodiment, the pulse width and phase shift of the PWM signal relative to the reference signal can be dynamically controlled. The waveform combiner is configured to generate the PWM in response to the phase shift signal, so that by changing the phase shift signal, the pulse width and phase shift of the PWM signal relative to the reference signal can be adjusted.

[0011] In embodiments, the phase shift circuit may include multiple phase shift elements coupled in a parallel or cascade configuration. In an embodiment, the phase shift circuit has at least three inputs and at least one The IQ modulator may include an in-phase / quadrature-phase (IQ) modulator having two outputs. One input of the IQ modulator may be configured to receive a reference signal, and two other inputs of the IQ modulator may be configured to receive baseband signals derived from the reference signal. The IQ modulator may include a summer coupled between its output and at least two of its inputs.

[0012]

[0012] In an embodiment, the waveform combiner may include at least one of an edge detector, a logic gate, a flip-flop, or an amplifier. The waveform combiner may also include a plurality of amplifiers, each having an input and an output. Each input of the amplifier may be configured to receive a phase-shifted signal. The waveform combiner may further include a logic gate having a plurality of inputs and at least one output. Each input of the waveform combiner may be configured to be coupled to the output of at least one amplifier.

[0013] In an embodiment, the phase shift circuit may be configured to generate two or more phase-shifted signals based on at least one predefined phase shift parameter. The phase shift circuit may also be configured to receive the at least one predefined phase shift parameter from a controller. The controller may be configured to generate the at least one predefined phase shift parameter based on a pulse width and a phase shift of the generated PWM signal relative to a reference signal.

[0014] In an embodiment, the PWM generator may be implemented in an integrated circuit.

[0015] The PWM generation techniques presented herein rely on the use of phase-shifting elements that take an input waveform and generate an output waveform that is locked to the input in both phase and frequency (or both delay and frequency). The phase shift (or delay) between the input and output can be dynamically controlled (by digital or analog methods), and the resolution to which the phase shift can be set ultimately determines the resolution to which the phase and pulse width of the PWM signal can be adjusted. These phase-shifting elements can be cascaded or connected in parallel to form cascaded or parallel system architectures, respectively.

[0015]

[0016] In another aspect of the concepts, systems, and techniques described herein, there is provided an apparatus for generating a dynamically controlled pulse width modulation (PWM) signal. The apparatus may include two or more phase shift elements. Each phase shift element may have an input and an output, with the input of each phase shift element configured to receive a reference signal. The apparatus may further include a waveform combiner that may be electronically coupled to the outputs of the phase shift elements. Each phase shift element may be configured to generate a respective phase-shifted signal at its output based on the reference signal and a respective predetermined phase shift parameter. The waveform combiner may also be configured to generate a PWM signal having a pulse width and a phase shift based on the phase-shifted signal generated at the output of the phase shift element.

[0016]

[0017] This particular configuration provides a parallel architecture for generating a desired PWM signal. In an embodiment, the PWM signal may have a dynamically adjustable pulse width and phase shift relative to a reference signal. By adjusting the phase shift parameters of the phase shift elements, the pulse width and phase shift of the PWM signal may be dynamically controlled.

[0017]

[0018] In an embodiment, each predefined phase shift parameter may include at least one of a predefined phase shift or a predefined pulse width.

[0019] In an embodiment, at least one of the phase shifting elements may include an in-phase / quadrature modulator or a phase locked loop.

[0018]

[0020] In an embodiment, each phase shift element may be coupled to a respective control signal. Each control signal may include a respective predefined phase shift parameter. The system may further include a phase detector coupled to the reference signal and the generated PWM signal. In an embodiment, the phase detector may be configured to generate a phase correction signal based on a comparison of the reference signal and the generated PWM signal. The phase correction signal may be provided to each phase shift element.

[0019]

[0021] In an embodiment, the waveform combiner may include at least one edge detector, each edge detector coupled to at least one flip-flop, which may be configured to generate a PWM signal based on a rising edge of at least one generated phase-shifted signal and a rising edge of at least one other generated phase-shifted signal.

[0020]

[0022] In another aspect of the concepts, systems, and techniques described herein, an apparatus for generating a dynamically controlled pulse-width modulated (PWM) signal is provided. The apparatus may include a first phase-shift element having an input and an output. The input of the first phase-shift element may be coupled to a reference signal. The apparatus may also include a second phase-shift element having an input and an output. The input of the second phase-shift element may be coupled to the output of the first phase-shift element. The apparatus may also include a waveform combiner electronically coupled to the outputs of the first and second phase-shift elements. The first phase-shift element may be configured to generate a first phase-shifted signal at its output based on the reference signal and a respective predetermined phase shift. The second phase-shift element may be configured to generate a second phase-shifted signal at its output based on the first phase-shifted signal and a respective predetermined phase shift. The waveform combiner may be configured to generate a PWM signal having a pulse width and a phase shift based on the first and second phase-shifted signals.

[0021]

[0023] This particular configuration provides a cascade structure for generating a desired PWM signal, where each phase shift element may receive a different, unrelated phase shift parameter, and therefore fewer phase shift parameters may need to be adjusted to achieve a desired pulse width and phase shift relative to a reference signal for the generated PWM signal.

[0022]

[0024] In an embodiment, each predefined phase shift parameter may include at least a predefined phase shift or a predefined pulse width.

[0025] In an embodiment, at least one of the phase-shift elements may include an in-phase / quadrature modulator. The apparatus may also include a control circuit coupled to the at least one in-phase / quadrature modulator, the control circuit configured to provide a control signal to the at least one in-phase / quadrature modulator. In an embodiment, the control signal may include respective predetermined phase-shift parameters for the in-phase / quadrature modulator.

[0023]

[0026] In an embodiment, at least one of the phase shift elements comprises a phase locked loop.

[0027] In an embodiment, the apparatus may further include a phase detector that may be coupled to the reference signal and the generated PWM signal. The phase detector may be configured to generate a phase correction signal based on a comparison of the reference signal and the generated PWM signal. In an embodiment, each phase shift element may be further configured to generate a phase-shifted signal based on the phase correction signal.

[0024]

[0028] In an embodiment, the waveform combiner may include at least one logic gate configured to compare the first and second phase-shifted signals.

[0029] In yet another aspect of the concepts, systems, and techniques described herein, an apparatus for generating a dynamically controlled pulse width modulated (PWM) signal is described. The apparatus may include a first set of phase shift elements electronically coupled in parallel, each having an input and an output. The inputs of the first set of phase shift elements may each be electronically coupled to a reference signal. The apparatus may also include a second set of phase shift elements electronically coupled in parallel, each having an input and an output. The inputs of the second set of phase shift elements may each be electronically coupled to an output of at least one phase shift element of the first set. The apparatus may also include a waveform combiner electronically coupled to the outputs of the first and second sets of phase shift elements. Each phase shift element of the first set may be configured to generate a respective phase-shifted signal at its output based on the reference signal and a respective predetermined phase shift. Each phase shift element of the second set may be configured to generate a respective phase-shifted signal at its output based on at least one phase-shifted signal generated by the phase shift elements of the first set and a respective predetermined phase shift. The waveform combiner may be configured to generate a dual-pulse PWM signal having a first pulse with a pulse width and a pulse shift based on the phase-shifted signals generated by the phase shift elements of the first set. The PWM signal may also have a second pulse with a pulse width and pulse shift based on the phase shifted signal produced by the second set of phase shift elements.

[0025]

[0030] In this particular configuration, an arrangement is provided for generating a dual-pulse PWM signal, which can have two pulse widths and a phase shift relative to a reference signal that can be dynamically adjusted. By having two pulse widths and a phase shift, multiple phase-switched reactive elements can be driven simultaneously.

[0026]

[0031] In an embodiment, the phase shift elements of the first set may be electronically coupled in a parallel configuration, and an input of each phase shift element of the first set may be coupled to a reference signal.

[0032] In an embodiment, the first set of phase shifting elements may be coupled in a cascade configuration.

[0027]

[0033] In yet another aspect of the concepts, systems, and techniques described herein, a method for generating a dynamically controlled pulse-width modulated (PWM) waveform is provided. The method may include receiving a reference signal at one or more phase-shift elements. Each phase-shift element may have a respective predefined phase-shift parameter. The method may also include generating respective phase-shifted signals at outputs of the one or more phase-shift elements based on the reference signal and the respective predefined phase-shift parameters. The method may further include combining the generated phase-shifted signals to obtain a PWM waveform having a pulse width and a phase shift based on the predefined phase-shift parameters of the phase-shift elements.

[0028]

[0034] In this particular configuration, a method is provided for generating a PWM signal with dynamically controlled pulse width and phase shift relative to a reference signal. By adjusting the phase shift parameters, the pulse width and phase shift of the PWM signal can be dynamically controlled.

[0029]

[0035] In an embodiment, the respective predefined phase shift parameters may include at least one of a respective predefined phase shift or a respective predefined pulse width.

[0036] In an embodiment, the method may further include providing a respective control signal to each phase shift element, The control signal may include a respective predefined phase shift parameter.

[0030]

[0037] In an embodiment, the method may also include generating a phase correction signal based on a comparison of the reference signal and the PWM waveform.

[0038] In an embodiment, the method further comprises: determining a generated phase shift based on a phase correction signal; The method may further include adjusting the received signal.

[0031]

[0039] In yet another aspect of the concepts, systems, and techniques described herein, a power generation and delivery system is provided having an input port and an output port. The power generation and delivery system may include a pulse width modulation (PWM) signal generator that may include one or more phase shift elements. The PWM signal generator may be configured to generate a PWM signal based on phase shift parameters associated with the one or more phase shift elements. The power generation and delivery system may also include a phase-switched tunable impedance network coupled to the output port. The phase-switched tunable impedance network may be configured to receive the generated PWM signal from the PWM signal generator and, in response, may vary its impedance to modulate the impedance presented to the output port.

[0032]

[0040] In this particular configuration, a phase-switched tunable impedance (PSIM) network is provided that is driven by a PWM signal. The PWM signal generated by the PWM generator may have its pulse width or phase shift relative to a reference signal dynamically adjusted, so that these parameters can be adjusted to change the impedance presented by the PSIM.

[0033]

[0041] In an embodiment, one or more phase shifting elements are electronically coupled in a parallel or cascade configuration.

[0042] Other aspects, features, and advantages of the broad concepts sought to be protected herein will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings, in which like reference numerals identify similar or identical elements. Reference numerals introduced herein in connection with a drawing may be repeated in one or more subsequent drawings without further description herein to provide context for other features. [Brief explanation of the drawings]

[0034] [Figure 1]

[0043] FIG. 1 is a block diagram of an exemplary tunable impedance matching network (TMN) in accordance with described embodiments. [Figure 2]

[0044] 2 is a schematic diagram of an exemplary phase-switched variable capacitance element of the TMN of FIG. 1. [Figure 3]

[0045] 3 is a plot of current and voltage versus phase for the control signal of the phase-switched varactor of FIG. 2; [Figure 4]

[0046] FIG. 2 is a schematic diagram of an exemplary phase-switched variable inductance element of the TMN of FIG. 1. [Figure 5]

[0047] 5 is a plot of current and voltage versus phase for the control signal of the phase-switched variable inductance element of FIG. 4. [Figure 6]

[0048] 5 is a plot of the normalized effective capacitance (or inductance) of the phase-switched elements of FIGS. 2 and 4 versus the control angle of the phase-switched elements. [Figure 7]

[0049] 5 is a plot of the total harmonic distortion of the phase-switched elements of FIGS. 2 and 4 versus the control angle of the phase-switched elements. [Figure 8]

[0050] 1 is a plot of current and voltage versus phase for a control signal of a full-wave switched varactor. [Figure 9]

[0051] 1 is a plot of current and voltage versus phase for a control signal of a full-wave switched variable inductance element. [Figure 10]

[0052] Figure 10A, Figure 10B, Figure 10C, and Figure 10D are schematic diagrams of example switched reactive elements according to described embodiments. [Figure 11]

[0053] FIG. 1 is a schematic diagram of an exemplary phase-switched tunable matching network (TMN) employing a digitally switched capacitance matrix. [Figure 12]

[0054] FIG. 1 is a schematic diagram of an exemplary phase-switched TMN employing a digitally switched inductance matrix. [Figure 13]

[0055] FIG. 1 is a schematic diagram of an exemplary phase-switched TMN in accordance with described embodiments. [Figure 14]

[0056] 14 is a Smith chart of the range of load impedances that can be matched by the tuning network of FIG. 13 for an exemplary operating range. [Figure 15]

[0057] FIG. 14 is a schematic diagram of additional details of the tuning network of FIG. 13. [Figure 16]

[0058] FIG. 1 is a block diagram of an example topology of a phase-switched impedance modulated amplifier in accordance with described embodiments. [Figure 17]

[0059] FIG. 10 is a block diagram of another exemplary topology of a phase-switched impedance modulated amplifier in accordance with described embodiments. [Figure 18A]

[0060] FIG. 1 is a schematic diagram of an exemplary three-switch phase switched impedance modulated amplifier in accordance with described embodiments. [Figure 18B] FIG. 1 is a schematic diagram of an exemplary three-switch phase switched impedance modulated amplifier in accordance with described embodiments. [Figure 18C] FIG. 1 is a schematic diagram of an exemplary three-switch phase switched impedance modulated amplifier in accordance with described embodiments. [Figure 18D] FIG. 1 is a schematic diagram of an exemplary three-switch phase switched impedance modulated amplifier in accordance with described embodiments. [Figure 18E] FIG. 1 is a schematic diagram of an exemplary three-switch phase switched impedance modulated amplifier in accordance with described embodiments. [Figure 19]

[0061] FIG. 1 is a schematic diagram of an exemplary two-switch phase-switched impedance modulated amplifier in accordance with described embodiments. [Figure 20] FIG. 1 is a schematic diagram of an exemplary two-switch phase-switched impedance modulated amplifier in accordance with described embodiments. [Figure 21]

[0062] 1 is a schematic diagram of an exemplary phase-switched impedance modulated amplifier over an exemplary operating range. [Figure 22]

[0063] 22 is a Smith chart illustrating the range of load impedances that can be matched by the phase-switched impedance modulated amplifier of FIG. 21 for an exemplary operating range. [Figure 23] 22 is a Smith chart illustrating the range of load impedances that can be matched by the phase-switched impedance modulated amplifier of FIG. 21 for an exemplary operating range. [Figure 24]

[0064] FIG. 1 is a flow diagram of an exemplary process for operating a TMN. [Figure 25A]

[0065] FIG. 1 is a block diagram of a system for generating a pulse-width modulated (PWM) signal having a predetermined phase shift and pulse width. [Figure 25B]

[0066] 1 is a plot of a pulse width modulated (PWM) waveform having a pulse width w and a phase shift φ relative to a reference signal, where the PWM signal is in phase and frequency locked with the reference signal. [Figure 26]

[0067] FIG. 1 is a block diagram of a PWM generating circuit having a parallel structure. [Figure 27]

[0068] FIG. 1 is a block diagram of a PWM generating circuit having a cascade structure. [Figure 28]

[0069] FIG. 2 is a block diagram of a PWM generator circuit having a double pulse PWM generation structure. [Figure 29]

[0070] FIG. 1 is a block diagram of a PWM generation circuit having a parallel PWM generation structure with two phase shift elements and a phase detector feedback loop. [Figure 30]

[0071] FIG. 1 is a block diagram of a system having a structure capable of generating multiple PWM waveforms that are phase and frequency locked to a common reference signal. [Figure 31]

[0072] FIG. 1 is a block diagram of a PWM generation circuit having an in-phase / quadrature (IQ) modulator. [Figure 32]

[0073] FIG. 1 is a phase diagram illustrating the phase shift according to the baseband input of an IQ modulator. [Figure 33]

[0074] FIG. 1 is a block diagram of a PWM generation circuit having a parallel PWM generation structure with two phase shifters implemented as an IQ modulator. [Figure 34]

[0075] 34 is a plot of phase shift command versus measured phase shift error for a pair of output signals from each of the IQ modulators of the PWM generation circuit of FIG. 33. [Figure 35]

[0076] 34 is a plot of phase shift command versus measured phase shift standard deviation for a pair of output signals from each of the IQ modulators of the PWM generation circuit of FIG. 33. [Figure 36]

[0077] FIG. 1 is a block diagram of a cascaded PWM waveform generator having phase-shifting elements implemented using a phase-locked loop (PLL) module coupled to a waveform combiner. [Figure 37]

[0078] FIG. 37 is a block diagram of the cascaded phase-locked PWM generator of FIG. 36, with a waveform combiner provided by a D-type flip-flop and an edge detector. [Figure 38]

[0079] FIG. 1 is a block diagram of a PWM signal generation system implemented with a PLL. [Figure 39]

[0080] FIG. 1 is a block diagram of a PWM generation system having a nested PLL structure with feedback. [Figure 40]

[0081] 1 is a flowchart of a method for generating a PWM signal having a desired phase shift and pulse width. [Figure 41A]

[0082] 1 is a block diagram of an impedance matching system comprising multiple phase-switched impedance (PSIM) elements driven by a PWM generator. [Figure 41B]

[0083] FIG. 1 is a block diagram of a radio frequency (“RF”) amplifier having a phase-switched tunable impedance network coupled to a system for generating a PWM signal having a desired phase shift and pulse width. [Figure 42]

[0084] FIG. 1 is a block diagram of a system having a phase-switched tunable impedance network with one phase-switched tunable impedance element coupled to a PWM generator. [Figure 43]

[0085] FIG. 1 is a block diagram of a system having a phase-switched tunable impedance network having two phase-switched tunable impedance elements coupled to two PWM generators. DETAILED DESCRIPTION OF THE INVENTION

[0035]

[0086] Table 1 compiles a list of acronyms used throughout this specification to aid in understanding the described embodiments.

[0036] [Table 1]

[0037]

[0087] The described embodiments are directed to phase-switched tunable matching networks (PS-TMNs) and phase-switched impedance-modulated amplifiers (PSIMs). Both phase-switched tunable matching networks and phase-switched impedance-modulated amplifiers include phase-switched variable network reactance elements. When configured in the context of PS-TMNs and phase-switched impedance-modulated amplifiers, such phase-switched variable network reactance elements provide high-speed, high-bandwidth, continuous impedance matching over a wide impedance range while operating efficiently at high power levels without requiring high bias voltages or currents. PS-TMNs may be employed alone or in combination with other matching techniques, such as discrete switched reactance banks.

[0038]

[0088] PS-TMNs can be employed in a variety of reconfigurable and adaptive RF systems, such as RF front-ends for software-defined radio (SDR) and cognitive radio (CR) applications, operating across a wide range of frequency bands at different bandwidths and according to various communication standards. PS-TMNs can also be employed in other RF applications, such as drivers for RF plasma loads to compensate for fast load changes, or in wireless power transfer (WPT) systems to compensate for impedance mismatch between a transmitter and receiver to maximize transmitted power and / or efficiency.

[0039]

[0089] A PSIM may be operable as a zero-voltage switching (ZVS) radio frequency (RF) amplifier. Such a PSIM amplifier may employ a PS-TMN to operate over a wide frequency range by efficiently modulating output power over the wide frequency range and / or matching to a highly variable load (e.g., a load that is variable over a wide impedance range).

[0040]

[0090] Referring to FIG. 1, a radio frequency (RF) system 100 has an impedance Z S and a source 102 having an impedance Z L a phase-switched tunable impedance matching network (PS-TMN) 112 coupled between the load 114 and the In some applications, the source 102, the control circuit 106, and the PS-TMN 112 (and other elements of the RF system 100) may be connected to a power supply voltage (e.g., V DC ) and ground. Control circuit 106 is coupled to PS-TMN 112 and provides control signals to PS-TMN 112 to control the operation of PS-TMN 112. In response to such control signals, PS-TMN 112 provides the desired impedance transformation characteristics. It should be understood that control circuit 106 may be an internal component of PS-TMN 112 or may be an external component coupled to some portions of PS-TMN 112 or control circuit 106 (alternatively, the functionality provided by control circuit 106 may be internal to PS-TMN 112, while other portions of control circuit 106 may be external to PS-TMN 112).

[0041]

[0091] In some embodiments, control circuit 106 controls operation of PS-TMN 112 based at least in part on information received from optional feedforward circuit 104 coupled to source 102 and / or optional feedback circuit 110 coupled to load 114. In some embodiments, optional feedforward circuit 104 includes adaptive predistortion circuit 107, and control circuit 106 includes look-up table (LUT) 108. For example, as described in more detail below, some embodiments may employ one or more nonlinear control techniques (e.g., by control circuit 106) to determine appropriate control signals for PS-TMN 112, such as employing a fixed or adaptive look-up table (e.g., LUT 108) to store predetermined control signal information, feedback compensation (e.g., by feedback circuit 110) and / or feedforward compensation (e.g., by feedforward circuit 104) to adaptively adjust the control signal information, or performing digital predistortion of the control signal (e.g., by predistortion circuit 107), or other similar techniques.

[0042]

[0092] The PS-TMN 112 includes one or more phase-switched reactive elements 116(1)-116(N). As described in more detail below, the phase-switched reactive elements 116(1)-116(N) may be implemented using one or more capacitive elements (e.g., capacitors), one or more inductive elements (e.g., inductors), or a combination of both. The phase-switched reactive elements 116(1)-116(N) determine the effective impedance (Z) presented to the terminals of the PS-TMN 112 at a desired frequency. S,IN , and Z L,IN). The phase switched reactive elements 116(1)-116(N) may be switched, for example, by either shunt or series switches, and the effective impedance of the phase switched reactive elements may be controlled by adjusting the phase and / or duty cycle of the shunt or series switches. In some embodiments, the desired frequency may be the RF frequency of operation of the RF source 102 (e.g., the frequency of the signal provided from the RF source 102 to the PS-TMN 112).

[0043]

[0093] The impedance presented by the PS-TMN 112 to the source 102 and / or load 114 can be adjusted, tuned, varied, or otherwise manipulated by modulating the effective impedance (e.g., by adjusting the impedance of the phase-switched reactive elements 116(1)-116(N)) at the desired frequency of operation of the RF system 100. For example, the phase-switched reactive elements 116(1)-116(N) may be configured to adjust, tune, vary, or otherwise manipulate the impedance presented by the PS-TMN 112 to the source 102 and / or load 114 to provide a desired impedance (Z S,IN ) from the source 102 to the PS-TMN 112, and the desired impedance (Z L,IN ) from the load 114 into the PS-TMN 112.

[0044]

[0094] The control signal provided to the PS-TMN 112 is an RF signal provided by the source 102. The PS-TMN 112 operates to control when the phase switched reactive elements 116(1)-116(N) are switched on and / or off with respect to the signal. This switching results in effective reactance values ​​of the phase switched reactive elements 116(1)-116(N) that affect the desired impedance transformation of the PS-TMN 112. The feedforward information may include information regarding the effective input impedance of the PS-TMN 112, the timing of the RF waveform, the specified signal level, and / or the impedance level, etc. The feedback information may include measurement information regarding the effective load impedance and / or the power reflected from the load, the timing of the RF waveform, etc.

[0045]

[0095] Thus, in some embodiments, the PS-TMN 112 may be employed to provide a desired impedance transformation between the source 102 and the load 114. For example, the PS-TMN 112 may provide impedance matching between the source 102 and the load 114. Alternatively, the impedance of the PS-TMN 112 may be adjusted so that the source 102 does not experience a more stable impedance (e.g., Z S,IN ) is coupled to the load 114. L ) can be adjusted to compensate for variations in

[0046]

[0096] 2, a sinusoidal current source 202 having a current I drives an exemplary phase switched variable reactance 200. The phase switched variable reactance is shown here as including a parallel combination of a capacitor 204 and a switch 206 to provide the phase switched variable reactance as a phase switched variable capacitance 200. The capacitor 204 has a physical capacitance C0 and a voltage V CThe state of switch 206 is controlled by the characteristics of signal Q. For example, switch 206 provides a low impedance signal path between its terminals (e.g., switch 206 is “on” or “closed”) when signal Q has a logic high value, and switch 206 provides a high impedance signal path between its terminals (e.g., switch 206 is “off” or “open”) when signal Q has a logic low value. Thus, switch 206 switches capacitor 204 into the circuit when the switch is open (current I flows into capacitor 204) and out of the circuit when the switch is closed (current I flows through the closed switch, bypassing capacitor 204).

[0047]

[0097] When switch 206 is always off (open), the effective capacitance C of phase switched variable capacitor 200 presented to source 202 is EFF is equivalent to the physical capacitance C of capacitor 204. Alternatively, if switch 206 is always on (closed), the low impedance path across the terminals of switch 206 effectively "shorts" capacitor 204, and phase switched variable capacitance 200 behaves as an infinite capacitor in the sense that the voltage across capacitor 204 remains zero regardless of current I. The effective capacitance C of capacitor 204 EFF can theoretically be controlled between C0 and infinity by controlling the conduction angle of switch 206 over an AC cycle of sinusoidal current source 202 from 0 to 2π. As used herein, the conduction angle is the angle of the sinusoidal signal when switch 206 is turned on. The conduction angle when the switch is turned on may be determined entirely by switching signal Q (e.g., switching angle), or partially by switching signal Q and partially by voltage V C and current I.

[0048]

[0098] Referring to Figure 3, the current I and the capacitor voltage V CExemplary waveforms of I(θ) (e.g., the voltage on capacitor 204) are shown as a function of cycle angle θ with respect to switch control signal Q. Specifically, curve 302 shows I(θ) and curve 306 shows V C 3, for each cycle of I(θ), the switch 206 is turned off (opened) α radians after the transition of I(θ) from negative to positive (e.g., the switch 206 is turned off (opened) α radians after the positive half-cycle of I(θ)). (The switch 206 is on / closed until α radians into the capacitor.) The switch 206 remains off (open) until after the capacitor voltage has ringed and dropped to zero. Biasing the switch to its conducting state (e.g., turning the switch on or closing the switch) after the capacitor voltage has ringed and dropped to zero ensures zero-voltage switching (ZVS) turn-on of the switch 206.

[0049]

[0099] If the switch includes a diode that naturally prevents the voltage from going negative, the timing of actively turning on switch Q can be relaxed because the switch naturally turns "on" when the switch voltage reaches zero and an active turn-on signal can be issued while the diode is conducting. Capacitor C0 across the switch provides a snubber for the turn-off transition, resulting in a zero-voltage switching (ZVS) turn-off of switch 206.

[0050]

[0100] As shown in Figure 3, if I(θ) is a perfectly sinusoidal current source, then the switch 206 remains off (open) until the conduction angle of the switch is reached (e.g., at 2α). Thus, in a half-wave switched capacitor, switch 206 is turned on and off once per cycle of the RF signal from source 102 (e.g., I(θ) as shown by curve 302).

[0051]

[0101] By adjusting α, it is possible to determine where in the cycle the switch 206 is turned on and off. (e.g., by controlling the conduction angle of switch 206), and therefore the voltage at which the capacitor peaks. Therefore, the switching angle (α) and V at the switching frequency C As a result, the effective capacitance C of capacitor 204 is EFF can be expressed as a function of α.

[0052]

number

[0053]

[0102] Referring to Figure 4, the phase switch variable reactance is set to the switching frequency. The inductor 404 may also be implemented as a switched inductor network that allows for continuous control of its effective inductance at . Such a switched inductor network is shown in Figure 4 as a phase switched variable inductance 400, which corresponds to the topological dual of the switched capacitor network 200 shown in Figure 2. As shown in Figure 4, the exemplary phase switched variable inductance 400 includes a series combination of an inductor 404 and a switch 406 driven by a sinusoidal voltage source 402 having a voltage V. The inductor 404 has a physical inductance L and an inductor current I L The state of switch 406 is controlled by signal Q; for example, switch 406 may be on (e.g., closed) when signal Q has a logic high value and may be open (e.g., open) when signal Q has a logic low value. Thus, switch 406 may be thought of as switching inductor 404 into the circuit when the switch is closed (applying voltage V to inductor 404) and out of the circuit when the switch is open (no voltage is applied to inductor 404).

[0054]

[0103] The phase-switched variable reactance switched capacitor described with reference to FIG. Similar to the capacitor implementation, the effective inductance L of the phase-switched variable inductance 400 at the switching frequency is EFF can be modulated from a base value L0 to infinity. For example, if the switch 406 is always on (closed), the effective inductance L of the phase-switched variable inductance 400 as seen from the source 402 is EFF is equivalent to the physical inductance L of inductor 404. Alternatively, if switch 406 is always off (open), then inductor 404 behaves as an infinite inductor in the sense that the current through inductor 404 remains zero regardless of the voltage V. The effective inductance L of inductor 404 is EFF can ideally be controlled between L0 and infinity by controlling the conduction angle of switch 406 over an AC cycle of sinusoidal voltage source 402 from 0 to 2π.

[0055]

[0104] Referring to FIG. 5, the current I and voltage V of the capacitor 204 C An example waveform of , as a function of cycle angle θ with respect to the switch control signal Q. As a result of the phase duality property, the voltage waveform of the switched capacitor network shown in FIG. 3 is similar to the current waveform of the switched inductor network shown in FIG. 5, and vice versa.

[0056]

[0105] Specifically, curve 502 is I L (θ), and curve 506 represents V(θ). where curve 504 shows the Q(θ) of the half-wave switched inductor. As shown in FIG. 5, for each cycle of V(θ), switch 406 is turned on (open) α radians after the negative-to-positive transition of V(θ) (e.g., switch 406 is off / open until α radians into the positive half-cycle of V(θ)). Switch 406 remains on (closed) until after the inductor current has ringed and fallen to zero. Because the switch has an inductor in series with it, zero-current switching (ZCS) turn-on of the switch can be achieved. Turning off the switch when the inductor current has ringed and fallen to zero ensures zero-current switching (ZCS) turn-off of switch 406. In duality with capacitive circuits, the use of a diode as part of switch Q allows for natural switch transition (turn-off) and mitigates the need for precise active timing of the switching control waveform turn-off. As shown in FIG. 5, if V(θ) is a perfectly sinusoidal voltage source, switch 406 will remain on (closed) until the conduction angle of the switch is reached (eg, at 2α).

[0057]

[0106] By adjusting α, it is possible to determine where in the cycle switch 406 is turned on and off. (e.g., controlling the conduction angle of switch 406), and therefore the peak inductor current. Thus, similar to the phase-switched variable reactance switched capacitor implementation described with respect to FIG. 2, the switching angle (α) and I at the switching frequency L As a result, the effective inductance L of inductor 404 is EFF can be expressed as a function of α.

[0058]

number

[0059]

[0107] As a result of phase duality, the equation for effective inductance (1b) is equivalent to the equation for effective capacitance ( Equation (1a) matches the intuitive prediction of infinite effective capacitance when the switch is permanently in the on state (α = π), and C when the switch is permanently off (α = 0). EFF Equation (1b) similarly matches the intuitive prediction of infinite effective inductance when the switch is permanently off (α = 0), and L when the switch is permanently on (α = π). EFF Therefore, according to equations (1a) and (1b), the effective capacitance C at the switching frequency is EFF or Effective inductance L EFF can be modulated by controlling the conduction angle of a switch associated with a capacitor or inductor.

[0060]

[0108] Referring to Figure 6, the normalized effective capacitance C EFF / C0, or normalized effective inductance Chest of Drawers L EFF / L0 is shown by curve 602 at the switching frequency. In a capacitive circuit, this is expressed as the normalized admittance Y EFF / Y0, but in an inductive circuit this is the normalized reactance X EFF / X0. As a result of phase duality, the normalized effective admittance Y of the phase switched capacitor circuit of Figure 2 is EFF / Y0 is the normalized reactance X of the phase switched inductor network shown in Figure 4. EFF Same as / X0.

[0061]

[0109] As shown in Figure 6, the normalized effective capacitance C EFF (or inductance L EF F ) increases rapidly with α and approaches infinity as α approaches π (e.g., 180 degrees).

[0062]

[0110] Referring to FIG. 7, curve 702 shows the results for a perfectly sinusoidal current (voltage) excitation source. The total harmonic distortion of the capacitor voltage (inductor current) versus α is shown. EFF or L EFF The practical range over which V can be modulated depends on the amount of harmonic distortion that may be present in the network. As α increases toward π (e.g., the conduction angle of the switch increases), the capacitor voltage V C (e.g., curve 306), or the inductor current I L (e.g., curve 502) is limited to a shorter period of time. This reduces the likelihood of large Y EFF / Y0 or X EFF / X0 (e.g., C EFF / C0 or L EFF / L0) ratio results in significant harmonic content in the capacitor voltage (e.g., as α increases, total harmonic distortion increases). The amount of harmonic distortion that can be tolerated in a given system depends on the specified limits on harmonic content allowed in the source and / or load, as well as the amount of filtering that is required or desired.

[0063]

[0111] Figure 7 shows the harmonic distortion of a phase-switched variable reactance (e.g., 2 and 4 ) to reduce the harmonic components injected into the source and / or load (e.g., source 102 and load 114) of the RF system.

[0064]

[0112] As described with respect to FIGS. 3 and 5, a phase-switched variable reactance ( For example, the phase switched variable capacitance 200 or the phase switched variable inductance 400 is half-wave switched, and the switches are operated such that the capacitor voltage (curve 306 in FIG. 3) and the inductor current (curve 502 in FIG. 5) are unipolar. However, other switching schemes are possible. For example, FIGS. 8 and 9 show example waveforms of the current I and voltage V for the switch control signal Q as a function of cycle angle θ for the switched capacitor network shown in FIG. 3 and the switched inductor network shown in FIG. 5, respectively.

[0065]

[0113] Specifically, as shown in FIG. 8, curve 802 represents I(θ), and curve 8 06 is V C 9, curve 902 shows the Q(θ) of the full-wave switched capacitor, and curve 804 shows the Q(θ) of the full-wave switched capacitor. L (θ), curve 906 shows V(θ), and curve 904 shows Q(θ) of a full-wave switched inductor. When capacitor 200 is of the full-wave switched type, the switch (e.g., switch 206) is turned off twice per cycle of I(θ) (e.g., Q(θ) is zero), with the off period centered around the instant when current I(θ) is zero. For a perfectly sinusoidal excitation current I(θ), this corresponds to a bipolar capacitor voltage waveform V C (θ) results in the capacitor voltage V C (θ) has a zero DC average value. Similarly, when the phase switched variable inductance 400 is a full-wave switched type, a switch (e.g., switch 406) is turned on (e.g., Q(θ) has a logic high value) twice per cycle of V(θ), with the on-period centered around the instant when the voltage V(θ) is zero. For a perfectly sinusoidal excitation voltage V(θ), this corresponds to a bipolar inductor current waveform I L This results in I(θ), which also has a zero DC average value. Thus, in a full-wave switched capacitor (or inductor), switch 206 is turned on and off twice per cycle of the RF signal from source 102 (e.g., I(θ) as shown by curve 802).

[0066]

[0114] Similar to half-wave switching (e.g., as shown in Figures 3 and 5), Effective capacitance C at switching frequency EFF and effective inductance L EFF can be modulated by controlling the switching angle α of the switch. EFF can be expressed as a function of α for the full-wave switched capacitor:

[0067]

number

[0068] Similarly, the effective inductance L of inductor 404 EFF can be expressed as a function of α.

[0069]

number

[0070]

[0115] Thus, a full-wave switched network ( The effective capacitance / inductance achievable for α (e.g., relationships (2a) and (2b)) is half that achievable with a half-wave switched network (e.g., relationships (1a) and (1b)). However, a full-wave switched network inherently results in reduced harmonic content in the capacitor voltage and inductor current compared to a half-wave switched network at the same switching angle α (i.e., the switching angle that controls the total switch conduction angle). On the other hand, implementing full-wave switching requires the switches to operate at twice the operating frequency (e.g., switching twice per cycle). Furthermore, capacitive modulation requires a bidirectional blocking switch, which can complicate switch implementations using typical semiconductor switches.

[0071]

[0116] The above relationships (1) and (2) are based on the switched network shown in Figs. We show that the effective capacitance and inductance of the switch can be based on the switching angle α for a perfectly sinusoidal excitation signal. For excitation signals that are not perfectly sinusoidal, the effective reactance can be determined by appropriately selecting the timing at which the switch turns off (or on) or the switching angle α. Although relationships (1) and (2) do not allow the exact value of α to be calculated, the switching angle α, together with the circuit waveform that determines the zero voltage (or zero current) point (for switch turn-on (or off), determines the total conduction angle of the switch during a cycle. For excitation signals that are not perfectly sinusoidal, an adaptive lookup table (e.g., LUT 108), feedback circuit 110, or feedforward circuit 104 (including optional digital predistortion circuit 107) can be employed to determine the required value of α for a given desired effective reactance.

[0072]

[0117] Phase switched variable capacitance 200 and phase switched variable inductance 400 can be employed as a building block for implementing phase-switched variable reactance and other tunable circuits such as TMNs. In particular, some applications can benefit substantially from a variable reactance whose value can be controlled over a range spanning both capacitive and inductive reactance, and / or by modulating the effective reactance over a more limited range. Augmenting the phase-switched variable capacitance 200 and / or the phase-switched variable inductance 400 with additional reactive components can provide a wider range of variable reactance.

[0073]

[0118] 10A-10D include both capacitive and inductive elements, thereby 1 illustrates an exemplary embodiment of a phase switched reactance circuit that expands the range over which the impedance of the phase switched reactance circuit can be tuned, as compared to the single element circuits shown in FIGS. 2 and 4.

[0074]

[0119] For example, FIG. 10A shows an inductor 1013 in series with a phase-switched capacitor 1013. 10B shows a phase-switched reactance circuit 1002 including a phase-switched capacitor 1012. A phase-switched capacitor 1013 includes a switch 1016 in parallel with a capacitor 1014, similar to that described with respect to FIG. 2. FIG. 10B shows a phase-switched reactance circuit 1004 including an inductor 1024 in series with a capacitor 1022, with the series combination of inductor 1024 and capacitor 1022 placed in parallel with a phase-switched capacitor 1025. Capacitor 1022 is not phase-switched, and therefore, C DC 10C shows a phase-switched reactance circuit 1006 including a capacitor 1032 in parallel with a phase-switched inductor 1033. The phase-switched inductor 1033 includes a switch 1036 in series with an inductor 1034, similar to that described with respect to FIG. 4. FIG. 10D shows a phase-switched reactance circuit 1008 including an inductor 1042 in parallel with a capacitor 1044, with the parallel combination of inductor 1042 and capacitor 1044 placed in series with a phase-switched capacitor 1045. Inductor 1042 is not phase-switched, and therefore L DC Phase switched inductor 1045 includes a switch 1048 in series with an inductor 1046, similar to that described with respect to FIG.

[0075]

[0120] As will be appreciated by those skilled in the art, circuits other than those illustrated in FIGS. 10A-10D may be used. Path variations are also possible. For example, placing a capacitor in series with a phase-switched capacitor results in a net effective impedance with a maximum capacitance equal to the series combination of the capacitor and the physical capacitance of the phase-switched capacitor, and a minimum capacitance equal to the series combination of the capacitor and the phase-switched capacitance value.

[0076]

[0121] As described with respect to FIGS. 6 and 7, the phase switched variable capacitor 200 and For phase-switched variable inductances 400, there is a tradeoff between their variable reactance range and the amount of harmonic content injected into the rest of the system. As such, the range over which the effective reactance can be controlled may be limited by the amount of harmonic content that can be tolerated in the system (e.g., by source 102 and / or load 114). Some embodiments may employ additional or external filtering components to reduce the harmonic content injected into source 102 and / or load 114. However, in some embodiments, employing additional filtering components may not be possible.

[0077]

[0122] 11 and 12, additional filtering components are employed. In other cases, harmonic content can be reduced by combining the phase-switched variable capacitance 200 and the phase-switched variable inductance 400 with one or more digitally controlled capacitor or inductor matrices that are not phase-switched. Such hybrid switched networks include RF switches operated at the RF operating frequency and with controlled phase and duty cycle relative to the RF waveform. The hybrid switched network also includes digital switches associated with one or more capacitors or inductors in the switched matrix. The digital switches are typically operated at frequencies much lower than the RF frequency, but with an effective reactance C EFF or L EFFIt can be operated up to an RF frequency determined by the control bandwidth (e.g., for each cycle).

[0078]

[0123] Referring to FIG. 11, the hybrid switched network 1100 has a phase switch type reactance (e.g., capacitor C01116 and parallel switch 1118), and a digitally controlled capacitor network 1102. Although shown as a phase switch type variable capacitor (e.g., capacitor C01116 and parallel switch 1118) coupled in parallel with the digitally controlled capacitor network 1102 and load 114, in other embodiments, the phase switch type reactance may be implemented as a phase switch type variable inductor (e.g., such as shown in FIG. 4) coupled in series with the digitally controlled capacitor network 1102 and load 114, or as one of the phase switch type reactance circuits shown in FIGS. 10A - D, or other equivalent circuits.

[0079]

[0124] The digitally controlled capacitor network 1102 includes a plurality of capacitors and associated switches shown as capacitors 1104, 1 108, and 1112, and switches 1106, 1110, and 1114. In some embodiments, each of capacitors 1104, 1108, and 1112 has a unique capacitance value, enabling the capacitance value of the digitally controlled capacitor network 1102 to vary over a large capacitance range. For example, as shown in FIG. 11, capacitors 1104, 1108, and 1112 may increase from a phase switch type capacitor base value (e.g., C0) by C0 each until reaching a maximum capacitance value (e.g., (2·2 N -1)·C0), where N is the number of capacitors in the digitally controlled capacitor network 1102).

[0080]

[0125] Switches 1106, 1110, and 1114 are for capacitors 1104, 110 11. The switches 1106, 1110, and 1114 are coupled in series with corresponding ones of the switches 1106, 1110, and 1112 and are operable to adjust the capacitance of the digitally controlled capacitor network 1102 by connecting (or disconnecting) their respective capacitors. The switches 1106, 1110, and 1114 may operate based on one or more control signals from the control circuit 106. As will be described, the switches 1106, 1110, and 1114 generally operate at frequencies below the RF frequency to adjust the capacitance value of the digitally controlled capacitor network 1102.

[0081]

[0126] Referring to FIG. 12, a hybrid switched network 1200 includes: The phase switch reactance (e.g., inductor L01 216 and series switch 1218) and the digitally controlled inductor network 1202. Although shown as a phase-switched variable inductance (e.g., inductor L01 216 and parallel switch 1218) coupled in series with inductor network 1202 and in parallel with load 114, in other embodiments, the phase-switched reactance may be implemented as a phase-switched variable capacitance (e.g., such as that shown in FIG. 2), or one of the phase-switched reactance circuits shown in FIGS. 10A-D, or other equivalent circuits.

[0082]

[0127] The digitally controlled inductor network 1202 includes inductors 1206, 1 12 includes multiple inductors and associated switches, shown as inductors 1206, 1210, and 1214, and switches 1204, 1208, and 1212. In some embodiments, inductors 1206, 1210, and 1214 each have a unique inductance value, allowing the inductance value of digitally controlled inductor network 1202 to vary over a large inductance range. For example, as shown in FIG. 12, inductors 1206, 1210, 1214, and 1218 may increase in increments of L from a phase-switched inductor base value (e.g., L) until they reach a maximum inductance value.

[0083]

[0128] Switches 1204, 1208, and 1212 are connected to inductors 1206, 121 Switches 1204, 1208, and 1212 are coupled in parallel with corresponding ones of switches 1204, 1208, and 1214 and are operable to adjust the inductance of digitally controlled inductor network 1202 by connecting (or shorting, e.g., providing a low impedance path to bypass) the respective inductors. Switches 1204, 1208, and 1212 may operate based on one or more control signals from control circuit 106. As will be described, switches 1204, 1208, and 1212 generally operate at frequencies below RF frequencies to adjust the capacitance value of digitally controlled inductor network 1202.

[0084]

[0129] Digitally controlled capacitor network 1102 and digitally controlled inductor The capacitor network 1202 extends the range over which the reactance of a phase switched reactance (e.g., capacitor C0 1116 and parallel switch 1118, or inductor L0 1216 and series switch 1218) can be continuously varied without introducing excessive harmonic content into the source 102 and / or load 114. For example, the embodiments shown in FIGS. 11 and 12 employ a digitally controlled capacitor network 1102 (or a digitally controlled inductor network 1202) to control the base capacitance C0 (or L0) of the switched network 1100 (or 1200). The switch of the phase switched reactance (e.g., switch 1118 or switch 1218) can be operated to gradually increase the base capacitance C0 (or inductance L0) by a factor determined by the relationships (1) and (2) described above.

[0085]

[0130] For example, the switches in the hybrid switched capacitor network 1100 Effective capacitance C at switching frequency EFFcan be controlled between a lower capacitance value C0 and an upper capacitance value by full-wave switching the RF switch with a switching angle α varying from 0 to approximately π / 2, as shown in Figure 3. As shown in Figure 7, RF switch operation at a switching angle α less than π / 2 (90 degrees) corresponds to peak harmonic distortion of approximately less than 35%. Thus, hybrid switched networks (e.g., 1100 and 1200) enable continuous control of effective reactance at switching frequencies over a wide capacitive (or inductive) range with minimal harmonic distortion and without the need for adjustable bias voltages or currents.

[0086]

[0131] In various embodiments, the RF switch of the TMN 112 (e.g., switch 2 The switching elements 406 (or switches 406) may be implemented as one or a combination of various types of switching elements, for example, lateral or vertical FETs, HEMTs, thyristors, diodes, etc., depending on, for example, the RF frequency or other operating parameters of the RF system 100. A logic circuit, a logic gate, or other similar circuit elements may be employed.

[0087]

[0132] Phase switched variable capacitance 200 and phase switched variable inductance 400 may be employed as a circuit element in a more complex phase-switched tunable matching network (PS-TMN), e.g., a Pi-network topology PS-TMN (Pi-TMN), although other network topologies are possible, such as an L-network, a T-network, or other similar networks. FIG. 13 shows a schematic of an exemplary RF system 1300 including an RF source 1301 coupled to a Pi-TMN 1302, which is coupled to an RF load 1303. The Pi-TMN 1302 includes two variable shunt capacitive susceptances B1 1310 and B2 1314. In the exemplary embodiment, the RF source 1301 is typically the output of a power amplifier or another RF system. As shown in FIG. 13, the RF source 1301 is represented by its Norton equivalent circuit as a source resistance R S1306 and source susceptance B S 1308. Similarly, the RF load 1303 can be represented as including a current source 1304 in parallel with a load susceptance B L Load resistor R in parallel with 1316 L 1318. The source and load impedance Z S and Z L can be expressed as follows, respectively: Z S =(R S -1 +jB S ) -1 (3) Z L =(R L -1 +jB L ) -1 (4) Therefore, the load impedance Z L is the source impedance Z S The susceptances B1 and B2 required to match are given by:

[0088]

number

[0089]

number

[0090] Therefore, the Pi-TMN1302 can adjust the load impedance Z by adjusting the values ​​of the variable shunt capacitive susceptances B11310 and B21314. L is the source impedance Z S can be adopted to match

[0091]

[0133] As shown in FIG. 13, the Pi-TMN1302 embodiment has two variable speed switches. Although the present invention includes shunt capacitive susceptances B1 and B2, and a fixed inductive reactance X1, numerous other implementations of the Pi-TMN are possible, such as employing variable shunt inductive susceptances and fixed capacitive reactances, or implementing all three reactive branches as variable components. Of course, it should be understood that it is also possible to realize an L-section TMN with one variable shunt path element and one variable series path element. Other types of networks may also be employed. As described in more detail below, ground-referenced variable capacitors are well suited to implementation with phase-switched variable reactance networks at RF frequencies.

[0092]

[0134] Referring to Figure 14, the load impedance that can be matched by the Pi-TMN1302 is An exemplary range of the variance is shown as the shaded area 1402 in the Smith chart plot 1400 (R S For example, the impedance value represented by the shaded area 1402 is normalized to X=R S , 1 / R S ~4 / R S The susceptance B1 and 1 / R are variable over a range of S ~2 / R S This can be achieved by an exemplary Pi-TMN having a susceptance B2 that is variable over a range of 1:4 and 1:2. As shown in FIG. 14, the Pi-TMN 1302 can match the impedance of the RF source 1301 to a load impedance that varies (both capacitively and inductively) over approximately a 10:1 resistive range and a 5:1 reactive range. To do this, the Pi-TMN 1302 modulates B1 over a 1:4 range and B2 over a 1:2 range, which can be achieved employing phase-switched variable reactance networks such as those shown in FIGS. 2 and 4.

[0093]

[0135] Figure 15 shows the power dissipation for a 50 Ω source impedance (e.g., R S About 1506 , shows an exemplary embodiment of a phase-switched Pi-TMN circuit 1502 for achieving the matching range shown in FIG. 14. The inductive reactance X is proportional to the Norton equivalent source resistance R S 15, the variable capacitive susceptances B1 and B2 are implemented as half-wave phase-switched capacitors (e.g., phase-switched capacitor 200 of FIG. 2). The variable capacitive susceptance B1 is selected to be equivalent in value to the phase-switched capacitor C P2 1514 and a FET switch 1512, which is controlled by a switching control signal q2 having a switching angle α2. The variable capacitive susceptance B2 is a phase-switched capacitor C P1 FET switch 1512 includes a switching control signal q1 having a switching angle α1.

[0094]

[0136] In an exemplary embodiment, the phase-switched Pi-TMN circuit 1502 includes two Operating at 7.12 MHz, by appropriately adjusting the switching angles of the switches (α1 and α2) and the phase shift between them (e.g., by adjusting the switching control signals q1 and q2), a 50 Ω source impedance can be matched to load impedances that vary (both capacitive and inductive) over a 10:1 resistive range and a 5:1 reactive range.

[0095]

[0137] Variable capacitive susceptances B1 and B2 are half-wave FET-switched capacitors. Implementing the variable reactances as a network provides zero-voltage switched (ZVS) operation of the switches, allowing each variable reactance to be implemented with a single ground-referenced switch (e.g., FET 1512 for variable capacitive susceptance B1 and FET 1522 for variable capacitive susceptance B2). ZVS operation is desirable in switched systems because it reduces switching power losses and improves overall system efficiency. Furthermore, the output (drain-source) capacitance of FETs 1512 and 1522 is reduced by the phase-switched capacitor C P1 and C P2 and therefore adds to the shunt capacitance and can be utilized as part of the TMN.

[0096]

[0138] In the exemplary Pi-TMN circuit 1502, the inductive reactor shown in FIG. The inductor X1 312 is connected in series between the variable susceptors B1 and B2, which are arranged as shunt elements (e.g., coupled to ground). S2 1516 and capacitor C S2 1518 is implemented as a series resonant circuit including inductor L S2 1516 and capacitor C S2 1518 is selected to have an inductive impedance approximately equal to the source impedance (eg, 50 ohms) at the desired frequency.

[0097]

[0139] In the embodiment shown in FIG. 15, two additional series resonant circuits are provided: One is included as an input filter and the other as an output filter of the Pi-TMN circuit 1502. , limit the amount of harmonic content injected into the source and load as a result of switching. For example, capacitor C S1 1508 and inductor L S1 1510 acts as a series resonant input filter between the source 1504 and the Pi-TMN circuit 1502. Similarly, inductor L S3 1524 and capacitor C S31526 acts as a series resonant output filter between the load 1528 and the Pi-TMN circuit 1502.

[0098]

[0140] L S2 1516 and C S2 The quality factor Q of the 1518 series resonant circuit is Tch type capacitor C P1 1520 and phase switched capacitor C P2 1514. For example, increasing the quality factor Q (e.g., L S2 1516 and C S2 1518), the phase-switched capacitor C P1 1520 and phase switched capacitor C P2 1514, but increasing the quality factor Q also reduces the effective bandwidth of the network.

[0099]

[0141] For example, a 50 Ω source at an exemplary desired frequency in the range of about 27 MHz. impedance (e.g., R S 1506), in the phase-switched Pi-TMN circuit 1502 to achieve the matching range shown in FIG. 14, the phase-switched capacitor C P1 1520 may have a physical value C0 of 130 pF and a phase-switched capacitor C P2 1514 may have a physical value C0 of 100 pF. P1 1520 and phase switched capacitor C P2 To achieve the desired quality factor Q, a series resonant circuit is formed between the 1514 and the capacitor C S2 1518 may have a value of 0.01 μF, and inductor L S2 1516 may have a value of 297 nH. To achieve the desired input and output filtering by a series resonant circuit, capacitor C S1 1508 and C S3 1526 may have a value of 23.4 pF, and inductor L S1 1510 and L S31524 may have a value of 1.47 μH. Additionally, FETs 1512 and 1522 may have an on-resistance of 10 mΩ, and the body diode of each FET may have a forward voltage of 0.4 V and an on-resistance of 10 mΩ.

[0100]

[0142] The switching of FETs 1512 and 1522 is based on the switching angle α, The switching angle α is synchronized with the drain current of the capacitor C P1 and C P2 As explained above for the half-wave phase switched capacitor, FETs 1512 and 1522 are turned off after their drain currents cross over from negative to positive, and then turned on again as their respective drain voltages ring and drop to zero. The appropriate value of α for each of FETs 1512 and 1522 is determined by the desired load impedance Z as given by relationships (5) and (6): L Once the respective capacitive susceptances B1 and B2 are known, their values ​​can be calculated by applying relationship (1a) (for half-wave phase switched capacitors) or relationship (2a) (for full-wave phase switched capacitors) to C EFF (where C0 is a known value for the physical capacitance of the capacitor), one can determine the value of α that corresponds to the desired susceptance value.

[0101]

[0143] As will be explained, a phase-switched network with current excitation that is not perfectly sinusoidal is In a switching network, relationships (1) and (2) may not result in an accurate value of α to achieve the desired susceptance. Furthermore, nonlinearities in the drain-source switch capacitance and the interaction of the two switched networks (e.g., capacitive susceptances B1 and B2) may also result in an inaccurate calculation of α. Therefore, some embodiments use nonlinear control techniques (e.g., by control circuit 106), such as a fixed or adaptive look-up table (e.g., LUT 108), feedback (e.g., by feedback circuit 110), feed-forward compensation (e.g., by feed-forward circuit 104), digital pre-distortion of the switching angle (e.g., by pre-distortion circuit 107), or other similar techniques, to determine the appropriate value of α. (This is the case when the

[0102]

[0144] FET1 is connected so that the Pi-TMN circuit 1502 achieves a given impedance. To set the correct value of the switching control parameter α for each of 512 and 1522, the LUT 108 may store predefined switching angles (e.g., α1 and α2) corresponding to various load impedances. For example, Table 2 shows an exemplary list of possible load impedances that the Pi-TMN circuit 1502 can match to a 50Ω source and the corresponding values ​​of the switching angles α1 and α2 for the switch control signals q1 and q2.

[0103] [Table 2]

[0104]

[0145] Table 2 shows how the Pi-TMN circuit 1502 can handle a 50 Ω source impedance with a small The results show that it is possible to match a load impedance that varies resistively over a factor of at least 10:1. The switching angles (α1 and α2) listed in Table 2 and the effective reactance (e.g., C EFF / C0 or L EFFBased on a plot of .lamda. / L0) versus .alpha., it can be shown that a 2:1 modulation of the effective capacitance can achieve impedance matching to a load impedance that resistively varies over a 10:1 range.

[0105]

[0146] Other types of systems may also be implemented using the phase-switched networks described herein. For example, a wide range of systems can benefit from RF power amplifiers (PAs) that deliver power at specific frequencies or across specific frequency bands. Such PAs can advantageously control output power over a wide range and maintain high efficiency over their operating range. Traditional linear amplifiers (e.g., Class A, Class B, Class AB, etc.) offer the advantages of wide-range dynamic output power control and high-fidelity amplification, but have limited peak efficiency that drops rapidly with power backoff. On the other hand, switching PAs (e.g., Class D, Class E, Class F, Class φ, etc. inverters) offer high peak efficiency but only generate a constant envelope signal while remaining in switch mode (at a constant supply voltage).

[0106]

[0147] One technique for controlling output power in a switching PA is through load modulation. In this case, the load of the PA is modulated by an external network. In the described embodiment, the load of the PA is modulated by a phase-switched tunable matching network (TMN) (e.g., a network including one or more phase-switched variable capacitances 200 or phase-switched variable inductances 400, such as Pi-TMN circuit 1502). For example, the impedance transformation of the phase-switched TMN can control the output power of the PA.

[0107]

[0148] Referring to FIG. 16, such a phase switched impedance modulation (PSI The RF PA 1602 is shown as a PSIM amplifier 1600. The PSIM amplifier 1600 includes an RF power amplifier (or inverter) 1602 that generates RF power at a particular frequency or over a particular frequency range. The RF PA 1602 is connected to a power source (e.g., a voltage V DC and ground) and the phase-switched TMN 1604. The phase-switched TMN 1604 has a load impedance Z L 16. The phase-switched TMN 1604 is coupled to an RF load 1606 having a load impedance Z. The phase-switched TMN 1604 is coupled to a controller 1608 that controls the operation of the TMN, for example, by providing control signals to switches of the TMN based on a switching angle (e.g., α) to achieve a desired impedance. Although not shown in FIG. 16, in some embodiments, the controller 1608 is coupled to the RF PA 1602 and also controls the operation of the PA. The phase-switched TMN 1604 is coupled to an RF load 1606 having a load impedance Z L to the impedance presented to the PA 1602. For example, the phase-switched TMN 1604 adaptively controls the load (e.g., Z TMN ) to control the output power of the PA 1602 and / or compensate for frequency and / or load impedance variations to provide high efficiency and desired power to the load.

[0108]

[0149] In various embodiments, the PA 1602 includes: (1) a switching inverter; (2) an amplitude-modulated linear PA, or (3) a combination thereof (e.g., depending on the desired output power). For example, FIG. 17 shows a block diagram of an exemplary PSIM amplifier 1700 including a switching PA 1702 (e.g., a Class E, Class F, or Class φ PA, etc.) that includes a single switch (e.g., a FET 1706). In other embodiments, other types of PAs may be employed, such as a linear PA (e.g., Class A, Class B, Class AB, or Class C) or other switching PAs (e.g., Class D, inverse Class D, etc.) that use two or more switches to convert DC power to RF power.

[0109]

[0150] As will be described, a phase-switched TMN (e.g., TMN1604 or 17 10) The effective load impedance Z seen by the PA TMN , to control the output power over the operating power range of the PSIM amplifier (e.g., amplifiers 1602 and 1702). In addition, the operating power range of the PSIM amplifier can be further extended by also employing amplitude modulation of the PA drive signal for large output power backoff.

[0110]

[0151] Some embodiments may also incorporate other techniques such as discrete or continuous drain modulation of a power amplifier. A number of power modulation techniques may be employed. Drain modulation of a PA modulates (e.g., switches) the bias voltage applied to the bias terminal of the PA. For example, one drain modulation technique may switch the bias voltage between multiple discrete voltage levels or continuously adjust the bias voltage over a voltage range.

[0111]

[0152] In addition to performing impedance modulation and output power control of the RF PA, A phase-switched TMN (e.g., TMN1604 or 1710) also has a load impedance Z L For example, a phase-switched TMN can be employed to compensate for variations in the amplifier's load network impedance as the operating frequency changes, thus maintaining ZVS operation, thereby providing a variable load impedance to match the desired RF inverter load impedance Z for a given output power level. T MN In this way, a PSIM amplifier (e.g., PSIM amplifiers 1600 and 1700) dynamically controls the output power it delivers to widely varying load impedances, such as RF plasma loads, over a large frequency range.

[0112]

[0153] Therefore, the PSIM amplifiers (e.g., PSIM amplifiers 1600 and 1700 ) enables (1) efficient dynamic control of output power over a wide power range, (2) the ability to match impedance and deliver power to a wide range of loads, and (3) full zero voltage switching (ZVS) operation over a frequency range for frequency agile operation.

[0113]

[0154] The blocks of the PSIM amplifiers 1600 and 1700 shown in FIGS. While the figures show the PSIM amplifier as a cascade combination of an RF PA (e.g., RF PAs 1602 and 1702) and a phase-switched TMN (e.g., phase-switched TMNs 1604 and 1710), other embodiments integrate the PS-TMN into the RF PA design. As a result, such an integrated PSIM amplifier can be viewed as an RF amplifier including two or more switches, where a first switch (or group of switches) is primarily responsible for generating RF power from DC input power and a second switch (or group of switches) is primarily responsible for modulating the effective impedance presented to the RF amplifier by the load network. In most embodiments, the second switch (or group of switches) does not convert DC power to RF power (e.g., the second switch provides zero power conversion from DC to RF), but in some embodiments, the second switch may convert some power from DC to RF or from RF to DC.

[0114]

[0155] In most embodiments, the PSIM amplifier is implemented with a switching transistor. It may be a zero-voltage switching (ZVS) amplifier that operates qualitatively in switch mode, turning on and off under zero voltage switching, allowing high efficiency to be achieved. In other implementations, the PSIM amplifier may provide switch mode operation (e.g., saturated operation) over part of its operating range (e.g., while delivering high output power) and utilize linear mode operation over other parts of its range.

[0115]

[0156] For example, FIG. 18A illustrates an example topology for a PSIM amplifier 1800A. As shown, the PSIM amplifier 1800A includes an inductor L F and this inductor L F However, transistor 1804 and capacitor C F The inductor L is coupled to the parallel combination of F , capacitor C F , and FET 1804 generally operate to generate RF output power from the DC source to the rest of the network. The branch reactance X1 is F and node N2, which is coupled to a first phase switched reactance (e.g., FET 1806, shunt reactance X S2 , and phase switch variable reactance X P2 ), and a second phase switched reactance (e.g., FET 1808, branch reactance X S3 , and phase switch variable reactance X P3 ) is coupled to the Pi-TMN, which includes a reactance X2 coupled between the Pi-TMN at node N1 and the load impedance Z L The branch reactances X1, X2, X3, and X S2 , X S3 , and phase switch variable reactance X P2 and X P3 can be implemented as a variety of different reactive networks depending on the required design functionality.

[0116]

[0157] FIG. 18B is an exemplary design 18 of the PSIM amplifier topology shown in FIG. 18A. 18B, the phase-switched variable reactance (FET switches 1806 and 1808 and phase-switched capacitor C P2 and C P3 18B) is implemented by a half-wave phase switched capacitor network such as that described with respect to Figures 2 and 3. As shown in Figure 18B, three switches 1814, 181 6 and 1818 are at DC (e.g., capacitors C S1 , C S2 , and C S3 FET switch 1814 is responsible for generating all the RF power, while FET switches 1816 and 1818 are responsible for generating the load Z L 1814 at node N2).

[0117]

[0158] FIG. 18C illustrates an exemplary design 18 of the PSIM amplifier topology shown in FIG. 18A. Network 1800C is similar to network 1800B, except that in network 1800C, a phase switched capacitor network (e.g., FET 1826 and capacitor C P2 and FET1828 and capacitor C P3 ) are the capacitors C P4 and C P5 This reduces the sensitivity of the PSIM amplifier to variations in the effective reactance of the switched capacitor network.

[0118]

[0159] FIG. 18D illustrates an exemplary design 18 of the PSIM amplifier topology shown in FIG. 18A. 00D, where FET switches 1834 and 1836 are DC coupled (e.g., coupled to inductor L S1 ) and therefore potentially one or both of FET switches 1834 and 1836 can be used to convert DC power to RF power or vice versa, while FET switch 1838 is DC isolated (e.g., via capacitor C S2 and C S3 ), and therefore the load impedance Z L It is used only for impedance matching to

[0119]

[0160] FIG. 18E illustrates an exemplary design 18 of the PSIM amplifier topology shown in FIG. 18A. 00E, where all three FET switches 1844, 1846, and 1848 are DC coupled (e.g., with inductor L S2 ), only the load is DC isolated (for example, through a capacitor C S3 Thus, in such an embodiment, all three FET switches 1844, 1846, and 1848 could potentially be used to convert between DC and RF power and / or serve to impedance match the network to a load, although it is not required that all three provide each function.

[0120]

[0161] As shown in FIG. 18E, the capacitor C F and FET switch 1844 The switch capacitor network is made up of capacitors C P2 , inductor L2, and FET switch 1846. As a result, some embodiments may combine these two networks into a single switched reactive network having an input current that matches the sum of the input currents of the two switched reactive networks associated with FETs 1844 and 1846. Thus, in some embodiments, the three-switch PSIM shown in FIG. 18E may be implemented as a two-switch PSIM such as those shown in FIGS. 19 and 20.

[0121]

[0162] Referring to FIG. 19, an exemplary topology for a two-switch PSIM 1900 The two-switch PSIM1900 is shown in the figure. F and this inductor L F is the FET1904 and capacitor C F The branch reactance X1 is connected to the parallel combination of the capacitor C F and the phase switched reactance X P2and reactance X coupled in series with the parallel combination of FET 1906. S2 The branch reactance X2 is coupled between the phase switched reactance network and the load impedance Z L The branch reactances X1, X2, and X S2 , and phase switch variable reactance X P2 can be implemented as a variety of different reactive networks depending on the required design functionality. Either one of the switch FETs 1904 and 1906, or both switches 1904 and 1906, converts between DC and RF power. It can be used to

[0122]

[0163] Referring to Figure 20, the inductor L S1 and capacitor C S1 Implemented as An example implementation of a two-switch PSIM 2000 is shown with a branch reactance X1. S1 provides DC isolation between FET switches 2004 and 2006. Thus, FET switch 2004 generates RF power and FET switch 2006 modulates the impedance presented to the source.

[0123]

[0164] FIG. 21 shows an example implementation of a three-switch PSIM amplifier 2100. The SIM amplifier 2100 operates over a frequency range of 20.86 MHz to 27.12 MHz (1.3 times the frequency). Additionally, the PSIM amplifier 2100 operates over an impedance Z of 50 Ω with ±10% impedance variation (resistive and reactive). L provides the capability for 10:1 dynamic control of the output power delivered to a load having

[0124]

[0165] The PSIM amplifier 2100 includes an RF PA (inverter) 2102 and a Pi-TM N2104, branch filter 2106, and load impedance Z LThe RF PA2102 includes a FET switch 2108, an inductor L F , and capacitor C F and C S1 and inductor L S1 In the embodiment shown in FIG. 21, the RF PA 2102 is a modified class E inverter with a FET switch 2108 that converts between DC and RF power. The Pi-TMN 2104 includes a first phase switched capacitor (e.g., C P2 and FET 2110), and a second phase switched capacitor (e.g., C P1 The branch filter 2106 includes a Pi-TMN 2104 and a load Z L An inductor L is coupled between S3 and capacitor C S3 Includes.

[0125]

[0166] Pi-TMN2104 is the inverter load impedance Z TMN RF PA When maintained as a nearly resistive load at the operating frequency of the RF PA2102, the RF PA2102 maintains zero voltage switching (ZVS) and high efficiency at different output power levels. TMN is 50Ω (for example, load impedance Z L The RF PA2102 dynamic power back-off control is TMN This can be achieved by the Pi-TMN2104 modulating the

[0126]

[0167] For operation over the frequency range of 20.86 MHz to 27.12 MHz, Figure 21 The exemplary embodiment of the PSIM amplifier 2100 shown in FIG. 2 includes an inductor L having a value of 113 nH. F , a capacitor C with a value of 180 pF F , a capacitor C with a value of 15.2 pF S1 , an inductor L with a value of 3.81 μH S1, a phase-switched capacitor C with a physical value C0 of 152 pF P2 , an inductor L with a value of 381 nH S2 , a capacitor C with a value of 0.01 μF S2 , a phase-switched capacitor C with a physical value C0 of 152 pF P1 , an inductor L with a value of 3.81 μH S3 , and a capacitor C with a value of 15.2 pF S3 In some embodiments, the Pi-TMN2104 employs a half-wave switched capacitor network (e.g., capacitor C P2 and FET2110 and capacitor C P1 and FET2112).

[0127]

[0168] Capacitor C S2 and inductor L S2 These series rears formed by The active network branch has a 50 Ω inductive impedance at a frequency of 20.86 MHz and includes two switched networks (e.g., capacitors C P2 and FET2110 and capacitor C P1 and FET2112) to provide DC isolation. Capacitor C S2 and inductor L S2 The impedance of the Pi-TMN2104 is Z TMN Sets the resistance range over which the capacitor C can be modulated. S3 and inductor L S3 The series resonant network formed by L Provides additional filtering of DC current and high frequency harmonic components are applied to the load Z L The Pi-TMN 2104 adjusts the impedance Z presented to the RF PA 2102 by appropriately driving the FET switches 2110 and 2112, for example by adjusting the conduction angle of the FETs. TMN The impedance Z presented to the RF PA2102 can be modulated. TMNBy modulating the , the Pi-TMN2104 transfers the load Z from the RF PA2102. L The output power delivered to the power supply can be controlled.

[0128]

[0169] Figure 22 shows the Z of the Pi-TMN2104. TMN is adjusted at 20.86MHz FIG. 23 shows an example impedance range (e.g., shaded area 2202) that can be TMN 2302. The Smith charts 2200 and 2300 are normalized to 50 Ω. The shaded areas 2202 and 2302 show an example impedance range (e.g., shaded area 2302) over which the phase-switched capacitor C can be adjusted at 27.12 MHz. The Smith charts 2200 and 2300 are normalized to 50 Ω. The shaded areas 2202 and 2302 show the impedance range of the phase-switched capacitor C over a 1:6 impedance range. P1 (e.g., varying the switching angle α1 of FET 2112 over approximately 0 degrees to 125 degrees), and varying the phase-switched capacitor C over a 1:10 impedance range. P1 (e.g., by varying the switching angle α2 of the FET 2110 from approximately 0 to 135 degrees), the Pi-TMN2104 can vary the load impedance Z over a 10:1 range. L Furthermore, Z TMN is the load impedance Z at the operating frequency of the RF PA2102 L can be modulated to account for ±10% variations in (resistive and reactive)

[0129]

[0170] FET211 so that Pi-TMN2104 achieves a given impedance To set the correct values ​​for the switching angle α of FET 2110 and the switching angle α of FET 2110, LUT 108 may store predefined switching angles (e.g., α and α) corresponding to various impedances. For example, Table 3 shows the predefined switching angles for a 50Ω load impedance Z L Possible impedances that can be matched to Z TMNand corresponding switching angles (e.g., α1 and α2). The values ​​in Table 3 may be determined based on simulations of PSIM amplifier 2100, where FETs 2110 and 2112 are modeled to have body diodes with an on-resistance of 10 mΩ and a 0.4 V forward voltage drop. The output power listed in Table 3 includes the power delivered at the fundamental frequency and at higher frequencies when the PSIM amplifier is supplied with a 48 VDC power supply.

[0130] [Table 3]

[0131]

[0171] As will be described, the PSIM amplifier 2100 can be used with a wide range of output power, load impedance, and impedance, and maintain zero voltage switching of all FET switches over the operating frequency. For example, the exemplary PSIM amplifier 2100 delivers 58.6 W of output power at 20.86 MHz with a 48 VDC supply voltage into a 50 Ω load Z L To deliver this, the TMN2102 provides near 1:1 impedance matching (e.g., Z L =Z TMN Under this operating condition, the required effective shunt capacitances at nodes N1 and N2 are C P1 and C P2 equivalent to a capacitance, and therefore FET switches 2110 and 2112 are off for the entire cycle, and the drain voltage waveforms of FET switches 2110 and 2112 are sinusoidal.

[0132]

[0172] As another example, the exemplary PSIM amplifier 2100 may be powered by a 48 VDC supply voltage. 3.50W output power at 27.12MHz into a 50Ω load L To deliver the required power, the TMN2102 presents an impedance Z of approximately 50 Ω (as shown in Table 3). TMN Under this operating condition, the required effective shunt capacitances at nodes N1 and N2 are C P1 and CP2 capacitance, so FET switches 2110 and 2112 are turned on for a certain portion of the cycle while maintaining ZVS. L The load current I L should remain approximately sinusoidal. In this way, the PSIM amplifier 2100 can provide dynamic output power control while matching to a variable load over a range of switching frequencies.

[0133]

[0173] Referring now to FIG. 25A, a pulse width modulation (PWM) generator 2500 , a phase shift circuit 2504 including one or more phase shift elements 2504a-2504N, each phase shift element having an input and an output. The PWM shift circuit 2504 receives one or more reference signals from a reference signal source 2502 and provides one or more phase-shifted signals 2510 at its output. The PWM generator further includes a PWM waveform combiner 2506, which is configured to receive signals provided thereto from the phase shift circuit 2504 and combine such signals to provide a PWM signal at its output. Thus, the PWM generator 2500 receives one or more reference signals 2508 and generates one or more PWM signals 2508 with the ability to dynamically control the pulse width and phase relative to the reference signals 2502. Specifically, the PWM generator 2500 is configured to generate one or more PWM signals 2508 having a predetermined pulse width and phase shift relative to the reference signals 2502. The reference signal source 2502 and the PWM signal 2508 are shown here in phantom lines since they are not strictly part of the PWM generator 2500 .

[0134]

[0174] The reference signal provided by 2502 is a sinusoidal waveform (e.g., a sinusoidal wave The reference signal may be provided as any arbitrary periodic waveform, including, but not limited to, periodic voltage and current waveforms having various waveform shapes, including, but not limited to, a square wave, a cosine wave, or portions thereof (e.g., a square wave), a rectangular wave, a triangular wave, or any combination thereof. For purposes of clarity, the reference signal will sometimes be referred to below as being a voltage waveform, but those skilled in the art will understand that a current waveform may also be used in accordance with the concepts described. Additionally, any other signal derived from a current and / or voltage signal may also be used as a reference.

[0135]

[0175] In an embodiment, at least one phase shifter in the phase shifter circuit 2504 The input of the element is configured to receive at least one reference signal 2502. In other embodiments, the inputs of more than one phase shift element 2504 may be configured to receive at least one reference signal 2502. Examples of different phase shift circuit structures are discussed below with reference to Figures 26 and 27.

[0136]

[0176] As will become apparent from the following description, each part of the phase shift circuit 2504 The phase shift elements are configured to generate, at their respective outputs, a phase-shifted signal 2510 relative to the received reference signal 2502 at their respective outputs based on a respective phase shift parameter. The phase shift parameter is provided from a controller 2509, which is shown here in phantom because it is not strictly part of PWM generator 2500. Each phase shift element may include analog and / or digital circuitry configured to apply a phase shift to a signal received at its input to generate a phase-shifted signal at its output; the phase shift element may comprise, for example, either an in-phase / quadrature ("IQ") circuit, a phase-locked loop ("PLL") circuit, or any combination thereof.

[0137]

[0177] In an embodiment, the phase shift parameter is a signal having a particular phase shift. , may include a predetermined phase shift and / or a predetermined pulse width used to generate (e.g., used to generate phase shifted signal 2510). According to some embodiments, each phase shift element 2504 is configured to receive its respective predetermined phase shift parameters from controller 2509. Controller 2509 may be provided as any type of processing circuitry, including, for example, but not limited to, a digital signal processor ("DSP"), a computer, a microprocessor, a microcontroller, or any combination thereof.

[0138]

[0178] As will be described in detail below in conjunction with at least FIG. 27, some embodiments In this embodiment, the first phase shift element 2504a may be configured to receive at its input at least one reference signal 2502, while the second phase shift element 2504b may be configured to receive at its input a generated phase-shifted signal (e.g., one of the signals 2510) from another (i.e., different) phase shift element (e.g., the first phase shift element 2504a).

[0139]

[0179] In an embodiment, each phase shift element 2504a-2504N has a width of approximately 25 Each phase shift element 2504 is configured to shift the phase of a signal received at its input based on a respective phase shift parameter to generate a corresponding one of phase-shifted signals 2510a-2510N denoted by 10. In an embodiment, some phase shift elements may be configured to shift the phase of a received reference signal 2502 to generate phase-shifted signal 2510, while other phase shift elements may be configured to shift the phase of a generated phase-shifted signal 2510 received from another phase shift element 2504. For example, a phase shift element 2504 may receive a phase shift parameter including a phase shift φ. This phase shift element 2504 may then generate a phase-shifted signal 2510 at its output by shifting the phase of the signal received at its input (e.g., reference signal 2502 or a generated phase-shifted signal) according to the phase shift φ.

[0140]

[0180] The waveform combiner 2506 is configured by phase shift elements 2504A-2504N. The waveform combiner 2506 is configured to receive one or more generated phase-shifted signals 2510A-2510N. The waveform combiner 2506 is configured to combine the phase-shifted signals provided thereto (e.g., phase-shifted signal 2510) to generate a PWM signal 2508. The waveform combiner 2506 may include analog / digital circuitry configured to generate, compare, sum, combine, detect, or amplify the PWM signal 2508. Such circuitry may include, but is not limited to, edge detectors, analog or digital logic gates, operational amplifiers, comparators, or any combination thereof. In some embodiments, the waveform combiner 2506 is configured to generate one or more PWM signals 2508 according to the received phase-shifted signals 2510. While configured, in other embodiments, the waveform combiner 2506 may be configured to generate two or more PWM signals 2508 according to the received phase-shifted signals 2510 .

[0141]

[0181] Generates a PWM signal 2508 according to the received phase-shifted signal 2510 2509。PWM controller 2509。PWM signal 2508 generated has a phase shift and pulse width relative to the reference signal 2502. These phase-shifted, pulse-width adjusted signals are determined from phase shift parameters applied by phase shift element 2504 in generating phase-shifted signal 2510. In some embodiments, the phase shift parameters are determined and stored in memory or other storage (e.g., memory that may be part of controller 2509 or separate therefrom). It should be understood that in some embodiments, the phase shift parameters are determined based on the signal duty cycle and phase shift required by the particular application of the PWM generating device. These parameters may be pre-stored within controller 2509 or in a separate external controller / memory. Typically, the phase shift parameters need to be dynamically adjusted depending on the particular application, so an external system controller may be tasked with inferring / calculating these parameters based on various inputs from the system and passing them to PWM controller 2509.

[0142]

[0182] As such, those skilled in the art will appreciate that the generated PW for the reference signal 2502 It is understood that the desired phase shift and pulse width of the M signal 2508 can be achieved by selecting the necessary phase shift parameters to achieve the desired phase shift and pulse width.

[0143]

[0183] In an embodiment, the controller 2509 controls the desired frequency of the generated PWM signal 2508. 2502。 For example, the controller 2509 may be configured to determine a desired phase shift and pulse width of the generated PWM signal 2508 relative to the reference signal 2502. Based on the desired phase shift and pulse width, the controller 2509 may determine the phase shift parameters using empirical or analytical techniques. More specifically, the phase shift parameters may be determined for one or more phase shift elements 2504 based on feedback or feedforward techniques, or a combination of both, such that the phase shift elements generate a phase shifted signal 2510, which may be used to generate a PWM signal 2508 having a desired phase shift and pulse width relative to the reference signal 2502.

[0144]

[0184] Furthermore, as will be explained in more detail later in this specification, the received phase-shifted By generating PWM signals 2508 according to the reference signal 2510, the pulse width and phase of each generated PWM signal 2508 can be independently adjusted over a range of 0° to 360° with arbitrarily fine resolution that is unaffected by the operating frequency (e.g., the frequency of the reference signal 2508). The generated PWM signals 2508 can maintain phase and frequency lock to the reference signal 2502 for a wide modulation range of the reference signal frequency. In embodiments, the PWM generator 100 is suitable for generating precise and dynamically adjustable PWM waveforms for high-frequency and ultra-high-frequency applications. The PWM generator 100 is particularly valuable in applications where the reference signal 2508 is derived from some radio frequency (“RF”) input source, relative to which precise timing of the PWM signal must be maintained, such as PSIM-based tunable matching networks and PSIM amplifiers.

[0145]

[0185] Referring now to FIG. 25B, a PWM generator (e.g., as described in conjunction with FIG. 25) An exemplary PWM signal Q(θ) generated by a PWM generator (such as the PWM generator 2500 shown) The portion 2508 has a pair of pulses 2508a, 2508b, each of which has a pulse width w 2512 and is connected to the reference signal V REF 25A. The PWM signal Q(θ) 2508 may be generated as discussed above in conjunction with FIG. 25A.

[0146]

[0186] In the exemplary embodiment of FIG. 25B, the generated PWM signal Q(θ) 250 8 is the reference signal V REF 2502 (identified by reference numeral 2514). Here, the phase shift φ 2514 is determined by the phase difference between the rising edge of the PWM signal Q(θ) 2508 and the rising edge of the reference signal V REF The phase shift 2514 illustrated in FIG. 25B is defined as the phase shift between a negative and a positive transition of (θ). Note that this definition of PWM phase shift is used throughout this disclosure. The phase shift 2514 illustrated in FIG. 25B is considered a positive phase shift. Note also that the definition of phase shift is only truly unique between two sinusoidal signals at the same frequency. When describing the relationship between PWM and sinusoidal signals such as those in FIG. 25B, the definition of phase shift is arbitrary. The phase shift definition used herein is chosen solely for purposes of convenience. However, if desired, phase shift can be defined in any other way, as long as the definition uniquely describes the relationship between the two signals in FIG. 25B. In such cases, phase shift based on one definition can always be converted to phase shift based on another definition without loss of generality. The phase shift definition does not affect the circuit implementation. As discussed above, those skilled in the art will understand that the desired pulse width w 2512 and phase shift φ 2514 for the reference signal 2502 can be achieved via the selected values ​​of the phase shift parameters provided to the PWM generator 2504 necessary for the phase shift element 2504 to achieve the desired phase shift.

[0147]

[0187] Referring now to FIG. 26, a PWM generator circuit 2600 generates a reference signal 26 20. The parallel structure includes a pair of phase shift elements 2016, 2018 coupled together such that the processing of the first and second signals occurs in parallel. Such a structure is referred to herein as a "parallel structure."

[0148]

[0188] The phase shift elements 2620, 2622 are the same as those described above in conjunction with FIG. 25. In the parallel architecture, the inputs of at least two phase shift elements 2616, 2618 may be the same as or similar to the phase shift elements 2504a-2504N. In the parallel architecture, the inputs of at least two phase shift elements are configured to receive a common reference signal (here, reference signal 2602), which may be the same as or similar to reference signal 2502. Each phase shift element 2616, 2618 is configured to generate a respective phase-shifted signal at its output based on the received reference signal 2602 and a received predetermined phase shift parameter provided from control signals 2620, 2632, which may be provided from one or more controllers (such as controller 2509 described above in conjunction with FIG. 25). Phase shift elements 2616, 2618 are each configured to generate the phase-shifted signal by applying a phase shift to the received reference signal 2602 according to a respective phase shift parameter included in each of the controller signals 2620, 2622.

[0149]

[0189] According to an embodiment, each phase shift element 2616, 2618 is controlled by a control signal 262 0, 2622, respectively. The control signals 2620, 2622 may include one or more predefined phase shift parameters for each of the respective phase shift elements 2616, 2618. In an embodiment, the control signals 2620, 2622 may be generated by a processing circuit such as, but not limited to, a DSP, a computer, a microprocessor, a microcontroller, or any combination thereof.

[0150]

[0190] In the exemplary embodiment of FIG. 26, the phase shift element 2616 The phase shift element 2618 may be configured to receive a control signal 2620 including phase shift parameters including a phase shift of φ and a pulse width of w. Further, the phase shift element 2618 may be configured to receive a control signal 2622 including phase shift parameters including a phase shift of φ and a pulse width of w. At their respective outputs, they produce phase-shifted signals A, B.

[0151]

[0191] The waveform combiner 2606 combines the phase shift elements 2616 and 2618 at their outputs. 25A . Waveform combiner 2606 may be the same as or similar to waveform combiner 2506 ( FIG. 25A ). Waveform combiner 2606 generates PWM signal 2608 in response to the phase-shifted signals A and B provided thereto. PWM signal 2608 has phase shift and pulse width characteristics according to the received phase-shifted signal A generated by phase shift element 2616 and the phase-shifted signal B generated by phase shift element 2618.

[0152]

[0192] In the exemplary embodiment of FIG. 26, the phase-shifted signals A and B are 2602 and are phase-shifted according to the respective phase shift values ​​(φ and w+φ) of the phase shift elements from which they were generated. In an embodiment, the phase-shifted signals A and B may then be appropriately combined, for example by a waveform combiner 2606, to synthesize a PWM signal 2608 having a pulse width w and a phase φ that is phase-locked to the reference signal 2602. Those skilled in the art will appreciate that the amount of phase shift required by the phase shift elements 2616, 2618 to generate the desired PWM waveform 2608 will depend greatly on the actual implementation of the waveform combiner 2608.

[0153]

[0193] FIG. 26 shows a parallel structure with only two phase shift elements, but the parallel structure It should be understood that the PWM generator circuit may be implemented using three or more phase shift elements. The number of phase shift elements included in the phase shifter circuit is selected according to the needs of a particular application. Factors to consider when selecting the number of phase shift elements to include in a PWM generator include, but are not limited to, the number of rising / falling edges the PWM waveform should have in a single period. Simply put, each phase shift element controls the position of one rising or falling edge of the PWM waveform relative to the start of that period. For example, in FIG. 26, the PWM waveform has a single pulse per period, and therefore has one rising edge and one falling edge; phase shift element 2616 sets the position of the rising edge, and phase shift element 2618 sets the position of the falling edge. In more complex PWM waveforms, where more than one pulse per period may be required, more falling and rising edges are required, and more phase shift elements are needed to control all the edges. For example, in FIG. 28, Q has two pulses that repeat per single period, for a total of four edges in the period. Therefore, four phase shift elements are required to control the relative position of each of these edges.

[0154]

[0194] Another reason to have more phase shift elements than the minimum required is for system redundancy and and reliability. For example, in FIG. 26, an additional redundant phase shift element (identical to 2616) may be implemented to generate another copy of signal A. If one of the phase shift elements fails, the waveform combiner can automatically select the other copy of signal A.

[0155]

[0195] Referring now to FIG. 27, a PWM generator circuit 2700, or more simply 27, the PWM generator includes a pair of phase shift elements 2716, 2718, where a first one of the phase shift elements (here, phase shift element 2716) has an input configured to receive a reference signal 2702 and has an output coupled to both the input of the waveform combiner 2706 and the input of a second phase shift element (here, phase shift element 2718). The output of the second phase shift element is coupled to the second input of the waveform combiner 2706. Such a structure is referred to herein as a "cascade structure."

[0156]

[0196] In the cascade structure, a phase shift element 2504 (FIG. 1) may be the same as or similar to the phase shift element 2504. A first phase shift element 2716, which may be a first phase shift element, is configured to receive a reference signal 2702 at its input. The first phase shift element 2716 is configured to generate a phase-shifted signal A at its output based on the reference signal 2702 and respective predefined phase shift parameters (e.g., provided by a controller, such as the controller 2509 described above in conjunction with FIG. 25A ). For example, the phase shift element 2716 may be configured to generate the phase-shifted signal A by shifting the phase of the reference signal 2702 according to the predefined phase shift parameters.

[0157]

[0197] As discussed above with respect to FIG. 26, the phase shift element may have a predetermined phase shift 27, the phase shift element 2716 may be configured to receive a control signal 2720 that includes the phase shift parameter φ.

[0158]

[0198] The cascade structure further includes a second phase shift element 2718, Phase shift element 2718 is configured to receive at its input the phase-shifted signal A generated by phase shift element 2716. Second phase shift element 2718 is configured to generate a phase-shifted signal B at its output based on phase-shifted signal A and a respective phase shift parameter. For example, in the exemplary embodiment of FIG. 27 , phase shift element 2718 is configured to generate phase-shifted signal B by shifting the phase of phase-shifted signal B according to a predetermined phase shift parameter, here denoted as (φ+w).

[0159]

[0199] A waveform combiner, which may be the same as or similar to waveform combiner 2506 (FIG. 25A). Inverter 2706 is configured to receive the phase-shifted signals produced at the outputs of phase shift elements 2716 , 2718 and generate a PWM signal 2708 having a desired pulse width and phase shift relative to reference signal 2702 .

[0160]

[0200] In the exemplary embodiment of FIG. 27, the phase shift elements 2716, 2718 are: 27. The phase shift elements 2716, 2718 are configured to generate phase-shifted signals A and B that are phase-locked to the reference signal 2702 and that are phase-shifted relative to the reference signal 2702 by a phase shift φ and a phase shift φ+w, respectively. However, the phase shift elements 2716, 2718 in the cascade structure introduce phase shifts of only φ and w (i.e., phase shift element 2716 introduces a phase shift φ and phase shift element 2718 introduces a phase shift w), whereas in the parallel structure, the phase shift elements phase-shift the reference signal by φ and φ+w (e.g., in FIG. 26, phase shift element 2616 introduces a phase shift φ and phase shift element 2618 introduces a phase shift φ+w).

[0161]

[0201] In general, when generating the same PWM waveform, the phase shift elements in a parallel configuration are: It should be able to provide a larger phase shift and operate over a wider phase shift range compared to what is found in a cascade structure.

[0162]

[0202] On the other hand, in a cascade structure, the generated PWM waveform is generated by a parallel structure. cascaded versus parallel PWM waveforms may suffer from more jitter. The choice of which system architecture to use depends on a variety of factors, including, but not limited to, the specific application and requirements of the PWM waveforms generated, as well as the characteristics of the circuitry available to implement them. While the range of phase shift that each phase shift element can generate is an important determining factor in choosing a cascaded versus parallel architecture, the dynamic behavior and transient response of the PWM generator also depend greatly on the generator architecture.

[0163] The parallel structure allows for independent control of the dynamics with which the rising and falling edges of the PWM waveform can be adjusted, whereas in the cascade structure, the dynamics with which the pulses of the PWM waveform can be controlled is the combination of the dynamic responses of all the phase shift elements.

[0164]

[0203] A single pulse PWM waveform (i.e., a periodic reference signal) such as that shown in FIG. For generating a single PWM pulse (one PWM pulse per cycle of signal 2502), a structure with two phase shift elements is sufficient (see FIGS. 26 and 27). However, by employing more phase shift elements, even more sophisticated PWM signals can be generated, including waveforms with multiple pulses and multiple associated PWM signals (such as might be used to drive multiple switches in a multi-switch amplifier or converter).

[0165]

[0204] Referring now to FIG. 28, a PWM generator 2800 generates a double pulse PWM The waveform combiner 2806 includes at least four phase shift elements 2824-2830 configured to generate the waveform 2808, each having an output coupled to an input of the waveform combiner 2806. A first set of phase shift elements 2824, 2826 are each configured to receive the reference signal 2802 at their respective inputs. The phase shift elements 2824, 2826 are each configured to generate a phase-shifted signal at their respective outputs in accordance with the reference signal 2802 and a respective phase shift parameter. For example, in the exemplary embodiment of FIG. 28 , the phase shift element 2824 is configured to generate a phase-shifted signal at its output by shifting the phase of the reference signal 2802 in accordance with the respective phase shift parameter (φ) of the phase shift element 2824. Similarly, the phase shift element 2826 is configured to generate a phase-shifted signal at its output by shifting the phase of the reference signal 2802 in accordance with the respective phase shift parameter (φ+α+γ) of the phase shift element 2826.

[0166]

[0205] A second set of phase shift elements 2828, 2830 each have at their inputs 28, phase shift element 2828 is configured to receive at its input the phase shifted signal generated by phase shift element 2824, and phase shift element 2830 is configured to receive at its input the phase shifted signal generated by phase shift element 2826.

[0167]

[0206] The second set of phase shift elements 2828, 2830 each shifts the phase of the first set. The phase shift elements 2828 are configured to generate phase shifted signals at their respective outputs based on the phase shifted signals generated by the phase shift elements and their respective phase shift parameters. For example, in the exemplary embodiment of FIG. 28 , the phase shift element 2828 is configured to generate the phase shifted signals by further shifting the phase of the phase shifted signal generated by the phase shift element 2824 that is provided to the input of the phase shift element 2828. The phase shift element 2828 shifts the phase of the signal provided thereto by a phase of (∝).

[0168]

[0207] Similarly, the phase shift element 2830 is The phase shift element 2826 is configured to generate a phase shifted signal by shifting the phase of the phase shifted signal generated by the phase shift element 2826 according to a phase shift parameter (β).

[0169]

[0208] The waveform combiner 2806 has at its input a phase shift element 2824-2 830 outputs a phase-shifted signal and combines the signals provided therein. 28. The PWM signal 2808 is generated in accordance with the received phase-shifted signal in combination with the reference signal 2802. In an embodiment, the PWM signal 2808 is a double-pulse PWM waveform (i.e., a pair of pulses occurring within a single cycle of the reference signal waveform) having a first pulse width and phase shift relative to the reference signal 2802 and a second pulse width and phase shift relative to the reference signal 2802.

[0170]

[0209] Using two sets of phase shift elements to generate the PWM signal 2808 28, the PWM waveform 2808 includes a dynamically and independently controlled phase φ with pulse widths α and β, and an inter-pulse spacing γ, while maintaining phase and frequency lock to the reference signal 2802.

[0171]

[0210] One possible way to achieve this behavior is to change the waveform combiner in this example to The idea is to design it so that its output Q toggles whenever one of its four inputs undergoes a negative-to-positive transition. For example, if REF is θ Let Q be a logic low when it undergoes a negative-to-positive transition at =0. The level of output signal Q is the point at which the output of phase shift element 2824 toggles output signal Q to a logic high. θ 28. The output signal Q remains low until it undergoes a negative-to-positive transition at ∝ = . The output signal Q remains at a logic high level for ∝ ...

[0172]

[0211] Referring now to FIG. 29, a PWM generator 2900 is shown, which is coupled in a parallel configuration. 29. The PWM generator 2900 includes a pair of phase shift elements 2916, 2918 that are coupled to the phase shift elements 2916, 2918. The phase shift elements 2916, 2918 may be the same as or similar to the phase shift elements described above in conjunction with FIGS. 25A and 26. The PWM generator 2900 also includes a phase detector 2932 that receives a portion of the reference signal at its input. The phase detector 2932 also receives a feedback signal at its input from the output of the waveform combiner 2906. The output of the phase detector 2932 is coupled to the phase shift elements 2916, 2918.

[0173]

[0212] In an embodiment, the phase detector 2932 detects a portion of the reference signal 2902 and P The phase detector 2932 is configured to receive a portion of the WM output signal 2908 and is configured to monitor (i.e., measure, detect, calculate, or otherwise determine) the phase between the PWM signal 2908 and the reference signal 2902. The phase detector 2932 may include analog and / or digital circuitry configured to detect and compare the phase of two or more signals, and may include a DSP, microprocessor, computer, or microcontroller.

[0174]

[0213] Waveform combiner 2908 may be the same as waveform combiner 2508 (FIG. 25), or In an embodiment, there may be a significant propagation delay associated with the circuitry of the waveform combiner 2908. Such propagation delay may result in phase modulation of the output of the waveform combiner 2908 (i.e., the phase of the waveform combiner's output signal may have frequency variations that may prevent phase lock between the reference signal 2902 and the PWM waveform 2902). In an embodiment, the phase detector 2932 may be configured to compare the phase between the PWM signal 2908 and the reference signal 2902 to a phase threshold. The phase threshold corresponds to a value of the phase that indicates that the phase between the PWM signal 2908 and the reference signal 2902 has become too great. In other words, the phase threshold may include a value that indicates that the PWM signal 2908 and the reference signal 2902 are no longer in phase lock.

[0175]

[0214] In an embodiment, a phase detector 2932 detects the PWM signal 2908 and the reference 29 29. The PWM signal 2908 and the reference signal 2902 may be configured to generate one or more phase correction signals when it is determined that the PWM signal 2908 and the reference signal 2902 are no longer in phase lock. The phase correction signals may include data indicating adjustments to one or more phase shift parameters of the respective phase shift elements to place the PWM signal 2908 and the reference signal 2902 in phase lock. Thus, the phase correction signals include data to correct for propagation delays that cause the PWM signal 2908 and the reference signal 2902 to no longer be in phase lock.

[0176]

[0215] In an embodiment, each phase shift element 2916, 2918 generates a phase correction signal 29. The waveform combiner 2908 is configured to receive a phase correction signal and adjust its phase shift parameters in response to the phase correction signal. By adjusting the phase shift parameters of the phase shift elements 2916, 2918, the phase shifted signals generated by the phase shift elements 2916, 2918 are also adjusted. Because the PWM signal 2902 is generated by the waveform combiner 2908 according to the received phase shift signal, adjusting the phase shift parameters allows for correction in the PWM signal 2902 generated by the waveform combiner 2906.

[0177]

[0216] Referring now to FIG. 30, a PWM generation system 3000 generates multiple PWM 25A, 26, 27, 28, and 29. Each of the PWM generators 3036a-N is configured to receive a reference signal 3002.

[0178]

[0217] In the exemplary embodiment of FIG. 30, each PWM generator 3036a-N It includes at least two phase shift elements 3016a-N, 3018a-N, which are configured to generate one or more phase shifted signals based on the reference signal 3002 and a phase shift parameter associated with each phase shift element 3016a-N, 3018a-N.

[0179]

[0218] For example, PWM generator 3036a includes phase shift elements 3016a, 3018 a, which are configured to generate two or more phase-shifted signals based on the reference signal 3002 and phase shift parameters associated with the phase shift elements 3016 a, 3018 a. Each phase-shifted signal generated by the phase shift elements A-N 3016 a-N, 3018 a-N is provided to a respective waveform combiner 3006 a-N to generate a respective PWM signal 3008 a-N.

[0180]

[0219] In this method, multiple PWMs are frequency and phase locked to a reference signal 3002. Signals 3008 a - N may be generated, each PWM signal 3008 a - N having a respective pulse width and phase shift relative to the reference signal 3002 .

[0181]

[0220] In the embodiment, each of the phase shift elements 3016a-N, 3018a-N is a control 3002。 In an embodiment, the controller 3034 is configured to receive inputs including desired pulse widths and phase shifts relative to the reference signal 3002 for one or more desired PWM signals 3008. It should be understood that the desired PWM pulse widths / phases may also be user-supplied inputs or may be predetermined and stored in some kind of look-up table in memory.

[0182]

[0221] However, typically the desired pulse width and phase depend on the impedance level. The reference signal 3002 may be a reference signal, or some other measured voltage / current / power signal in the system, and may be determined by the controller in conjunction with some type of system feedback. In an embodiment, the controller 3034 may receive inputs, including a desired pulse width and phase shift for the reference signal 3002, from, for example, a computer, microcontroller, processor, graphic user interface, interactive device (i.e., keyboard, mouse, touch screen, etc.), or any combination thereof. Based on these desired pulse widths and phase shifts for the reference signal 3002, the controller 3034 is configured to determine the phase shift parameters for each phase shift element required to achieve the desired pulse width and phase shift, and provide them to the respective phase shift elements.

[0183]

[0222] The controller 3034 determines the phase shift parameters and maps them to the desired pulse width. By providing each phase shift element necessary to achieve the phase shift, each PWM waveform 3008A-N generated by the PWM generation system 300 can be dynamically and independently adjusted by the controller 3034. In many applications, there is a need to generate multiple PWM waveforms that are properly synchronized with respect to each other. This is particularly noticeable in many types of converters that require precise switching between two or more switches. For example, driving switches in a half-bridge requires the generation of two PWM waveforms with controllable duty cycles and separately controllable dead times for each transition. Both the phase φ and pulse width w of each PWM waveform can be dynamically and independently adjusted by the controller.

[0184]

[0223] Those skilled in the art will appreciate that the exemplary embodiment of FIG. 30 includes all N PWM generators 303 6a-N are shown based on a parallel structure (FIG. 26), it is understood that other structures may be used, such as a cascade structure, or any combination of the two. Depending on the specific requirements of the application, PWM generators having different structures and / or implementations may be connected together and fed with a common reference signal.

[0185]

[0224] Those skilled in the art will appreciate that the characteristics of a particular PWM generating structure will influence the phase shift elements and waveform combining. It should be noted that the implementation details of the PWM generator are highly dependent on the implementation details. As discussed below, PWM generation structures have phase shift element implementations based on both IQ modulators and phase-locked loops. Designs based on IQ modulators and phase-locked loops often allow for phase shift control over a wide operating frequency range while preventing phase shift modulation due to frequency variations. Those skilled in the art should note that there are other possible ways to implement phase shift elements, such as programmable / voltage-controlled delay lines and delay-locked loops.

[0186]

[0225] 31 to 35, the embodiment of the PWM generator is implemented by an IQ modulator. In an embodiment, the IQ modulator allows the RF carrier signal to be modulated according to a range of amplitude, frequency, and phase modulation operations.

[0187]

[0226] Referring now to FIG. 31, a PWM generation circuit 3100 includes a local oscillator (LO ) signal 3140. The PWM generation circuit further comprises a pair of optional amplifiers 3144, 3146. In this exemplary embodiment, the first of the amplifiers is implemented as an IQ modulator including an amplitude and phase shift circuit 3152 having a first input configured to receive an in-phase signal component I (herein referred to as I BB and identified by reference numeral 3138), and the second of the pair of amplifiers is configured to receive a quadrature-phase signal component Q (referred to herein as Q BBThe amplifiers 3144, 316 receive each of the I and Q signals provided thereto and pass the appropriately amplified signals to a pair of mixers (or multipliers) 3418, 3150. The mixers 3148, 3150 receive at their second inputs an appropriately phase- and amplitude-adjusted LO signal from an amplitude and phase shift circuit 3152. The outputs of the mixers 3148, 3150 are coupled to inputs of a summing circuit 3154, which appropriately sums the signals provided thereto to provide a phase-shifted signal 3110 (an example of which is illustrated and described in conjunction with FIG. 25B above).

[0188]

[0227] Therefore, the IQ modulator generates a signal that is the same as or similar to the reference signal 2502. The IQ modulator 3100 is configured to receive a local oscillator ("LO") 3140, which may be a 1 / 2 radian or 90° phase shifter. The IQ modulator 3100 is configured to split the LO 3140 into two quadrature signal components I3138 and Q3132. Signal component I3138 represents the in-phase component with respect to the LO 3140; in other words, components I3138 and LO 3140 have the same phase. Component Q3132 represents the quadrature component of the LO 3140, which has a phase shift relative to the LO 3140. For example, component Q3132 may have a phase shift of 90° or π / 2 radians with respect to the LO 3140.

[0189]

[0228] In an embodiment, one or more signals derived from LO 3140 have amplitudes and phase shift circuit 3152. Amplitude and phase shift circuit 3152 may include analog and / or digital circuitry configured to shift the phase and / or amplitude of LO 3140 to generate one or more signals derived from LO 3140. In an embodiment, amplitude and phase shift circuit 3152 shifts component I 3138 (I BB ), and the signal derived from LO 3140 to be applied to component Q 3132 (Q BB) to generate a signal derived from the LO 3140 to be applied to the LO 3140. In an embodiment, the amplitude and phase shift circuit 3152 is configured to generate a baseband signal to achieve a desired phase shift of the LO 3140.

[0190]

[0229] In an embodiment, component I 3138 is provided to multiplier 3148. In some embodiments, component I 3138 may be first provided to amplifier 3144 before being provided to multiplier 3148. It should be understood that amplifiers 3144, 3146 may generally be used for any input signal conditioning, buffering, or amplification / attenuation. In this exemplary embodiment, circuits 3144, 3146 are schematically illustrated as amplifiers, but it should be understood that the actual functionality of circuits 3144 / 3146 will depend greatly on the particular implementation of the IQ modulator. Furthermore, a signal derived from LO 3140, generated by amplitude and phase shift circuit 3152, is also provided to multiplier 3148. Multiplier 3148 is configured to multiply component I 3138 and the signal derived from LO 3140 and provide the product to summer 3154. Similarly, component Q 3142 is provided to multiplier 3150. In some embodiments, component Q 3142 may be provided to an amplifier 3146 before being provided to multiplier 3150. Additionally, a second signal derived from LO 3140 generated by amplitude and phase shift circuit 3152 is provided to multiplier 3150. Multiplier 3150 is configured to multiply component Q 3142 and the signal derived from LO 3140 and provide the product to summer 3154. Each multiplier 3148, 3150 comprises analog and / or digital circuitry configured to multiply two or more signals together.

[0191]

[0230] Summer 3154 is an analog circuit configured to sum two or more signals together. The adder 3154 is configured to generate the phase-shifted signal 3110 by summing the products provided by the multiplier 3148 and the multiplier 3150. In other words, the adder 3154 adds the LO 3140 and the generated baseband signal I BB and Q BB The phase shifter is configured to generate a phase shifted signal according to

[0192]

[0231] In an embodiment, the output of the IQ modulator may be expressed as:

[0193]

number

[0194]

[0232] In this equation, RF(t) is the phase-shifted signal generated by the IQ modulator. Represents the number.

[0233] For simplicity, the LO3140 uses two orthogonal cos(ωt) and - sin(ωt) signals. Any absolute phase offset in the LO 3140 results in an identical absolute phase offset in the phase-shifted signals.

[0195]

[0234] As shown in Equation 1, I BB 2 +Q BB 2 Keeping constant, Q BB vs. I BB The ratio of By adjusting the phase shift θ, the phase shift θ can be controlled between the local oscillator input and the RF output while maintaining a constant RF magnitude. In embodiments, using an IQ modulator in this manner, specifically as a phase modulator, is particularly well suited to implementing the phase shift elements required for PWM generation.

[0196]

[0235] Referring now to FIG. 32, a phasor diagram of an example I / Q modulation (i.e., A polar plot is provided. Represented in the polar plot is the Q BB 3242, and I along the X axis BB 3238, and the phase shifted signal 3210 produced by the I / Q modulator is represented as a phasor between the two. BB 3238 essentially controls the real component of the phase-shifted signal phasor, while Q BB sets its imaginary component. Therefore, those skilled in the art can BB and Q BB It is to be understood that by appropriately controlling , both the amplitude and phase of the phase shifted signal 3210 can be independently modulated. In an embodiment, frequency modulation is also possible by appropriately modulating the phase of the output.

[0197]

[0236] As can be seen from Figure 32, I BB 2 +Q BB 2 Keeping constant, Q BB vs. I BB By adjusting the ratio of , the phase shift θ can be controlled between the LO 3240 input and the phase shifted signal output 3110 while maintaining a constant magnitude of the phase shifted signal. Using an IQ modulator in this manner, strictly as a phase modulator, is particularly well suited to implementing the phase shift elements required for PWM generation.

[0198]

[0237] The phase of the PWM waveform is determined by the frequency at a fixed set of baseband inputs I and Q. Note that while the frequency may vary, the pulse width 11' (electrical magnitude) remains constant and is not affected by the frequency modulation. This is primarily due to the symmetrical structure and balanced path delays of the structure of Figure 33 (referred to herein as a parallel structure).

[0199]

[0238] The bandpass filters of the two IQ modulators in Figure 33 have identical frequency-phase responses. It should also be understood that, if the PWM waveform has a common mode phase shift, then frequency variations will cause the same phase offset in both IQ1 and IQ2. However, the pulse width of the PWM waveform is equal to the differential phase of the two logic gate inputs relative to the REF signal. Therefore, if the propagation delays from IQ1 and IQ2 to the output Q are also matched, frequency modulation will only cause a common-mode phase shift to the logic gate inputs and therefore will not affect the pulse width w. This is one reason for using comparators with matched propagation delays in a common package for the waveform combiner implementation (i.e., the comparators are implemented in the same integrated circuit package, and therefore they will experience similar manufacturing process variables and other factors that result in nearly matched propagation delays). and temperature).

[0200]

[0239] Those skilled in the art will appreciate that for constant baseband inputs I and Q, a PWM waveform with a frequency It will be appreciated that if modulation of the waveform phase φ is undesirable in a particular application, several approaches can be pursued to alleviate this problem. For example, I and Q can be tuned in response to frequency variations to correct for any phase error in φ. However, this approach requires accurate measurement of the frequency-phase response of the IQ modulator and the propagation delay associated with the waveform combiner circuit. Furthermore, the controller that combines the I and Q signals must keep track of the operating frequency, which can be undesirable and cumbersome in some applications.

[0201]

[0240] To achieve precise phase control of the phase shift element, a look-up table is used. , implemented in a controller the same as or similar to controller 3034, which maps a set of baseband I and Q values ​​to a phase shift between the IQ outputs of the phase shift element and its reference signal.

[0202]

[0241] In an exemplary embodiment, the I and Q values ​​are synthesized by a 12-bit OAC. Therefore, they can only take on one of 4096 discrete values. To create the lookup table, one of the baseband inputs is swept across its entire digital range while the other is swept across its entire digital range, as shown by (I). 2 +Q 2 The phase shift between REF and IQ is measured for each of the 4096 pairs of baseband inputs and stored in a look-up table. This control technique compensates for any nonlinearities in the DAC transfer function, mismatches in the gain of the IQ modulator baseband channels, and the insertion phase of the output bandpass filter at the particular operating frequency.

[0203]

[0242] Referring now to FIG. 33, a PWM generator 3300 is shown. The PWM waveforms are synchronized to a reference signal that is fed to both IQ modulators and serves as their local oscillator inputs. A pair of DACs controlled by a microcontroller can be used to synthesize appropriate values ​​for the I and Q signals for each IQ modulator, thus controlling the phase shift of their outputs, IQ1 and IQ2, relative to the REF signal.

[0204]

[0243] In the exemplary embodiment of FIG. 33, the PWM generator 3300 performs a pair of comparisons. 33 includes a waveform combiner 3306 implemented by a single logic gate, shown here as an AND gate. It should be understood that in the example implementation shown in FIG. 33, the logical AND gate has one inverting input. The gate is shown this way only to simplify circuit complexity. However, in reality, the circuit could be implemented by an AND gate with two non-inverting inputs, along with a NOT gate at one of its inputs.

[0205]

[0244] Another way to implement the same circuit function is to use the + / - connections of comparator 3368 (and The solution is to invert (i.e., flip) the outputs of the two comparators (which negate the outputs of the comparators) and feed the outputs of the two comparators into an AND gate with two non-inverting inputs. In fact, the latter is the actual circuit implementation used to build the prototype of the present invention. The output Q of waveform combiner 3306 is asserted (logic high) only while signal IQ1 is positive and signal IQ2 is negative. Therefore, to generate a PWM waveform with pulse width w and phase φ, the IQ modulator outputs IQI and IQ2 must be phase shifted relative to the REF signal by φ and φ+w, respectively.

[0206]

[0245] The resolution with which w and φ can be controlled is determined by the DACs used to control the I and Q inputs of the two IQ modulators. It should be understood that the resolution at which IQ1 and IQ2 can be synthesized depends on the resolution at which IQ1 and IQ2 can be synthesized. Note that the implementation of the waveform combiner in Figure 33 limits the pulse width of the output PWM waveform to a maximum of 1800, which corresponds to IQ1 and IQ2 being 1800 out of phase. However, as will be explained below, this limitation can be relaxed with different implementations of the waveform combiner.

[0207]

[0246] In one embodiment, an IQ modulator-based implementation of a single phase shift element This embodiment utilizes the LTC5598 (Analog Devices, Inc.) chip, which provides an integrated implementation of an IQ modulator with differential baseband I and Q inputs and a differential LO input. The differential voltage at the I and Q inputs is converted to a current, which drives a double-balanced mixer. The outputs of these mixers are summed and applied to a buffer, which converts the differential mixer signal to a 50n single-ended, buffered RF output. The LTC5598 supports a baseband bandwidth of over 400 MHz, enabling ultrafast adjustment of PWM waveforms, while also allowing operation over a local oscillator frequency range of 5 MHz to 1600 MHz. The I and Q inputs are combined by a pair of 12-bit DACs (AD5624, Analog Devices, Inc.), and their single-ended outputs are buffered and converted to differential signals by a pair of fully differential operational amplifiers (LTC6362, Linear Technology Corporation). The DACs are controlled by a microcontroller through a standard SPI serial interface. A passive impedance matching network and I:1 balun (TC II TG2+, Mini-Circuits) transforms the differential LO input of the IQ modulator to a single-ended 50n reference input REF.

[0208]

[0247] Referring now to Figure 34, a plot of phase shift command versus measured phase shift error is shown. The graph illustrates good agreement between the commanded phase shift and the phase shift achieved in response to such commanded phase shift. In some embodiments, to control the phase shift produced by an IQ-modulator-based phase shift element, appropriate I and Q inputs must be provided to the IQ modulator. One way to determine these inputs is through the use of a lookup table. A predetermined lookup table stored in the controller's memory lists the I and Q signal values ​​required to produce a particular commanded phase shift. This lookup table can be pre-calculated or empirically measured. As FIG. 34 shows, this lookup table approach can be used to control the phase of the phase shift element output (e.g., the phase shift signals IQ1 and IQ2 in the circuit of FIG. 33 can be controlled to within 0.5° over the entire 360° range of commanded phase shift). If desired, control precision can be further improved by synthesizing the I and Q inputs using a DAC with a larger number of bits.

[0209]

[0248] Referring now to FIG. 35, phase shift command vs. measured phase shift standard deviation The plot of the difference (STD) illustrates the standard deviation of the measured phase error achieved in the prototype circuit. The standard deviation of the measured phase error in Figure 35 can be considered an indirect measure of jitter at the output of the prototype IQ modulator-based phase shift element. Figure 35 shows the robustness of the phase error measurement in Figure 34 taken for a given commanded phase shift over the entire range of -180° to 180°.

[0210]

[0249] FIG. 35 serves as an important metric that validates the phase error measurement of FIG.

[0250] As described above, the standard deviation of the measured phase error in FIG. 35 is This can be thought of as a measure of jitter in the output of the child, which is primarily due to jitter in the reference signal and the oscilloscope acquisition system on which the phase measurement was made. Figure 35 therefore serves to validate the measurement of the phase error in Figure 34. Figure 35 essentially demonstrates that the measured phase error shown in Figure 34 is accurate to within approximately ±0.1°. In other words, Figure 34 shows the measured phase error, and Figure 35 shows how certain the measurement is (known as the standard deviation).

[0211]

[0251] Next, we will explain how to implement phase shift elements for PWM waveform generation. Further described is a design example of a cascaded PWM generation structure having multiple phase-shift elements with a PLL.

[0212]

[0252] In general, PLL-based techniques for generating variable duty cycle waveforms are , allowing dynamic control of both angular pulse width and phase φ (relative to a reference signal) independent of frequency, i.e., frequency modulation has no effect on w or φ. Angular pulse width here refers to the width of a pulse in a PWM waveform expressed in degrees out of a 360° cycle (one full period).

[0213]

[0253] For example, a PWM waveform with a period of 100 ns and a pulse width of 25 ns is 9 It has an angular pulse width of 0° (one-quarter of a single period). Using this concept of angular pulse width, we can describe the width of a pulse in relation to its period without having to specify its frequency. This is somewhat similar to the concept of using a 0-100% duty cycle to describe a PWM waveform.

[0214]

[0254] Referring now to Figure 36, it is possible to generate a variable duty cycle waveform. The circuit 3600 includes a phase shift circuit 3604 comprising a pair of phase shift elements 3604a, 3604b. The phase shift elements 3604a, 3604b each comprise a PLL 3616, 3618, a first of the PLLs 3616 having an input 3616a configured to receive the reference signal 3602. The PLL 3616 provides a phase-shifted signal A at its output 3616b. The PLL output 3616b is coupled to a first input of the waveform combiner 3606 via a signal path. A portion of the PLL output signal A is also coupled to both an input 3618a of a second PLL 3618 as well as to a feedback input 3616c of the PLL 3616 via a time delay circuit 3674. The first and second phase shift elements 3604a, 3604b are thus coupled such that the phase-shifted output signal produced by the first phase shift element 3604a serves as a reference signal (i.e., input signal) for the second phase shift element 3604b, and the phase shift elements 3604a, 3604b are thus said to be coupled in a so-called "cascade" configuration.

[0215]

[0255] A time delay element 3674 is provided in the feedback path of the PLL 3616. The time delay τ is selected to match the propagation delay through waveform combiner circuit 3603 from input 3606a (i.e., signal A input in FIG. 36) to output 3606c (i.e., signal Q output in FIG. 36). Such delays may possibly include switch gate driver delays as well as any other delays. As will be explained in more detail below, time delay element 3674 provides a time delay τ that is selected to substantially reduce (and ideally eliminate) the dependence of phase shift φ on frequency modulation.

[0216]

[0256] PLL 3618 responds to a signal provided to its input 3618a by adjusting its output The PLL 3618 provides a phase-shifted signal B at output 3618b. Output 3618b of the PLL 3618 is coupled via a signal path to a second input of the waveform combiner 3606. A portion of the PLL output signal B is also coupled to a feedback input 3618c of the PLL 3618.

[0217]

[0257] The waveform combiner 3606 has inputs 3606a, 3606b provided thereto. The waveform combiner 3606 combines the signals provided thereto to provide a PWM signal 3608 having a desired waveform at output 3606c. 36. The PWM signal 3608 may be generated using any of the techniques described above, or any other suitable technique.

[0218]

[0258] Each PLL module 3616, 3618 has a feedback input At their respective outputs 3616b, 3618b, they generate respective output signals A, B such that the fed back signals are frequency locked to the input signals provided at their respective inputs 3616a, 3618a and phase shifted a certain amount relative thereto (i.e., phase shifted relative to the respective input signals). The PLL modules 3616, 3618 thus allow direct control of the phase shift between the input and feedback signals.

[0219]

[0259] This phase shift can be digitally controlled (e.g., by a microcontroller (μ C) 3662 or by some other control source) and with arbitrary resolution from -180° to +180°. The resolution may depend, for example, on the implementation of the PLL. Depending on the implementation of a PLL-based phase shift element, the phase shift it provides is typically controlled using an analog current or voltage signal. The resolution at which this analog signal can be synthesized ultimately determines the resolution at which the phase shift can be controlled. Often, the analog control signal is synthesized by a digital-to-analog converter (DAC). The DAC itself may be part of the microcontroller or may be part of the design of the PLL phase shift element.

[0220]

[0260] In the former case, the microcontroller directly synthesizes the analog control signal and In this case, the resolution of the microcontroller in fact determines the resolution with which the phase shift can be controlled.

[0221]

[0261] However, in the latter case, the microcontroller must use a PLL phase shift element. The DAC that is part of the PLL can be digitally controlled, in which case the PLL implementation determines the resolution to which the phase shift can be controlled.

[0222]

[0262] Thus, FIG. 36 shows a phase-locked loop module coupled to a waveform combiner. 1 is an example of a cascaded PWM waveform generator with phase-shift elements implemented using logic gates. In embodiments, the waveform combiner may be implemented using one or more logic gates, such as a single AND gate. Such an approach allows for the generation of PWM waveforms with dynamically adjustable duty cycles and phases φ. Note that with a waveform combiner implemented from a single logic gate, the angular pulse width w of the PWM waveform may be limited to a maximum of 180°.

[0223]

[0263] Considering circuit 3600 of FIG. 36, in the feedback path of PLL 3616 If the time delay element τ of is zero and PLL 3616 (PLL1) is commanded to provide a phase shift of φ between its input and the feedback signal, this causes output signal A (i.e., the output of PLL 3616) to be frequency locked to the reference input REF and phase shifted by φ relative to it (assuming τ=0). In this example, a phase shift of φ between reference signal REF and output signal A implies that the rising edge of the output signal pulse lags the negative-to-positive transition in the reference signal by a phase of φ.

[0224]

[0264] Similarly, PLL3618 (PLL2) is a clock that is a function of its input and feedback signal. Suppose PLL1 is commanded to provide a phase shift of w between them. The output of PLL1 serves as the input to PLL2, so that signal B has a phase shift of w relative to signal A and therefore lags the reference signal REF by a phase shift of φ+w.

[0225]

[0265] In one embodiment, signals A and B are combined with a logical AND gate. This may result in an output signal Q having an angular pulse width w and a phase shift φ between its rising edge and the negative-to-positive transition of the REF signal. Note that in this scenario, signal B is first inverted before being logically combined with signal A (i.e., via an AND logic gate). Note also that due to the propagation delay of the waveform combiner circuit, any frequency modulation of the REF signal will cause a corresponding change in the phase shift φ of the PWM waveform. This dependence of PWM waveform phase on frequency can be substantially reduced (ideally eliminated) by tuning the time delay τ in the feedback path of PLL1 to match the propagation delay of the waveform combiner logic gate (e.g., an AND gate).

[0226]

[0266] To make this more clear, PLL1 in Figure 36 has its input and feedback Suppose PLL 3616 is commanded to provide a phase shift φ between the reference signal REF and the PLL 3616. A time delay τ in the feedback path of PLL 3616 causes output signal A to lead the signal at feedback input 3616c (also shown as FB in FIG. 36) by time τ. If the time delay τ matches the propagation delay of the waveform combiner, signal Q will be in phase with the signal at feedback input 3616c (FB); therefore, output signal Q will lag reference signal REF by a phase φ corresponding to the commanded phase shift. Thus, the phase of the PWM waveform is set by the commanded phase shift of PLL 3616 and is not affected by frequency variations.

[0227]

[0267] This method compensates for the feedback loop while ensuring PLL stability. Note that the amount of propagation delay that can be compensated for depends on the phase margin and bandwidth of the PLL feedback loop. PLL designs with high loop bandwidth can only tolerate a small amount of loop delay and therefore require the use of logic circuits in the waveform combiner that have sufficient operating speed to support such operation. On the other hand, being able to fully compensate for the propagation delay of a waveform combiner with a large propagation delay (as may be the case when using transistor gate drivers as logic gates) requires the design of a PLL with a slow loop bandwidth, thus limiting the speed at which the phase of the PWM waveform can be adjusted.

[0228]

[0268] A single logic gate (e.g., having an inverting input coupled to PLL output 3618b) While a waveform combiner comprising only a single AND logic gate (signal A and signal B) is relatively simple to implement, it only allows for the generation of PWM waveforms with a maximum angular pulse width of 180 degrees (50% duty cycle), corresponding to signals A and B being 180 degrees out of phase. Furthermore, this is only possible if signals A and B both have a 50% duty cycle. However, many applications require the ability to control the duty cycle of PWM waveforms over a wider range. Therefore, an alternative implementation of a waveform combiner that alleviates the above limitations is described below in conjunction with FIG. 37.

[0229]

[0269] In overall view, FIG. 37 shows an edge detector coupled to a D-type flip-flop. 37. The waveform combiner circuit shown in FIG. 37 is a cascaded phase-locked PWM generator 3700 with a waveform combiner provided from a PLL. This approach allows dynamic adjustment of the PWM phase φ and angular pulse width w over a 360° range. As discussed above, the time delay element τ included in the feedback path of the first PLL receiving the reference signal is selected to substantially match the propagation delay through the waveform combiner circuit from input A to output Q, thus eliminating the dependence of φ on frequency modulation.

[0230]

[0270] Referring now to FIG. 37, an exemplary circuit for PWM waveform generation is shown in FIG. The phase shifter 3704 includes a pair of phase shift elements 3704, 3704 coupled to a combiner 3706. The shift elements 3704, 3704 may be the same as or similar to the phase shift elements 3604a, 3604b described above in conjunction with FIG. 36. In this exemplary embodiment, the waveform combiner 3706 includes a pair of edge detectors 3778, 3780, each of which receives an input from a respective one of the phase shift elements 3704, 3704. The edge detectors 3778, 3780 are here implemented by logic gates (illustrated here as AND logic gates having an inverter coupled to one input thereof). Those skilled in the art will, of course, understand that the edge detectors may be implemented using any type of circuit. Those skilled in the art will further understand that any type of circuit capable of detecting signal edges (e.g., rising and / or falling edges of a signal) may also be used.

[0231]

[0271] The output of the first of the edge detectors, here edge detector 3778, is The output of a second one of the edge detectors, here edge detector 3780, is coupled to a clock input, CLK, of a D-type flip-flop 3782. The output of a second one of the edge detectors, here edge detector 3780, is coupled to a reset input, RESET, of D-type flip-flop 3782. The D input of flip-flop 3782 is coupled to a reference signal (here a logic signal having a value of logic 1).

[0232]

[0272] This D-type flip-flop configuration alleviates the above limitations of the circuit of FIG. The D input of the flip-flop is coupled to a signal having a logic high signal level, so that a rising edge at the CLK input sets output signal Q high (i.e., a logic high signal level), while a rising edge at the RES input clears Q (i.e., sets output signal Q to a logic low signal level). Edge detectors 3778, 3780 at the inputs of the combiner generate a pulse to drive the flip-flop when a rising edge occurs in signal A or B.

[0233]

[0273] Of course, depending on the implementation of the flip-flop, an edge detector may need to be used. It should also be understood that this may not be required.

[0274] For a flip-flop with an asynchronous reset input, the output signal Q is is a logic high independent of the CLK input, it forces a logic low signal level. In such cases, it is important to use an edge detector to prevent the flip-flop from "skip" the rising edge of signal A while signal B is a logic high. When using an edge detector, the maximum PWM pulse width that can be obtained is approximately equal to the time period of the REF signal minus the pulse width of the edge detector output. It should therefore be appreciated that waveform combiner 3706 allows control of the angular pulse width and phase of the PWM waveform over a nearly 360° range.

[0234]

[0275] In some applications, it is possible to generate multiple related "single pulse" PWM waveforms. In some cases, it may be desirable or necessary to generate a PWM waveform with a wide variety of pulse widths and inter-pulse spacing. In general, a PWM waveform may contain multiple pulses within a single period, with varying pulse widths and inter-pulse spacing. In such a "multi-pulse" PWM waveform, the pulse pattern repeats every cycle at the PWM waveform frequency. For example, in FIG. 28, each 360° cycle of the generated PWM waveform has two pulses with widths α and β.

[0235]

[0276] A PWM waveform that contains only a single pulse per 360° cycle (one complete period) is These are referred to herein as "single-pulse PWM waveforms." Circuits and systems capable of generating multiple such single-pulse PWM waveforms may be used, for example, to drive complementary switches in a half-bridge with controllable duty cycles and separately controllable dead times between the switches. In other applications, it may be desirable or necessary to provide controllable time overlap, or three or more related single-pulse waveforms, rather than controllable dead times. FIG. 38 illustrates multiple PWM waveforms that are phase and frequency locked to a common reference signal REF. Here we present an example design of a PWM generation system capable of generating several PWM waveforms, here two.

[0236]

[0277] Referring now to FIG. 38, a PWM generation system 3800 generates a reference signal. The reference signal is provided to the input of each of a plurality of PLL-based PWM generators 3836a-3836N, which may be the same as or similar to the PWM generator 3700 described above in conjunction with FIG.

[0237]

[0278] The PWM generator 3836a is a representative of the PWM generators 3836a to 3836N. The PWM generator then includes a pair of PLLs 3816a, 3816b coupled in a cascade configuration. As explained above, in the cascade configuration, a first of the PLLs 3816a receives a reference signal from a reference signal source 3802 at its input, and the output of the PLL 3816a is coupled to the input of a second, different PLL 3818a, such that the phase-shifted output signal from the PLL 3816a serves as the reference signal (i.e., the input signal) for the PLL 3818a. As explained above, the output of the PLL 3816a is coupled to the feedback input of the PLL 3816a through a time delay circuit 3874a. The phase-shifted signals generated by the PLLs 3816a, 3818a are provided to the input of a waveform combiner to generate the PWM output signal Q at the output 3808a of the PWM generator 3836a.

[0238]

[0279] The PMW generation system 3800 further includes a controller 3834. 4 provides phase shift parameter values ​​to the phase shift elements in each of the PWM generators 3836a through 3836N. Specifically, the controller 3834 provides phase shift parameter values ​​3812a through 3812N to the PLLs 3816a through 3816N, 3838a through 3838N, respectively.

[0239]

[0280] Therefore, the system 3800 can be configured to use PLL-based With two PWM generators 3836, the system can independently control the phase shifts φ1, φ2 and pulse widths w1, w2 of the two PWM waveforms Q1 and Q2, respectively.

[0240]

[0281] The circuit of FIG. 38, for example, has a controllable duty cycle and dead time. The PWM generators 3836 may be used to generate drive signals for two complementary switches in a half-bridge circuit. In an embodiment having two PWM generators 3836 and in which the reference signal frequency can vary over a range of 5 MHz to 20 MHz, PWM waveforms Q1 and Q2 may be provided with approximately a 25% duty cycle and a 25% symmetrical dead time, i.e., the dead time at each transition is about 25% of the PWM period. The rising edges of Q1 and Q2 may be 180° apart and aligned with the maximum and minimum values ​​of the reference signal, respectively. In such an embodiment, the PWM duty cycle, dead time, and phase shift are unaffected as the frequency varies over the entire 5 MHz to 20 MHz range.

[0241]

[0282] Referring now to FIG. 39, an exemplary PWM generation system 3900 includes a first 39. The PLL 3916 includes first and second phase shift elements 3904a, 3904b coupled such that the phase-shifted output signal produced by the first PLL 3916 serves as a reference signal (input) for a second PLL 3918. The PLLs 3916, 3918 are thus coupled in a so-called cascade configuration, as described above in conjunction with FIG.

[0242]

[0283] However, in contrast to the cascade configuration described above in conjunction with FIG. In the exemplary embodiment of 39, the frequency provided to the FB input 3916c of the PLL 3916 is The feedback signal is taken directly from the output of waveform combiner 3906 (ie, a portion of output signal Q is provided to feedback input 3916c of PLL 3916).

[0243]

[0284] The system controller 3934 controls the phase shift parameters of the phase shift element 390 39. The phase shift parameters include at least one or more phase shift values. In the example of Figure 39, the system controller 3934 provides a phase shift value of φ to phase shift element 3904a and a phase shift value of w to phase shift element 3904b.

[0244]

[0285] By providing a predetermined phase shift value of φ to phase shift element 3904a, This causes PLL 3916 to adjust the phase of its output signal (i.e., signal A in FIG. 39) until the phase shift between reference signal REF and the feedback signal provided to the FB input of PLL 3916 is a phase of φ. As explained above, phase shift elements 3916, 3918 are coupled in a so-called cascade configuration, which results in phase shift element 3904b generating phase-shifted signal B having a phase shift of φ+w. The phase-shifted signals generated by phase shift elements 3904a, 3904b are combined in waveform combiner 3906 to generate PWM signal 3908 (i.e., output signal Q) having a phase shift φ and pulse width w. Thus, the phase of the PWM waveform relative to reference signal REF can be directly controlled as the frequency varies, without having to compensate for propagation time delays in the waveform combiner circuitry.

[0245]

[0286] Referring now to FIG. 40, the desired pulse width and phase shift relative to the reference signal The flow diagram of a process for generating a PWM signal having a reference signal begins at processing block 4002, where a PWM generator receives a reference signal. Such a PWM generator may be the same as or similar to any of the PWM generators described herein and is configured to receive at least one reference signal. The reference signal may be the same as or similar to the reference signals described herein (including, but not limited to, reference signal 2502 described above in conjunction with FIG. 25B). In an embodiment, the PWM generator may include at least one phase shift element, which may be the same as or similar to phase shift element 2504. The phase shift elements of the PWM generator may have either a parallel structure, a cascade structure, or both, as discussed above with respect to FIGS. 26 and 27.

[0246]

[0287] The process then proceeds to determine whether at least one phase shift element of the PWM generator is at its output. The process then proceeds to processing block 4004, which generates a phase-shifted signal. Such a phase-shifted signal may be the same as or similar to phase-shifted signal 2508 described in conjunction with FIG. 25B. The phase shift of the phase-shifted signal may be based on the reference signal provided in processing block 4002 and respective predefined phase-shift parameters. The phase-shift parameters may include a predefined phase shift and / or a predefined pulse width used to generate the phase-shifted signal. For example, the predefined phase-shift parameters may include a desired phase shift that each phase-shift element applies to the reference signal to generate the phase-shifted signal. In an embodiment, some phase-shift elements may be configured to generate the phase-shifted signal by phase-shifting the reference signal according to the predefined phase-shift parameters, while other phase-shift elements may be configured to generate the phase-shifted signal by phase-shifting a phase-shifted signal generated by another phase-shift element.

[0247]

[0288] In an embodiment, the predetermined phase shift parameters are determined by the constraints described herein. The PWM signal may be generated by a controller, which may be the same as or similar to any of the PWM generators. The controller may be configured to generate predetermined phase shift parameters for the PWM signal generated by the PWM generator based on a desired pulse width and phase relative to a reference signal. In an embodiment, the controller is configured to provide the generated predefined phase shift parameters to each phase shift element.

[0248]

[0289] The process then continues with the phase shifted signals generated in process block 4004. The phase-shifted signals generated in processing block 4004 proceed to processing block 4006 where they are combined to generate one or more PWM signals. The phase-shifted signals generated in processing block 4004 may be combined using a variety of techniques, including any of the techniques described herein. For example, the phase-shifted signals may be combined by providing the phase-shifted signals to a waveform combiner, which may be the same as or similar to any of the waveform combiners described herein. For example, the waveform combiner may operate to compare, sum, detect, divide (or any combination thereof) the received shifted signals to generate the PWM signal. In an embodiment, the generated PWM signal has a desired pulse width and phase shift relative to the reference signal based on the predetermined phase shift parameters of the phase-shift elements.

[0249]

[0290] Referring now to FIG. 41A, the first and second ports 4127, 4129 The exemplary power generation and delivery system 4100 includes a phase switched and tunable impedance matching network 4188 (PSIM TMN) having an input coupled to port 4127 and an output coupled to port 4129.

[0250]

[0291] The means for monitoring the impedance at port 4127 is and the PSIM TMN input 4188a, and a means for monitoring impedance 4196 is coupled between the PSIM TMN output 4188b and port 4129. The means for monitoring impedance 4194, 4196 may measure, detect, calculate, or otherwise determine the impedance at one or both of the ports 4127, 4129. The use of such means allows the impedance to be determined dynamically.

[0251]

[0292] The PSIM TMN4188 is a single or multiple phase switched impedance The PWM generator 4136 includes a phase-switched integrated (PSIM) element, where N PSIM elements 4190a-N are shown. In an embodiment, the PSIM elements 4190a-N may be the same as or similar to the phase-switched elements described herein (e.g., the phase-switched reactance element 116 discussed above with reference to FIG. 1). Each PSIM element 4190a-N is coupled to a PWM generation circuit 4136 that includes at least one PWM generator. In an embodiment, the PWM generator in the PWM generation circuit 4136 may be the same as or similar to the PWM generator described herein.

[0252]

[0293] The PSIM elements 4190a-N are provided by the PWM generation circuit 4136 The PSIM TMN4088 is configured to respond to a PWM signal. Specifically, in response to a PWM signal generated by the PWM generation circuit 4136, the PSIM TMN4088 adjusts the impedance present at (i.e., towards) either or both of the first and second ports 4127, 4129.

[0253]

[0294] In an embodiment, signals provided to and from the PSIM TMN4188 A portion of the provided signal is coupled to a PWM generator 4136. It should be understood that the input / output signals of the TMN in Figure 41A can be used as reference signals for the PWM generator to properly synchronize the switching of the PSIM elements to the currents / voltages in the TMN network. As shown by Figure 41A, an external SYNC signal can also be used as a reference for the PWM generator.

[0254] Each PWM generator 4136 generates at least one reference signal and at least one control signal. 41A, M reference signals are shown, denoted as SYNC1-M (M≦N), where N refers to the number of PSIM elements.

[0255]

[0295] Of course, in general, a PWM generator takes an arbitrary number M of SYNC signals. It should be understood that the constraint M≦N may be incorporated and that the constraint M≦N is not actually required (i.e., in some embodiments, M>N may be desirable or even necessary). For example, a PWM generator may incorporate more SYNC signals than there are PSIM elements, and dynamically switch which SYNC signal to use for which PSIM element based on internal control or some command from a system controller.

[0256]

[0296] The PWM generator circuit 4136 generates a reference signal in response to a signal provided thereto. The controller 4184 may include one or more phase shift elements configured to generate phase-shifted signals (based, at least in part, on phase shift parameters provided by the controller 4184), and one or more waveform combiners configured to generate at least one PWM signal based on the generated phase-shifted signals.

[0257]

[0297] In an embodiment, the PSIM TMN4188 includes a PWM signal generator 413 6 relative to a reference signal. In other words, the impedance presented at port 1 and / or port 2 is determined based on the pulse width and phase shift (relative to a reference signal) of the PWM signal generated by PWM signal generator circuit 4136.

[0258]

[0298] The desired impedance values ​​presented at port 1 and / or port 2 are: This can be achieved by appropriately selecting the pulse width and phase shift values ​​of the PWM signal provided to the PSIM TMN. After reading the description provided herein, one skilled in the art will further understand that the desired value of impedance presented at port 1 and / or port 2 can be achieved by selecting appropriate phase shift parameters provided to the phase shift elements of the PWM generators included in PWM generation circuitry 4136.

[0259]

[0299] In an embodiment, the predefined phase shift parameters are set by the system controller 4184 to the phase shift elements of the PWM generator. The system controller 4184 may include a DSP, a processor, a microprocessor, a computer, a microcontroller, or any combination thereof, to name a few. In some embodiments, the system controller 4184 is configured to generate the predefined phase shift parameters based on desired values ​​of pulse width and phase shift of the PWM signal generated by the PWM generator 4136 relative to a reference signal. In other embodiments, the system controller 4184 is configured to generate the predefined phase shift parameters based on desired values ​​of impedance presented at port 1 and / or port 2.

[0260]

[0300] In some embodiments, the means for monitoring impedance 414 9, 4196 may be provided as one or more current and / or voltage (IV) probes, with at least one IV probe coupled to port 1 and at least one IV probe A lobe is coupled to port 2. Each IV probe is configured to monitor (e.g., measure, detect, calculate, or otherwise determine) the load impedance and / or impedance load of ports 1 and 2 and provide a signal representative of the monitored load impedance and / or impedance load to system controller 4184.

[0261]

[0301] In an embodiment, the system controller 4184 may be configured to 1 and 2. The system controller 4184 is configured to adjust the generated predefined phase shift parameters provided to the phase shift elements 4190a-4190N to adjust the impedance values ​​at port 1 and / or port 2 to desired values. Accordingly, the system controller 4184 can control the PWM generator and the PSIM TMN 4188 based on the monitored load impedance and / or the impedance load monitored (e.g., measured, detected, or otherwise determined) at port 1 and / or port 2.

[0262]

[0302] Referring now to FIG. 41B, an exemplary RF power generation and delivery system 41 4188 includes a system controller having a first output coupled to the RF input of an inverter 4186 and a second output coupled to the input of a PWM generator circuit 4136. The PWM generator circuit 4136 includes one or more PWM generators, each of which may be the same as or similar to any of the PWM generators described herein. The output of the RF inverter 4186 is coupled to the input of a PSIM TMN 4188. The output of the PSIM TMN 4188 is coupled to a load 4192.

[0263]

[0303] The PSIM TMN 4188 includes a plurality of PSIM elements 4190a to 4190N. The PSIM elements 4190a-N are coupled to at least one PWM generator of the PWM generation circuit 4136. The PWM generator in the PWM generation circuit 4136 is configured to generate a PWM signal having a pulse width and phase shift relative to a reference signal. The PWM generator in Figure 41B can take a reference signal from the control system, from the input / output of the TMN, any internal current / voltage signal from the TMN, or any other externally provided SYNC signal (as indicated by the dashed line) similar to Figure 41A.

[0264]

[0304] The specific width and phase shift provided by the PWM generator is determined by the system control The phase shift parameters provided by the control system are based on the phase shift parameters provided by the reference signal 4184. Some of the phase shift parameters provided by the control system are responsible for controlling the phase of the generated PWM waveform relative to the reference signal, while other phase shift parameters control the pulse width of the PWM waveform.

[0265]

[0305] Generally, the phase shift parameters that control the PWM pulse width are dynamically adjusted. must be determined, often through some kind of feedback (e.g., TMN input / load impedance measurements, reflected power at the TMN ports, etc.) These can also be controlled / overridden directly by the user.

[0266]

[0306] The phase shift parameters that control the phase of the PWM waveform are typically dynamically adjusted. The phase shift parameters do not need to be preset but may be pre-stored in a look-up table that may be obtained by system calibration. In general, however, these phase shift parameters may also be determined based on feedback (e.g., voltage and current waveforms within the TMN, power dissipation within the PSIM device, etc.) and may be dynamically adjusted by a control system (or overridden by a user) to meet system requirements. In response to signals provided to and / or from the PWM generation circuitry, the PSIM TMN4188 adjusts the impedance presented at its input and output.

[0267]

[0307] Therefore, an RF inverter is coupled to the input of the 4188 and the load is the PSIM In response to the PWM signal generated by the PWM generator 4136 while coupled to the output of the TMN 4188, the impedance presented to the RF inverter 4186 and / or the load 4092 may be adjusted. In an embodiment, the system controller 4184 may generate predetermined phase shift parameter values ​​to be provided to the PWM generator circuitry 4136 such that a desired value of impedance presented to the RF inverter 4186 and / or the load 4092 may be achieved. Those skilled in the art will understand that the desired value of impedance presented to the RF inverter 4186 and / or the load 4092 will depend on the operation, use, design, etc. of the RF power generation and delivery system.

[0268]

[0308] Referring now to FIG. 42, an exemplary rf power generation and delivery system 420 4200 includes an RF inverter or amplifier 4286 having an output coupled to the input of a PSIM TMN4288. The PSIM TMN4288 includes at least one PSIM element. The RF inverter 4286 here includes a voltage source 4203 and a resistor R S4205. An IV probe 4294 is coupled between the RF inverter and the PSIM TMN. The load impedance Z L A load 4298 having a voltage Vcc is coupled to the output of the PSIM TMN 4288. An IV probe is coupled between the PSIM TMN 4288 and the load 4298.

[0269]

[0309] This system includes a PWM waveform generator 4236 (phase shift element A4216, 4286, and the load 4298. Thus, in this exemplary embodiment, the PSIM TMN 4288 is coupled at its input to an RF inverter or amplifier 4286 and at its output to a load 4298, and is configured to adjust the impedance presented to the RF inverter or amplifier 4286 and the impedance presented to the load 4298.

[0270]

[0310] In an embodiment, the PSIM element is a capacitor C S1 4207, C S2 42 17, and C P1 , inductor L S1 4209 and L S2 4215, and transistor q1. Transistor q1 is configured to receive a drive signal 4208 from a PWM generator 4236 and, in response, adjust the impedance presented at the input and / or output terminals of the PSIM TMN 4288 (i.e., adjust the impedance presented to the RF inverter or amplifier 4286 and / or load 4298). The drive signal may be provided as a PWM signal generated by the PWM generator 4236 using any of the techniques described herein.

[0271]

[0311] The input of the PSIM TMN4288 is A signal (e.g., a voltage signal) is coupled to the input of the PWM generator 4236 (here through a level adjustment circuit 4233, which may comprise, for example, an attenuator) to be provided to the PWM 4236 as a reference signal 4202. In an embodiment, the signal at the input of the PSIM TMN 4288 may first be provided to an attenuator 4284 before being provided as the reference signal 4202 to ensure compatibility with the internal circuitry of the PWM generator 4236. In this exemplary embodiment, a PWM generator 4236 having a parallel structure is provided. Thus, the reference signal 4202 is provided to both phase shift elements A, B 4216, 4218, with each phase shift element configured to generate a phase-shifted signal 4210A, 4210B based on a respective predefined phase shift parameter. In an embodiment, the predefined phase shift parameters may be provided to the phase shift elements 4216, 4218 by the system control 4284. Of course, it should be understood that in other embodiments it may be desirable or necessary to provide a PWM generator 4236 with a cascaded structure.

[0272]

[0312] The IV probes 4294 and 4296 are connected to the load 4298 and the RF inverter 42 4298 and RF inverter 4286 and provides the monitored impedance to system control 4284. In an embodiment, system control 4284 is configured to generate a predetermined phase shift parameter based on the monitored impedance to achieve a desired value of the impedance presented to load 4298 and RF inverter 4286.

[0273]

[0313] Referring now to FIG. 43, an exemplary rf power generation and delivery system 430 0 includes a PSIM TMN4388 with input and output terminals and two PSIM elements, and an RF inverter or amplifier 4386 (voltage source 4303 and resistor R S4305), PWM waveform generators A, B 4236A, 4326B (each including a first phase shift element 4316A,B and a second phase shift element 4318A,B and a waveform combiner 4306A,B), IV probes 4394, 4396, and a system controller 4384. In an embodiment, the PSIM TMN 4388 is coupled at its input to an RF inverter or amplifier 4386 and at its output to a load 4398 and configured to adjust the impedance presented to the RF inverter or amplifier 4386 and the impedance presented to the load 4298.

[0274]

[0314] The first PSIM element receives the drive signal and, in response, The second PSIM element includes a transistor q1 4321 configured to receive the drive signal and, in response thereto, adjust the impedance presented at the input terminal of PSIM TMN4388 (i.e., adjust the impedance presented to RF inverter or amplifier 4386). In an embodiment, the drive signal for q1 4321 may be provided as a PWM signal generated by PWM generator 4336A. The second PSIM element includes a transistor q2 4311 configured to receive the drive signal and, in response thereto, adjust the impedance presented at the input terminal of PSIM TMN4388 (i.e., adjust the impedance presented to RF inverter or amplifier 4386). In an embodiment, the drive signal for q2 4311 may be provided as a PWM signal generated by PWM generator 4336B.

[0275]

[0315] Each PWM generator 4336 provides to its phase shift elements 4316, 4318 In an embodiment, these phase shift parameters may be generated by system control 4384, which is configured to generate the pre-defined phase shift parameters based on desired values ​​of impedance provided at the input and output of PSIM TMN 4388.

[0276]

[0316] Each PWM signal generated by the PWM generators 4336A and 4336B is a PWM signal. The reference signals provided to PWM generator A 4336A may include one or more signals (e.g., voltage signals) at the output of PSIM TMN4388, and the reference signals provided to PWM generator B 4336B may include one or more signals (e.g., voltage signals) at the input of PSIM TMN4388. To do this, PWM generator A 4336A generates PWM signals having pulse widths and phase shifts relative to the signals at the output of PSIM TMN4388, and PWM generator B 4336B generates PWM signals having pulse widths and phase shifts relative to the signals at the output of PSIM TMN4388. It generates a PWM signal with a pulse width and phase shift relative to the signal at the input of the TMN4388.

[0277]

[0317] In an embodiment, I- The V-probes 4396, 4398 monitor the impedance presented at the input and output of the PSIM TMN 4338, and based on this, the system control 4384 determines the impedance of each PW The operation (eg, operating frequency, output power) of the M generator 4336 and the RF inverter or amplifier 4386 can be controlled.

[0278]

[0318] References herein to "one embodiment" or "an embodiment" refer to that implementation. It means that a particular feature, structure, or characteristic described in connection with an embodiment can be included in at least one embodiment of the claimed subject matter. The appearances of the phrase "in one embodiment" in various places in the specification do not necessarily all refer to the same embodiment, nor are they necessarily mutually exclusive separate or alternative embodiments from other embodiments. The same applies to the term "implementation."

[0279]

[0319] As used in this application, the words "exemplary" and "illustrative" mean an example, instance, or demonstration. The term "exemplary" or "illustrative" is used herein to mean "to exemplify" or "to serve as an example." Any aspect or design described herein as "exemplary" or "illustrative" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words "exemplary" and "illustrative" is intended to present concepts in a concrete manner.

[0280]

[0320] In addition, the term "or" is used inclusively rather than exclusively. That is, unless otherwise stated or clear from the context, "X employs A or B" is intended to mean any of the natural inclusive arrangements. That is, if X employs A, X employs B, or X employs both A and B, then "X employs A or B" would be satisfied under any of the foregoing examples. Additionally, the articles "a" and "an," as used in this application and the appended claims, should be construed generally to mean "one or more," unless otherwise stated or clear from the context that the singular form is intended.

[0281]

[0321] To the extent that directional terms are used in this specification and claims, In the context of terms such as "upper," "lower," "parallel," "perpendicular," etc., these terms are merely intended to aid in the description of the embodiments and are not intended to limit the scope of the claims in any way. Such terms do not require precision (e.g., exact perpendicularity or exact parallelism), but rather are intended to apply normal tolerances and ranges. Similarly, unless expressly stated otherwise, each numerical value and range should be interpreted as an approximation, as if the words "about," "substantially," or "approximately" precede the value or range.

[0282]

[0322] Some embodiments are in the form of methods and apparatus for practicing those methods. In addition, as will be apparent to those skilled in the art, various functions of circuit elements may also be implemented as processing blocks in a software program. The described embodiments may also be implemented in the form of program code embodied in a tangible medium, such as a magnetic recording medium, a hard drive, a floppy disk, a magnetic tape medium, an optical recording medium, a compact disk (CD), a digital versatile disk (DVD), a solid-state memory, a hybrid magnetic and solid-state memory, or any other machine-readable storage medium, which, when loaded into and executed by a machine, such as a computer, makes the machine an apparatus for practicing the claimed invention. The described embodiments may also be implemented in the form of program code, for example, whether stored on a storage medium, loaded into and / or executed by a machine, or transmitted over some transmission medium or carrier wave, for example, through an electrical wire or cable, by optical fiber, or via electromagnetic radiation, which, when loaded into and executed by a machine, makes the machine an apparatus for practicing the claimed invention. When implemented on a processing device, the program code segments combine with the processor to provide a unique device that operates analogously to specific logic circuits. The device may include, for example, a general-purpose microprocessor, a digital signal processor (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic array (PLA), a microcontroller, an embedded controller, a micro-core processor, and / or others including combinations of the above. The described embodiments may also be implemented in the form of a bit stream or other sequence of signal values ​​transmitted electrically or optically over a medium, stored magnetic field variations in a magnetic recording medium, or the like, generated using the methods and / or apparatus recited in the claims.

[0283]

[0323] Also, for purposes of this description, "couple" and "connect" The terms "coupling," "coupled," "connect," "connecting," or "connected" refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, where the interposition of one or more additional elements is contemplated but not required. Conversely, terms such as "directly coupled," "directly connected," etc., suggest the absence of such additional elements. Signals and corresponding nodes or ports may be referred to by the same name and are interchangeable for convenience herein.

[0284]

[0324] The steps of the methods set forth herein do not necessarily have to be performed in the order described. It should be understood that this is not necessarily required, and that the ordering of steps in such methods is merely illustrative. Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined, in a manner consistent with various embodiments.

[0285]

[0325] Various modifications in the details, materials and arrangements of parts described and illustrated herein may be made without departing from the spirit and scope of the present invention. It is to be understood that various modifications can be made by one skilled in the art without departing from the scope of the following claims.

Claims

1. 1. A pulse width modulation (PWM) generator, comprising: a phase shift element; Waveform combiner and Equipped with The phase shift element is a pair of IQ modulators configured to receive a reference signal with which the PWM waveforms are synchronized, the reference signal serving as a local oscillator input to each of the IQ modulators; a digital-to-analog converter (DAC) having first and second outputs coupled to respective I / Q inputs of one of the pair of IQ modulators, and third and fourth outputs coupled to respective I / Q inputs of the other of the pair of IQ modulators; and an input; By providing one or more signals to the DAC to control the DAC, values ​​for the I and Q signals for each of the pair of IQ modulators are synthesized, and the signals IQ of the outputs of each of the pair of IQ modulators are calculated relative to the reference signals provided to the pair of IQ modulators. １ and signal IQ ２ a microcontroller coupled to control the phase shift of the Including, A pulse width modulation (PWM) generating device, wherein the waveform combiner has a first input coupled to the output of one of the pair of IQ modulators and a second input coupled to the output of the other of the pair of IQ modulators, and is configured to combine signals IQ1 and IQ2 from the outputs of each of the pair of IQ modulators to generate the PWM waveform.

2. The waveform combiner comprises: a first comparator having a first input coupled to the output of one of the pair of IQ modulators, a second input coupled to a reference potential, and an output; a second comparator having a first input coupled to the output of the other of the pair of IQ modulators, a second input coupled to a reference potential, and an output; a single logic gate having a first input coupled to the output of one of the first and second comparators, a second input coupled to the output of the other of the first and second comparators, and an output; 2. The PWM generating device of claim 1, comprising:

3. 3. A PWM generator as claimed in claim 2, wherein said single logic gate is provided as a logic AND gate with one inverting input.

4. 3. A PWM generating device as claimed in claim 2, wherein the single logic gate is provided as a logic AND gate with two non-inverting inputs and a NOT gate at one of the inputs.

5. an output of the one IQ modulator of the pair of IQ modulators is coupled to a positive input of the first comparator; 3. The PWM generating device of claim 2, wherein the output of the other of the pair of IQ modulators is coupled to the positive input of the second comparator.

6. an output of one of the pair of IQ modulators is coupled to a positive input terminal of the first comparator, and the reference potential is coupled to a negative input terminal of the first comparator; 3. The PWM generating device according to claim 2, wherein the output of the other of the pair of IQ modulators is coupled to the negative input terminal of the second comparator, and the reference potential is coupled to the positive input terminal of the second comparator.

7. 7. The PWM generating apparatus of claim 6, wherein the outputs of the first and second comparators are fed to an AND gate having two non-inverting inputs.

8. The Q output of the waveform combiner is the signal IQ １ is positive, and the signal IQ ２ 8. The PWM generating device of claim 7, wherein the signal .PHI. is asserted (to a logic high) only during periods when .PHI. is negative.

9. A PWM generating device as described in claim 1, wherein the resolution at which the pulse width w and phase φ of the PWM waveform can be controlled depends on the resolution at which the DAC can synthesize the I input and Q input signals supplied to the pair of modulators.

10. 1. A pulse width modulation (PWM) generator, comprising: an IQ modulator integrated circuit having differential baseband I and Q inputs and a differential LO input; A PWM generator in which the differential voltage at the I input and the Q input is converted to a current that drives a plurality of double balanced mixers, the outputs of which are summed and applied to a buffer that converts the differential mixer signals to a single-ended, buffered RF output.

11. 11. The PWM generating device of claim 10, wherein the IQ modulator based single phase shift element implementation comprises an integrated circuit.

12. 11. The PWM generator of claim 10, wherein the integrated circuit is configured such that the PWM generator operates over a local oscillator frequency range of 5 MHz to 1600 MHz and has a baseband bandwidth greater than 400 MHz.

13. 11. The PWM generator of claim 10, wherein the I and Q inputs are combined with a pair of 12-bit DACs.

14. 14. The PWM generating device of claim 13, wherein the pair of 12-bit DACs have single-ended outputs.

15. 15. The PWM generating device of claim 14, wherein the single-ended outputs of the pair of 12-bit DACs are buffered and converted to differential signals with a pair of fully differential operational amplifiers.

16. 16. The PWM generator of claim 15, further comprising a microcontroller coupled to the pair of 12-bit DACs.

17. a passive impedance matching network; a 1:1 balun coupled to convert the differential LO input of the IQ modulator to a single-ended reference input; The PWM generating device of claim 15 further comprising:

Images