Multiplexed controller for motors

Abstract

Techniques are provided for applying multiplexed controllers to the control of motors. [Solution] The multiplexing control device 210 includes three controllers C1 to C3 that output digital voltage signals including voltage command values ​​in a two-phase Cartesian coordinate (fixed coordinate) system (α, β) for the motor 300, and a signal control unit 211 that inputs digital voltage signals output from at least two of the three controllers C1 to C3, selects the digital voltage signal output by a controller C that is not faulty among the controllers C that output the input digital voltage signals based on a predetermined priority, and generates and outputs a PWM signal based on the selected digital voltage signal.

Description

[Technical Field]

[0001] The present invention relates to multiplexed control techniques for motors. [Background technology]

[0002] A multiplexed control device disclosed in Patent Document 1 is sometimes used to control various components such as hydraulic actuators in aircraft. The multiplexed control device disclosed in Patent Document 1 has three controllers. The same input signal is input to the three controllers, and the three controllers output the same output signal. The output signals of the three controllers are input to a majority circuit. The majority circuit determines the final output by taking a majority vote of the inputs from the three controllers. In this way, the multiplexed control device disclosed in Patent Document 1 forms a multiplexed redundant system processing circuit that can obtain correct processing results as output data even if a failure occurs in one system. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Unexamined Patent Publication No. 1-98034 Summary of the Invention [Problem to be solved by the invention]

[0004] There is a demand for a multiplexed control device such as the technology described in Patent Document 1 to be used for controlling the motors that drive the rotary wing sections of flying bodies such as electric vertical take-off and landing aircraft (hereinafter referred to as eVTOL).

[0005] In view of the above, an object of the present invention is to provide a technique for applying a multiplexed control device to motor control. [Means for solving the problem]

[0006] In order to solve the above problem, a multiplexing control device according to one embodiment of the present invention includes three controllers that output digital voltage signals including voltage command values ​​in a two-phase Cartesian coordinate system for a motor, and a signal control unit that inputs the digital voltage signals output from at least two of the three controllers, selects, based on a predetermined priority, the digital voltage signal output by a controller that is not faulty among the controllers that output the input digital voltage signals, and generates and outputs a PWM signal based on the selected digital voltage signal.

[0007] Any combination of the above components, and any transformation of the present invention into a method, device, system, recording medium, computer program, etc., are also valid aspects of the present invention. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a technique for applying a multiplexed control device to motor control. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a top view schematically illustrating an eVTOL according to an embodiment. [Figure 2] 1 is a schematic configuration diagram of a motor control device according to an embodiment; [Figure 3] FIG. 2 is a schematic configuration diagram of a first controller according to the embodiment. [Figure 4] FIG. 2 is a schematic configuration diagram of a signal control unit according to the embodiment. [Figure 5] 10A and 10B are diagrams illustrating the state of a multiplexing control device for each case. DETAILED DESCRIPTION OF THE INVENTION

[0010] Embodiment Hereinafter, an embodiment of a multiplexing control device applied to an aircraft such as an eVTOL will be described with reference to the drawings.

[0011] FIG. 1 is a top view that schematically illustrates an eVTOL1 of this embodiment. The eVTOL1 of this embodiment is configured as an unmanned aerial vehicle that can take off and land vertically. The eVTOL1 includes a main body 10 that forms the fuselage portion of the eVTOL1, six arms 20, and six rotating wing units 30. Each arm 20 supports a corresponding rotating wing unit 30. The six rotating wing units 30 are each disposed at the end of the arm 20. Each rotating wing unit 30 has three blades 35 that are disposed at equal angular intervals from one another. The eVTOL1 of this embodiment is an example of an air vehicle.

[0012] Each rotating blade section 30 includes a motor control device 200, a motor 300, and a rotation detection sensor 400. The motor 300 is driven to rotate by receiving power from a battery 50. The motor 300 is, for example, a three-phase brushless motor. The motor control device 200 controls the driving of the motor 300 based on a speed command from the upper control device 100. The rotation detection sensor 400 detects the rotation speed of the rotating blade section 30. In this embodiment, the rotation detection sensor 400 detects the rotation speed of a rotor (not shown) of the motor 300 as the rotation speed of the rotating blade section 30, but is not limited to this. For example, the rotation speed of the blades 35 of the rotating blade section 30 may be detected. The detection result of the rotation detection sensor 400 is output to the upper control device 100.

[0013] The main body 10 houses a battery 50 and a host control device 100. The battery 50 supplies power to the host control device 100, the motor control device 200, the motor 300, the rotation detection sensor 400, etc., which are provided in each rotating blade section 30. The battery 50 is a secondary battery such as a lithium-ion battery that can be repeatedly charged and discharged.

[0014] The host control device 100 executes various processes in the eVTOL 1. The host control device 100 is configured to be able to communicate with the motor control devices 200 provided in each rotating wing section 30. The host control device 100 outputs a speed command to the motor control device 200 to control the rotational speed of the rotating wing section 30 by controlling the motor 300. The speed command in this embodiment includes a command value for the rotational speed of the rotating wing section 30 (hereinafter referred to as the speed command value). The host control device 100 generates the speed command value in the speed command in response to, for example, user input via a user controller (not shown) for the user to operate the eVTOL 1.

[0015] 2 is a schematic configuration diagram of a motor control device 200 of this embodiment. As shown in FIG. 2, the motor control device 200 includes a multiplexing control device 210 and a gate driver 220.

[0016] The multiplexing control device 210 includes first to third controllers C1 to C3 and a signal control unit 211. The first to third controllers C1 to C3 basically have the same configuration except where otherwise noted. In this specification, the first to third controllers C1 to C3 may be collectively referred to as controller C when describing any one of them.

[0017] The first controller C1 generates digital voltage signals (hereinafter referred to as digital voltage signals) indicating voltage command values ​​Vα1 and Vβ1 in a two-phase Cartesian coordinate (fixed coordinate) system (α, β) for the motor 300 based on a speed command from the upper control device 100. The second controller C2 generates digital voltage signals indicating two-phase voltage command values ​​Vα2 and Vβ2 for the motor 300 based on the speed command from the upper control device 100. The third controller C3 generates digital voltage signals indicating two-phase voltage command values ​​Vα3 and Vβ3 for the motor 300 based on the speed command from the upper control device 100.

[0018] Furthermore, the first controller C1 outputs status signals St1_1, St1_2, and St1_3 to the signal control unit 211. The second controller C2 outputs status signals St2_1, St2_2, and St2_3 to the signal control unit 211. The third controller C3 outputs status signals St3_1, St3_2, and St3_3 to the signal control unit 211. Hereinafter, when describing any of the status signals St1_1, St1_2, St1_3, St2_1, St2_2, St2_3, St3_1, St3_2, and St3_3, they may be collectively referred to as status signals St. The status signal St will be described later.

[0019] The gate driver 220 has a U-phase arm, a V-phase arm, and a W-phase arm, each of which has two switching elements (not shown) connected in series. Coils of corresponding phases in the motor 300 are connected between the two switching elements of the U-, V-, and W-phase arms of the gate driver 220. The gate driver 220 generates U-phase, V-phase, and W-phase currents Iu, Iv, and Iw, respectively, by a known method based on PWM signals Up and Ud, Vp and Vd, and Wp and Wd output from a PWM output unit 75 (described later), and outputs these currents to the motor 300 via the U-phase arm, V-phase arm, and W-phase arm. The motor 300 is controlled by the U-phase, V-phase, and W-phase currents Iu, Iv, and Iw of the gate driver 220. The switching elements used in the gate driver 220 in this embodiment are IGBTs, but are not limited thereto and may be, for example, FETs.

[0020] A detection unit 215 is connected to the gate driver 220. The detection unit 215 detects three-phase currents Iu, Iv, and Iw output from the gate driver 220, and outputs them to the first to third controllers C1 to C3.

[0021] 3 is a schematic configuration diagram of the first controller C1 of this embodiment. The first controller C1 includes a current command generator 51, a Clarke converter 52, a Park converter 53, a d-axis target value generator 54, a q-axis target value generator 55, an inverse Park converter 56, and first to third state monitors 58 to 60.

[0022] Based on the difference between the speed command input from the upper control device 100 and the rotation speed detected by the rotation detection sensor 33, the current command generation unit 51 generates a d-axis current command value and a q-axis current command value so as to follow the speed command from the upper control device 100. The current command generation unit 51 outputs the d-axis current command value to a d-axis target value generation unit 54, and outputs the q-axis current command value to a q-axis target value generation unit 55.

[0023] Clarke conversion unit 52 performs Clarke conversion on the measurement values ​​of three-phase currents Iu, Iv, and Iw measured by detection unit 215, to calculate currents Iα and Iβ in a two-phase orthogonal coordinate (fixed coordinate) system (α, β), and outputs the calculated currents to Park conversion unit 53. Park conversion unit 53 performs Park conversion on the currents Iα and Iβ to calculate a q-axis detected value Iq and a d-axis detected value Id in the rotating coordinates from the currents Iα and Iβ in the two-phase fixed coordinates, and outputs the calculated values ​​to d-axis target value generation unit 54 and q-axis target value generation unit 55.

[0024] The d-axis target value generator 54 sets a d-axis current target value based on the d-axis current command value output from the current command generator 51, the rotation speed output from the rotation detection sensor 33, and the d-axis detected value Id output from the park converter 53. The d-axis target value generator 54 also calculates a d-axis voltage target value at predetermined intervals based on the d-axis current target value. For example, the d-axis target value generator 54 performs current feedback control such as proportional-integral control (PI control) on the current deviation between the d-axis detected value Id and the d-axis current target value. This causes the d-axis voltage target value to be calculated so as to bring the d-axis detected value Id closer to the d-axis current target value, and outputs the calculated value to the inverse park converter 56. Similarly, the q-axis target value generator 55 sets a q-axis current target value based on the q-axis current command value and the q-axis detected value Iq output from the park converter 53, calculates a q-axis voltage target value, and outputs the calculated value to the inverse park converter 56.

[0025] The inverse Park transformation unit 56 calculates voltage command values ​​Vα1, Vβ1 of two-phase fixed coordinates from the rotating coordinates by performing an inverse Park transformation on the d-axis voltage target value and the q-axis voltage target value, and outputs them as digital voltage signals to the second controller C2, the third controller C3, and the signal control unit 211, respectively.

[0026] The second controller C2 also calculates voltage command values ​​Vα2 and Vβ2 in the same manner as the first controller and outputs them as digital voltage signals to the first controller C1, the third controller C3, and the signal control unit 211. The third controller C3 also calculates voltage command values ​​Vα3 and Vβ3 in the same manner as the first controller and outputs them as digital voltage signals to the first controller C1 and the second controller C2. On the other hand, the third controller C3 of this embodiment does not output these signals to the signal control unit 211.

[0027] The first state monitoring unit 58 receives the voltage command values ​​Vα1 and Vβ1 included in the two-phase digital voltage signal generated by the inverse Park conversion unit 56 and the voltage command values ​​Vα2 and Vβ2 included in the two-phase digital voltage signal output from the second controller C2. The first state monitoring unit 58 compares the difference between the average value of the voltage command values ​​Vα1 and Vβ1 and the average value of the voltage command values ​​Vα2 and Vβ2 with a predetermined threshold. If the difference between this difference and the predetermined threshold is smaller than another predetermined threshold, the first state monitoring unit 58 determines that the second controller C2 is not malfunctioning and outputs a value of 1 to the signal control unit 211 as the status signal St1_2. If the difference between this difference and the predetermined threshold is equal to or greater than the other threshold, the first state monitoring unit 58 determines that the second controller C2 is malfunctioning and outputs a value of 0 to the signal control unit 211 as the status signal St1_2. For example, when the second controller C2 fails and abnormal values ​​are output as the voltage command values ​​Vα2, Vβ2, a value of 0 is output as the state signal St1_2.

[0028] The second state monitoring unit 59 receives the voltage command values ​​Vα1 and Vβ1 contained in the two-phase digital voltage signal generated by the inverse Park conversion unit 56 and the voltage command values ​​Vα3 and Vβ3 contained in the two-phase digital voltage signal output from the third controller C3. The second state monitoring unit 59 compares the difference between the average value of the voltage command values ​​Vα1 and Vβ1 and the average value of the voltage command values ​​Vα3 and Vβ3 with a predetermined threshold. If the difference between this difference and the predetermined threshold is smaller than another predetermined threshold, the first state monitoring unit 58 determines that the third controller C3 is not malfunctioning and outputs a value of 1 to the signal control unit 211 as the status signal St1_3. If the difference between this difference and the predetermined threshold is equal to or greater than the other threshold, the first state monitoring unit 58 determines that the third controller C3 is malfunctioning and outputs a value of 0 to the signal control unit 211 as the status signal St1_3. For example, when the third controller C3 fails and abnormal values ​​are output as the voltage command values ​​Vα3 and Vβ3, a value of 0 is output as the state signal St1_3.

[0029] The third status monitoring unit 60 outputs a status signal St1_1 based on whether or not an external failure has occurred. Here, an external failure refers to a failure in any part of the motor control device 200 other than the multiplexing control device 210 (such as the gate driver 220). The external failure is detected using a known external failure detection device for the motor control device 200. If no external failure has occurred, the third status monitoring unit 60 outputs a value of 1 as the status signal St1_1 to the signal control unit 211. If an external failure has occurred, the third status monitoring unit 60 outputs a value of 0 as the status signal St1_1 to the signal control unit 211.

[0030] The second controller C2 also outputs status signals St2_1, St2_2, and St2_3 in the same manner as the first controller C1. For example, the first status monitoring unit 58 of the second controller C2 determines whether or not there is a failure in the first controller C1 based on the voltage command values ​​Vα2 and Vβ2 included in the two-phase digital voltage signal generated by the inverse Park conversion unit 56 and the voltage command values ​​Vα1 and Vβ1 included in the two-phase digital voltage signal output from the first controller C1, and outputs the result as a status signal St2_1 having a value of 0 or 1 to the signal control unit 211. Also, for example, the second status monitoring unit 59 of the second controller C2 determines whether or not there is a failure in the third controller C3 based on the voltage command values ​​Vα2 and Vβ2 included in the two-phase digital voltage signal generated by the inverse Park conversion unit 56 and the voltage command values ​​Vα3 and Vβ3 included in the two-phase digital voltage signal output from the third controller C3, and outputs the result as a status signal St2_3 having a value of 0 or 1 to the signal control unit 211. Furthermore, for example, the third state monitoring unit 60 of the second controller C2 outputs a state signal St2_2 having a value of 0 or 1 to the signal control unit 211 based on whether or not an external failure has occurred.

[0031] The third controller C3 also outputs status signals St3_1, St3_2, and St3_3 in the same manner as the first controller C1. For example, the first status monitoring unit 58 of the third controller C3 determines whether or not the first controller C1 has a malfunction based on the voltage command values ​​Vα3 and Vβ3 included in the two-phase digital voltage signal generated by the inverse Park conversion unit 56 and the voltage command values ​​Vα1 and Vβ1 included in the two-phase digital voltage signal output from the first controller C1, and outputs the result as a status signal St3_1 having a value of 0 or 1 to the signal control unit 211. Also, for example, the second status monitoring unit 59 of the third controller C3 determines whether or not the second controller C2 has a malfunction based on the voltage command values ​​Vα3 and Vβ3 included in the two-phase digital voltage signal generated by the inverse Park conversion unit 56 and the voltage command values ​​Vα2 and Vβ2 included in the two-phase digital voltage signal output from the second controller C2, and outputs the result as a status signal St3_2 having a value of 0 or 1 to the signal control unit 211. Furthermore, for example, the third state monitoring unit 60 of the third controller C3 outputs a state signal St3_3 having a value of 0 or 1 to the signal control unit 211 based on whether or not an external failure has occurred.

[0032] 4 is a schematic configuration diagram of the signal control unit 211 of this embodiment. The signal control unit 211 includes a fault determination unit 72, a selection unit 73, an inverse Clarke conversion unit 74, and a PWM output unit 75. The fault determination unit 72 determines whether or not there is a fault in the first to third controllers C1 to C3 based on the state signals St output from the first to third controllers C1 to C3. The fault determination unit 72 also determines whether or not there is an external fault. The fault determination unit 72 includes first to fourth AND circuits 61, 63, 66, 71, first to fourth OR circuits 65, 68-70, and first to third latch circuits 62, 64, 67.

[0033] The first AND circuit 61 receives the status signals St1_2 and St2_1. When one of the received status signals St1_2 and St2_1 has a value of 0 (i.e., when the first controller C1 determines that the second controller C2 has failed or when the second controller C2 determines that the first controller C1 has failed), the first AND circuit 61 outputs a value of 0 to the first latch circuit 62. On the other hand, when both of the received status signals St1_2 and St2_1 have a value of 1 (i.e., when the first controller C1 determines that the second controller C2 has not failed and when the second controller C2 determines that the first controller C1 has not failed), the first AND circuit 61 outputs a value of 1 to the first latch circuit 62.

[0034] The first latch circuit 62 receives the output signal of the first AND circuit 61. When the value of the output signal of the first AND circuit 61 is 1, the first latch circuit 62 outputs an output signal of 1 to the first OR circuit 65. On the other hand, when the value of the output signal of the first AND circuit 61 is 0, the first latch circuit 62 outputs an output signal of 0 to the first OR circuit 65, and thereafter maintains its own output signal at 0.

[0035] The second AND circuit 63 receives the status signals St1_3 and St3_1. If one of the received status signals St1_3 and St3_1 has a value of 0 (i.e., the first controller C1 determines that the third controller C3 has failed, or the third controller C3 determines that the first controller C1 has failed), the second AND circuit 63 outputs a value of 0 to the second latch circuit 64. On the other hand, if both of the received status signals St1_3 and St3_1 have a value of 1 (i.e., the first controller C1 determines that the third controller C3 has not failed, and the third controller C3 determines that the first controller C1 has not failed), the second AND circuit 63 outputs a value of 1 to the second latch circuit 64.

[0036] The second latch circuit 64 receives the output signal of the second AND circuit 63. When the value of the output signal of the second AND circuit 63 is 1, the second latch circuit 64 outputs an output signal of 1 to the first OR circuit 65. On the other hand, when the value of the output signal of the second AND circuit 63 is 0, the second latch circuit 64 outputs an output signal of 0 to the first OR circuit 65, and thereafter maintains its own output signal at 0.

[0037] The first OR circuit 65 receives the output signals of the first and second latch circuits 62, 64. When both of the input output signals are 0 (i.e., when either the second or third controller C2 or C3 determines that the first controller C1 is faulty, or when the first controller C1 determines that either the second or third controller C2 or C3 is faulty), the first OR circuit 65 outputs a value of 0 to the selection unit 73. On the other hand, when at least one of the input output signals is 1 (i.e., when at least one of the second controller C2 or the third controller C3 determines that the first controller C1 is not faulty), the first OR circuit 65 outputs a value of 1 to the selection unit 73. Hereinafter, the signal output by the first OR circuit 65 is referred to as StP. When the signal StP is 1, it indicates that the first controller C1 is normal. When the signal StP is 0, it indicates that the first controller C1 is faulty.

[0038] Note that, if the only purpose is to simply determine whether the first controller C1 has failed, there is no need to monitor the status signals St1_2 and St1_3 in the first and second AND circuits 61 and 63. The reason why the status signals St1_2 and St1_3 are monitored in the first and second AND circuits 61 and 63 is that if the first controller C1 fails in the second controller C2, the status signal St2_1 of the second controller C2 will be in an indefinite state, which will be described later, and a situation will occur in which the signal StP cannot be set to the value of 0, and this will prevent a malfunction.

[0039] The third AND circuit 66 receives the status signals St3_2 and St2_3. When one of the received status signals St3_2 and St2_3 has a value of 0 (i.e., when the third controller C3 determines that the second controller C2 has failed or when the second controller C2 determines that the third controller C3 has failed), the third AND circuit 66 outputs a value of 0 to the third latch circuit 67. On the other hand, when both of the received status signals St3_2 and St2_3 have a value of 1 (i.e., when the third controller C3 determines that the second controller C2 has not failed and when the second controller C2 determines that the third controller C3 has not failed), the third AND circuit 66 outputs a value of 1 to the third latch circuit 67.

[0040] The third latch circuit 67 receives the output signal of the third AND circuit 66. When the value of the output signal of the third AND circuit 66 is 1, the third latch circuit 67 outputs an output signal with a value of 1 to the selection unit 73. On the other hand, when the value of the output signal of the third AND circuit 66 is 0, the third latch circuit 67 outputs an output signal with a value of 0 to the selection unit 73, and thereafter maintains its own output signal at a value of 0. Hereinafter, the signal output by the third OR circuit 67 will be referred to as StS. When the signal StS has a value of 1, it indicates that the second controller C2 is normal. When the signal StS has a value of 0, it indicates that the second controller C2 is faulty.

[0041] If it is simply to determine whether the second controller C2 has failed, there is no need to monitor the status signal St2_3 in the third AND circuit 66. The reason why the status signal St2_3 is monitored in the third AND circuit 66 is to prevent malfunction when the third controller C3 has failed.

[0042] The second OR circuit 68 receives the status signals St1_1 and St2_2. If both of the received status signals St1_1 and St2_2 have a value of 0 (i.e., if it is determined by both the first controller C1 and the second controller C2 that an external fault has occurred), the second OR circuit 68 outputs a value of 0 to the fourth AND circuit 71. On the other hand, if at least one of the received output signals has a value of 1 (i.e., if it is determined by at least one of the first controller C1 and the second controller C2 that no external fault has occurred), the second OR circuit 68 outputs a value of 1 to the fourth AND circuit 71.

[0043] The third OR circuit 69 receives the status signals St1_1 and St3_3. If both of the received status signals St1_1 and St3_3 have a value of 0 (i.e., if it is determined by both the first controller C1 and the third controller C3 that an external fault has occurred), the third OR circuit 69 outputs a value of 0 to the fourth AND circuit 71. On the other hand, if at least one of the received output signals has a value of 1 (i.e., if it is determined by at least one of the first controller C1 and the third controller C3 that no external fault has occurred), the third OR circuit 69 outputs a value of 1 to the fourth AND circuit 71.

[0044] The fourth OR circuit 70 receives the status signals St2_2 and St3_3. When both the received status signals St2_2 and St3_3 have a value of 0 (i.e., when it is determined by both the second controller C2 and the third controller C3 that an external fault has occurred), the fourth OR circuit 70 outputs a value of 0 to the fourth AND circuit 71. On the other hand, when at least one of the received output signals has a value of 1 (i.e., when it is determined by at least one of the second controller C2 and the third controller C3 that no external fault has occurred), the fourth OR circuit 70 outputs a value of 1 to the fourth AND circuit 71.

[0045] The fourth AND circuit 71 receives the output signals of the second to fourth OR circuits 68 to 70. If at least one of the input signals is 0, the fourth AND circuit 71 outputs a value of 0 to the selection unit 73 (i.e., if it is determined that an external fault has occurred by at least two of the first to third controllers C1 to C3). On the other hand, if all of the input signals are 1 (i.e., if it is determined that an external fault has occurred by any one of the first to third controllers C1 to C3, or if it is determined that no external fault has occurred by all of the first to third controllers C1 to C3), the fourth AND circuit 71 outputs a value of 1 to the selection unit 73. Hereinafter, the signal output by the fourth AND circuit 71 will be referred to as StC.

[0046] The selector 73 receives the signals StP, StS, and StC output from the first OR circuit 65, the third latch circuit 67, and the fourth AND circuit 71, the voltage command values ​​Vα1 and Vβ1 output from the first controller C1, and the voltage command values ​​Vα2 and Vβ2 output from the second controller C2. Based on the signals output from the first OR circuit 65, the third latch circuit 67, and the fourth AND circuit 71 and a predetermined priority order, the selector 73 selects a voltage command value to be used from the voltage command values ​​Vα1 and Vβ1, the voltage command values ​​Vα2 and Vβ2, and 0, and outputs the selected voltage command value to the inverse Clarke transformer 74. In this embodiment, the first priority is assigned to the first controller C1, the second priority is assigned to the second controller C2, and 0 is assigned to the third priority order. Among the first to third priorities, the first priority is the highest, the second priority is the second highest, and the third priority is the lowest. Therefore, for example, when both the first controller C1 and the second controller C2 are normal, the voltage command values ​​Vα1 and Vβ1 generated from the output signal of the first controller C1 are preferentially selected by the selector 73 as the voltage command values ​​Vα and Vβ based on the priority order. Also, for example, when the first controller C1 is faulty, the voltage command values ​​Vα2 and Vβ2 generated from the output signal of the second controller C2 are preferentially selected by the selector 73 as the voltage command values ​​Vα and Vβ based on the priority order. Also, for example, when both the first controller C1 and the second controller C2 are faulty, the selector 73 selects a value of 0 as the voltage command values ​​Vα and Vβ based on the priority order. Note that, since no priority order is set for the third controller C3, the digital voltage signal output by the third controller C3 is not selected by the selector 73 (in this embodiment, the digital voltage signal output by the third controller C3 is not input to the signal control unit 211 in the first place). The signal selection method by the selector 73 will be described later with reference to FIG. 5.

[0047] The inverse Clarke transformation unit 74 performs an inverse Clarke transformation on the two-phase fixed coordinate voltage command values ​​Vα and Vβ output from the selection unit 73 to generate three-phase digital voltage signals including a U-phase voltage target value VU, a V-phase voltage target value VV, and a W-phase voltage target value VW, and outputs the signals to the PWM output unit 75.

[0048] The PWM output unit 75 receives three-phase digital voltage signals including a U-phase voltage target value VU, a V-phase voltage target value VV, and a W-phase voltage target value VW from the inverse Clarke transformation unit 74. The PWM output unit 212 generates and outputs PWM signals Up, Ud, Vp, Vd, Wp, and Wd for driving the switching elements (not shown) of the three-phase bridge circuit based on the U-phase voltage target value VU, the V-phase voltage target value VV, and the W-phase voltage target value VW and a carrier wave (carrier wave), for example, a triangular wave carrier.

[0049] 5 is a diagram showing the state of the multiplexing control device 210 for each case. For example, when all the controllers C are in a normal state (case in FIG. 5: "normal"), all the state signals St have a value of 1 indicating normality, and the signals StP and StS also have a value of 1. As a result, the selector 73 selects, based on the priority order, the voltage command values ​​Vα1 and Vβ1 generated from the output signal of the first controller C1, to which the first priority order is set.

[0050] For example, let us consider a case where the first controller C1 fails when the first to third controllers C1 to C3 are normal (case "C1 failure" in FIG. 5). Because the first controller C1 is faulty, the status signals St1_1 to St1_3 output from the first controller C1 are indefinite and can be either 0 or 1. In FIG. 5, the indefinite state of the status signals St1_1 to St1_3 is indicated by "X." In the case of "C1 failure," the voltage command value output from the first controller C1 becomes significantly different from the voltage command values ​​output from the second and third controllers C2 and C3, respectively, and the status signals St2_1 and St3_1 become 0. As a result, the first and second AND circuits 61 and 63 output a value of 0, and the first OR circuit 65 outputs a signal StP with a value of 0. On the other hand, because the second and third controllers C2 and C3 are both normal, the third AND circuit 66 outputs a signal StS with a value of 1. Therefore, the selector 73 selects, based on the priority order, the voltage command values ​​Vα2 and Vβ2 generated from the output signal of the second controller C2 to which the second priority order is set.

[0051] For example, a case will be described in which the first to third controllers C1 to C3 are in a normal state, but at least one of the second controller C2 and the third controller C3 fails (cases in FIG. 5: "C2 failure" and "C3 failure"). In this case, the signal StP takes a value of 1, while the signal StS takes a value of 0. Therefore, the selector 73 selects the voltage command values ​​Vα1, Vβ1 generated from the output signal of the first controller C1 based on the priority order.

[0052] For example, a case will be described in which the second controller C2 fails after the first controller C1 fails (the case in FIG. 5: "C1 failure → C2 failure"). In this case, not only the status signals St1_1 to St1_3 output from the first controller C1 but also the status signals St2_1 to St2_3 output from the second controller C2 become indefinite. In this case, the output signals of the first and second latch circuits 62 and 64 are held at 0, so a signal StP of 0 is output from the first OR circuit 65. On the other hand, because the second controller C2 has failed, a signal StS of 0 is output from the third AND circuit 66. Therefore, the selector 73 selects and outputs a signal of 0 to which the third priority is set based on the priority order ("output 0" in the selection result in FIG. 5). When the selector 73 outputs a signal of 0, the motor 300 stops.

[0053] For example, if an external failure occurs after the first controller C1 fails (case "C1 failure → external failure" in Figure 5), if an external failure occurs after the second controller C2 fails (case "C2 failure → external failure" in Figure 5), or if an external failure occurs after the third controller C3 fails (case "C3 failure → external failure" in Figure 5), the selection unit 73 outputs a signal with a value of 0, and the motor 300 stops.

[0054] For example, when the normal state is restored after an external fault occurs (the case "external fault → normal" in FIG. 5), the first controller C1 may have been the cause of the external fault. Therefore, the state signals St1_1 to St1_3 output from the first controller C1 become indefinite, and the first OR circuit 65 outputs a signal StP with a value of 0. On the other hand, since the second and third controllers C2 and C3 are all normal, the third AND circuit 66 outputs a signal StS with a value of 1. Therefore, the selector 73 selects the voltage command values ​​Vα2 and Vβ2 generated from the output signal of the second controller C2, which is assigned the second priority, based on the priority order. Thereafter, even after the normal state is restored, the voltage command values ​​Vα2 and Vβ2 generated from the output signal of the second controller C2 are selected. Similarly, when the normal state is restored after an external fault occurs and the first controller C1 subsequently fails (the case "external fault → normal → C1 failure" in FIG. 5), the voltage command values ​​Vα2 and Vβ2 generated from the output signal of the second controller C2 are selected. When an external failure occurs and then the normal state is restored and the second controller C2 then fails (case "external failure → normal → C2 failure" in FIG. 5), when an external failure occurs and then the normal state is restored and the third controller C3 then fails (case "external failure → normal → C3 failure" in FIG. 5), and when an external failure occurs and then the normal state is restored and an external failure then occurs (case "external failure → normal → external failure" in FIG. 5), the selection unit 73 outputs a signal with a value of 0, and the motor 300 stops.

[0055] In the embodiment, an example has been shown in which the multiplexing control device 210 is applied to the motor 300 of the eVTOL 1. However, the present invention is not limited to this. The multiplexing control device 210 of the present embodiment can be applied to various motors.

[0056] In the embodiment, the digital voltage signal output from the third controller C3 is not input to the signal control unit 211, but this is not limiting and the signal may be input to the signal control unit 211. In this case, the output signal of any one of the three controllers C1 to C3 may be selected.

[0057] The multiplexing control device 210 may also include two controllers C that output a status signal St to the signal control unit 211 indicating the health of the other controllers C based on a comparison between the voltage command values ​​for each of the two phases generated by the controller C itself and the voltage command values ​​for each of the two phases of the other controllers C, and internal logic (e.g., a CPLD) in the signal control unit 211 that transfers control to the other controller C if one controller C fails and stops control if there is a difference in output between the other controller C that is functioning normally and the one controller C. This reduces the number of components used in the multiplexed redundant circuit, making it possible to perform redundant PWM control with a simplified circuit. Furthermore, because each output line is switched using the digital processing described above, PWM control of the motor can be performed with fewer transients (temporary changes) and ensured redundancy.

[0058] In the embodiment, an example in which three controllers C1 to C3 are provided is shown, but the present invention is not limited to this, and it is sufficient that two or more (plural) controllers are provided.

[0059] In summary, the multiplexing control device 210 of this embodiment includes three controllers C1 to C3 that output digital voltage signals containing voltage command values ​​in a two-phase Cartesian coordinate (fixed coordinate) system (α, β) for the motor 300, and a signal control unit 211 that receives digital voltage signals from at least two of the three controllers C1 to C3, selects a digital voltage signal output by a controller C that is not malfunctioning among the controllers C that output the input digital voltage signals based on a predetermined priority, and generates and outputs a PWM signal based on the selected digital voltage signal. This configuration enables multiplexing control to be performed using digital signal processing. As a result, resolution can be improved and the influence of PWM noise can be reduced. Furthermore, because each controller C does not need to generate a PWM signal, the circuit size of the controller C can be reduced, resulting in a simpler and more lightweight device configuration.

[0060] In the multiplexing control device 210 of this embodiment, each controller C includes a first status monitoring unit 58 that outputs a first status signal indicating whether or not one of the other controllers has a fault based on a comparison between the voltage command values ​​for each of the two phases generated by the controller C itself and the voltage command values ​​for each of the two phases of one of the other controllers C, and a second status monitoring unit 59 that outputs a second status signal indicating whether or not the other of the other controllers C has a fault based on a comparison between the voltage command values ​​for each of the two phases generated by the controller C itself and the voltage command values ​​for each of the other two phases of the other controllers C. The signal control unit 211 identifies a non-faulty controller C based on the first status signal and the second status signal output from each controller C. This configuration enables accurate determination of whether or not each controller C has a fault using digital signal processing. Furthermore, because the presence or absence of a fault in each controller C is determined using voltage command values ​​for two layers in a Cartesian coordinate system, the calculation load can be reduced.

[0061] In the multiplexing control device 210 of this embodiment, the three controllers C are a first controller C1, a second controller C2, and a third controller C3. The signal control unit 211 receives digital voltage signals from the first controller C1 and the second controller C2 as input. The signal control unit 211 includes a failure determination unit 72 that determines whether or not there is a failure in the first controller C1 based on the first status signal output from the second controller C2 and the third controller C3, and determines whether or not there is a failure in the second controller based on the second status signal output from the third controller; a selection unit 73 that selects and outputs a voltage command value in the digital voltage signal output by the controller C that is not at fault among the first and second controllers; an inverse Clarke conversion unit 74 that performs inverse Clarke conversion on the voltage command value output from the selection unit 73, and outputs digital voltage signals of three phases, namely, U phase, V phase, and W phase; and a PWM output unit 75 that outputs a PWM signal based on the three-phase digital voltage signals output from the inverse Clarke conversion unit 74. According to this configuration, it is possible to appropriately select the digital voltage signal of the controller C that is not malfunctioning from the first controller C1 or the second controller C2 and output the PWM signal.

[0062] In the multiplexing control device 210 of this embodiment, when both the first controller C1 and the second controller C2 are faulty, the selector 73 selects and outputs a value of 0 as the voltage command value. With this configuration, it is possible to prevent the motor 300 from running out of control when both the first controller C1 and the second controller C2 are faulty.

[0063] The present invention has been described above based on the embodiments. The embodiments are merely examples, and it will be understood by those skilled in the art that various modifications are possible in the combination of the respective components and treatment processes, and that such modifications are also within the scope of the present invention.

[0064] The functional configuration of each device described in the embodiments can be realized by hardware resources, software resources, or a combination of hardware and software resources. Examples of hardware resources include processors, ROMs, RAMs, CPLDs, and other LSIs. Examples of software resources include operating systems, applications, and other programs.

[0065] Among the embodiments disclosed in this specification, those in which multiple functions are provided in a distributed manner may have some or all of the multiple functions integrated together, and conversely, those in which multiple functions are provided in a distributed manner may have some or all of the multiple functions integrated together. Regardless of whether the functions are integrated or distributed, it is sufficient that the configuration can achieve the object of the invention. [Explanation of symbols]

[0066] 1 eVTOL, 10 main body, 20 arm, 30 rotating wing section, 35 blade, 50 battery, 100 upper control device, 200 motor control device, 210 multiplexing control device, 211 signal control section, 220 gate driver, 300 motor, 400 rotation detection sensor, C controller.

Claims

1. Three controllers output digital voltage signals including voltage command values ​​in a two-phase Cartesian coordinate system for the motor; a signal control unit that receives the digital voltage signals output from at least two of the three controllers, selects the digital voltage signal output by a controller that is not faulty among the controllers that output the received digital voltage signals based on a predetermined priority order, and outputs a PWM signal based on the selected digital voltage signal; Equipped with Each controller is a first state monitoring unit that outputs a first state signal indicating whether or not one of the other controllers has a fault based on a comparison between the voltage command values ​​for each of the two phases generated by the controller itself and the voltage command values ​​for each of the two phases of one of the other controllers; a second state monitoring unit that outputs a second state signal indicating whether or not the other of the other controllers has a failure based on a comparison between the voltage command values ​​for each of the two phases generated by the controller itself and the voltage command values ​​for each of the other two phases of the other controller; Including, The signal control unit selects the digital voltage signal output by the non-faulty controller based on the first status signal and the second status signal output from each controller.

2. the three controllers are a first controller, a second controller, and a third controller; the signal control unit receives the digital voltage signals from the first controller and the second controller; The signal control unit a failure determination unit that determines whether or not there is a failure in the first controller based on the first status signals output from the second controller and the third controller, and that determines whether or not there is a failure in the second controller based on the second status signals output from the first controller and the third controller; a selection unit that selects and outputs the voltage command value in the digital voltage signal output by the controller that is not faulty out of the first controller and the second controller; an inverse Clarke transformation unit that performs an inverse Clarke transformation on the voltage command value output from the selection unit to output digital voltage signals of three phases, i.e., a U phase, a V phase, and a W phase; a PWM output unit that outputs the PWM signal based on the three-phase digital voltage signal output from the inverse Clarke conversion unit; 2. The multiplexing control device of claim 1, comprising:

3. the selection unit selects and outputs a value of 0 as the voltage command value when both the first controller and the second controller are faulty.

3. The multiplexing control device according to claim 2.

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