Graphics processing method, apparatus and computer-readable storage medium

Abstract

This application relates to the field of graphics processing, and more particularly to a graphics processing method, an apparatus, and a computer-readable storage medium. The graphics processing method includes the steps of: obtaining a graphics object to be processed, the graphics object including a plurality of sub-graphics; performing graphics processing on the plurality of sub-graphics using a plurality of graphics processing modules; obtaining a memory space size required by each of the graphics processing modules when processing the sub-graphics; and allocating a corresponding number of memory units to each of the graphics processing modules based on the memory space size, so that each of the graphics processing modules processes at most one of the sub-graphics within one processing cycle. Compared to the prior art, the graphics processing method, the apparatus, and the computer-readable storage medium according to the embodiments of this application have the advantage of reducing the overall memory space requirement.

Description

[Technical Field]

[0001] The present application is in the field of graphics processing, and specifically relates to graphics processing methods, apparatus and computer-readable storage media. [Background technology]

[0002] With the development of machine vision and the Internet of Things, the requirements for the area and performance of graphics processor chips are increasing, as are the requirements for internal and external memory of the chips. For complex graphics processing, the graphics processor is divided into multiple graphics processing modules, and each of the multiple graphics processing modules processes a different part of the graphics simultaneously.

[0003] In different scenarios, the memory space used by each graphics processing module is not completely consistent depending on the sub-graphics processed by each graphics processing module. In the prior art, when allocating memory space to each graphics processing module, the maximum memory space required in different scenarios is allocated to each area to ensure normal operation of each graphics processing module, which places a high demand on the overall memory space size. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application aims to provide a graphics processing method, apparatus and computer-readable storage medium that can reduce the overall requirement for memory space. [Means for solving the problem]

[0005] In a first aspect, the present application provides a graphics processing method, the graphics processing method being used in a graphics processing device, the graphics processing device including a graphics processing means and a memory, the graphics processing means including a plurality of graphics processing modules, and the memory including a plurality of memory units, the graphics processing method comprising the steps of: acquiring graphics to be processed, the graphics including a plurality of sub-graphics; performing graphics processing on the sub-graphics using the plurality of graphics processing modules; acquiring a size of memory space required by each of the graphics processing modules when processing the sub-graphics; and allocating a corresponding number of the memory units to each of the graphics processing modules based on the size of the memory space, wherein each of the graphics processing modules processes at most one of the sub-graphics within one processing cycle.

[0006] Compared with the prior art, in the graphics processing method according to the embodiment of the present application, when each target graphic is processed by the graphics processing means, the target graphic is divided into a plurality of sub-graphics, and each graphics processing module in the graphics processing means processes one sub-graphic, and in this process, a corresponding number of memory units are allocated to each graphics processing module based on the size of memory space required by each graphics processing module when processing the corresponding sub-graphics. This allows memory units in the memory to be freely allocated without affecting the processing of the corresponding sub-graphics by each graphics processing module, and reduces the overall memory space requirement of the graphics processing means.

[0007] In an alternative embodiment, the step of allocating a corresponding number of the memory units to each of the graphics processing modules based on the size of the memory space includes the steps of: allocating a corresponding cache address to each of the graphics processing modules based on the number of the memory units; and establishing a correspondence between the cache address, the memory unit number, and an intra-unit address, where the intra-unit address is a storage address within the memory unit. The cache address is allocated to each graphics processing module based on the memory space requirement of each graphics processing module, and conversion is performed between the allocated cache address, the memory unit number, and the intra-memory unit address, thereby allowing the memory units allocated to each graphics processing module to be distributed at any location in memory, thereby making better use of the memory space in memory.

[0008] In an alternative embodiment, the step of performing graphics processing on the plurality of sub-graphics using the plurality of graphics processing modules includes the steps of obtaining write information and a corresponding write cache address, obtaining a target number and an address within the target unit of the memory unit corresponding to the write cache address based on the correspondence, and writing the write information to a storage location corresponding to the target number and the address within the target unit. When writing write information to memory, writing the write information to a storage location corresponding to the target number and the address within the target unit allows the write information to be written more accurately in memory units distributed throughout the memory.

[0009] In an alternative embodiment, the step of performing graphics processing on the plurality of sub-graphics using the plurality of graphics processing modules includes the steps of obtaining a read cache address, obtaining a target number and an address within the target unit of the memory unit corresponding to the read cache address based on the correspondence, and reading target information from a storage location corresponding to the target number and the address within the target unit. When reading the target information from memory, reading the target information from a storage location corresponding to the target number and the address within the target unit allows the target information to be read more accurately from memory units distributed throughout the memory.

[0010] In an alternative embodiment, after reading target information from a storage location corresponding to the target number and the address within the target unit, the graphics processing method further includes releasing a cache address corresponding to the target number and the address within the target unit. Releasing the corresponding cache address after the read operation allows the cache address to be used repeatedly, thereby improving the efficiency of memory space usage in the memory.

[0011] In an alternative embodiment, the step of performing graphics processing on the plurality of sub-graphics using the plurality of graphics processing modules includes the step of releasing all memory units allocated to the graphics processing module after each of the graphics processing modules has completed graphics processing on the sub-graphics. Releasing all memory units after graphics processing for each frame is completed facilitates reallocation and use of memory units in subsequent graphics processing steps, thereby improving memory space utilization efficiency.

[0012] In an alternative embodiment, the number of graphics to be processed is plural, and the graphics processing method includes determining the size of the memory unit based on the graphics formats and resolutions of the plural graphics to be processed. By determining the size of the memory unit based on the graphics formats and resolutions of all the plural graphics to be processed, memory space can be better divided and utilized according to actual needs.

[0013] In a second aspect, the present application provides a graphics processing device including a graphics processing means and a memory, the memory including a plurality of memory units, the graphics processing means including a graphics acquisition means, a plurality of graphics processing modules, and a memory unit allocation means, the graphics acquisition means being configured to acquire graphics to be processed, the graphics processing modules including a plurality of sub-graphics, the plurality of graphics processing modules being configured to perform graphics processing on the plurality of sub-graphics, each of the graphics processing modules processing at most one of the sub-graphics within one processing cycle, and the memory unit allocation means being configured to acquire a size of memory space required by each of the graphics processing modules when processing the sub-graphics, and to allocate a corresponding number of the memory units to each of the graphics processing modules based on the size of the memory space.

[0014] In an alternative embodiment, the graphics processing module further includes a cache address management sub-means, wherein the memory unit allocation means is configured to allocate a corresponding cache address to each of the graphics processing modules based on the number of the memory units, and the cache address management sub-means is configured to establish a correspondence between the cache address, the memory unit number, and an intra-unit address, the intra-unit address being a storage address within the memory unit.

[0015] In an optional embodiment, the graphics processing module further includes a cache write sub-means configured to obtain write information and a corresponding write cache address, obtain a target number and an address within the target unit of the memory unit corresponding to the write cache address based on the correspondence, and write the write information to a memory location corresponding to the target number and the address within the target unit.

[0016] In an optional embodiment, the graphics processing module further includes a cache read sub-means, which is configured to obtain a read cache address, obtain a target number and an address within the target unit of the memory unit corresponding to the read cache address based on the correspondence, and read target information from a memory location corresponding to the target number and the address within the target unit.

[0017] In an optional embodiment, after the cache read sub-means reads the target information from the memory location corresponding to the target number and the address within the target unit, the cache address management sub-means further releases the cache address corresponding to the target number and the address within the target unit.

[0018] In an alternative embodiment, after each of the graphics processing modules has completed graphics processing for the sub-graphics, the memory unit allocation means further releases all memory units allocated to the graphics processing module.

[0019] In an alternative embodiment, the number of graphics to be processed is plural, and the memory unit allocation means further determines the size of the memory unit based on the graphics format and resolution of the plurality of graphics to be processed.

[0020] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored therein, the computer program being executed by a processor to realize a graphics processing method according to any one of the above embodiments.

[0021] Compared with the prior art, in the graphics processing method, apparatus, and computer-readable storage medium according to the embodiments of the present application, by allocating a corresponding number of memory units to each graphics processing module based on the size of memory space required by each graphics processing module when processing the corresponding sub-graphics, memory units in the memory can be freely allocated without affecting the processing of the corresponding sub-graphics by each graphics processing module, and the overall memory space requirement of the graphics processing means can be reduced.

[0022] In order to more clearly explain the technical solutions of the embodiments of the present application, the drawings used in the embodiments will be briefly described below. The drawings described are only for illustrating some embodiments of the present application and are not intended to limit the scope. Those skilled in the art can obtain other related drawings based on these drawings without using inventive abilities. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a schematic flowchart of a graphics processing method according to a first embodiment of the present application; [Figure 2] 1 is a schematic diagram showing the correspondence between a cache address, a memory unit number, and an address within the unit in a graphics processing method according to a first embodiment of the present application; [Figure 3] FIG. 10 is a schematic configuration diagram of a graphics processing device according to a second embodiment of the present application. [Figure 4]FIG. 10 is a schematic configuration diagram of a graphics processing device according to another embodiment of the present application. [Figure 5] 1 is a schematic flow chart of an exemplary graphics processing method in the present application. DETAILED DESCRIPTION OF THE INVENTION

[0024] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings used in the embodiments of the present application. The described embodiments are only some of the embodiments of the present application, and are not all of the embodiments. The components in the embodiments of the present application shown in the drawings can be arranged and designed in various arrangement ways.

[0025] Therefore, the following detailed description of the embodiments of the present application shown in the drawings merely illustrates selected embodiments of the present application and does not limit the scope of the present application to be protected. All other embodiments that a person skilled in the art can obtain based on the embodiments of the present application without using his or her inventive abilities also fall within the scope of protection of the present application.

[0026] Like reference numerals refer to like objects in the drawings, so that a definition in one drawing does not require further definition or interpretation in other drawings.

[0027] In the description of this application, directions or positional relationships expressed by terms such as "upper," "lower," "inner," and "outer" are based on the drawings or are the normal arrangement directions or positional relationships of the inventive products, and are merely for the purpose of simply and concisely explaining this application. They do not expressly or imply that the relevant devices or elements necessarily have a specific orientation or are configured or operated in a specific direction, and therefore do not limit this application.

[0028] Additionally, terms such as "first," "second," etc. are for descriptive purposes only and do not express or imply any relative importance.

[0029] Unless there is a contradiction, the features in the embodiments of the present application can be combined with each other.

[0030] Embodiment 1 of the present application provides a graphics processing method, which is used in a graphics processing device, where the graphics processing device includes a graphics processing means and a memory, the graphics processing means includes a plurality of graphics processing modules, and the memory includes a plurality of memory units. As shown in Figure 1, the graphics processing method includes the following steps:

[0031] Step S101: A graphics object including a plurality of sub-graphics is obtained.

[0032] In this step, the target graphics to be processed is an image to be processed by the graphics processing unit, and may be different images in different embodiments. For example, in some embodiments of the present application, the target graphics to be processed is an image frame in a video, or in other embodiments of the present application, the target graphics to be processed is an image in an image set during a model training process, etc. In different application scenarios, the target graphics to be processed may be different images.

[0033] In this step, each sub-graphic is a part of the target graphics, i.e., one target graphics can be divided into multiple sub-graphics. In different embodiments of the present application, the sub-graphics are different parts of the target graphics. For example, in some embodiments of the present application, the target graphics are divided into regions, and the part of the target graphics in each region is a sub-graphic. In other embodiments of the present application, the target graphics are divided into layers, and each layer of the target graphics is formed as a sub-graphic. In different application scenarios, the sub-graphics can be different parts of the target graphics.

[0034] In some embodiments of the present application, the method of dividing each target graphic into sub-graphics may be different. For example, in a moving image application, a series of frame images may be used as the target graphic, and each frame image may be divided into sub-graphics using a different method. Specific methods can be freely set according to actual needs.

[0035] In addition, in different embodiments of the present application, the division of the target graphics into multiple sub-graphics may be performed by the graphics processing means of the embodiment of the present application, or may be performed by other means, in which case the graphics processing means of the embodiment of the present application can directly obtain each sub-graphics when obtaining the target graphics, and specific settings can be freely made according to actual needs.

[0036] Step S102: Perform graphics processing on the multiple sub-graphics using multiple graphics processing modules.

[0037] In this step, each graphics processing module processes at most one subgraphic within one processing cycle. During the graphics processing of one target graphic, subgraphics are assigned to multiple graphics processing modules based on the number of subgraphics actually processed. For example, if the number of subgraphics is fewer than the number of graphics processing modules, one subgraphic is assigned to each of the graphics processing modules for graphics processing, while no subgraphics are assigned to other graphics processing modules. If the number of subgraphics is equal to the number of graphics processing modules, one subgraphic is assigned to each of the graphics processing modules for graphics processing. If the number of subgraphics is greater than the number of graphics processing modules, one or more subgraphics are assigned to each of the graphics processing modules for graphics processing. Regardless of the number of subgraphics assigned to each graphics processing module, one graphics processing module processes only one subgraphic within one processing cycle, i.e., one module processing subprocess. If multiple subgraphics are assigned to one graphics processing module for graphics processing, the graphics processing module processes only one subgraphic at a time, and after processing this subgraphic, it processes the other subgraphics.

[0038] Step S103: The size of memory space required by each graphics processing module when processing sub-graphics is obtained.

[0039] In different embodiments of the present application, the size of memory space required by each graphics processing module when processing sub-graphics may be obtained by the graphics processing means of the embodiment of the present application, and may be determined based on graphics parameters such as the size, resolution, and graphics format of the sub-graphics, or may have been determined by other means. In this case, the size of memory space required for processing each sub-graphics when the graphics processing means of the embodiment of the present application obtains the graphics to be processed is directly obtained. Specifically, the size of memory space may be freely set according to actual needs.

[0040] Step S104: Allocate a corresponding number of memory units to each graphics processing module based on the size of the memory space.

[0041] In this step, a memory unit is the smallest storage unit in memory for allocating memory space. That is, when allocating memory space, memory units are allocated in integer numbers, for example, 2, 3, 4, 5, 6, etc., to one graphics processing module. If the memory space required by one graphics processing module is not an integer multiple of the memory space of the memory unit, the memory units can be allocated using a round-up method. For example, if the memory space required by one graphics processing module is 1.5 times the memory space of the memory unit, two memory units are allocated to the graphics processing module.

[0042] The size of the memory unit can be determined based on actual needs. When the graphics processing means processes multiple related graphics objects at once, such as when performing graphics processing on each frame image of a single video image, the size of the memory unit is determined based on graphics data such as the graphics format, resolution, and size of all the graphics objects. For example, the size of the memory unit can be determined based on the memory space required by each of the graphics objects, using the greatest common divisor, or a fraction of the greatest common divisor. In some other embodiments of the present application, the size of the memory unit can be determined based on the method of dividing the sub-graphics, and can be freely set according to actual needs.

[0043] In some embodiments of the present application, the process of allocating a corresponding number of memory units to each graphics processing module involves allocating a corresponding cache address to each graphics processing module based on the number of memory units allocated to each graphics processing module. For example, in some embodiments of the present application, if three memory units are allocated to graphics processing module A1, cache addresses 0 to 3A-1 are allocated to graphics processing module A1; if four memory units are allocated to graphics processing module A2, cache addresses 3A to 7A-1 are allocated to graphics processing module A2; and other situations are also determined in this manner.

[0044] As shown in FIG. 2, after assigning cache addresses to each graphics processing module, a correspondence relationship is established between the cache addresses 0 to nA-1, the memory unit numbers 0 to n-1, and the intra-unit addresses 0 to A-1, where the intra-unit addresses are storage addresses within the memory units. The memory unit numbers identify which memory units correspond to the cache addresses, and the intra-memory unit storage addresses are storage addresses within each memory unit, where one memory unit contains intra-memory unit storage addresses 0 to A-1, and A is the size of the memory unit's memory space. Each cache address corresponds to one {memory unit number, intra-memory unit storage address}. For example, if the cache address is 2A-15, the correspondence relationship is {1, A-15}, where 1 is the memory unit number and A-15 is the storage location of the cache address A-15 within the memory unit whose number is 1. A cache address is assigned to each graphics processing module based on the memory space requirement of each graphics processing module, and a conversion is performed between the assigned cache address, the memory unit number, and the address within the memory unit. When searching for each cache address, the corresponding memory unit is searched for based on the corresponding memory unit number, and the corresponding storage address is searched for based on the address within the unit. This allows the memory units assigned to each graphics processing module to be distributed at any position in memory, eliminates the need to assign consecutive memory areas to each graphics processing module, and enables better utilization of memory space in memory.

[0045] For example, a process of performing graphics processing on multiple sub-graphics using multiple graphics processing modules includes a write operation, i.e., writing write information that needs to be written to memory to memory. The write operation process first obtains the write information and its corresponding write cache address, where the write cache address is the address of the memory area to which the write information is written. Then, based on the correspondence, the target number and address within the target unit of the memory unit corresponding to the write cache address are obtained, and the write information is written to a storage location corresponding to the target number and address within the target unit. When writing the write information to memory, writing the write information to a storage location corresponding to the target number and address within the target unit allows the write information to be written more accurately to memory units distributed throughout the memory.

[0046] In some embodiments of the present application, the write information may be, for example, pixel point information of the graphics to be processed, and after writing the pixel point information to a memory unit in the memory, a correspondence relationship between the pixel point information and the write cache address is established.

[0047] Furthermore, the process of using multiple graphics processing modules to perform graphics processing on multiple sub-graphics further includes a read operation, i.e., reading target information stored in memory from memory. In the read operation, a read operation address, i.e., the address of the storage of the target information, is first obtained, and then the target number and intra-target address of the memory unit corresponding to the read cache address are obtained based on the correspondence, and the target information is read from the storage location corresponding to the target number and intra-target address. When reading the target information from memory, reading the target information from the storage location corresponding to the target number and intra-target address allows for more accurate reading of the target information from memory units distributed throughout the memory.

[0048] In some embodiments of the present application, the target information may also be, for example, pixel point information of the graphics to be processed. In this case, the read operation address is obtained based on, for example, the correspondence between the pixel point information and the write cache address, and the cache address corresponding to the pixel point information in the target information is used as the read operation address.

[0049] In some embodiments of the present application, the method further includes freeing a cache address corresponding to the target number and the address within the target unit after reading the target information from the storage location corresponding to the target number and the address within the target unit. After the cache address is freed, when a write operation is performed, the freed cache address can be reused to write data to the corresponding cache location, thereby allowing the cache address to be used repeatedly and improving the utilization efficiency of memory space in the memory.

[0050] In some embodiments of the present application, after each graphics processing module completes its graphics processing for a sub-graphics block, all memory units allocated to that graphics processing module are released. For example, if graphics processing module A1 allocates three memory units numbered 0, 1, and 2 to graphics processing module A1 during the processing of sub-graphics block B1, the three memory units numbered 0, 1, and 2 are released after the processing of sub-graphics block B1 by graphics processing module A1 is completed. These memory units can then be allocated to other graphics processing modules or reallocated to graphics processing module A1 for use in processing other sub-graphics blocks. Releasing all memory units after the graphics processing for each frame is completed facilitates the reallocation and use of memory units in subsequent graphics processing steps, thereby improving the efficiency of memory space utilization.

[0051] In addition, in some embodiments of the present application, before a read or write operation is performed, arbitration may be performed on the read and write operations, and only the read and write operations that meet the requirements can be performed.

[0052] Compared with the prior art, in the graphics processing method according to Example 1 of the present application, when each target graphic is processed by the graphics processing means, the target graphic is divided into a plurality of sub-graphics, and each graphics processing module in the graphics processing means processes one sub-graphic, and in this process, a corresponding number of memory units are allocated to each graphics processing module based on the size of memory space required by each graphics processing module to process the corresponding sub-graphics. This allows for free allocation of memory units in the memory without affecting the processing of the corresponding sub-graphics by each graphics processing module, and reduces the overall memory space requirement of the graphics processing means.

[0053] In a specific embodiment of the present application, in an example where the number of images to be processed is three, for example, one memory granule is used as a memory unit, and the size of one memory granule is 32 KB (a total of 32 storage locations, each of which is 1 KB in size). In this case, the processing process includes the following:

[0054] Scene 1: Process image 1. Subgraphics 0 requires 2 memory units, subgraphics 1 requires 2 memory units, subgraphics 2 requires 1 memory unit, and subgraphics 3 requires 2 memory units.

[0055] Scene 2: Processing image 2. Subgraphics 0 requires 4 memory units, subgraphics 1 requires 1 memory unit, subgraphics 2 requires 2 memory units, and subgraphics 3 requires none.

[0056] Scene 3: Process image 3. Subgraphics 0 requires 3 memory units, subgraphics 1 requires 3 memory units, subgraphics 2 requires 1 memory unit, and subgraphics 3 requires 1 memory unit.

[0057] A single sub-graphic requires a maximum of four memory units, and eight memory units are required to process image 3. According to the graphics processing method of the embodiment of the present application, the total size of the memory space only needs to be eight memory units, whereas the prior art graphics processing method requires four memory units for each sub-graphic, for a total of 16 memory units.

[0058] There are eight 32KB memory units, e.g., eight 32KB memory granules, numbered grp0, grp1, grp2, ..., grp7, with corresponding cache address ranges of 0-31 {0, 0-31}, 32-63 {1, 0-31}, 64-95 {2, 0-31}, ..., 224-255 {7, 0-31}. In a graphics processing method according to an embodiment of the present application, when processing each target graphic, the number of memory granules to be allocated to each sub-graphic is determined, and the memory unit allocation means assigns the corresponding memory granule number to the corresponding sub-graphic. For example, when processing target graphic 1, sub-graphic 0 uses grp2 and grp3, totaling 64KB of memory space, and sub-graphic 1 uses grp7, grp0, and grp1, totaling 96KB of memory space. Based on the size of the space currently to be allocated to the sub-graphics notified by the software, the cache address management sub-means assigns an address in the corresponding memory space. For example, if a 96 KB memory space is allocated to sub-graphics 1, the cache address management sub-means assigns addresses 0 to 95 to sub-graphics 1. Addresses 0 to 31 correspond to the memory granule grp7, addresses 32 to 63 correspond to the memory granule grp0, and addresses 64 to 95 correspond to the memory granule grp1. When the cache address management sub-means and the cache read sub-means use a read cache address to read a pixel point, they convert the corresponding address into a target number and an address within the target unit of {memory granule number grpN, 0 to 31} and send them to the memory access management means. After receiving the target number and address within the target unit, the memory access management means converts them into an access signal for the corresponding memory granule based on the memory granule number grpN higher than the address, and executes data reading in accordance with the access signal.

[0059] Processing graphics 1 corresponds to scene 1, and processing graphics 2 corresponds to scene 2. In this case, when processing graphics 1, the memory unit allocating means allocates grp0 and grp1 to subgraphics 0, grp2 and grp3 to subgraphics 1, grp4 to subgraphics 2, and grp5 and grp6 to subgraphics 3. When processing graphics 2, the memory unit allocating means allocates grp7, grp0, grp1, and grp2 to subgraphics 0, grp3 to subgraphics 1, grp4 and grp5 to subgraphics 2, and no allocation to subgraphics 3.

[0060] When processing sub-graphics 0 in graphics 1, a 64 KB memory space is allocated, the cache address management sub-means releases addresses 0 to 63, the cache write sub-means matches them with addresses 0 to 63 based on the numbers grp0 and grp1, sends a write access {0 / 1, 0 to 31}, and writes corresponding info information to the cache address management sub-means, the info information includes the correspondence between pixel point information and write cache addresses, and based on the info information, the cache read sub-means sets the cache address corresponding to the coordinates of the requested pixel point as the read cache address. After the cache read sub-means identifies the address, it matches it with the cache address based on the granule number and sends a read access {0 / 1, 0-31}. After reading the cache pixel point, it releases the address to the cache address management sub-means, which then releases the address to the cache write sub-means for reuse. After processing of one graphics object is completed, the cache read sub-means releases the memory granule to the memory unit allocation means and notifies it that grp0 and grp1 may be reclaimed since the cache space is no longer needed. Then, based on the higher order address of the read / write access, the memory granule that is the target of local access is obtained and converted into the corresponding access timing.

[0061] Processing sub-graphics 0 of graphics 2 requires allocation of 128 KB of memory space. 32 KB of cache space for grp7 remains for processing graphics 1. After processing sub-graphics 0 of graphics 1 is completed, grp0 and grp1 are released. In this case, allocation of the 128 KB of memory space to sub-graphics 0 of graphics 2 must wait until the space is released after processing of other sub-graphics of graphics 1 is completed. After the allocation is completed, processing of sub-graphics 0 begins, corresponding to memory granule numbers grp7, grp0, grp1, and grp2. The cache address management sub-means releases addresses 0 to 127, and the cache write sub-means matches them with addresses 0 to 127 based on the numbers grp7, grp0, grp1, and grp2, sends write access {7 / 0 / 1 / 2, 0 to 31}, and writes the corresponding info information to the cache address management sub-means. Based on the info information, the cache read sub-means matches the requested pixel point information with the read cache address. After the cache read sub-means identifies the address, it matches it with the cache address based on the granule number and sends a read access {7 / 0 / 1 / 2, 0-31}. After reading the cache pixel point information, it releases the address to the cache address management sub-means, which then releases the address to the cache write sub-means for reuse. After reading all pixel points of graphics 2 has been completed, the cache read sub-means releases the granule to the memory unit allocation means and notifies it that grp7, grp0, grp1 and grp2 may be reclaimed since the cache space is no longer needed.

[0062] A second embodiment of the present application provides a graphics processing device, which includes: a graphics processing means 100 and a memory 200, and the memory 200 includes a plurality of memory units 201. As shown in FIG.

[0063] The graphics processing means 100 includes a graphics acquisition means 101, a plurality of graphics processing modules 102, and a memory unit allocation means 103. The graphics acquisition means 101 is configured to acquire graphics to be processed, which include a plurality of sub-graphics. The plurality of graphics processing modules 102 are configured to perform graphics processing on the plurality of sub-graphics, with each graphics processing module 102 processing at most one sub-graphics. The memory unit allocation means 103 is configured to acquire the size of memory space required by each graphics processing module 102 when processing the sub-graphics, and to allocate a corresponding number of memory units to each graphics processing module based on the size of the memory space.

[0064] In some embodiments of the present application, the graphics processing means 100 is a graphics processor, and the memory 200 is an external storage device connected to the graphics processor. In other embodiments of the present application, the graphics processing means 100 is a part of the graphics processor, and the memory 200 is also a part of the graphics processor, i.e., the memory 200 is an internal cache unit in the graphics processor.

[0065] Compared with the prior art, in the graphics processing device according to the second embodiment of the present application, when the graphics processing means 100 processes each target graphic, the graphics acquisition means 101 divides the target graphic into a plurality of sub-graphics, and each graphics processing module 102 processes one sub-graphic. In this process, a corresponding number of memory units 201 are allocated to each graphics processing module 102 based on the size of memory space required by each graphics processing module 102 to process the corresponding sub-graphics. This allows the memory units 201 in the memory 200 to be freely allocated without affecting the processing of the corresponding sub-graphics by each graphics processing module 102, and reduces the overall memory space requirement of the graphics processing means 100.

[0066] In some other embodiments of the present application, as shown in FIG. 4, the graphics processing module 102 includes a cache write sub-means 1021, a cache read sub-means 1022, and a cache address management sub-means 1023.

[0067] The memory unit allocation means 103 allocates a cache unit to each graphics processing module 102 and allocates a cache address to each graphics processing module 102. The cache address management sub-means 1023 is configured to establish a correspondence between the cache address, the memory unit number, and the intra-unit address, where the intra-unit address is a storage address within the memory unit.

[0068] The cache write sub-means 1021 is configured to obtain write information and a corresponding write cache address, obtain a target number of a memory unit corresponding to the write cache address and an address within the target unit based on the correspondence established by the cache address management sub-means 1023, and write the write information to a storage location corresponding to the target number and address within the target unit. After writing of the information is completed, the cache address management sub-means 1023 includes, for example, a first part 1024, which notifies the cache read sub-means 1022 of the number of the written information, the storage location corresponding to the address within the unit, and the corresponding write cache address, so that the cache read sub-means 1022 can later read the information from the storage locations where the information was written.

[0069] The cache read sub-means 1022 is configured to obtain a read cache address, obtain a target number and an address within the target unit of the memory unit corresponding to the read cache address based on the correspondence, and read target information from a storage location corresponding to the target number and the address within the target unit. After the cache read sub-means 1022 reads the target information from the storage location corresponding to the target number and the address within the target unit, the cache address management sub-means 1023, for example, includes a second part 1025, which releases the cache address corresponding to the target number and the address within the target unit so that the cache write sub-means 1021 can rewrite data to the already released cache location.

[0070] The cache address management sub-means 1023 converts the allocated cache address, the memory unit number, and the address within the memory unit, so that the memory units allocated to each graphics processing module can be distributed to different locations in the memory, thereby making better use of the memory space in the memory.

[0071] In addition, in some embodiments of the present application, the memory unit allocation means 103 is further configured to release all memory units allocated to each graphics processing module 102 after the graphics processing for the sub-graphics by that graphics processing module 102 is completed.

[0072] In some embodiments of the present application, the number of graphics to be processed is plural, and the memory unit allocating means 103 further determines the size of the memory unit based on the graphics format and resolution of the plural graphics to be processed.

[0073] Hereinafter, a graphics processing device and a graphics processing method according to an embodiment of the present application will be described with reference to an example. The following is merely a specific embodiment of the present application and is not intended to be limiting. As shown in FIG. 5, the following is specifically included:

[0074] The process of allocating memory units in advance before processing the graphics to be processed includes determining the size of the memory units in step S501. Specifically, for example, the memory unit allocation means 103 determines the size of the memory units based on the graphics format and resolution of the graphics to be processed.

[0075] S502: Allocate a memory unit. Specifically, for example, the memory unit allocation means 103 allocates a memory unit to the cache address management sub-means 1023.

[0076] During the process of processing the graphics to be processed, it is determined in real time whether the graphics to be processed have been processed. Specifically, it includes the following steps: S503: Determine whether the graphics to be processed have been processed. If they have been processed, execute S504; if they have not been processed, execute S506 or S512.

[0077] S504: The cache read sub-means releases all memory units to the memory unit allocation means. Since the graphics to be processed has been processed and the cache read sub-means no longer uses the memory units, all memory units are released to the memory unit allocation means 103 so that they can be reallocated.

[0078] S505: The memory unit allocation means releases all memory units. All memory units are released by the memory unit allocation means 103, so that other subsequent means can use the memory units.

[0079] When processing the graphics to be processed, a data write operation and a data read operation are performed. The data write operation specifically includes the following steps: S506: Allocate a write cache address. Specifically, the memory unit allocation means 103 allocates a write cache address to the cache write sub-means 1021.

[0080] S507: Determine the target number and the address in the target unit of the memory unit corresponding to the write cache address. Specifically, obtain the target number and the address in the target unit of the memory unit corresponding to the write cache address based on the correspondence established by the cache address management sub-means.

[0081] S508: Light information is acquired. Specifically, the light information is pixel point information, such as coordinate information, corresponding to the graphics to be processed.

[0082] S509: Perform round-robin arbitration. Specifically, performing round-robin arbitration determines whether the corresponding read operation or write operation is permitted. If the arbitration result indicates that the corresponding read operation or write operation is permitted, the cache write sub-means 1021 performs the corresponding write operation, or the cache read sub-means 1022 performs the corresponding read operation. If the arbitration result indicates that the corresponding read operation or write operation is not permitted, the cache write sub-means 1021 temporarily stops the corresponding write operation, or the cache read sub-means 1022 temporarily stops the corresponding read operation.

[0083] S510: Write the write information to the memory unit. Specifically, the cache write sub-means 1021 writes the write information to the storage location of the address in the target unit in the memory unit 201 with the target number corresponding to the write cache address.

[0084] S511: Determine the correspondence between the write cache address and the write information. Specifically, the write information may be, for example, pixel point information of the graphics to be processed. After the pixel point information is written to the memory unit 201 in the memory, the correspondence between the pixel point information and the write cache address is established, and the correspondence between the pixel point information and the write cache address is sent to the cache address management sub-means 1023.

[0085] The data read operation specifically includes the following steps: S512: Determine target information of the read operation. Specifically, the target information is, for example, pixel point information, such as coordinate information, corresponding to the graphics to be processed.

[0086] S513: Determine the read operation address. Specifically, obtaining the read operation address involves, for example, determining the cache address corresponding to the pixel point information in the target information as the read operation address based on the correspondence between the pixel point information and the write cache address.

[0087] S514: The memory unit and the address within the unit corresponding to the read operation are determined.

[0088] S509: Perform round-robin arbitration. Specifically, performing round-robin arbitration determines whether the corresponding read operation or write operation is permitted. If the arbitration result indicates that the corresponding read operation or write operation is permitted, the cache write sub-means 1021 performs the corresponding write operation, or the cache read sub-means 1022 performs the corresponding read operation. If the arbitration result indicates that the corresponding read operation or write operation is not permitted, the cache write sub-means 1021 temporarily stops the corresponding write operation, or the cache read sub-means 1022 temporarily stops the corresponding read operation.

[0089] S515: Read the target information and release the corresponding read operation address.

[0090] A third embodiment of the present application provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the above-described method embodiment is realized.

[0091] As will be understood by those skilled in the art, all or part of the steps of the methods according to the above embodiments can be realized by instructing related hardware through a program. The program is stored in a storage medium and includes multiple commands for causing a device (which may be a microcontroller, chip, etc.) or a processor to execute all or part of the steps of the methods according to the embodiments of the present application. The storage medium includes various media capable of storing program code, such as a USB disk, a portable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0092] The above are only specific embodiments of the present application, and the scope of protection of the present application is not limited thereto. Any modifications or substitutions made by those skilled in the art within the technical scope disclosed in the present application will fall within the scope of protection of the present application. Therefore, the scope of protection of the present application is subject to the scope of the claims.

Claims

1. 1. A graphics processing method comprising: The graphics processing method is used in a graphics processing device, the graphics processing device including a graphics processing means and a memory, the graphics processing means including a plurality of graphics processing modules, and the memory including a plurality of memory units, the graphics processing method comprising: obtaining a target graphic including a plurality of subgraphics; performing graphics processing on the plurality of sub-graphics using the plurality of graphics processing modules; obtaining the size of memory space required by each of the graphics processing modules when processing the sub-graphics; and allocating a corresponding number of the memory units to each of the graphics processing modules based on the size of the memory space; each of said graphics processing modules processes at most one of said sub-graphics within one processing cycle; the step of allocating a corresponding number of the memory units to each of the graphics processing modules based on the size of the memory space, assigning a corresponding cache address to each of the graphics processing modules based on the number of memory units; and establishing a correspondence between the cache address, the memory unit number, and an intra-unit address, the intra-unit address being a storage address within the memory unit. A graphics processing method comprising:

2. The step of performing graphics processing on the plurality of sub-graphics using the plurality of graphics processing modules includes: obtaining write information and a corresponding write cache address; obtaining a target number and an address within the target unit of the memory unit corresponding to the write cache address based on the correspondence; writing the write information to a storage location corresponding to the target number and the address within the target unit.

2. The graphics processing method of claim 1.

3. The step of performing graphics processing on the plurality of sub-graphics using the plurality of graphics processing modules includes: obtaining a read cache address; obtaining a target number and an address within the target unit of the memory unit corresponding to the read cache address based on the correspondence; reading target information from a storage location corresponding to the target number and the address within the target unit.

2. The graphics processing method of claim 1.

4. After the step of reading target information from a storage location corresponding to the target number and the target intra-unit address, the graphics processing method includes: and releasing a cache address corresponding to the target number and the target unit address.

4. The graphics processing method of claim 3.

5. The step of performing graphics processing on the plurality of sub-graphics using the plurality of graphics processing modules includes: and releasing all memory units allocated to the graphics processing module after the graphics processing for the sub-graphics by each of the graphics processing modules is completed.

2. The graphics processing method of claim 1.

6. A graphics processing method, comprising: The graphics processing method is used in a graphics processing device, the graphics processing device including a graphics processing means and a memory, the graphics processing means including a plurality of graphics processing modules, and the memory including a plurality of memory units, the graphics processing method comprising: obtaining a target graphic including a plurality of subgraphics; performing graphics processing on the plurality of sub-graphics using the plurality of graphics processing modules; obtaining the size of memory space required by each of the graphics processing modules when processing the sub-graphics; and allocating a corresponding number of the memory units to each of the graphics processing modules based on the size of the memory space; each of said graphics processing modules processes at most one of said sub-graphics within one processing cycle; the number of graphics to be processed is plural, and the graphics processing method includes: determining a size of the memory unit based on a graphics format and a resolution of the plurality of graphics to be processed. A graphics processing method comprising:

7. 1. A graphics processing unit comprising: a graphics processing means and a memory, the memory including a plurality of memory units; the graphics processing means includes a graphics acquisition means, a plurality of graphics processing modules, and a memory unit allocation means, wherein the graphics acquisition means is configured to acquire graphics to be processed, the graphics including a plurality of sub-graphics, the plurality of graphics processing modules are configured to perform graphics processing on the plurality of sub-graphics, each of the graphics processing modules processes at most one of the sub-graphics within one processing cycle, and the memory unit allocation means is configured to acquire a size of memory space required by each of the graphics processing modules when processing the sub-graphics, and allocate a corresponding number of the memory units to each of the graphics processing modules based on the size of the memory space; The graphics processing module further includes a cache address management sub-means; The memory unit allocation means is configured to allocate a corresponding cache address to each of the graphics processing modules based on the number of the memory units, and the cache address management sub-means is configured to establish a correspondence between the cache address, the number of the memory unit, and an intra-unit address, the intra-unit address being a storage address within the memory unit. A graphics processing device comprising:

8. The graphics processing module further includes a cache write sub-means; The cache write sub-means is configured to obtain write information and a write cache address corresponding thereto, obtain a target number and an address within the target unit of the memory unit corresponding to the write cache address based on the correspondence relationship, and write the write information to a storage location corresponding to the target number and the address within the target unit.

8. The graphics processing unit of claim 7.

9. The graphics processing module further includes a cache read sub-means; The cache read sub-means is configured to acquire a read cache address, acquire a target number and an address within the target unit of the memory unit corresponding to the read cache address based on the correspondence relationship, and read target information from a storage location corresponding to the target number and the address within the target unit.

8. The graphics processing unit of claim 7.

10. After the cache read sub-means reads the target information from the storage location corresponding to the target number and the address within the target unit, the cache address management sub-means further releases the cache address corresponding to the target number and the address within the target unit. The graphics processing unit of claim 9 .

11. After each of the graphics processing modules has completed the graphics processing for the sub-graphics, the memory unit allocation means further releases all the memory units allocated to the graphics processing module.

8. The graphics processing unit of claim 7.

12. A graphics processing unit, comprising: a graphics processing means and a memory, the memory including a plurality of memory units; the graphics processing means includes a graphics acquisition means, a plurality of graphics processing modules, and a memory unit allocation means, wherein the graphics acquisition means is configured to acquire graphics to be processed, the graphics including a plurality of sub-graphics, the plurality of graphics processing modules are configured to perform graphics processing on the plurality of sub-graphics, each of the graphics processing modules processes at most one of the sub-graphics within one processing cycle, and the memory unit allocation means is configured to acquire a size of memory space required by each of the graphics processing modules when processing the sub-graphics, and allocate a corresponding number of the memory units to each of the graphics processing modules based on the size of the memory space; The number of the graphics to be processed is plural, and the memory unit allocation means further determines the size of the memory unit based on the graphics format and resolution of the plural graphics to be processed. A graphics processing device comprising:

13. A computer-readable storage medium, comprising: A computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the graphics processing method according to any one of claims 1 to 6 is realized. A computer-readable storage medium comprising:

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