Integrated circuit and power supply circuit

Abstract

To provide an integrated circuit and a power supply circuit that properly detects the voltage from an auxiliary coil.SOLUTION: There is provided an integrated circuit 42 that outputs a drive signal Vg that drives a transistor of a power supply circuit that generates output voltage of a target level from an input voltage, including a transformer with primary, secondary and auxiliary coils, and a transistor that controls the current flowing through the primary coil. Also included are a VCC terminal to which voltage corresponding to the coil voltage of the auxiliary coil is applied when the transistor is off, an FB terminal to which a feedback voltage corresponding to the output voltage is applied, a CS terminal to which voltage corresponding to the current flowing through the transistor is applied when the transistor is on, and voltage corresponding to the coil voltage is applied when the transistor is off, a detection circuit 60 that detects whether the voltage of the CS terminal is lower than a first reference voltage when the transistor is off, and a control circuit that controls the transistor switching based on the feedback voltage, the voltage of the CS terminal when the transistor is on, and the detection result of the detection circuit.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an integrated circuit and a power supply circuit. [Background technology]

[0002] Some AC-DC converters generate voltages in the secondary coil and auxiliary coil by switching a transistor that controls the inductor current in the primary coil of the transformer. In such AC-DC converters, the integrated circuit that drives the transistor generally operates using the voltage from the auxiliary coil as its power supply voltage.

[0003] Some integrated circuits include a detection circuit that detects the power of the load based on the voltage level of the power supply terminal to which the power supply voltage from the auxiliary coil is applied, and changes the mode in which the transistor is driven (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-127109 Summary of the Invention [Problem to be solved by the invention]

[0005] Generally, the power supply voltage of the power supply terminal of an integrated circuit is generated based on the voltage from the auxiliary coil, and therefore can vary significantly due to the superposition of noise, etc. Furthermore, the number of turns of the auxiliary coil, etc., of the power supply voltage is set taking into consideration other circuits connected to the power supply terminal (for example, a circuit that detects a drop in the power supply voltage), so it has been difficult to operate the above-mentioned detection circuit appropriately based on the voltage of the power supply terminal.

[0006] The present invention has been made in view of the above-mentioned problems in the prior art, and an object of the present invention is to provide an integrated circuit that can appropriately detect the voltage from the auxiliary coil. [Means for solving the problem]

[0007] A first aspect of the integrated circuit of the present invention that solves the above-mentioned problems is an integrated circuit that drives the transistor of a power supply circuit that generates an output voltage of a target level from an input voltage, and includes a transformer including a primary coil, a secondary coil, and an auxiliary coil, and a transistor that controls the current flowing in the primary coil, and includes: a first terminal to which a voltage corresponding to the coil voltage of the auxiliary coil is applied when the transistor is off; a second terminal to which a feedback voltage corresponding to the output voltage is applied; a third terminal to which a voltage corresponding to the current flowing in the transistor is applied when the transistor is on and a voltage corresponding to the coil voltage is applied when the transistor is off; a first detection circuit that detects whether the voltage at the third terminal when the transistor is off is lower than a first reference voltage; and a control circuit that controls switching of the transistor based on the feedback voltage, the voltage at the third terminal when the transistor is on, and the detection result of the first detection circuit.

[0008] A first aspect of the power supply circuit of the present invention that solves the above-mentioned problems is a power supply circuit that generates an output voltage of a target level from an input voltage, comprising: a transformer including a primary coil, a secondary coil, and an auxiliary coil; a transistor that controls a current flowing through the primary coil; and an integrated circuit having first to third terminals and driving the transistor, the power supply circuit including: a first diode that rectifies a coil voltage of the auxiliary coil; a first capacitor connected to the first terminal and charged with a current from the first diode; a detection resistor connected to the third terminal and detecting a current flowing through the transistor when it is on; a second diode that rectifies the coil voltage; and a second capacitor connected to the third terminal and charged with a current from the second diode, the integrated circuit including a first detection circuit that detects whether a voltage at the third terminal when the transistor is off is lower than a first reference voltage; and a control circuit that controls switching of the transistor based on a feedback voltage applied to the second terminal, the voltage at the third terminal when the transistor is on, and the detection result of the first detection circuit.

[0009] A second aspect of the integrated circuit of the present invention that solves the above-mentioned problems is an integrated circuit that drives the transistor of a power supply circuit that generates an output voltage of a target level from an input voltage, and includes a transformer including a primary coil, a secondary coil, and an auxiliary coil, and a transistor that controls the current flowing in the primary coil, and includes a first terminal to which a voltage corresponding to the coil voltage of the auxiliary coil is applied when the transistor is off, a second terminal to which a feedback voltage corresponding to the output voltage is applied, a third terminal to which a voltage corresponding to the current flowing in the transistor is applied when the transistor is on, a detection circuit that detects whether the voltage of the first terminal when the transistor is off is lower than a reference voltage, and a control circuit that controls switching of the transistor based on the feedback voltage, the voltage of the third terminal when the transistor is on, and the detection result of the detection circuit.

[0010] A second aspect of the power supply circuit of the present invention that solves the above-mentioned problems is a power supply circuit that generates an output voltage of a target level from an input voltage, comprising: a transformer including a primary coil, a secondary coil, and an auxiliary coil; a transistor that controls a current flowing in the primary coil; and an integrated circuit having first to third terminals and driving the transistor, the power supply circuit including: a first diode that rectifies the coil voltage of the auxiliary coil; a first capacitor connected to the first terminal and charged with a current from the first diode; and a detection resistor connected to the third terminal and detecting a current flowing in the transistor when the transistor is on; and the integrated circuit includes a detection circuit that detects whether the voltage of the first terminal when the transistor is off is lower than a reference voltage, and a control circuit that controls switching of the transistor based on a feedback voltage applied to the second terminal corresponding to the output voltage, the voltage of the third terminal when the transistor is on, and the detection result of the detection circuit. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide an integrated circuit that can appropriately detect the voltage from the auxiliary coil. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a diagram illustrating an example of the configuration of an AC-DC converter 10a. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of a control IC 42a. [Figure 3] FIG. 2 is a diagram showing an example of the configuration of a control circuit 62a. [Figure 4] FIG. 2 is a diagram illustrating an example of the configuration of an OCP 102. [Figure 5] FIG. 2 is a diagram illustrating an example of the configuration of an oscillator circuit 80. [Figure 6] FIG. 2 is a diagram illustrating an example of the configuration of a voltage controlled oscillation circuit 124. [Figure 7]1A is a diagram showing changes in the oscillation frequency Fsw of the signal Ss in the "normal mode." FIG. 1B is a table showing the relationship between the voltages V1 and V3 and the reference voltages VREF4 to VREF6 when the voltage Vfb becomes the voltages Vfba to Vfbd. [Figure 8] FIG. 10 is a diagram showing a change in the oscillation frequency Fsw of the signal Ss in the "OPP mode." [Figure 9] FIG. 10 is a diagram illustrating an example of the operation of the control IC 42a in the "normal mode." [Figure 10] FIG. 10 is a diagram illustrating an example of the operation of the control IC 42a when transitioning from the "normal mode" to the "OPP mode." [Figure 11] FIG. 10 is a diagram illustrating an example of the operation of the control IC 42a when transitioning from the "OPP mode" to the "normal mode." [Figure 12] FIG. 10 is a diagram showing an OPP 60b which is a modified example of the OPP 60a. [Figure 13] FIG. 2 is a diagram illustrating an example of the configuration of an AC-DC converter 10b. [Figure 14] FIG. 2 is a diagram illustrating an example of the configuration of a control IC 42b. [Figure 15] FIG. 2 is a diagram showing an example of the configuration of a control circuit 62b. [Figure 16] FIG. 10 is a diagram illustrating an example of the operation of the control IC 42b when transitioning from the "normal mode" to the "OPP mode." [Figure 17] FIG. 10 is a diagram illustrating an example of the operation of the control IC 42b when transitioning from the "OPP mode" to the "normal mode." DETAILED DESCRIPTION OF THE INVENTION

[0013] At least the following matters will become clear from the description of this specification and the accompanying drawings. =====This embodiment===== 1 is a diagram showing an example of the configuration of an AC-DC converter 10a according to one embodiment of the present invention. The AC-DC converter 10a is a flyback power supply circuit that generates an output voltage Vout at a target level from an AC voltage Vac of a commercial power supply.

[0014] <<<Overview of the AC-DC Converter 10a>>> The AC-DC converter 10a is composed of a full-wave rectifier circuit 20, capacitors 21, 25, a transformer 22, a control block 23, a diode 24, Zener diodes 26, 27, a light-emitting diode 28, and a switch 29. And the AC-DC converter 10a supplies power to the motor 30.

[0015] The full-wave rectifier circuit 20 full-wave rectifies a given input AC voltage Vac and outputs it as a voltage Vrec to the primary coil L1 of the transformer 22 and the capacitor 21. Also, the capacitor 21 smoothes the voltage Vrec. The AC voltage Vac is, for example, a voltage with an effective value of 100 to 240 V and a frequency of 50 to 60 Hz.

[0016] The transformer 22 has a primary coil L1, a secondary coil L2 magnetically coupled to the primary coil L1, and an auxiliary coil L3. Here, the secondary coil L2 and the auxiliary coil L3 are wound so that the voltages generated in the secondary coil L2 and the auxiliary coil L3 have polarities opposite to that of the voltage generated in the primary coil L1.

[0017] The control block 23 controls the voltage generated in the secondary coil L2 of the transformer 22 by controlling the inductor current IL flowing through the primary coil L1 on the primary side of the transformer 22. As a result, an output voltage Vout at a target level is generated on the secondary side of the transformer 22.

[0018] The diode 24 rectifies the current from the secondary coil L2 of the transformer 22 and supplies it to the capacitor 25. Since the capacitor 25 is charged by the current from the diode 24, an output voltage Vout is generated between the terminals of the capacitor 25.

[0019] The Zener diodes 26 and 27 and the light-emitting diode 28 are connected in series between the cathode of the diode 24 and the ground, and the Zener diodes 26 and 27 are connected in series so that a voltage corresponding to the output voltage Vout becomes a reverse voltage. The light-emitting diode 28 is also connected between the cathode of the diode 24 and the cathode of the Zener diode 27.

[0020] The Zener diodes 26 and 27 are elements that output a constant voltage when a reverse voltage is applied.

[0021] The light emitting diode 28 is an element that emits light with an intensity that corresponds to the voltage between the output voltage Vout and the cathode of the Zener diode 27 .

[0022] The switch 29 is connected in parallel with the Zener diode 26, and is turned on and off in response to an external signal ExSig from a device (not shown) that controls the motor 30. The switch 29 is turned on when the motor 30 enters a standby state.

[0023] The motor 30 is a load connected to the AC-DC converter 10a, and an output voltage Vout is applied to the motor 30. The current flowing through the motor 30 is referred to as an output current Iout.

[0024] <<<Overview of Control Block 23>>> The control block 23 is a circuit block for controlling the AC-DC converter 10a and includes a power transistor 40, resistors 41, 44, 46, and 51, a control IC 42a, capacitors 43, 47, and 49, diodes 45 and 50, and a phototransistor .

[0025] The power transistor 40 is an NMOS transistor for controlling the power supplied to the motor 30. In this embodiment, the power transistor 40 is a MOS (Metal Oxide Semiconductor) transistor, but is not limited to this. The power transistor 40 may be, for example, a bipolar transistor, etc., as long as it is a transistor that can control power.

[0026] The resistor 41 is a resistor for detecting the inductor current IL that flows through the primary coil L1 when the power transistor 40 is on, and has one end connected to the source electrode of the power transistor 40 and the other end grounded.

[0027] The control IC 42a is an integrated circuit that controls the switching of the power transistor 40 so that the level of the output voltage Vout becomes a target level. Specifically, the control IC 42a drives the power transistor 40 based on the inductor current IL and the output voltage Vout.

[0028] The control IC 42a is provided with terminals CS, FB, OUT, and VCC, the details of which will be described later. The gate electrode of the power transistor 40 is connected to the terminal OUT. The actual control IC 42a is also provided with other terminals, but these are omitted for convenience of explanation.

[0029] Capacitor 43 is provided between terminal CS and ground, and the voltage across resistor 41 generated by the flow of inductor current IL is applied via resistor 44. Capacitor 43 and resistor 44 form a low-pass filter, stabilizing voltage Vcs at terminal CS.

[0030] The anode of the diode 45 is connected to the auxiliary coil L3, and the cathode is connected via a resistor 46 to the terminal CS.

[0031] The capacitor 47 is provided between the terminal FB and ground and stabilizes the voltage Vfb at the terminal FB. The voltage Vfb is a feedback voltage corresponding to the output voltage Vout and is applied to the terminal FB. As will be described in detail later, the control IC 42a turns on the power transistor 40 at a frequency corresponding to the voltage Vfb. Normally, when the voltage Vcs exceeds the voltage Vfb while the power transistor 40 is on, the control IC 42a turns off the power transistor 40.

[0032] The phototransistor 48 is provided between the terminal FB and ground, and forms a photocoupler together with the light-emitting diode 28 on the secondary side of the transformer 22. Furthermore, when the intensity of light emitted by the light-emitting diode 28 increases, the phototransistor 48 causes a larger sink current Ia to flow through the terminal FB.

[0033] Capacitor 49 is provided between terminal VCC and ground. Diode 50 has an anode connected to auxiliary coil L3 and a cathode connected to terminal VCC via resistor 51. Voltage Va generated in auxiliary coil L3 is applied to capacitor 49 via diode 50 and resistor 51, and the voltage of capacitor 49 becomes power supply voltage Vcc of control IC 42a. When power transistor 40 is off, a voltage corresponding to voltage Va of auxiliary coil L3, i.e., the voltage of capacitor 49, is applied to terminal VCC.

[0034] As will be described in detail later, voltage Vfb changes according to output voltage Vout and determines the value of inductor current IL. That is, output voltage Vout determines the value of inductor current IL. Changes in the value of inductor current IL change voltage Va. Changes in voltage Va also change power supply voltage Vcc.

[0035] Therefore, when the level of the output voltage Vout changes, the power supply voltage Vcc also changes, so that by detecting the change in the power supply voltage Vcc, it is possible to detect the change in the level of the output voltage Vout.

[0036] Furthermore, the power supply voltage Vcc is determined by adjusting the winding ratio of the transformer's primary coil L1, secondary coil L2, and auxiliary coil L3. In this case, it is difficult to adjust the winding ratio to output the target level of output voltage Vout in order to detect changes in output voltage Vout, and it is therefore necessary to adjust the resistance value of resistor 51.

[0037] However, if the power supply voltage Vcc changes due to the adjustment of the resistance value of the resistor 51, this will also affect a circuit block in the control IC 42a (described later) that detects and operates the power supply voltage Vcc. Therefore, it is difficult to detect a change in the output voltage Vout without affecting the circuit block.

[0038] The AC voltage Vac corresponds to the "input voltage," and the voltage Va corresponds to the "coil voltage." The capacitor 49 corresponds to the "first capacitor," and the capacitor 43 corresponds to the "second capacitor." The diode 50 corresponds to the "first diode," and the diode 45 corresponds to the "second diode." The terminal VCC corresponds to the "first terminal," the terminal FB corresponds to the "second terminal," and the terminal CS corresponds to the "third terminal." The resistor 41 corresponds to the "detection resistor."

[0039] <<<Configuration of control IC 42a>>> 2 is a diagram showing an example of the configuration of the control IC 42a. The control IC 42a includes an OPP 60a, a resistor 61, and a control circuit 62a.

[0040] The overpower protection circuit (OPP) 60a detects that the target level of the output voltage Vout has been changed by the external signal ExSig. Specifically, when the power transistor 40 is off and the voltage Vcs remains lower than the reference voltage VREF0 for a predetermined period of time, the OPP 60a outputs a signal opp_o at an “H” level.

[0041] On the other hand, when the power transistor 40 is off and the voltage Vcs becomes higher than the reference voltage VREF0, the OPP 60a outputs an “L” level signal opp_o. The OPP 60a includes a comparator 70, a one-shot circuit 71, a D flip-flop 72, and a timer 73.

[0042] The comparator 70 compares the voltage Vcs with the reference voltage VREF0, and outputs a signal at a low level if the voltage Vcs is higher than the reference voltage VREF0. On the other hand, the comparator 70 outputs a signal at a high level if the voltage Vcs is lower than the reference voltage VREF0.

[0043] The one-shot circuit 71, which will be described in detail later, is a circuit that generates a pulse signal at the falling edge of the signal Sdrv output by the control circuit 62a.

[0044] When the UVLO 84 (described later) outputs a reset signal rst at the "L" level and the one-shot circuit 71 outputs a pulse signal, the D flip-flop 72 outputs the signal from the comparator 70 as the signal opp_cmp. On the other hand, when the UVLO 84 outputs a reset signal rst at the "L" level and the one-shot circuit 71 does not output a pulse signal, the D flip-flop 72 maintains the signal opp_cmp at its previous logic level. Furthermore, the D flip-flop 72 is reset when the UVLO 84 (described later) outputs a reset signal rst at the "H" level.

[0045] That is, when the reset signal rst is at the "L" level, the comparator 70, one-shot circuit 71, and D flip-flop 72 output a signal opp_cmp indicating whether the voltage Vcs is higher than the reference voltage VREF0 at the falling edge of the signal Sdrv.

[0046] The timer 73 is a circuit that determines whether or not the "H" level signal opp_cmp is input for a predetermined period of time, and when the "H" level signal opp_cmp is input for the predetermined period of time, the timer 73 outputs the "H" level signal opp_o. On the other hand, when the "L" level signal opp_cmp is input, the timer 73 outputs the "L" level signal opp_o.

[0047] The operation mode of the control IC 42a when the signal opp_o is at "L" level is referred to as "normal mode," and the operation mode of the control IC 42a when the signal opp_o is at "H" level is referred to as "OPP mode."

[0048] The resistor 61 is provided between the terminal FB and a node to which an internal voltage Vdd generated by an internal power supply (not shown) from a power supply voltage Vcc is applied, and generates a voltage Vfb according to the sink current Ia flowing from the phototransistor .

[0049] The control circuit 62a is a circuit that controls the switching of the power transistor 40 based on the voltage Vfb, the voltage Vcs when the power transistor 40 is on, and the signal opp_o.

[0050] The comparator 70 corresponds to a "comparison circuit," the "H" level signal opp_cmp corresponds to a "first signal," and the "L" level signal opp_cmp corresponds to a "second signal." The timer 73 corresponds to an "output circuit." The OPP 60a corresponds to a "first detection circuit," and the reference voltage VREF0 corresponds to a "first reference voltage." The signal opp_o corresponds to a "detection result."

[0051] <<<Configuration of control circuit 62a>>> 3 is a diagram showing an example of the configuration of the control circuit 62a. The control circuit 62a includes an oscillation circuit 80, a drive circuit 81, an OCP 82, an OVP 83, a UVLO 84, an OLP 85, an OR circuit 86, and a latch 87.

[0052] The oscillation circuit 80 outputs an oscillation signal Vosc having a frequency Fsw that corresponds to the voltage Vfb and the signal opp_o. Specifically, when the OPP 60a outputs a high-level signal opp_o, the oscillation circuit 80 outputs an oscillation signal Vosc with a frequency Fsw0. On the other hand, when the OPP 60a outputs a low-level signal opp_o, the oscillation circuit 80 outputs an oscillation signal Vosc with a frequency between Fsw0 and Fsw2 that corresponds to the voltage Vfb. Details of the oscillation circuit 80 will be described later.

[0053] The drive circuit 81 is a circuit that turns on the power transistor 40 based on the oscillation signal Vosc, and turns off the power transistor 40 based on the voltage Vcs when the power transistor is on and the voltage Vfb.

[0054] The drive circuit 81 includes a one-shot circuit 90, an SR flip-flop 91, OR circuits 92, 94, and 96, a buffer 93, and a comparator 95.

[0055] The one-shot circuit 90 is a circuit that outputs a pulse signal Ss at the rising edge of the oscillation signal Vosc. Specifically, when the voltage Vfb is lower than the reference voltage VREF1, the one-shot circuit 90 stops outputting the pulse signal Ss. On the other hand, when the voltage Vfb is higher than the reference voltage VREF1, the one-shot circuit 90 outputs a pulse signal Ss with a frequency Fsw corresponding to the frequency Fsw of the oscillation signal Vosc.

[0056] When the one-shot circuit 90 outputs the pulse signal Ss, the SR flip-flop 91 outputs a signal Vp1 of "H" level. On the other hand, as will be described in detail later, when the OR circuit 96 outputs a signal Sr of "H" level, the SR flip-flop 91 outputs a signal Vp1 of "L" level.

[0057] The OR circuit 92 takes the logical sum of the pulse signal Ss and the signal Vp1 and outputs it as the signal Sdrv. That is, when the pulse signal Ss or the signal Vp1 goes high, the OR circuit 92 outputs the signal Sdrv at high level. On the other hand, when the pulse signal Ss and the signal Vp1 go low, the OR circuit 92 outputs the signal Sdrv at low level.

[0058] The buffer 93 amplifies the signal Sdrv and outputs it as a drive signal Vg. Specifically, when the OR circuit 92 outputs the signal Sdrv at a high level and the OR circuit 94 outputs the signal Soff at a low level, the buffer 93 outputs the drive signal Vg that turns on the power transistor 40. On the other hand, when the OR circuit 92 outputs the signal Sdrv at a low level and the OR circuit 94 outputs the signal Soff at a low level, the buffer 93 outputs the drive signal Vg that turns off the power transistor 40. Furthermore, when the OR circuit 94 outputs the signal Soff at a high level, the buffer 93 outputs the drive signal Vg that turns off the power transistor 40.

[0059] The OR circuit 94 is an element that takes the logical sum of a reset signal rst from the UVLO 84 (described later) and a signal lat_o from the latch 87 (described later). Specifically, when the signal rst or the signal lat_o is at the “H” level, the OR circuit 94 causes the buffer 93 to stop switching of the power transistor 40. On the other hand, when the signal rst and the signal lat_o are at the “L” level, the OR circuit 94 causes the buffer 93 to output a drive signal Vg that switches the power transistor 40.

[0060] The comparator 95 is a circuit that compares the voltage Vcs with the voltage Vfb when the power transistor 40 is on, and outputs a signal Vr at a high level when the voltage Vcs is higher than the voltage Vfb. Note that the comparator 95 outputs a signal Vr at a low level when the voltage Vcs is lower than the voltage Vfb when the power transistor 40 is on.

[0061] The voltage Vcs may be input to the comparator 95 as the voltage Vcs1 via a slope compensation circuit (not shown). In this case, the voltage Vcs1 is compared with the voltage Vfb, and the comparator 95 outputs a signal Vr at an "H" level when the voltage Vcs1 exceeds the voltage Vfb. On the other hand, the comparator 95 outputs a signal Vr at an "L" level when the voltage Vcs1 does not exceed the voltage Vfb.

[0062] The OR circuit 96 is an element that takes the logical sum of a signal ocp_o from the OCP 82 (described later) and the signal Vr, and outputs the result as a signal Sr. Normally, the OCP 82 outputs the signal ocp_o at an "L" level, so the signal Sr is the same as the signal Vr.

[0063] Therefore, when the voltage Vcs becomes higher than the voltage Vfb and the comparator 95 outputs the signal Vr at the high level, the SR flip-flop 91 outputs the signal Vp1 at the low level, which turns off the power transistor 40 when the voltage Vcs becomes higher than the voltage Vfb.

[0064] The overcurrent protection circuit (OCP) 82 is a circuit that determines whether the inductor current IL flowing through the power transistor 40 is greater than a predetermined current indicating an overcurrent, based on the voltage Vcs and the signal opp_o. Specifically, when the inductor current IL is greater than the predetermined current, the OCP 82 outputs a signal ocp_o at an "H" level. On the other hand, when the inductor current IL is smaller than the predetermined current, the OCP 82 outputs a signal ocp_o at an "L" level. Details of the OCP 82 will be described later.

[0065] The overvoltage protection circuit (OVP) 83 is a circuit that causes the buffer 93 to stop switching of the power transistor 40 and turn off the power transistor 40 when the power supply voltage Vcc remains higher than a first predetermined voltage (e.g., 25.5 V) for a predetermined period of time. Specifically, the OVP 83 outputs a signal ovp_o at an "H" level when the power supply voltage Vcc remains higher than the first predetermined voltage for a predetermined period of time. On the other hand, the OVP 83 outputs a signal ovp_o at an "L" level when the power supply voltage Vcc does not remain higher than the first predetermined voltage for a predetermined period of time. The OVP 83 corresponds to a "third detection circuit," and the first predetermined voltage corresponds to a "second reference voltage."

[0066] The undervoltage lockout circuit (UVLO) 84 resets the control IC 42a when the power supply voltage Vcc is equal to or lower than a second predetermined voltage (e.g., 6.5V). Specifically, when the power supply voltage Vcc is equal to or lower than the second predetermined voltage, the UVLO 84 outputs a reset signal rst at an "H" level to reset the control IC 42a. On the other hand, when the power supply voltage Vcc is higher than a third predetermined voltage (e.g., 13V), the UVLO 84 outputs a signal rst at an "L" level.

[0067] The overload protection circuit (OLP) 85 is a circuit that detects the inductor current IL by the voltage Vcs when the power transistor 40 turns on, and detects whether the motor 30 is in an overload state. Specifically, the OLP 85 is a circuit that outputs a signal olp_o of "H" level when the overload state continues for a predetermined period of time. On the other hand, the OLP 85 outputs a signal olp_o of "L" level when the overload state does not continue for the predetermined period of time.

[0068] When the OLP 85 outputs the signal olp_o at the "H" level, the buffer 93 stops switching of the power transistor 40. The value of the voltage Vcs at which the OLP 85 determines that the motor 30 is in an overload state is lower than the value of the voltage Vcs at which the OCP 82 determines that the current flowing through the power transistor 40 is greater than a predetermined current.

[0069] The OR circuit 86 is an element that takes the logical sum of the signal ovp_o and the signal olp_o.

[0070] When the UVLO 84 outputs a signal rst at the "L" level, the latch 87 outputs a signal lat_o at the "H" level when the OR circuit 86 outputs a signal at the "H" level, and is a circuit that stops the switching of the power transistor 40 to the buffer 93.

[0071] Also, when the UVLO 84 outputs a signal rst at the "L" level, even if the OR circuit 86 outputs a signal at the "L" level after outputting a signal at the "H" level, the latch 87 does not output a signal lat_o at the "L" level and continues to output a signal lat_o at the "H" level. On the other hand, when the UVLO 84 outputs a signal rst at the "H" level, the latch 87 outputs a signal lat_o at the "L" level.

[0072] The discharge circuit 88 is a circuit that discharges the capacitor 43 connected to the terminal CS when the power transistor 40 is turned on, that is, at the rising of the signal Sdrv. The discharge circuit 88 includes an NMOS transistor 100 and a one-shot circuit 101. <00002-seven9><00002-eight0>The NMOS transistor 100 is turned on in response to a pulse signal Vp2 with a pulse width shorter than the on-period Ton of the power transistor 40 from the one-shot circuit 101, and discharges the charge accumulated in the capacitor 43 to the ground. <00002-eight1><00002-eight2><00002-eight3>When the OR circuit 92 outputs a signal Sdrv at the "H" level, the one-shot circuit 101 outputs a pulse signal Vp2 with a pulse width shorter than the on-period Ton of the power transistor 40. <00002-eight4><00002-eight5><00002-eight6><<<Configuration of OCP82>>> <00002-eight7>4 is a diagram showing an example of the configuration of the OCP 82. Specifically, the OCP 82 compares a predetermined current (i.e., a current value determined by a reference voltage ocp_ref) adjusted based on the signal opp_o with the inductor current IL when the power transistor 40 is on. When the voltage Vcs when the power transistor 40 is on becomes higher than the reference voltage ocp_ref, the OCP 82 outputs an "H" level signal ocp_o. On the other hand, when the voltage Vcs is lower than the reference voltage ocp_ref, the OCP 82 outputs an "L" level signal ocp_o.

[0076] The OCP 82 includes an inverter 110, transfer gates 111 and 112, and a comparator 113. If the voltage Vcs when the power transistor 40 is off is lower than the reference voltage VREF0, the OPP 60a causes the OCP 82 to switch the reference voltage ocp_ref to the reference voltage VREF3 and adjust the predetermined current. On the other hand, if the voltage Vcs when the power transistor 40 is off is higher than the reference voltage VREF0, the OPP 60a causes the OCP 82 to switch the reference voltage ocp_ref to the reference voltage VREF2 and adjust the predetermined current so that it becomes larger. Note that the reference voltage VREF2 is higher than the reference voltage VREF3.

[0077] In this way, the OPP 60a causes the OCP 82 to lower the reference voltage ocp_ref, which is used to determine whether the inductor current IL flowing through the power transistor 40 is greater than a predetermined current when the control IC 42a operates in the "OPP mode," to the reference voltage VREF3.

[0078] This allows the control IC 42a to limit the output power in "OPP mode." This also eliminates the need to select components for the AC-DC converter 10a to accommodate cases where the output voltage Vout is low, taking into account that the output current Iout increases when the output voltage Vout is low. The OCP 82 corresponds to a "second detection circuit."

[0079] <<<Configuration of Oscillator Circuit 80>>> FIG. 5 is a diagram illustrating an example of the configuration of an oscillator circuit 80. The oscillator circuit 80 is a circuit that outputs an oscillation signal Vosc having a frequency Fsw or a frequency Fsw0 corresponding to the voltage Vfb. Specifically, when the oscillator circuit 80 receives an “H” level signal opp_o (i.e., in “OPP mode”), it outputs the oscillation signal Vosc having a frequency Fsw0 regardless of changes in the voltage Vfb. On the other hand, when the oscillator circuit 80 receives an “L” level signal opp_o (i.e., in “normal mode”), it outputs an oscillation signal Vosc having a frequency Fsw that is equal to or higher than the frequency Fsw0 and that corresponds to the voltage Vfb. That is, when the oscillator circuit 80 receives an “L” level signal opp_o, it gradually increases the frequency of the oscillation signal Vosc from frequency Fsw0 to frequency Fsw2 via frequency Fsw1 based on the voltage Vfb, which changes in response to a decrease in the output voltage Vout.

[0080] The oscillation circuit 80 includes a voltage dividing circuit 120, a voltage selecting circuit 121, a first voltage circuit 122, a second voltage circuit 123, and a voltage controlled oscillation circuit .

[0081] The voltage dividing circuit 120 is a circuit that divides the voltage Vfb to generate voltages Vfb0 and Vfb1. The voltage dividing circuit 120 divides the voltage Vfb and outputs the divided voltages so that the voltage Vfb0 is lower than the voltage Vfb1.

[0082] The voltage-dividing circuit 120 includes resistors 130 to 132. The voltage-dividing circuit 120 has one end to which a voltage Vfb is applied and the other end that is grounded. The resistors 130 to 132 are connected in series between the one end and the other end. The voltage-dividing circuit 120 generates a voltage Vfb1 at the connection point between the resistor 130 and the resistor 131, and generates a voltage Vfb0 at the connection point between the resistor 131 and the resistor 132.

[0083] The voltage selection circuit 121 is a circuit that outputs either the voltage Vfb0 or the ground voltage as the voltage V0 depending on the logic level of the signal opp_o output by the OPP 60a. Specifically, when the OPP 60a outputs the signal opp_o at an "L" level, the voltage selection circuit 121 outputs the voltage Vfb0 as the voltage V0. On the other hand, when the OPP 60a outputs the signal opp_o at an "H" level, the voltage selection circuit 121 outputs the ground voltage as the voltage V0.

[0084] The voltage selection circuit 121 includes inverters 140 and 141 and NMOS transistors 142 and 143. When the OPP 60a outputs a signal opp_o at an "L" level, the NMOS transistor 142 is turned on, and the voltage selection circuit 121 outputs the voltage Vfb0 as the voltage V0. On the other hand, when the OPP 60a outputs a signal opp_o at an "H" level, the NMOS transistor 143 is turned on, and the voltage selection circuit 121 outputs the ground voltage as the voltage V0.

[0085] The first voltage circuit 122 is a circuit that outputs, as voltage V2, either a voltage V1 corresponding to voltage V0 or a reference voltage VREF4, whichever is higher. Specifically, when voltage Vfb changes and voltage V1 corresponding to voltage Vfb0 is lower than reference voltage VREF4, the first voltage circuit 122 outputs reference voltage VREF4 as voltage V2. When voltage Vfb changes and voltage V1 becomes higher than reference voltage VREF4, the first voltage circuit 122 outputs voltage V1 as voltage V2. The first voltage circuit 122 is configured to include operational amplifiers 150 and 155 and resistors 152 to 154.

[0086] The operational amplifier 150 and resistors 151 to 154 output a voltage V1 that increases as the voltage V0 increases. The operational amplifier 155 outputs the higher of the voltage V1 connected to its two non-inverting inputs or a reference voltage VREF4 as a voltage V2.

[0087] Therefore, the operational amplifier 155, i.e., the first voltage circuit 122, outputs the reference voltage VREF4 as the voltage V2 until the voltage V0 rises and the voltage V1 becomes equal to the reference voltage VREF4, and when the voltage V1 becomes higher than the reference voltage VREF4, it outputs the voltage V1 as the voltage V2.

[0088] The second voltage circuit 123 is a circuit that outputs, as voltage V4, either a voltage V3 corresponding to voltage Vfb1 or a reference voltage VREF5, whichever is higher. Specifically, when the voltage Vfb changes and the voltage V3 corresponding to voltage Vfb1 is lower than the reference voltage VREF5, the second voltage circuit 123 outputs the reference voltage VREF5 as voltage V4. When the voltage Vfb changes and the voltage V3 becomes higher than the reference voltage VREF5, the second voltage circuit 123 outputs the voltage V3 as voltage V4. The second voltage circuit 123 is configured to include operational amplifiers 160 and 165 and resistors 162 to 164.

[0089] Furthermore, operational amplifier 160 corresponds to operational amplifier 150, resistors 162 to 164 correspond to resistors 152 to 154, and operational amplifier 165 corresponds to operational amplifier 155. Furthermore, voltage Vfb1 corresponds to voltage V0, and voltage V4 corresponds to voltage V2. Therefore, second voltage circuit 123 operates in the same manner as first voltage circuit 122.

[0090] The voltage controlled oscillator circuit 124 is a circuit that outputs an oscillation signal Vosc having a frequency Fsw based on the voltages V2, V4 or the reference voltage VREF6.

[0091] <<<Configuration of the voltage-controlled oscillator circuit 124>>> 6 is a diagram showing an example of the configuration of the voltage controlled oscillator circuit 124. The voltage controlled oscillator circuit 124 is a circuit that outputs an oscillation signal Vosc with an oscillation frequency Fsw based on the lowest voltage among voltages V2, V4, and reference voltage VREF6. Note that reference voltage VREF4 is lower than reference voltage VREF5, which is lower than reference voltage VREF6.

[0092] First, a description will be given of changes in the frequency of the oscillation signal Vosc output by the voltage-controlled oscillation circuit 124 when the signal opp_o is at the "L" level (i.e., in the "normal mode"), followed by a description of the configuration of the voltage-controlled oscillation circuit 124.

[0093] When the signal opp_o is at the "H" level (i.e., in the "OPP mode"), the voltage controlled oscillator circuit 124 outputs an oscillation signal Vosc of a predetermined frequency. The frequency of the signal Ss that sets the signal Sdrv that drives the power transistor 40 to the "H" level will be described later with reference to FIGS.

[0094] When the voltage Vfb changes and the voltage V1 corresponding to the voltage Vfb0 is lower than the reference voltage VREF4, the voltage controlled oscillator circuit 124 outputs an oscillation signal Vosc with a frequency Fsw0 based on the reference voltage VREF4. When the voltage Vfb changes and the voltage V1 becomes higher than the reference voltage VREF4, the voltage controlled oscillator circuit 124 outputs an oscillation signal Vosc with a frequency Fsw based on the voltage V1, which is higher than the frequency Fsw0. The voltage Vfb when the voltage V1 becomes the reference voltage VREF4 is referred to as voltage Vfba.

[0095] When voltage Vfb changes and voltage V1 becomes higher than reference voltage VREF5, voltage controlled oscillator 124 outputs oscillation signal Vosc with frequency Fsw1 based on reference voltage VREF5. When voltage Vfb changes and voltage V3 becomes higher than reference voltage VREF5, voltage controlled oscillator 124 outputs oscillation signal Vosc with frequency Fsw based on voltage V3, which is higher than frequency Fsw1. Note that the voltage of voltage Vfb when voltage V1 becomes reference voltage VREF5 is defined as voltage Vfbb, and the voltage of voltage Vfb when voltage V3 becomes reference voltage VREF5 is defined as voltage Vfbc.

[0096] When the voltage Vfb changes and the voltage V3 becomes higher than the reference voltage VREF6, the voltage-controlled oscillation circuit 124 outputs an oscillation signal Vosc having a frequency Fsw2 based on the reference voltage VREF6. Note that the voltage Vfb when the voltage V3 becomes the reference voltage VREF6 is referred to as a voltage Vfbd.

[0097] The voltage controlled oscillation circuit 124 includes an operational amplifier 170, NMOS transistors 171, 176, 177, and 179, a resistor 172, PMOS transistors 173, 174, 175, and 178, a capacitor 180, and a hysteresis comparator 181.

[0098] The operational amplifier 170 adjusts the gate voltage V6 of the NMOS transistor 171 so that the lowest voltage among the voltages V2 and V4 applied to the three non-inverting inputs and the reference voltage VREF6 becomes the voltage V5 of the node to which the inverting input is connected. As a result, if the current flowing through the resistor 172 is the current I0, the voltage generated across the resistor 172 when the current I0 flows through the resistor 172 becomes the voltage V5.

[0099] PMOS transistors 173 to 175 form a current mirror circuit. PMOS transistor 174 passes a current corresponding to the current I0 flowing through PMOS transistor 173, and PMOS transistor 175 passes a current I1 corresponding to the current I0 flowing through PMOS transistor 173 when PMOS transistor 178 is turned on.

[0100] The NMOS transistors 176 and 177 also form a current mirror circuit. The NMOS transistor 176 passes the current that flows through the PMOS transistor 174. When the NMOS transistor 179 is turned on, the NMOS transistor 177 passes a current I2 that corresponds to the current that flows through the PMOS transistor 174 and the NMOS transistor 176.

[0101] The PMOS transistor 178 and the NMOS transistor 179 are turned on and off according to the logic level of the oscillation signal Vosc. When the oscillation signal Vosc is at the "L" level, the PMOS transistor 178 is turned on and the capacitor 180 is charged with the current I1. At this time, the NMOS transistor 179 is turned off.

[0102] On the other hand, when the oscillation signal Vosc is at the "H" level, the NMOS transistor 179 is turned on and the capacitor 180 is discharged with the current I2. At this time, the PMOS transistor 178 is turned off.

[0103] The hysteresis comparator 181 compares the voltage of the capacitor 180 with a high threshold voltage Vthh or a low threshold voltage Vthl generated based on the reference voltage VREF7, and outputs an oscillation signal Vosc at an "H" level if the voltage of the capacitor 180 is higher than the high threshold voltage Vthh. On the other hand, the hysteresis comparator 181 outputs an oscillation signal Vosc at an "L" level if the voltage of the capacitor 180 is lower than the low threshold voltage Vthl.

[0104] As explained above, when the signal opp_o is at the "L" level, the voltage-controlled oscillator circuit 124 outputs the oscillation signal Vosc with a frequency Fsw that varies in accordance with the voltage Vfb. As is clear from the circuit configuration of the voltage-controlled oscillator circuit 124 described above, the operational amplifier 170 passes a larger current I0 through the resistor 172 the higher the voltage value of the voltage V5, i.e., the lowest voltage among the voltages V2, V4, and the reference voltage VREF6. As a result, the currents I1 and I2 also increase. When the currents I1 and I2 increase, the voltage-controlled oscillator circuit 124 charges and discharges the capacitor 180 more quickly, and therefore outputs the oscillation signal Vosc with a higher frequency Fsw.

[0105] Next, the operation of the voltage controlled oscillation circuit 124 when the signal opp_o is at the “H” level (i.e., in the “OPP mode”) will be described. When the signal opp_o is at the “H” level, the voltage selection circuit 121 outputs the ground voltage as the voltage V0.

[0106] When the first voltage circuit 122 receives the voltage V0, which is the ground voltage, it generates a voltage V1 that is lower than the reference voltage VREF4. As a result, the first voltage circuit 122 outputs the reference voltage VREF4 as the voltage V2.

[0107] When the voltage controlled oscillator 124 receives the voltage V2 that is the reference voltage VREF4, the voltage controlled oscillator 124 outputs the oscillation signal Vosc with the frequency Fsw0 regardless of changes in the voltage Vfb because the reference voltage VREF4 is lower than the reference voltages VREF5 and VREF6.

[0108] <<<<Frequency Fsw of signal Ss in "normal mode">>> 7A is a diagram showing changes in the oscillation frequency Fsw of the signal Ss in the "normal mode." Also, FIG. 7B is a table showing the relationship between the voltages V1 and V3 and the reference voltages VREF4 to VREF6 when the voltage Vfb becomes the voltages Vfba to Vfbd. As described above, in the "normal mode," the oscillation circuit 80 outputs the oscillation signal Vosc with the frequency Fsw corresponding to the voltage Vfb.

[0109] As described above, the one-shot circuit 90 receives the oscillation signal Vosc and outputs the pulse signal Ss when the voltage Vfb is higher than the reference voltage VREF1. On the other hand, the one-shot circuit 90 does not output the pulse signal Ss when the voltage Vfb is lower than the reference voltage VREF1.

[0110] Specifically, when the voltage Vfb is lower than the reference voltage VREF1, the pulse signal Ss is not output. When the voltage Vfb is higher than the reference voltage VREF1 and lower than the voltage Vfba, that is, when the voltage V1 is lower than the reference voltage VREF4, the frequency Fsw of the pulse signal Ss becomes the frequency Fsw0 based on the reference voltage VREF4.

[0111] Furthermore, when the voltage Vfb becomes the voltage Vfba, the voltage V1 becomes the reference voltage VREF4, and the frequency of the pulse signal Ss becomes the frequency Fsw0 based on the voltage V1.

[0112] Furthermore, when voltage Vfb is higher than voltage Vfba and lower than voltage Vfbb, that is, when voltage V1 is higher than reference voltage VREF4 and lower than reference voltage VREF5, frequency Fsw of pulse signal Ss increases in proportion to an increase in voltage Vfb (i.e., an increase in voltage V1).

[0113] Furthermore, when the voltage Vfb becomes the voltage Vfbb, the voltage V1 becomes the reference voltage VREF5, and the frequency of the pulse signal Ss becomes the frequency Fsw1 based on the reference voltage VREF5.

[0114] Furthermore, when the voltage Vfb is higher than the voltage Vfbb and lower than the voltage Vfbc, that is, when the voltage V3 is lower than the reference voltage VREF5, the frequency Fsw of the pulse signal Ss becomes the frequency Fsw1 based on the reference voltage VREF5.

[0115] Furthermore, when the voltage Vfb becomes the voltage Vfbc, the voltage V3 becomes the reference voltage VREF5, and the frequency of the pulse signal Ss becomes the frequency Fsw1 based on the voltage V3.

[0116] Furthermore, when the voltage Vfb is higher than the voltage Vfbc and lower than the voltage Vfbd, that is, when the voltage V3 is higher than the reference voltage VREF5 and lower than the reference voltage VREF6, the frequency Fsw of the pulse signal Ss increases in proportion to the increase in the voltage Vfb (i.e., the increase in the voltage V3).

[0117] Furthermore, when the voltage Vfb becomes the voltage Vfbd, the voltage V3 becomes the reference voltage VREF6, and the frequency of the pulse signal Ss becomes the frequency Fsw2 based on the reference voltage VREF6.

[0118] Finally, when the voltage Vfb becomes higher than the voltage Vfbd, that is, when the voltage V3 becomes higher than the reference voltage VREF6, the frequency Fsw of the pulse signal Ss becomes the frequency Fsw2 based on the reference voltage VREF6.

[0119] <<<Frequency Fsw of signal Ss in "OPP mode">>> 8 is a diagram showing changes in the oscillation frequency Fsw of the signal Ss in the "OPP mode." As described above, in the "OPP mode," the oscillation circuit 80 outputs the oscillation signal Vosc with the frequency Fsw0 regardless of changes in the voltage Vfb.

[0120] As described above, the one-shot circuit 90 receives the oscillation signal Vosc and outputs a pulse signal Ss having a frequency Fsw0 when the voltage Vfb is higher than the reference voltage VREF1. On the other hand, the one-shot circuit 90 does not output the pulse signal Ss when the voltage Vfb is lower than the reference voltage VREF1.

[0121] The frequency Fsw0 corresponds to the "first frequency", the frequency Fsw1 corresponds to the "second frequency", and the frequency Fsw2 corresponds to the "third frequency".

[0122] <<<Operation of the control IC 42a in "normal mode">>> 9 is a diagram showing an example of the operation of the control IC 42a in "normal mode." For ease of explanation, it is assumed that the inductor current IL flowing through the power transistor 40 does not become an overcurrent. Therefore, it is assumed that the timing at which the power transistor 40 is turned off is determined by the voltage Vcs when the power transistor 40 is on and the voltage Vfb.

[0123] Furthermore, voltage Vfb is assumed to be higher than reference voltage VREF1, and one-shot circuit 90 outputs pulse signal Ss. Furthermore, OR circuit 94 does not output "H" level signal Soff, and buffer 93 outputs drive signal Vg for switching power transistor 40. The voltage generated across resistor 41 is assumed to be voltage Vb, and the voltage at the cathode of diode 45 is assumed to be voltage Vc. Furthermore, voltage Vc is applied to capacitor 43 via resistor 46.

[0124] Furthermore, since the control IC 42a operates in the "normal mode", the AC-DC converter 10a applies to the motor 30 the output voltage Vout at the first target level (for example, 32 V).

[0125] At time t0, the oscillation circuit 80 outputs an oscillation signal Vosc at a high level based on a frequency corresponding to the voltage Vfb, causing the one-shot circuit 90 to output a pulse signal Ss. Upon receiving the pulse signal Ss, the OR circuit 92 outputs an Sdrv at a high level, and the SR flip-flop 91 outputs a signal Vp1 at a high level.

[0126] This turns on the power transistor 40, causing the inductor current IL to flow through the primary coil L1. When the inductor current IL flows through the power transistor 40, a voltage Vb corresponding to the inductor current IL is generated across the resistor 41.

[0127] When the discharge circuit 88 receives the “H” level signal Sdrv, it discharges the charge in the capacitor 43. As a result, the voltage Vcs becomes 0 V. Thereafter, the voltage Vb generated across the resistor 41 increases in response to the increase in the inductor current IL, so the voltage Vcs gradually increases.

[0128] Furthermore, when the inductor current IL flows through the primary coil L1, a voltage Va having a polarity opposite to that of the voltage generated in the primary coil L1 is generated in the auxiliary coil L3.

[0129] At this time, since the voltage Va is a negative voltage, no current flows to the capacitor 43 via the diode 45 and the resistor 46, and the auxiliary coil L3 does not charge the capacitor 43.

[0130] At time t1 when the oscillation circuit 80 outputs the oscillation signal Vosc at the "H" level, the one-shot circuit 90 outputs the pulse signal Ss. However, since the SR flip-flop 91 has already output the "H" level signal Vp1, the signal Sdrv remains at the "H" level.

[0131] At time t2, when the voltage Vcs rises and becomes equal to the voltage Vfb, the comparator 95 outputs a high-level signal Vr. This causes the SR flip-flop 91 to output a low-level signal Vp1, and the OR circuit 92 to output a low-level signal Sdrv. This turns off the power transistor 40. Furthermore, when the power transistor 40 is turned off, the inductor current IL does not flow through the primary coil L1.

[0132] When the inductor current IL stops flowing through the primary coil L1, the voltage generated in the primary coil L1 becomes a voltage of opposite polarity to that when the power transistor 40 is turned on. As a result, the voltage Va generated in the auxiliary coil L3 becomes a positive voltage. And, because the inductor current IL does not flow, the voltage Vb becomes 0 V.

[0133] At this time, since voltage Va is a positive voltage, voltage Vc, which is transmitted from voltage Va via diode 45 and resistor 46, becomes a positive voltage, and voltage Vc is applied to capacitor 43, which is charged by voltage Va generated in auxiliary coil L3. Also, since voltage Vb is 0 V, voltage Vcs becomes voltage Vc, which is higher than reference voltage VREF0.

[0134] Furthermore, voltage Va is also used to generate power supply voltage Vcc for control IC 42a, and is therefore higher than voltage Vcs generated by voltage Vb. When output voltage Vout changes, inductor current IL changes, and voltage Va changes accordingly, so voltage Vcs also changes when power transistor 40 is off. The period from time t0 to time t2 is referred to as on-period Ton.

[0135] After time t3 when the oscillation circuit 80 outputs the oscillation signal Vosc at "H" level, the operation from time t0 to time t3 is repeated. The period from time t2 to time t3 is referred to as an off period Toff.

[0136] In this way, during the on-period Ton, the capacitor 43 is charged by the voltage Vb generated across the resistor 41 in accordance with the inductor current IL. As a result, the voltage Vcs becomes a voltage in accordance with the inductor current IL.

[0137] On the other hand, during the off period Toff, the inductor current IL does not flow, so the capacitor 43 is not charged by the voltage Vb, but is charged by the voltage Va generated in the auxiliary coil L3. As a result, the voltage Vcs during the off period Toff is higher than the voltage Vcs during the on period Ton.

[0138] As described above, the voltage Vcs when the power transistor 40 is off changes depending on the output voltage Vout, so that changes in the output voltage Vout can be detected using the voltage Vcs in the same way that changes in the output voltage Vout can be detected using the power supply voltage Vcc.

[0139] <<<Operation of the control IC 42a when the mode transitions>>> ===Transition from "Normal Mode" to "OPP Mode"=== FIG. 10 is a diagram showing an example of the operation of the control IC 42a when transitioning from "normal mode" to "OPP mode." Note that the voltage Vfb will never become lower than the reference voltage VREF1. Also, the OR circuit 94 will not output an "H" level signal Soff. For ease of explanation, the period of the signal Sdrv is different from that in actual operation.

[0140] At time t10, when the one-shot circuit 90 outputs the pulse signal Ss, the OR circuit 92 outputs the signal Sdrv at the "H" level, which turns on the power transistor 40. Thereafter, in the AC-DC converter 10a, when the switch 29 is turned on by the external signal ExSig, the output voltage Vout begins to decrease to a second target level (e.g., 12 V).

[0141] At time t11 when the voltage Vcs becomes the voltage Vfb when the power transistor 40 is on, the comparator 95 outputs a high-level signal Vr, and the OR circuit 96 outputs a high-level signal Sr. Then, the SR flip-flop 91 outputs a low-level signal Vp1, and the OR circuit 92 outputs a low-level signal Sdrv. This turns off the power transistor 40.

[0142] When the power transistor 40 is turned off, the voltage Vcs is charged from the auxiliary coil L3 via the diode 45 and the resistor 46. At this time, the output power Pout begins to decrease, and the output voltage Vout also decreases slightly from the first target level (for example, 32 V). However, since the output current Iout is large, the inductor current IL when the power transistor 40 is on is also large. Therefore, the voltage Va of the auxiliary coil L3 is also large, and the voltage Vcs when the power transistor 40 is off is higher than the reference voltage VREF0.

[0143] At time t12 when the output voltage Vout reaches the second target level (for example, 12 V), the one-shot circuit 90 outputs the pulse signal Ss, and the power transistor 40 turns on, similar to time t10.

[0144] At this time, the switch 29 is turned on, which increases the voltage between the output voltage Vout and the cathode of the Zener diode 27, increasing the intensity of the light emitted by the light-emitting diode 28. This causes a large sink current Ia to flow through the phototransistor 48, resulting in a decrease in the voltage Vfb. Furthermore, as the voltage Vfb decreases below the voltage Vfba, the one-shot circuit 90 begins to output a pulse signal Ss with a frequency Fsw0.

[0145] At time t13, when the voltage Vcs when the power transistor 40 is turned on reaches the reduced voltage Vfb, the power transistor 40 is turned off, just as at time t11. At this time, the voltage Vcs is charged by the voltage Va from the auxiliary coil L3, but because the output power Pout and the output voltage Vout have already decreased, the inductor current IL when the power transistor 40 is on becomes small. Therefore, the voltage Va of the auxiliary coil L3 also becomes small, and the voltage Vcs when the power transistor 40 is off is lower than the reference voltage VREF0.

[0146] At time t14, when the voltage Vcs when the power transistor 40 is off continues to be lower than the reference voltage VREF0 for a predetermined period of time from time t13, the OPP 60a outputs an "H" level signal opp_o. At this time, the oscillator circuit 80 outputs an oscillation signal Vosc with a frequency Fsw0. The OCP 82 then switches the reference voltage ocp_ref from reference voltage VREF2 to reference voltage VREF3. Note that the control IC 42a operates in "normal mode" before time t14, and operates in "OPP mode" after time t14.

[0147] ===Transition from "OPP mode" to "normal mode"=== FIG. 11 is a diagram showing an example of the operation of the control IC 42a when transitioning from "OPP mode" to "normal mode." It is assumed that the control IC 42a is operating in "OPP mode" before time t15, and that the control IC 42a continues to operate in "OPP mode" from time t15 to time t16. It is also assumed that the voltage Vfb does not become lower than the reference voltage VREF1. It is also assumed that the OR circuit 94 does not output an "H" level signal Soff. As with FIG. 10, for ease of explanation, the period of the signal Sdrv is different from that in actual operation.

[0148] At time t15, when the output current Iout increases due to a sudden change in the load on the motor 30, the current flowing through the light-emitting diode 28 decreases, and the intensity of the light emitted by the light-emitting diode 28 weakens. This causes the phototransistor 48 to pass a small sink current Ia, resulting in an increase in the voltage Vfb. At this time, the voltage Vfb becomes higher than the reference voltage VREF3 of the OCP 82 when the signal opp_o is at the “H” level.

[0149] As a result, at time t15, the OCP 82 outputs a high-level signal ocp_o. When the high-level signal ocp_o is output, the SR flip-flop 91 outputs a low-level signal Vp1, and the OR circuit 92 outputs a low-level signal Sdrv. This causes an inductor current IL, which is an overcurrent, to flow through the power transistor 40, and the power transistor 40 is turned off.

[0150] At time t16, when the voltage Vcs when the power transistor 40 is off exceeds the reference voltage VREF0, the OPP 60a outputs a low-level signal opp_o. As a result, if the voltage Vfb is higher than the voltage Vfbd, the oscillator circuit 80 outputs an oscillation signal Vosc with a frequency Fsw2. Furthermore, when the OPP 60a outputs the low-level signal opp_o, the OCP 82 switches the reference voltage ocp_ref to the reference voltage VREF2.

[0151] === Variations === 12 is a diagram showing an OPP 60b, which is a modification of the OPP 60a. The OPP 60b includes a one-shot circuit 190, an NMOS transistor 191, a capacitor 192, a comparator 193, and a timer 73.

[0152] When the control circuit 62a outputs the signal Sdrv at the "L" level, the one-shot circuit 190 generates a pulse signal that turns on the NMOS transistor 191 at the falling edge of the signal Sdrv.

[0153] When the NMOS transistor 191 is turned on, a voltage corresponding to the voltage Vcs is applied to the capacitor 192. On the other hand, when the NMOS transistor 191 is turned off, the capacitor 192 holds the voltage corresponding to the voltage Vcs.

[0154] The comparator 193 compares the voltage of the capacitor 192 with the reference voltage VREF0, and when the voltage of the capacitor 192 is lower than the reference voltage VREF0, outputs a signal opp_cmp of "H" level. On the other hand, when the voltage of the capacitor 192 is higher than the reference voltage VREF0, the comparator 193 outputs a signal opp_cmp of "L" level.

[0155] When a signal opp_cmp of "H" level is input for a predetermined period, the timer 73 outputs a signal opp_o of "H" level. On the other hand, when a signal opp_cmp of "L" level is input, the timer 73 outputs a signal opp_o of "L" level.

[0156] <<Other Embodiments of the AC-DC Converter>> FIG. 13 is a diagram showing an example of the configuration of an AC-DC converter 10b, which is a modification of the AC-DC converter 10a in FIG. 1. The AC-DC converter 10b is controlled by a control IC 42b, which is a modification of the control IC 42a, and is a circuit that does not use the diode 45 and the resistor 46 of the AC-DC converter 10a. In this embodiment, the same or similar configurations may be denoted by common reference numerals and redundant descriptions may be omitted.

[0157] By the way, the control IC 42a in FIG. 2 described above detects that the target level of the output voltage Vout has been changed based on the voltage Vcs of the terminal CS. However, in order to detect that the target level of the output voltage Vout has been changed, it is not always necessary to use the voltage Vcs of the terminal CS. The control IC 42b of this embodiment detects that the target level of the output voltage Vout has been changed based on the power supply voltage Vcc of the terminal VCC.

[0158] 14 is a diagram showing an example of the configuration of a control IC 42b. The control IC 42b includes an OPP 60c, which is a modified version of the OPP 60a, and a control circuit 62b, which is a modified version of the control circuit 62a. In FIG. 14, the resistor 61 and the terminals VCC, FB, CS, and OUT, which are assigned the same reference numerals as in FIG. 2, are the same as in FIG.

[0159] The OPP 60c detects that the target level of the output voltage Vout has changed based on the power supply voltage Vcc at the terminal VCC. Specifically, when the power supply voltage Vcc becomes lower than the reference voltage VREF8, the OPP 60c outputs a signal opp_o at an “H” level.

[0160] On the other hand, when the power supply voltage Vcc becomes higher than the reference voltage VREF8, the OPP 60c outputs a signal opp_o at a low level. The OPP 60c includes a comparator 74. The comparator 74 compares the power supply voltage Vcc with the reference voltage VREF8, and outputs a signal оpp_о at a low level when the power supply voltage Vcc is higher than the reference voltage VREF8. On the other hand, the comparator 74 outputs a signal оpp_о at a high level when the power supply voltage Vcc is lower than the reference voltage VREF8. The OPP 60c corresponds to a "detection circuit."

[0161] Fig. 15 is a diagram showing an example of the configuration of a control circuit 62b, which is a modified example of the control circuit 62a of Fig. 3. Since the control IC 42b does not operate when the power supply voltage Vcc applied to the terminal VCC is discharged, the discharge circuit 88 of Fig. 3 is not included in the control circuit 62b of Fig. 15. Furthermore, a description of other identical configurations will be omitted.

[0162] As described above, since the OPP 60c in the control IC 42b of this embodiment detects the voltage Vcc at the terminal VCC, the control IC 42b can detect that the target level of the output voltage Vout has been changed based on the voltage Vcc.

[0163] In this embodiment, the OCP 82 determines whether the inductor current IL flowing through the power transistor 40 is an overcurrent. The reference voltage ocp_ref, which is the determination threshold for determining an overcurrent by the OCP 82, is switched to the reference voltage VREF2 or VREF3 by the signal оpp_о, which is the detection result using the reference voltage VREF8 of the OPP 60c. The OCP 82 corresponds to an "overcurrent detection circuit."

[0164] <<<Operation of the control IC 42a when the mode transitions>>> ===Transition from "Normal Mode" to "OPP Mode"=== FIG. 16 is a diagram showing an example of the operation of the control IC 42b when transitioning from "normal mode" to "OPP mode." It is assumed that the voltage Vfb never becomes lower than the reference voltage VREF1. It is also assumed that the OR circuit 94 does not output an "H" level signal Soff. For ease of explanation, the period of the signal Sdrv is different from that in actual operation.

[0165] Furthermore, times t20 to t24 in Figure 16 correspond to times t10 to t14 in Figure 10. The decrease in voltage Vcc is also depicted as being gradual, unlike the actual decrease in voltage Vcc. The differences between Figure 16 and Figure 10 are explained below.

[0166] At time t21, when the voltage Vcs when the power transistor 40 is on becomes voltage Vfb, the power transistor 40 is turned off. When the power transistor 40 is turned off, the voltage Vcc is charged from the auxiliary coil L3 via the diode 50 and the resistor 51. At this time, the output power Pout begins to decrease, and the output voltage Vout also decreases slightly from the first target level (e.g., 32 V). However, because the output current Iout is large, the inductor current IL when the power transistor 40 is on is also large. Therefore, the voltage Va of the auxiliary coil L3 is also large, and the voltage Vcc does not decrease much regardless of the power consumption of the control IC 42b. Note that the voltage Vcs when the power transistor 40 is turned off becomes zero volts because the charge stored in the capacitor 43 is discharged via the resistors 41 and 44.

[0167] At time t23, when the voltage Vcs at which the power transistor 40 is turned on reaches the reduced voltage Vfb, the power transistor 40 is turned off, just as at time t21. At this time, the voltage Vcc is charged by the voltage Va from the auxiliary coil L3, but because the output power Pout and the output voltage Vout have already decreased, the inductor current IL when the power transistor 40 is on decreases. Therefore, the voltage Va of the auxiliary coil L3 also decreases, and the voltage Vcc gradually decreases in accordance with the power consumption of the control IC 42b.

[0168] At time t24, when the gradually decreasing voltage Vcc becomes lower than the reference voltage VREF8, the OPP 60c outputs an "H" level signal opp_o. At this time, the oscillator circuit 80 outputs an oscillation signal Vosc with a frequency Fsw0. The OCP 82 then switches the reference voltage ocp_ref from reference voltage VREF2 to reference voltage VREF3. Note that the control IC 42b operates in "normal mode" before time t24, and operates in "OPP mode" after time t24.

[0169] ===Transition from "OPP mode" to "normal mode"=== FIG. 17 is a diagram showing an example of the operation of the control IC 42b when transitioning from "OPP mode" to "normal mode." It is assumed that the control IC 42a is operating in "OPP mode" before time t25, and that the control IC 42a is operating in "OPP mode" from time t25 to time t26. It is also assumed that the voltage Vfb does not become lower than the reference voltage VREF1. It is also assumed that the OR circuit 94 does not output an "H" level signal Soff. As with FIG. 10, for ease of explanation, the period of the signal Sdrv is different from that in actual operation.

[0170] 17 corresponds to times t15 and t16 in FIG. 11. The rise in voltage Vcc is also depicted as being gradual, unlike the actual rise in voltage Vcc. The differences between FIG. 17 and FIG. 11 are explained below.

[0171] At time t25, it is determined that an inductor current IL that becomes an overcurrent flows through the power transistor 40, and the power transistor 40 is turned off. Therefore, the flow of the inductor current IL that becomes an overcurrent increases the voltage Va of the auxiliary coil L3, and the voltage Vcc begins to gradually rise regardless of the power consumption of the control IC 42b. Note that the voltage Vcs when the power transistor 40 is turned off becomes zero volts because the charge stored in the capacitor 43 is discharged via the resistors 41 and 44.

[0172] At time t26, when the gradually increasing voltage Vcc exceeds the reference voltage VREF8, the OPP 60c outputs a low-level signal opp_o. As a result, if the voltage Vfb is higher than the voltage Vfbd, the oscillator circuit 80 outputs an oscillation signal Vosc with a frequency Fsw2. Furthermore, when the OPP 60c outputs the low-level signal opp_o, the OCP 82 switches the reference voltage ocp_ref to the reference voltage VREF2.

[0173] ===Summary=== The AC-DC converter 10a of this embodiment has been described above. The control IC 42a includes an OPP 60a and a control circuit 62a. The OPP 60a detects whether the voltage Vcs when the power transistor 40 is off is lower than the reference voltage VREF0. This allows the control IC 42a to detect changes in the output voltage Vout of the AC-DC converter 10a using the voltage Vcs rather than the power supply voltage Vcc. This makes it possible to provide an integrated circuit that can more easily detect changes in the output voltage level. Cut.

[0174] The OPP 60a also includes a comparator 70 and a timer 73. The timer 73 outputs a signal opp_o based on whether the voltage Vcs remains lower than the reference voltage VREF0 for a predetermined period of time. This allows the OPP 60a to prevent erroneous detection of a drop in the voltage Vcs when the power transistor 40 is off during startup of the AC-DC converter 10a.

[0175] The control circuit 62a also includes an OCP 82 and a drive circuit 81. When the voltage Vcs drops below the reference voltage VREF0 for a predetermined period while the power transistor 40 is off, the OPP 60a outputs an "H" level signal opp_o and switches the reference voltage ocp_ref of the OCP 82 so that the overcurrent value decreases. This makes it possible to limit the power supplied to the secondary side of the transformer 22 in "OPP mode."

[0176] Furthermore, if the voltage Vcs when the power transistor 40 is off is higher than the reference voltage VREF0, the OPP 60a outputs a signal opp_o at an "L" level and switches the reference voltage ocp_ref of the OCP 82 so that the overcurrent value increases. This allows power to be appropriately supplied to the secondary side of the transformer 22 in "normal mode."

[0177] The control circuit 62a also includes an oscillation circuit 80. When a high-level signal opp_o is input to the oscillation circuit 80, the oscillation circuit 80 outputs an oscillation signal Vosc with a frequency Fsw0, and when a low-level signal opp_o is input, the oscillation circuit 80 outputs an oscillation signal Vosc with a frequency between Fsw0 and Fsw2. This prevents excessive power from being supplied to the secondary side of the transformer 22 in the OPP mode.

[0178] Furthermore, when the oscillator circuit 80 receives the signal opp_o at the "L" level, it outputs an oscillation signal Vosc with a frequency Fsw that increases stepwise from frequency Fsw0 to frequency Fsw2 as the voltage Vfb increases. This allows the oscillator circuit 80 to output an oscillation signal Vosc with a frequency Fsw1 even if the voltage Vfb varies within a predetermined range. Furthermore, it is possible to output an oscillation signal Vosc with a frequency Fsw2 only when it is desired to supply a large amount of power to the motor 30.

[0179] The control circuit 62a further includes an OVP 83. The OVP 83 outputs an “H” level signal ovp_o when the power supply voltage Vcc remains higher than the first predetermined voltage for a predetermined period of time. When the OVP 83 outputs the “H” level signal ovp_o, the buffer 93 turns off the power transistor 40.

[0180] Furthermore, a diode 50 that rectifies the voltage Va and a capacitor 49 are connected to the terminal VCC, and a diode 45 that rectifies the voltage Va and a capacitor 43 are connected to the terminal CS. This makes it possible to detect changes in the output voltage Vout using the voltage Vcs in the same way as detecting changes in the output voltage Vout using the power supply voltage Vcc. Furthermore, detecting changes in the output voltage Vout using the voltage Vcs enables various power supply circuits to detect changes in the output voltage Vout more easily than detecting changes in the output voltage Vout using the power supply voltage Vcc.

[0181] The control circuit 62a further includes a discharge circuit 88. The discharge circuit 88 discharges the capacitor 43 at the rising edge of the signal Sdrv. This allows the control IC 42a to detect, as the voltage Vcs, both the voltage Vb when the power transistor 40 is on and the voltage Va when the power transistor 40 is off.

[0182] The control IC 42b also includes an OPP 60c and a control circuit 62b. The OPP 60c detects whether the power supply voltage Vcc at the terminal VCC is lower than the reference voltage VREF8. This allows the control IC 42b to detect changes in the target level of the output voltage Vout of the AC-DC converter 10b based on the power supply voltage Vcc at the terminal VCC. This makes it possible to provide an integrated circuit that can more easily detect changes in the output voltage level.

[0183] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit thereof, and the present invention includes equivalents thereof. [Explanation of symbols]

[0184] 10a, 10b AC-DC converter 20 Full wave rectifier circuit 21, 25, 43, 47, 49, 180 capacitors 22 Transformer 23 Control Blocks 24,45 diode 26,27 Zener diode 28 Light-emitting diode 29 Switch 30 motor 40 Power transistor 42a, 42b Control IC 41,44,46,51,61,130,131,132,151,152,153,154,162,163,164,172 Resistance 48 Phototransistor 62a, 62b Control circuit 70,95,113,193 Comparators 71 One-shot circuit 72 D Flip-Flop 73 Timer 80 Oscillator Circuit 81 Drive circuit 86, 92, 94, 96 OR circuit 87 Latch 88 Discharge circuit 90,101,190 One-shot circuit 91 SR Flip-Flop 93 buffers 100,142,143,171,176,177,179,191 NMOS transistors 110,140,141 Inverter 111,112 Transfer Gate 120 Voltage divider circuit 121 Voltage selection circuit 122 First voltage circuit 123 Second voltage circuit 124 Voltage Controlled Oscillator Circuit 150, 155, 160, 165, 170 Op-amps 173, 174, 175, 178 PMOS transistors 181 Hysteresis Comparator

Claims

1. An integrated circuit for driving a transistor of a power supply circuit that generates an output voltage of a target level from an input voltage, the power supply circuit comprising: a transformer including a primary coil, a secondary coil, and an auxiliary coil; and a transistor that controls a current flowing through the primary coil, a first terminal to which a voltage corresponding to a coil voltage of the auxiliary coil is applied when the transistor is off; a second terminal to which a feedback voltage corresponding to the output voltage is applied; a third terminal to which a voltage corresponding to the current flowing through the transistor is applied when the transistor is on, and to which a voltage corresponding to the coil voltage is applied when the transistor is off; a first detection circuit that detects whether the voltage at the third terminal when the transistor is off is lower than a first reference voltage; a control circuit that controls switching of the transistor based on the feedback voltage, the voltage of the third terminal when the transistor is on, and the detection result of the first detection circuit; Including, The control circuit a second detection circuit that detects whether the current flowing through the transistor is greater than a predetermined current that is adjusted based on the detection result; a drive circuit that turns on the transistor based on an oscillation signal and turns off the transistor based on the voltage of the third terminal when the transistor is on and the feedback voltage; Including, The first detection circuit adjusting the predetermined current to be smaller when detecting that the voltage at the third terminal is lower than the first reference voltage when the transistor is off; The drive circuit When the current flowing through the transistor reaches the predetermined current, the transistor is turned off. Integrated circuit.

2. 10. The integrated circuit of claim 1, The first detection circuit a comparison circuit that compares the voltage of the third terminal with the first reference voltage; an output circuit that outputs the detection result based on whether or not a period during which the voltage of the third terminal is lower than the first reference voltage continues for a predetermined period when the transistor is off; An integrated circuit comprising:

3. 10. The integrated circuit of claim 1, The first detection circuit and adjusting the predetermined current to be larger when it is detected that the voltage at the third terminal when the transistor is off is higher than the first reference voltage. Integrated circuit.

4. 4. An integrated circuit according to claim 3, The first detection circuit When detecting that the voltage at the third terminal when the transistor is off is lower than the first reference voltage, a first signal is output as the detection result, and when detecting that the voltage at the third terminal when the transistor is off is higher than the first reference voltage, a second signal is output as the detection result; The control circuit an oscillation circuit that outputs the oscillation signal of a first frequency when the first signal is input, and outputs the oscillation signal of a frequency that is equal to or higher than the first frequency and that corresponds to the feedback voltage when the second signal is input; Integrated circuit.

5. 5. An integrated circuit according to claim 4, The oscillator circuit comprises: When the second signal is input, the frequency of the oscillation signal is increased stepwise from the first frequency to a third frequency via the second frequency based on the feedback voltage that changes in accordance with the decrease in the output voltage. Integrated circuit.

6. An integrated circuit according to any one of claims 1 to 5, The control circuit a third detection circuit for detecting whether the voltage at the first terminal is higher than a second reference voltage; The drive circuit turning off the transistor when the voltage at the first terminal is higher than the second reference voltage; Integrated circuit.

7. An integrated circuit according to any one of claims 1 to 6, The first terminal has a first diode that rectifies the coil voltage and a first capacitor that is charged with a current from the first diode are connected; The third terminal has a detection resistor that detects a current flowing through the transistor when the transistor is on, a second diode that rectifies the coil voltage, and a second capacitor that is charged with a current from the second diode are connected; Integrated circuit.

8. 8. An integrated circuit according to claim 7, The control circuit a discharge circuit configured to discharge the second capacitor for a period shorter than an on-period of the transistor when the transistor is turned on; Integrated circuit.

9. A power supply circuit that generates an output voltage of a target level from an input voltage, comprising: a transformer including a primary coil, a secondary coil, and an auxiliary coil; a transistor that controls a current flowing through the primary coil; and an integrated circuit that has first to third terminals and drives the transistor, a first diode that rectifies the coil voltage of the auxiliary coil; a first capacitor connected to the first terminal and charged with current from the first diode; a detection resistor connected to the third terminal and configured to detect a current flowing through the transistor when the transistor is turned on; a second diode for rectifying the coil voltage; a second capacitor connected to the third terminal and charged with current from the second diode; Including, The integrated circuit comprises: a first detection circuit that detects whether the voltage at the third terminal when the transistor is off is lower than a first reference voltage; a control circuit that controls switching of the transistor based on a feedback voltage that corresponds to the output voltage applied to the second terminal, a voltage of the third terminal when the transistor is on, and a detection result of the first detection circuit; Including, The control circuit a second detection circuit that detects whether the current flowing through the transistor is greater than a predetermined current that is adjusted based on the detection result; a drive circuit that turns on the transistor based on an oscillation signal and turns off the transistor based on the voltage of the third terminal when the transistor is on and the feedback voltage; Including, The first detection circuit adjusting the predetermined current to be smaller when detecting that the voltage at the third terminal is lower than the first reference voltage when the transistor is off; The drive circuit When the current flowing through the transistor reaches the predetermined current, the transistor is turned off. power circuit.

10. An integrated circuit for driving a transistor of a power supply circuit that generates an output voltage of a target level from an input voltage, the power supply circuit comprising: a transformer including a primary coil, a secondary coil, and an auxiliary coil; and a transistor that controls a current flowing through the primary coil, a first terminal to which a voltage corresponding to a coil voltage of the auxiliary coil is applied when the transistor is off; a second terminal to which a feedback voltage corresponding to the output voltage is applied; a third terminal to which a voltage corresponding to a current flowing through the transistor when the transistor is turned on is applied; a detection circuit that detects whether the voltage at the first terminal when the transistor is off is lower than a reference voltage; a control circuit that controls switching of the transistor based on the feedback voltage, the voltage of the third terminal when the transistor is on, and the detection result of the detection circuit; Including, an overcurrent detection circuit that determines whether a current flowing through the transistor is an overcurrent or not is connected to the third terminal; An integrated circuit in which a determination threshold for determining an overcurrent of the overcurrent detection circuit is switched depending on a detection result using the reference voltage of the detection circuit.

11. A power supply circuit that generates an output voltage of a target level from an input voltage, comprising: a transformer including a primary coil, a secondary coil, and an auxiliary coil; a transistor that controls a current flowing through the primary coil; and an integrated circuit that has first to third terminals and drives the transistor, a first diode that rectifies the coil voltage of the auxiliary coil; a first capacitor connected to the first terminal and charged with current from the first diode; a detection resistor connected to the third terminal and configured to detect a current flowing through the transistor when the transistor is turned on; Including, The integrated circuit comprises: a detection circuit that detects whether the voltage at the first terminal when the transistor is off is lower than a reference voltage; a control circuit that controls switching of the transistor based on a feedback voltage that corresponds to the output voltage applied to the second terminal, a voltage of the third terminal when the transistor is on, and a detection result of the detection circuit; Including, an overcurrent detection circuit that determines whether a current flowing through the transistor is an overcurrent or not is connected to the third terminal; A power supply circuit in which a determination threshold for determining an overcurrent in the overcurrent detection circuit is switched depending on a detection result using the reference voltage of the detection circuit.

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