Display driver and display module

Abstract

To provide a display driver and a display module that can properly detect an abnormal state of an output signal.SOLUTION: A display driver 20 includes: a driver circuit 31 that drives an electro-optical panel 200; an output terminal TO that outputs an output signal SGO from the driver circuit 31; an output line LO that connects an output of the driver circuit 31 and the output terminal TO to each other; and an inspection circuit 41 that monitors the voltage of the output signal SGO that the driver circuit 31 outputs to the output line LO to detect an abnormality in the output signal SGO. The inspection circuit 41 compares a reference voltage VREF in which voltage changes for every given period and the voltage of the output signal SGO with each other to determine whether the voltage of the output signal SGO is abnormal or not.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a display driver, a display module, and the like. [Background technology]

[0002] Patent Document 1 discloses a common driver for a display panel that includes: a voltage output circuit that outputs different test voltages to a test voltage output line in a first period and a second period, and outputs a first voltage to a first segment electrode and a second voltage to a second segment electrode in the first period and the second period, a signal output circuit that outputs a first signal voltage to a signal voltage output line in the first period and a second signal voltage in the second period, and a test circuit that tests for abnormalities based on the voltage of the test voltage output line and the voltage of the signal voltage output line. This common driver can detect abnormalities in the voltage applied to the electrodes of the display panel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-56344 Summary of the Invention [Problem to be solved by the invention]

[0004] The common driver of the display panel shown in Patent Document 1 has a fixed reference voltage value set to determine whether the output voltage of the output signal of the common driver is normal or not, so depending on the value of the output voltage when an abnormal state occurs, the abnormal state may not be properly determined. [Means for solving the problem]

[0005] One aspect of the present disclosure includes a driver circuit that drives an electro-optical panel, an output terminal that outputs an output signal from the driver circuit, an output line that connects the output of the driver circuit to the output terminal, and an inspection circuit that detects abnormalities in the output signal by monitoring the voltage of the output signal that the driver circuit outputs to the output line, wherein the inspection circuit is related to a display driver that determines whether the voltage of the output signal is abnormal by comparing the voltage of the output signal with a reference voltage that changes at every given period.

[0006] Another aspect of the present disclosure relates to a display module including the display driver described above and the electro-optical panel. [Brief explanation of the drawings]

[0007] [Figure 1] 3 shows an example of the configuration of a display driver according to the present embodiment. [Figure 2] FIG. 4 is an explanatory diagram of the wiring state between a display driver and segment electrodes of an electro-optical panel. [Figure 3] FIG. 4 is an explanatory diagram of the wiring state between the display driver and the common electrode of the electro-optical panel. [Figure 4] 3 shows a detailed configuration example of a display driver according to the present embodiment. [Figure 5] 3 shows an example of the configuration of an electrostatic protection circuit according to the present embodiment. [Figure 6] 3 shows an example of the configuration of an electrostatic protection circuit according to the present embodiment. [Figure 7] 3 shows an example of the configuration of an electrostatic protection circuit according to the present embodiment. [Figure 8] 3 shows an example of the configuration of a reference voltage generating circuit according to the present embodiment. [Figure 9] 3 shows an example of the configuration of a selector of the reference voltage generating circuit of the present embodiment. [Figure 10] 10 shows an example of criteria for determining an abnormal state of the voltage of the output signal in the segment inspection circuit. [Figure 11] Equivalent circuit diagram when the panel signal line is shorted to the power supply voltage. [Figure 12] Examples of signal waveforms when a panel signal line is shorted to the power supply voltage. [Figure 13] Example of waveforms of various signals when an abnormal voltage state is not properly determined when a panel signal line is shorted to the power supply voltage. [Figure 14] An example of the waveforms of various signals when an abnormal voltage state is properly determined when a panel signal line is shorted to the power supply voltage. [Figure 15] Equivalent circuit diagram when the panel signal line is shorted to ground. [Figure 16] Examples of signal waveforms when a panel signal line is shorted to ground. [Figure 17] Example of waveforms of various signals when an abnormal voltage state is not properly determined when a panel signal line is shorted to ground. [Figure 18] Example of various signal waveforms when an abnormal voltage state is properly determined when a panel signal line is shorted to ground. [Figure 19] 10 is a first signal waveform example of the reference voltage of the present embodiment when a panel signal line is shorted to the power supply voltage. [Figure 20] 10 is a first signal waveform example of the reference voltage of the present embodiment when a panel signal line is shorted to ground. [Figure 21] 10 shows a second signal waveform example of the reference voltage of the present embodiment when a panel signal line is shorted to the power supply voltage. [Figure 22] 10 shows a second signal waveform example of the reference voltage of the present embodiment when a panel signal line is shorted to ground. [Figure 23] Example of command settings for the first reference voltage. [Figure 24] Example of command settings for the second reference voltage. [Figure 25] 2 shows an example of the configuration of a display module according to the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the content of the claims. Furthermore, not all of the configurations described in the present embodiment are necessarily essential components.

[0009] 1. Display driver 1 shows an example of the configuration of a display driver 20 of this embodiment. The display driver 20 includes a segment driver circuit 30, a common driver circuit 70, a segment inspection circuit 40, a common inspection circuit 80, a line latch 50, a data storage unit 60, an oscillator circuit 102, a control circuit 100, and an interface circuit 110. A processing device 120 is provided outside the display driver 20. The processing device 120 can communicate with the display driver 20 regarding, for example, information to be displayed on the electro-optical panel 200. Based on signals from the display driver 20, the electro-optical panel 200 displays numbers and the like using segments, which will be described later in FIGS. 2 and 3.

[0010] The interface circuit 110 performs communication between the display driver 20 and the processing device 120. Specifically, the interface circuit 110 receives segment drive data SGD from the processing device 120. The segment drive data SGD is data for controlling the display of the electro-optical panel 200, which will be described later with reference to FIGS. 2 and 3. For example, in the case of static drive, the segment drive data SGD is data for turning on or off the display of the electro-optical panel 200. Alternatively, in the case of PWM drive in static drive, the segment drive data SGD is data for setting the display gradation of the electro-optical panel 200.

[0011] The processing device 120 is a host device for the display driver 20. The processing device 120 is, for example, a processor or a display controller. Here, the processor is, for example, a CPU or a microcomputer. As a communication method for the interface circuit 110, a serial interface method such as an I2C (Inter Integrated Circuit) method or an SPI (Serial Peripheral Interface) method can be adopted. Alternatively, a parallel interface method may be adopted as the communication method for the interface circuit 110. The interface circuit 110 can include an input / output buffer circuit and a control circuit that realize these communication methods.

[0012] The control circuit 100 is a logic circuit that operates based on a clock signal input from, for example, an oscillator circuit 102. The control circuit 100 is responsible for all the control required to drive the electro-optical panel 200. Specifically, the control circuit 100 controls the segment driver circuit 30 and the common driver circuit 70, and monitors the display state of the electro-optical panel 200, which will be described later with reference to FIG.

[0013] The data storage unit 60 mainly stores information input from the control circuit 100. The data storage unit 60 is, for example, a RAM. Alternatively, the data storage unit 60 may be a register.

[0014] The line latch 50 latches one frame of segment drive data read from the data storage unit 60. The line latch 50 is configured by, for example, a flip-flop circuit.

[0015] The segment driver circuit 30 drives the electro-optical panel 200. The segment driver circuit 30 supplies voltage to the segment electrodes ES, which will be described later in Fig. 2. Specifically, the segment driver circuit 30 supplies voltage to the segment electrodes ES by outputting a segment drive signal according to the polarity from a segment terminal.

[0016] The common driver circuit 70 drives the electro-optical panel 200 together with the segment driver circuit 30. The common driver circuit 70 supplies a voltage to the common electrodes EC, which will be described later in FIG. 3. Specifically, the common driver circuit 70 supplies a voltage to the common electrodes EC by outputting a common drive signal according to the polarity from a common terminal. The common drive signal is a low-level signal when it is positive polarity and a high-level signal when it is negative polarity.

[0017] The segment inspection circuit 40 inspects whether the display on the electro-optical panel 200 is normal. Specifically, it inspects whether the voltage of the output signal from the segment driver circuit 30 is a desired voltage. The segment inspection circuit 40 outputs the inspection result to the control circuit 100. If the detection result indicates a drive abnormality, the control circuit 100 notifies the processing device 120 of the drive abnormality via the interface circuit 110.

[0018] Like the segment inspection circuit 40, the common inspection circuit 80 also inspects whether the display on the electro-optical panel 200 is normal. Unlike the segment inspection circuit 40, the common inspection circuit 80 inspects whether the voltage of the output signal from the common driver circuit 70 is the desired voltage. The common inspection circuit 80 outputs the inspection result to the control circuit 100. If the detection result indicates a drive abnormality, the control circuit 100 notifies the processing device 120 of the drive abnormality via the interface circuit 110.

[0019] 2 and 3 are diagrams showing the wiring state of the electro-optical panel 200 and the display driver 20. Fig. 2 shows an example of connection between the display driver 20 and the segment electrodes ES, and Fig. 3 shows an example of connection between the display driver 20 and the common electrodes EC. The electro-optical panel 200 includes a glass substrate on which the segment electrodes ES are provided, a glass substrate on which the common electrodes EC are provided, and liquid crystal provided between them.

[0020] As shown in FIG. 2, the electro-optical panel 200 includes segment electrodes ESD1, ESD2, and ESS1 to ESS7 and segment signal lines LSD1 to LSD4 and LSS1 to LSS7. In this embodiment, these segment electrodes and segment signal lines are collectively referred to as segment electrodes ES and segment signal lines LS, as appropriate. The display driver 20 includes segment terminals TSD1 to TSD4 and TSS1 to TSS7 and common terminals TCD1 and TCD2. As shown in FIG. 3, the electro-optical panel 200 includes common electrodes ECD1, ECD2, and ECS1 to ECS7 and common signal lines LCD1 to LSD6. In this embodiment, these common electrodes and common signal lines are collectively referred to as common electrodes EC and common signal lines LC, as appropriate. The segment electrodes ES and segment signal lines LS are transparent conductive films provided on a glass substrate. The transparent conductive film is, for example, ITO (Indium Tin Oxide). Of this transparent conductive film, the portion facing the common electrode EC across the liquid crystal is the segment electrode ES, and the portion that supplies a segment drive signal to the segment electrode ES is the segment signal line LS. For example, the segment electrode ESD1 and the segment signal lines LSD1 and LSD2 are formed from an integrated transparent conductive film. Of these, the portion facing the common electrode ECD1 in FIG. 3 is the segment electrode ESD1. In the following description, the segment signal line LS and the common signal line LC will each be referred to as a panel signal line LPN, and the segment terminals TSD1 to TSD4, TSS1 to TSS7 and the common terminals TCD1 and TCD2 will each be referred to as an output terminal TO, as appropriate.

[0021] The display driver 20 is mounted on the glass substrate of the electro-optical panel 200. Specifically, the display driver 20 is an integrated circuit device, and pads formed on its semiconductor substrate correspond to the segment terminals TSD1 to TSD4 and TSS1 to TSS7. The semiconductor substrate is mounted on the electro-optical panel 200 so that the surface on which the pads are provided faces the glass substrate of the electro-optical panel 200. At this time, the segment terminal TSD1 is connected to the segment signal line LSD1 via, for example, a metal bump. Similarly, the segment terminals TSD2 to TSD4 are connected to the segment signal lines LSD2 to LSD4, and TSS1 to TSS7 are connected to the segment signal lines LSS1 to LSS7. Note that while FIG. 2 shows the surface of the semiconductor substrate on which no segment terminals are provided, segment terminals and the like hidden by the semiconductor substrate are also shown.

[0022] The display driver 20 outputs a segment drive signal from the segment terminal TSD1, thereby supplying a voltage to the segment electrode ESD1 via the segment signal line LSD1. The segment electrode ESD1 has a predetermined icon shape, and the display driver 20 controls whether the icon is displayed or not by supplying a voltage to the segment electrode ESD1. The segment drive signal is then fed back from the segment electrode ESD1 to the segment terminal TSD2 via the segment signal line LSD2. This fed-back segment drive signal is called a segment monitor signal. The display driver 20 detects an abnormality in the voltage supplied to the segment electrode ESD1 based on the segment monitor signal input to the segment terminal TSD2. Such an abnormality may occur, for example, when the segment drive signal voltage that should be applied to the segment electrode ES is not applied. Such an abnormality may be due to, for example, an abnormality in the segment signal line, a poor connection at the segment terminal, or an abnormality in the segment drive signal.

[0023] Similarly, the display driver 20 supplies a voltage to the segment electrode ESD2 by outputting a segment drive signal from the segment terminal TSD3. The display driver 20 then detects an abnormality in the voltage supplied to the segment electrode ESD2 based on the segment monitor signal input to the segment terminal TSD4.

[0024] The display driver 20 outputs segment drive signals from the segment terminals TSS1 to TSS7, thereby supplying voltages to the segment electrodes ESS1 to ESS7 via the segment signal lines LSS1 to LSS7.

[0025] 2. Detailed configuration example Fig. 4 shows a detailed configuration example of the display driver 20 of this embodiment. In addition to the configuration of the display driver 20 shown in Fig. 1, the display driver 20 in Fig. 4 has a polarity inversion circuit 82, an electrostatic protection circuit 90, and an output terminal TO. The driver circuit 31 has a level shifter 32 and an output driver 34, and the inspection circuit 41 has a reference voltage generation circuit 140, a comparison circuit 150, a level shifter 152, a determination circuit 160, and a switch SW. The driver circuit 31 in Fig. 4 corresponds to each of the segment driver circuit 30 and the common driver circuit 70, and the inspection circuit 41 corresponds to each of the segment inspection circuit 40 and the common inspection circuit 80.

[0026] The polarity inversion circuit 82 performs polarity inversion processing on the segment drive data SGD based on the polarity signal POL from the control circuit 100. That is, in frames of positive polarity, the polarity inversion circuit 82 outputs segment drive data SGD at the same logical level as the segment drive data SGD, and in frames of negative polarity, outputs segment drive data SGD with the logical level of the segment drive data SGD inverted.

[0027] The level shifter 32 of the driver circuit 31 performs a level shift on the segment signal SLAT. Specifically, the level shifter 32 outputs a signal with the same waveform as the input segment signal SLAT but a different voltage. The level shifter 32 can be configured with an inverter, a MOS transistor, a resistor element, etc.

[0028] The output driver 34 outputs the output signal SGO to the electrostatic protection circuit 90 based on the signal output from the level shifter 32. The output driver 34 can be configured by an inverter configured by, for example, a P-type transistor and an N-type transistor.

[0029] The output terminal TO is an external connection terminal of the display driver 20. When a voltage is supplied from the display driver 20 to the segment electrodes ES and common electrodes EC of the electro-optical panel 200, the voltage is supplied from the output terminal TO. As described above with reference to FIGS. 2 and 3, TCD1, TCD2, TSS1 to TSS7, and TSD1 to TSD4 correspond to the output terminal TO in FIG.

[0030] The output line LO is an electrical wiring that electrically connects the driver circuit 31 and the output terminal TO. The output signal SGO output from the driver circuit 31 is input to the electrostatic protection circuit 90 via the output line LO. The output signal SGO is then input from the output terminal TO to the electro-optical panel 200 via the panel signal line LPN. Here, the output signal output from the output terminal TO to the electro-optical panel 200 is referred to as an output signal SGOP to distinguish it from the output signal SGO inside the display driver 20. In this way, a voltage is supplied to the segment electrodes ES of the electro-optical panel 200.

[0031] The reference voltage generation circuit 140 generates a reference voltage VREF that serves as a reference when the inspection circuit 41 determines whether the voltage of the output signal SGO is a predetermined voltage. The generated reference voltage VREF is then output to the comparison circuit 150. The reference voltage generation circuit 140 can be realized by, for example, a bandgap reference circuit, a circuit using a difference in gate work function, or a circuit using a difference in threshold voltage caused by changing the channel impurity concentration.

[0032] As described above, the display driver 20 of this embodiment includes a driver circuit for driving the electro-optical panel 200, an output terminal TO for outputting an output signal SGO from the driver circuit, an output line LO connecting the output of the driver circuit to the output terminal TO, and an inspection circuit 41 for detecting an abnormality in the output signal by monitoring the voltage of the output signal SGO output from the driver circuit to the output line LO. The inspection circuit 41 determines whether the voltage of the output signal is abnormal by comparing the voltage of the output signal with a reference voltage VREF, which changes every given period. For example, a certain reference voltage VREF setting may not accurately determine whether the voltage of the output signal SGO is the desired voltage. However, according to this embodiment, the reference voltage VREF can be changed every given period, allowing for reliable detection of abnormalities in the output signal SGO depending on individual abnormalities. In the display driver 20 of this embodiment, the given period is a frame period T, and the inspection circuit 41 may compare the voltage of the output signal SGO with a reference voltage VREF, which changes every frame period T. In this way, an abnormal state in the voltage of the output signal SGO of the driver circuit 31 can be detected within the frame period T. Furthermore, the given period is a frame division period Tdiv obtained by dividing the frame period T, and the inspection circuit may compare the voltage of the output signal SGO with a reference voltage VREF, whose voltage changes every frame division period Tdiv. In this way, when the given period of the reference voltage VREF is set to the frame division period Tdiv, the period of the signal waveform of the reference voltage VREF is shorter than when the given period is set to the frame period T, and an abnormal state in the voltage of the output signal SGO can be detected quickly.

[0033] The electrostatic protection circuit 90 in Fig. 4 is a protection circuit for ESD (Electro-Static Discharge). The electrostatic protection circuit 90 is provided between the driver circuit 31 and the output terminal TO. When a surge voltage such as static electricity is applied to the output terminal TO, the electrostatic protection circuit 90 protects the circuits and elements provided inside the display driver 20 by discharging the static charge to ground or a power supply. The electrostatic protection circuit 90 is configured, for example, by an electrostatic protection element, which is an ESD protection element. The electrostatic protection element is, for example, an electrostatic protection diode or an electrostatic protection resistor.

[0034] 5 to 7 show specific configuration examples of the electrostatic protection circuit 90. The basic configuration of the electrostatic protection circuit 90 is such that an output signal SGOP containing noise due to an external surge voltage or the like is input to the internal circuit 132 via a protective resistor RESD. Two PN diodes are provided to connect to either or both of the wiring between the output terminal TO and the protective resistor RESD and the wiring between the protective resistor RESD and the internal circuit 132, so that charge due to overvoltage is discharged to the power supply or ground. In the configuration of FIG. 5, the wiring connecting the output terminal TO and the protective resistor RESD is connected to the power supply and ground via PN diodes. In the configuration of FIG. 6, the wiring connecting the protective resistor RESD and the internal circuit 132 is connected to the power supply and ground via PN diodes. In addition, in the configuration of FIG. 7, PN diodes are connected to the wiring connecting the output terminal TO and the protective resistor RESD and the wiring connecting the protective resistor RESD and the internal circuit 132.

[0035] As described above, the display driver 20 of this embodiment may include an electrostatic protection circuit 90 provided between the output line LO and the output terminal TO. In this way, when a surge voltage such as static electricity is applied to the output terminal TO, the static charge is discharged to the ground or the power supply, thereby protecting the circuits and elements provided inside the display driver 20 from malfunctions due to overvoltage. Furthermore, the electrostatic protection circuit 90 of the display driver 20 of this embodiment may include a protective resistor RESD provided between the output line LO and the output terminal TO. In this way, even when a large surge voltage is applied to the output terminal TO, the circuits and elements provided inside the display driver 20 can be appropriately protected from malfunctions due to overvoltage.

[0036] 4 is provided between the output line LO connecting the driver circuit 31 and the electrostatic protection circuit 90 and the comparison circuit 150 of the inspection circuit 41. The on / off of the switch SW is controlled based on a signal from the control circuit 100. Specifically, when the switch is turned on, the voltage of the output signal SGO of the output line LO is input to the comparison circuit 150, making it possible to monitor the voltage of the output signal SGO in the comparison circuit 150. The switch SW can be realized by a MOS transistor or the like.

[0037] The aforementioned reference voltage generation circuit 140 will now be described in detail. FIG. 8 shows a detailed configuration example of the reference voltage generation circuit 140. The reference voltage generation circuit 140 includes a selector 142, a selector 144, and resistors RH0-RH7 and RL0-RL7. Here, the reference voltage VREF includes a first reference voltage VREFH and a second reference voltage VREFL. When the inspection circuit 41 inspects the voltage of the output signal SGO for abnormalities, the reference voltage used when inspecting the high state of the signal waveform is the first reference voltage VREFH, and the reference voltage used when inspecting the low state is the second reference voltage VREFL. The control circuit 100 instructs the reference voltage generation circuit 140 as to which of multiple voltages to select as the reference voltage VREF, and the reference voltage generation circuit 140 generates the first reference voltage VREFH and the second reference voltage VREFL based on the instruction. Specifically, the control circuit 100 transmits a signal SVREFH to the selector 142 to set the first reference voltage VREFH, and the selector 142 generates the first reference voltage VREFH based on the signal SVREFH. The control circuit 100 also transmits a signal SVREFL to the selector 144 to set the second reference voltage VREFL, and the selector 144 generates the second reference voltage VREFL based on the signal SVREFL. The resistors RH0 to RH7 are each connected in series between the ground voltage VGND and the power supply voltage VDD. Voltages VRH0 to VRH7 and VRL0 to VRL7 are generated within the reference voltage generating circuit 140 in accordance with the voltage drops across the resistors RH0 to RH7. The voltages VRH0 to VRH7 are input to the selector 142, and the voltages VRL0 to VRL7 are input to the selector 144.

[0038] 9 shows the internal configuration of the selectors 142, 144 of the reference voltage generating circuit 140. The selectors 142, 144 are configured with an inverter and multiple switches SW. The input voltage signal IN0 is a voltage signal corresponding to the voltage VRH0 or the voltage VRL0. The same applies to the input voltage signals IN1 to IN7. The selectors 142, 144 select one of the input voltage signals IN1 to IN7 based on instructions from the control circuit 100, and are able to output the voltage instructed by the control circuit 100. In this way, the selectors 142 and 144 generate the first reference voltage VREFH and the second reference voltage VREFL, which are then output from the reference voltage generating circuit 140.

[0039] The comparator circuit 150 in FIG. 4 inspects the voltage of the output signal SGO of the driver circuit 31. Specifically, the comparator circuit 150 performs this inspection by comparing the voltage of the output signal SGO with a first reference voltage VREFH and a second reference voltage VREFL. The comparator circuit 150 may be configured, for example, with a comparator. FIG. 10 shows an example of criteria for determining whether the voltage of the output signal is in an abnormal state. This determination is performed by comparing the voltage of the output signal SGO with a first voltage VH, a second voltage VL, a first reference voltage VREFH, and a second reference voltage VREFL. Here, the first voltage VH is a high-potential voltage, such as a power supply voltage. The second voltage VL is a low-potential voltage, such as a ground voltage VGND. The relationship is VH > VREFH > VREFL > VL. If the voltage of the output signal SGO is between the first reference voltage VREFH and the first voltage VH, the comparator circuit 150 determines that the voltage is in a High state. If the voltage of the output signal SGO is between the second voltage VL and the second reference voltage VREFL, it is determined to be in the Low state. If the output voltage is between the first reference voltage VREFH and the second reference voltage VREFL, it is determined to be an error. The comparator circuit 150 outputs the determination result CQ to the level shifter 152.

[0040] The level shifter 152 performs a level shift on the output signal of the comparison circuit 150. Specifically, the level shifter 152 outputs a signal with the same waveform as the determination result CQ from the comparison circuit 150 but with a different voltage value. For example, the level shifter 152 performs level conversion from a high-voltage power supply voltage level to a low-voltage power supply voltage level. Like the level shifter 32, the level shifter 152 can be configured using inverters, MOS transistors, resistor elements, etc.

[0041] Based on the segment monitor output signal SGMO output from the level shifter 152, the judgment circuit 160 judges whether the output signal SGO output from the driver circuit 31 is being normally supplied to the segment electrode ES of the electro-optical panel 200, and transmits the judgment result SGDT to the control circuit 100.

[0042] As described above, in the display driver 20 of this embodiment, the inspection circuit 41 may include a reference voltage generation circuit 140 that generates a plurality of voltages and outputs a reference voltage VREF selected from the plurality of voltages for each given period, and a comparison circuit 150 that compares the reference voltage VREF with the voltage of the output signal SGO. In this way, by comparing the reference voltage VREF selected from a plurality of voltage levels for each given period with the voltage of the output signal SGO in the comparison circuit 150, it is possible to reliably detect an abnormal state of the voltage of the output signal SGO of the driver circuit 31.

[0043] Furthermore, the control circuit 100 of the display driver 20 of this embodiment may instruct the reference voltage generation circuit 140 which of a plurality of voltages to select as the reference voltage VREF. In this way, when the voltage change of the output signal SGO of the driver circuit 31 is within a certain range, the setting level of the reference voltage VREF can be preset in the control circuit 100.

[0044] FIG. 11 is an equivalent circuit diagram of the display driver 20 when the panel signal line LPN, i.e., the wiring between the output terminal TO and the segment electrode ES of the electro-optical panel 200, is shorted to the power supply voltage VDD. In FIG. 11, the N-type transistor constituting the output driver 34 is on, and the voltage of the output signal SGO is set to the ground voltage VGND. The output driver 34 can be configured with a P-type transistor and an N-type transistor connected in series between VDD and GND. The switch SW is also on. In this case, the panel signal line LPN is shorted to the power supply voltage VDD, so the output signal SGOP supplied to the electro-optical panel 200 is the power supply voltage VDD. Therefore, the voltage at the wiring node between the on-resistance RON and the protective resistor RESD is between the ground voltage VGND and the power supply voltage VDD, and is the voltage divided by the on-resistance RON of the N-type transistor of the output driver 34 and the protective resistor RESD, VDV1 = (VDD - VGND) × RON / (RON + RESD). That is, during the period when the N-type transistor of the output driver 34 is turned on and the output signal SGO is normally at the ground voltage VGND, the occurrence of the short circuit causes the output signal SGO to increase to the divided voltage VDV1 = (VDD - VGND) x RON / (RON + RESD).

[0045] FIG. 12 is a signal waveform diagram showing the waveforms of various signals when the panel signal line LPN is shorted to the power supply voltage VDD. The segment drive data SGD is a rectangular wave synchronized with a clock signal of a constant frequency controlled by the oscillator circuit 102. The latch pulse LP is a pulse signal for latching the segment drive data SGD at the center of a high-level period or a low-level period. The segment signal SLAT is a signal obtained by latching the segment drive data SGD using the latch pulse LP. As shown in FIG. 12, T1 denotes the first frame period, T2 denotes the second frame period, T3 denotes the third frame period, and so on. This also applies to FIGS. 13 to 22. A frame period is the period of a display frame of the electro-optical panel 200, and the latch pulse LP is a pulse signal that goes high every frame period. FIG. 12 shows a case where a short circuit between the panel signal line LPN and the power supply voltage VDD occurs at the beginning of the fifth frame period T5. After the fifth frame period T5 in which the short circuit occurs, the voltage of the panel signal line LPN becomes the power supply voltage VDD due to the short circuit. Therefore, the voltage of the output signal SGO on the output line LO becomes the divided voltage VDV1=(VDD-VGND)×RON / (RON+RESD) during the fifth frame period T5 and the seventh frame period T7, which are periods when the voltage is normally ground voltage, as described above.

[0046] FIG. 13 is a signal waveform diagram showing various signal waveforms in the comparison circuit 150 and the determination circuit 160 in the case of FIG. 12. The signal waveform diagram shown in the upper part of FIG. 13 is a signal waveform diagram in which the output signal SGO input to the comparison circuit 150, the first reference voltage VREFH, and the second reference voltage VREFL are superimposed. Here, the output signal SGO is indicated by a solid line, the first reference voltage VREFH by a dashed line, and the second reference voltage VREFL by a dashed-dotted line. As described above, in the fifth frame period T5 and the seventh frame period T7, when the output signal SGO is to output the divided voltage VDV1=(VDD-VGND)×RON / (RON+RESD), the output signal SGO does not fall to the ground voltage VGND. Therefore, the determination circuit 160 should normally determine that the voltage of the output signal SGO is abnormal. However, in the example of Figure 13, the second reference voltage VREFL, indicated by the dashed-dotted line, is set to a voltage greater than the divided voltage VDV1, resulting in an erroneous determination that the voltage of the output signal SGO is normal during the fifth frame period T5 and the seventh frame period T7. Figure 14 shows an example in which the voltage levels of the first reference voltage VREFH and the second reference voltage VREFL are different from those in Figure 13. That is, compared to the example of Figure 13, the first reference voltage VREFH is closer to the first voltage VH, e.g., the power supply voltage VDD, and the second reference voltage VREFL is closer to the second voltage VL, e.g., the ground voltage VGND. In this case, during the fifth frame period T5 and the seventh frame period T7, which were erroneously determined in Figure 13, the voltage of the output signal SGO is higher than the second reference voltage VREFL, indicated by the dashed-dotted line, resulting in a correct determination that the output signal SGO is in an abnormal state.

[0047] 15 is an equivalent circuit diagram inside the display driver 20 when the panel signal line LPN, i.e., the wiring between the output terminal TO and the segment electrode ES of the electro-optical panel 200, is shorted to the ground voltage VGND. In FIG. 15, the P-type transistor constituting the output driver 34 is on, and the voltage of the output signal SGO is set to the power supply voltage VDD. Furthermore, the switch SW is on. In this case, the panel signal line LPN is shorted to the ground voltage VGND, and therefore the output signal SGOP supplied to the electro-optical panel 200 is set to the ground voltage VGND. Therefore, the voltage of the output signal SGO at the wiring node between the on-resistance RON and the protective resistor RESD is between the ground voltage VGND and the power supply voltage VDD, and is the voltage divided by the on-resistance RON of the P-type transistor of the output driver 34 and the protective resistor RESD of the electrostatic protection circuit 90, VDV2 = (VDD - VGND) × RESD / (RON + RESD). That is, during the period when the P-type transistor of the output driver 34 is turned on and the output signal SGO is normally at the power supply voltage VDD, the short circuit occurs, causing the output signal SGO to decrease to the divided voltage VDV2 = (VDD - VGND) × RESD / (RON + RESD).

[0048] FIG. 16 is a signal waveform diagram showing the waveforms of various signals when the panel signal line LPN is shorted to the ground voltage VGND. The segment drive data SGD, latch pulse LP, and segment signal SLAT are as described in FIG. 12. FIG. 16 illustrates a case where the short occurs in the middle of the fourth frame period T4. In FIG. 16, due to the short, the voltage of the panel signal line LPN becomes the ground voltage VGND from the middle of the fourth frame period T4. Therefore, as described above, during the fourth frame period T4, sixth frame period T6, and eighth frame period T8, when the output signal SGO should be the power supply voltage VDD, the output signal SGO becomes a divided voltage VDV2=(VDD-VGND)×RESD / (RON+RESD) obtained by dividing the on-resistance RON of the output driver 34 and the protective resistance RESD of the electrostatic protection circuit 90.

[0049] FIG. 17 is a signal waveform diagram showing various signal waveforms in the comparison circuit 150 and the determination circuit 160 in the case of FIG. 16. The signal waveform diagram shown in the upper part of FIG. 17 shows the signal waveforms of the output signal SGO, the first reference voltage VREFH, and the second reference voltage VREFL input to the comparison circuit 150, superimposed on each other. As in FIGS. 13 and 14, in FIGS. 17 and 18, the output signal SGO is shown by a solid line, the first reference voltage VREFH is shown by a dashed line, and the second reference voltage VREFL is shown by a dashed line. As described above, in the fourth frame period T4 and the seventh frame period T7 when the output signal SGO is not normally outputting the power supply voltage VDD, the determination circuit 160 should normally determine that the voltage of the output signal SGO is abnormal. However, in the example of Figure 17, the first reference voltage VREFH indicated by the dashed dotted line is set to a voltage level lower than the above-mentioned divided voltage VDV2=(VDD-VGND)×RESD / (RON+RESD), and therefore the output signal SGO is erroneously determined to be normal in the fourth frame period T4, the sixth frame period T6, and the eighth frame period T8. On the other hand, Figure 18 shows an example in which the voltage levels of the first reference voltage VREFH and the second reference voltage VREFL are set differently from those in Figure 17. That is, the first reference voltage VREFH in Figure 18 is set to a higher voltage than in Figure 17, and the second reference voltage VREFL in Figure 18 is set to a lower voltage than in Figure 17. In this case, in the fourth frame period T4, sixth frame period T6, and eighth frame period T8 in Fig. 17, the output signal SGO was erroneously determined to be normal, but in Fig. 18, the voltage of the output signal SGO becomes lower than the first reference voltage VREFH indicated by the dashed line, and the output signal SGO is correctly determined to be abnormal. By changing the set voltages of the first reference voltage VREFH and the second reference voltage VREFL in this way, the inspection circuit 41 can correctly determine that the output signal SGO is abnormal, even if the output signal SGO has deviated from its original signal waveform due to the short circuit.Specifically, by setting the first reference voltage VREFH to a lower voltage than the first voltage VH and setting the second reference voltage VREFL to a higher voltage than the second voltage VL, an abnormal state can be reliably detected even if the output signal SGO deviates from its original rectangular signal waveform.

[0050] 19 is a signal waveform diagram showing the case of FIG. 12, i.e., when the panel signal line LPN is shorted to the power supply voltage VDD, in which the voltage levels of the first reference voltage VREFH and the second reference voltage VREFL are changed over time. Specifically, the first reference voltage VREFH changes in voltage every frame period T, varying between three voltage levels. Similarly, the second reference voltage VREFL also changes in voltage every frame period T, varying between three voltage levels.

[0051] 19, the second reference voltage VREFL, indicated by a dashed line, changes to a voltage lower than the second reference voltage VREFL in the first frame period T1 when the first frame period T1 transitions to the second frame period T2. Then, when the second frame period T2 transitions to the third frame period T3, the second reference voltage VREFL changes to a voltage higher than the second reference voltage VREFL in the first frame period T1. The second reference voltage VREFL similarly changes for each frame period T from the fourth frame period T4 onward. During the fifth frame period T5, when a short circuit occurs between the panel signal line LPN and the power supply voltage VDD, the second reference voltage VREFL is set to a voltage lower than the divided voltage VDV1=(VDD-VGND)×RON / (RON+RESD), which is the voltage of the output signal SGO. Therefore, an abnormal state of the voltage of the output signal SGO can be properly detected. 17 and 18, when the first reference voltage VREFH and the second reference voltage VREFL are each set to a constant voltage, if the voltage level of the second reference voltage VREFL is inappropriate, an abnormal state of the output signal SGO due to a short circuit in the panel signal line LPN cannot be properly detected. However, by changing the reference voltage VREF for each frame period T as shown in Fig. 19, it becomes possible to detect this abnormal state. In the following description, the first reference voltage VREFH and the second reference voltage VREFL will be collectively referred to as the reference voltage VREF where appropriate.

[0052] FIG. 20 is a signal waveform diagram illustrating the case of FIG. 16, i.e., when the panel signal line LPN is shorted to the ground voltage VGND, in which the reference voltage VREF changes every frame period T, as in FIG. 19. As described above, due to this short, the voltage of the output signal SGO in the High state becomes lower than the power supply voltage VDD starting midway through the fourth frame period T4. Here, the first reference voltage VREFH indicated by the dashed line is set to a voltage lower than the divided voltage VDV2=(VDD-VGND)×RESD / (RON+RESD), which is the voltage of the output signal SGO, during the fourth frame period T4. This results in the output signal SGO being determined to be in the High state, making it impossible to detect an abnormal voltage state of the output signal SGO. Furthermore, during the sixth frame period T6, the first reference voltage VREFH is set to a voltage lower than that during the fourth frame period T4, making it impossible to detect an abnormal voltage state of the output signal SGO. However, during the eighth frame period T8, the first reference voltage VREFH is set to a voltage higher than the divided voltage VDV2, which is the voltage of the output signal SGO, making it possible to detect an abnormal state of the voltage of the output signal SGO. For example, when the reference voltage VREF is set to a constant voltage, an abnormal state of the output signal SGO may not be properly determined if the resistance values ​​of the on-resistance RON of the output driver 34 and the protective resistor RESD of the electrostatic protection circuit 90 fluctuate, causing fluctuations in the divided voltages VDV1 and VDV2, which are the voltage of the output signal SGO. The resistance values ​​of the on-resistance RON and the protective resistor RESD vary due to manufacturing process variations, temperature, etc. Furthermore, the on-resistance RON varies depending on the gate voltage. For this reason, it is not easy to predict the divided voltages VDV1 and VDV2 of the output signal SGO in advance and set the reference voltage VREF when a short circuit occurs. However, as described above, if the reference voltage VREF is changed every frame period T, it is possible to reliably detect an abnormal state of the output signal SGO even when the divided voltages VDV1 and VDV2, which are the voltages of the output signal SGO, change. According to the method described in Figures 19 and 20, it is sufficient to change the reference voltage in synchronization with the frame period T, which makes it easy to control the change of the reference voltage.For example, the control circuit can easily control the reference voltage because it only needs to issue an instruction to change the reference voltage VREF in synchronization with the latch pulse LP. Also, while FIGS. 19 and 20 illustrate an example in which the reference voltage VREF changes between three different voltage levels, the number of set voltage levels for the reference voltage VREF is not limited to this. That is, if the number of set voltage levels for the reference voltage VREF is M, the reference voltage VREF will return to the initial voltage level of the reference voltage VREF after a period of T×M has elapsed. Here, if the number M of set voltage levels is increased, it becomes possible to detect voltage abnormalities even with slight changes in the voltage of the output signal SGO.

[0053] 21 and 22 show examples of signal waveforms different from the signal waveform of the reference voltage VREF shown in FIGS. 19 and 20. Specifically, while the voltage level of the reference voltage VREF changes every frame period T in FIGS. 19 and 20, the difference in FIGS. 21 and 22 is that it changes every frame division period Tdiv, which is obtained by dividing the frame period T into three. In this way, when a given period is set to the frame period T, the reference voltage VREF returns to the initial voltage level of the reference voltage VREF after a period of T×M has elapsed, whereas the reference voltage VREF returns to the initial voltage level of the reference voltage VREF after a frame period has elapsed. This makes it possible to quickly detect an abnormal state in the voltage of the output signal SGO. Note that, as in the cases of FIGS. 19 and 20, the set levels of the voltage level of the reference voltage VREF in FIGS. 21 and 22 are not limited to three levels.

[0054] Here, one method for setting the reference voltage VREF is to set it from the external processing device 120 described above. Below, a description will be given of the method for setting the reference voltage VREF from the external processing device 120. When setting the reference voltage VREF using this method, the display driver 20 has, for example, a command setting register 112. The command setting register 112 stores setting information for commands input to the processing device 120. The command setting register 112 can be realized, for example, by a flip-flop circuit or a memory such as RAM. The information input to the processing device 120 is input to the interface circuit 110, and the interface circuit 110 writes the command setting information to the command setting register 112. Based on this information, the control circuit 100 outputs information such as the voltage to be set as the reference voltage VREF to the reference voltage generation circuit 140.

[0055] 23 and 24 illustrate the commands and the corresponding values ​​of the reference voltage VREF. The first command in FIG. 23 is a command for setting the voltage level of the first reference voltage VREFH. In the case of FIG. 23, the first command sets a value from 0 to 5, and the first reference voltage VREFH can be set to any of 0.70V, 0.75V, 0.80V, 0.85V, 0.90V, and 0.95V depending on the set value. The second command in FIG. 24 is a command for setting the voltage level of the second reference voltage VREFL. In the case of FIG. 24, the second command sets a value from 0 to 5, and the second reference voltage VREFL can be set to any of 0.05V, 0.10V, 0.15V, 0.20V, 0.25V, and 0.30V depending on the set value.

[0056] That is, the display driver 20 includes a command setting register 112 in which a command is set from an external processing device 120, and the control circuit 100 may instruct the reference voltage generation circuit 140 as to which of a plurality of voltages to select as the reference voltage VREF based on the command setting in the command setting register 112. In this way, it is possible to easily deal with cases where, for example, the divided voltages VDV1 and VDV2, which are the voltages of the output signal SGO, fluctuate due to various factors such as process variations, and it is necessary to individually set the reference voltages VREF to be compared.

[0057] 23 and 24, the processing device 120 may set a command in the command setting register at each given cycle. For example, while FIGS. 19 to 22 illustrate how a short circuit between the output terminal TO and the segment electrode ES of the electro-optical panel 200 can be reliably detected by changing the reference voltage VREF at each given cycle, the setting of this reference voltage VREF can also be changed by an external processing device 120. That is, in the display driver 20 of this embodiment, the control circuit 100 may instruct the reference voltage generation circuit 140 which of a plurality of voltages to select as the reference voltage VREF based on a command setting set by the processing device 120 at each given cycle in the command setting register 112. In this way, when a short circuit such as that described in FIGS. 11 and 15 occurs, the control circuit 100 can instruct the reference voltage generation circuit 140 at each given cycle which of a plurality of voltages to select as the reference voltage VREF for determining whether the voltage of the output signal SGO is in an abnormal state.

[0058] Although the above explanation has been given on the assumption that the driving method is static driving, the display driver 20 of this embodiment is not limited to this and can also be applied to a driving method based on duty driving. In the case of a driving method based on duty driving, a time-divided segment drive signal is input to each of the segment electrodes ESS1 to ESS7 within a frame period. That is, a voltage synchronized with a latch pulse is supplied to each of the segment electrodes ESS1 to ESS7, thereby controlling the display of numbers and predetermined symbols.

[0059] 3. Display module 25 shows an example of the configuration of a display module 300 of this embodiment. The display module 300 includes a display driver 20 and an electro-optical panel 200. The display driver 20 has the same configuration as the display driver 20 described with reference to FIGS. 1 and 4. The electro-optical panel 200 also has the same configuration as the electro-optical panel 200 described with reference to FIGS. 2 and 3. The display module 300 can be expected to be applied to, for example, wristwatches, wearable devices, biometric information measuring devices, smartphones, mobile phones and other personal digital assistants, cordless telephones, shavers, electric toothbrushes, handheld terminals, automobiles, and the like.

[0060] According to this embodiment, the display module 300 can be applied to a variety of electronic devices, and even if a malfunction occurs in the display of the electro-optical panel 200, the reference voltage can be changed at a given period, making it possible to reliably detect an abnormal state according to the voltage of the output signal SGO of the driver circuit.

[0061] As described above, the display driver of this embodiment includes a driver circuit that drives the electro-optical panel, an output terminal that outputs an output signal from the driver circuit, an output line that connects the output of the driver circuit to the output terminal, and an inspection circuit that detects abnormalities in the output signal by monitoring the voltage of the output signal that the driver circuit outputs to the output line, and the inspection circuit is related to the display driver and determines whether the voltage of the output signal is abnormal by comparing the voltage of the output signal with a reference voltage whose voltage changes every given period.

[0062] According to this embodiment, the reference voltage generation circuit can change the reference voltage at a given period, making it possible to properly detect an abnormal state even when the voltage change of the output signal of the driver circuit is not constant.

[0063] In this embodiment, the given period may be a frame period, and the inspection circuit may compare the voltage of the output signal with a reference voltage that changes every frame period.

[0064] In this way, the reference voltage can be changed in synchronization with the frame period, which makes it easier to control the change of the reference voltage.

[0065] In this embodiment, the given period is a frame division period obtained by dividing the frame period, and the inspection circuit may compare the voltage of the output signal with a reference voltage that changes for each frame division period.

[0066] In this way, the period of the signal waveform of the reference voltage becomes shorter than when a given period is set as the frame period, and an abnormal state of the voltage of the output signal of the driver circuit can be detected quickly.

[0067] In this embodiment, the display driver may also include an electrostatic protection circuit provided between the output line and the output terminal.

[0068] In this way, when a surge voltage such as static electricity is applied to the output terminal, the static charge can be discharged to ground or the power supply, thereby protecting the circuits and elements inside the display driver from malfunctions caused by overvoltage.

[0069] In this embodiment, the electrostatic protection circuit of the display driver may include a protection resistor provided between the output line and the output terminal.

[0070] In this way, even if a large surge voltage is applied to the output terminal, the circuits and elements provided inside the display driver can be appropriately protected from malfunctions due to overvoltage.

[0071] In addition, in this embodiment, the inspection circuit may include a reference voltage generation circuit that generates a plurality of voltages and outputs a reference voltage selected from the plurality of voltages at each given period, and a comparison circuit that compares the reference voltage with the voltage of the output signal.

[0072] In this way, a reference voltage that can properly determine the voltage of the output signal of the driver circuit can be generated, and an abnormal state of the voltage of the output signal can be reliably detected within a fixed period.

[0073] In this embodiment, the display driver may include a control circuit, and the control circuit may instruct the reference voltage generating circuit which of the multiple voltages to select as the reference voltage.

[0074] In this way, when the voltage change of the output signal of the driver circuit is within a certain range, the voltage level of the reference voltage can be set in advance in the control circuit.

[0075] In addition, in this embodiment, the display driver includes a command setting register in which commands are set from an external processing device, and the control circuit may instruct the reference voltage generation circuit which of the multiple voltages to select as the reference voltage based on the command setting in the command setting register.

[0076] In this way, an appropriate reference voltage can be set from outside the electro-optical panel 200 in response to factors such as process variations when determining whether the voltage of the output signal from the driver circuit is abnormal, and the abnormal state can be determined based on this.

[0077] In addition, in this embodiment, the control circuit of the display driver may instruct the reference voltage generation circuit which of multiple voltages to select as the reference voltage based on the command setting set in the command setting register from the processing device at each given period.

[0078] In this way, an abnormal state of the voltage of the output signal of the driver circuit can be determined for each given period based on an appropriate reference voltage.

[0079] The display module of this embodiment also includes a driver circuit that drives the electro-optical panel, an output terminal that outputs an output signal from the driver circuit, an output line that connects the output of the driver circuit to the output terminal, and an inspection circuit that detects abnormalities in the output signal by monitoring the voltage of the output signal that the driver circuit outputs to the output line, and the inspection circuit is related to a display module that includes a display driver that determines whether the voltage of the output signal is abnormal or not by comparing the voltage of the output signal with a reference voltage that changes every given period.

[0080] According to this embodiment, the display module can be applied to a variety of electronic devices, and even if a malfunction occurs in the display of the electro-optical panel, the reference voltage can be changed at a given period, making it possible to reliably detect abnormal conditions according to the voltage of the output signal of the driver circuit.

[0081] Although the present embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configurations and operations of the display driver, display module, etc. are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0082] 20...display driver, 30...segment driver circuit, 31...driver circuit, 32...level shifter, 34...output driver, 40...segment inspection circuit, 41...inspection circuit, 50...line latch, 60...data storage unit, 70...common driver circuit, 80...common inspection circuit, 82...polarity inversion circuit, 90...electrostatic protection circuit, 100...control circuit, 102...oscillating circuit, 110...interface circuit, 112...command setting register, 120...processing device, 132...internal circuit, 140...reference voltage generation circuit, 142... Selector, 144...selector, 150...comparison circuit, 152...level shifter, 160...determination circuit, 200...electro-optical panel, 300...display module, CQ...determination result, EC...common electrode, ECD1...common electrode, ECD2...common electrode, ECS1 to ECS7...common electrode, ES...segment electrode, ESD1...segment electrode, ESD2...segment electrode, ESS1 to ESS7...segment electrode, LO...output line, LP...latch pulse, LPN...panel signal line, LSD1 to LSD4...segment signal line, LSS1 ~LSS7...segment signal line, LCD1~LSD6...common signal line, POL...polarity signal, RESD...protection resistor, RH0~RH7...resistor, RL0~RL7...resistor, RON...on resistance, SGD...segment drive data, SGDT...judgment result, SGMO...segment monitor output signal, SGO...output signal, SGOP...output signal, SLAT...segment signal, SVREFH...signal, SVREFL...signal, SW...switch, T...frame period, T1...first frame period, T2...second frame period, T3...third frame period, T4...fourth frame period, T5...fifth frame period, T6...sixth frame period, T7...seventh frame period, T8...eighth frame period, TCD1...common pin, TCD2...common pin, Tdiv...frame division period, TO...output pin, TSD1 to TSD4...segment pin, TSS1 to TSS7...segment pin, VDD...power supply voltage, VDV1...divided voltage, VDV2...divided voltage, VGND...ground voltage, VH...first voltage, VL...second voltage, VREF...reference voltage, VREFH...first reference voltage, VREFL...second reference voltage

Claims

1. a driver circuit for driving the segment electrodes of the electro-optical panel; an output terminal for outputting an output signal from the driver circuit; an output line connecting the output of the driver circuit and the output terminal; an inspection circuit that detects an abnormality in the output signal by monitoring the voltage of the output signal that the driver circuit outputs to the output line; Including, The driver circuit outputting a constant first voltage to the output line for driving the segment electrodes in one of the odd-numbered frames and the even-numbered frames, and outputting a constant second voltage lower than the first voltage to the output line for driving the segment electrodes in the other of the odd-numbered frames and the even-numbered frames; The inspection circuit a reference voltage generating circuit that generates a first plurality of reference voltages that are lower than the first voltage and higher than the second voltage and that are different from each other, and a second plurality of reference voltages that are higher than the second voltage and lower than any of the first plurality of reference voltages and that are different from each other, and that selects a first reference voltage from the first plurality of reference voltages for each given period, and selects a second reference voltage from the second plurality of reference voltages for each given period; a comparison circuit that compares the first reference voltage and the second reference voltage with the voltage of the output signal; a determination circuit that, based on the result of the comparison, determines that an abnormality has occurred in the one frame when the voltage of the output signal is lower than the first reference voltage, and determines that an abnormality has occurred in the other frame when the voltage of the output signal is higher than the second reference voltage, and determines that an abnormality has occurred in the other frame when the voltage of the output signal is lower than the second reference voltage; A display driver comprising:

2. 2. The display driver according to claim 1, A display driver, wherein the given period is a frame period.

3. 2. The display driver according to claim 1, A display driver, wherein the given period is a frame division period obtained by dividing a frame period.

4. 4. A display driver according to claim 1, A display driver comprising: an electrostatic protection circuit provided between the output line and the output terminal.

5. 5. The display driver according to claim 4, The display driver, wherein the electrostatic protection circuit includes a protection resistor provided between the output line and the output terminal.

6. 6. A display driver according to claim 1, a control circuit; The control circuit a display driver that instructs the reference voltage generation circuit which voltage from the first plurality of reference voltages to select as the first reference voltage and which voltage from the second plurality of reference voltages to select as the second reference voltage.

7. 7. The display driver according to claim 6, a command setting register in which a command is set from an external processing device; The control circuit A display driver characterized in that it instructs the reference voltage generation circuit which voltage from the first plurality of reference voltages to select as the first reference voltage and which voltage from the second plurality of reference voltages to select as the second reference voltage based on the command setting of the command setting register.

8. 8. The display driver according to claim 7, The control circuit a display driver that instructs the reference voltage generation circuit which voltage from the first plurality of reference voltages to select as the first reference voltage and which voltage from the second plurality of reference voltages to select as the second reference voltage based on the command setting set from the processing device to the command setting register for each given period.

9. 9. A display driver according to claim 1, The one frame is One of a non-inversion drive frame and an inversion drive frame in polarity inversion drive, The other frame is the other of the non-inverted drive frame and the inverted drive frame.

10. A display driver according to any one of claims 1 to 9; the electro-optical panel; A display module comprising:

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