Isolation Module and Gate Driver

Abstract

This insulation module is provided with: a first conductor and a second conductor, which are buried in an insulating layer so as to face each other at a distance in the thickness direction of the insulating layer; a first electrode which is connected to the first conductor; a second electrode which is connected to the second conductor, while being arranged at a position that is away from the first electrode when viewed from the thickness direction of the insulating layer; a passivation layer which is formed on the surface of the insulating layer; a low dielectric constant layer which is formed on the surface of the passivation layer, and has a lower dielectric constant than the passivation layer; and a mold resin which covers the low dielectric constant layer.

Description

[Technical Field]

[0001] The present disclosure relates to an isolation module and a gate driver. [Background technology]

[0002] BACKGROUND ART Conventionally, an insulating transformer is known that has a primary coil and a secondary coil arranged opposite each other with an insulating layer interposed therebetween (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-49035 Summary of the Invention [Problem to be solved by the invention]

[0004] In a conventional isolation transformer, each coil is covered with an insulating layer, and the surface of the insulating layer is covered with a protective insulating layer made of silicon nitride (SiN), which is then covered with a molding resin.

[0005] When a high voltage is applied to an isolation transformer, creeping discharge may occur at the interface between the protective insulating layer and the molded resin. This problem is not limited to isolation transformers, but also applies to isolation modules that use capacitors for insulation. [Means for solving the problem]

[0006] An insulating module that solves the above problem comprises a first conductor and a second conductor embedded in an insulating layer and arranged opposite each other with a space between them in the thickness direction of the insulating layer, a first electrode connected to the first conductor, a second electrode connected to the second conductor and located at a space between them when viewed in the thickness direction of the insulating layer, a passivation layer formed on the surface of the insulating layer, a low-dielectric layer formed on the surface of the passivation layer and having a lower dielectric constant than the passivation layer, and a molding resin covering the low-dielectric layer.

[0007] a first conductor and a second conductor embedded in an insulating layer and arranged opposite to each other and spaced apart in a thickness direction of the insulating layer; a first electrode connected to the first conductor; a second electrode connected to the second conductor and spaced apart from each other when viewed in the thickness direction of the insulating layer; a passivation layer formed on a surface of the insulating layer to protect the insulating layer; a low-dielectric layer formed on the surface of the passivation layer and having a lower dielectric constant than the passivation layer; and a molding resin covering the low-dielectric layer. [Effects of the Invention]

[0008] The above-described insulating module and gate driver can suppress the occurrence of creeping discharge. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic circuit diagram of a gate driver according to the first embodiment. [Figure 2]FIG. 2 is a plan view showing the internal configuration of the gate driver of the first embodiment. [Figure 3] FIG. 3 is a perspective view of a transformer chip of the gate driver according to the first embodiment. [Figure 4] FIG. 4 is a plan view of the transformer chip of FIG. [Figure 5] FIG. 5 is a cross-sectional view schematically showing the internal structure of the transformer chip of FIG. [Figure 6] FIG. 6 is a cross-sectional view schematically showing the internal structure of the transformer chip of FIG. 3 at a position different from that of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line 7-7 in FIG. 4, showing a state in which the transformer chip is mounted on the low-voltage die pad. [Figure 8] FIG. 8 is an enlarged view of a portion of the transformer chip of FIG. [Figure 9] FIG. 9 is an enlarged view of a part of the transformer chip of FIG. 7 that is different from that of FIG. [Figure 10] FIG. 10 is a cross-sectional view of the gate driver according to the second embodiment, showing a state in which the transformer chip is mounted on a low-voltage die pad. [Figure 11] FIG. 11 is a schematic circuit diagram of a gate driver according to the third embodiment. [Figure 12] FIG. 12 is a plan view showing the internal configuration of the gate driver of the third embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view of the gate driver according to the third embodiment, in a state where the transformer chip is mounted on a low-voltage die pad. [Figure 14] FIG. 14 is a schematic circuit diagram of a gate driver according to the fourth embodiment. [Figure 15] FIG. 15 is a cross-sectional view showing a state in which the transformer chip of the gate driver according to the fourth embodiment is mounted on a low-voltage die pad. [Figure 16] FIG. 16 is a plan view showing the internal configuration of a gate driver according to a modified example. [Figure 17] FIG. 17 is a schematic circuit diagram of a gate driver according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0010] The following describes embodiments of a gate driver with reference to the drawings. The embodiments shown below are intended to exemplify configurations and methods for embodying the technical concepts, and are not intended to limit the materials, shapes, structures, arrangements, dimensions, etc. of the components described below.

[0011] [First embodiment] A gate driver 10 of the first embodiment will be described with reference to Figures 1 to 9. Figure 1 shows a simplified example of the circuit configuration of the gate driver 10.

[0012] As shown in FIG. 1 , a gate driver 10 applies a drive voltage signal to the gate of a switching element and is applied to, for example, an inverter device 500 mounted on an electric vehicle or a hybrid vehicle. The inverter device 500 includes a pair of switching elements 501 and 502 connected in series, a gate driver 10, and an ECU (Electronic Control Unit) 503 that controls the gate driver 10. The switching element 501 is, for example, a high-side switching element connected to a drive power supply, and the switching element 502 is a low-side switching element. Examples of the switching elements 501 and 502 include transistors such as SiMOSFETs (Si Metal-Oxide-Semiconductor Field-Effect Transistors), SiCMOSFETs, and IGBTs (Insulated Gate Bipolar Transistors). The gate driver 10 of this embodiment applies a drive voltage signal to the gate of the switching element 501. In the following description, it is assumed that SiCMOSFETs are used for the switching elements 501 and 502.

[0013] A gate driver 10 is provided for each of the switching elements 501 and 502, and individually drives the switching elements 501 and 502. In this embodiment, for convenience of explanation, the gate driver 10 that drives the switching element 501 will be described.

[0014] The gate driver 10 includes a low-voltage circuit 20 to which a first voltage V1 is applied, a high-voltage circuit 30 to which a second voltage V2 higher than the first voltage V1 is applied, and a transformer 40 provided between the low-voltage circuit 20 and the high-voltage circuit 30. In other words, the low-voltage circuit 20 and the high-voltage circuit 30 are connected via the transformer 40. The first voltage V1 and the second voltage V2 are DC voltages.

[0015] The gate driver 10 of this embodiment is configured so that, based on a control signal from the ECU 503, a signal is transmitted from the low-voltage circuit 20 via the transformer 40 to the high-voltage circuit 30, and a drive voltage signal is output from the high-voltage circuit 30.

[0016] The signal transmitted from the low-voltage circuit 20 to the high-voltage circuit 30, i.e., the signal output from the low-voltage circuit 20, is, for example, a signal for driving the switching element 501, and examples thereof include a set signal and a reset signal. The set signal is a signal that transmits the rising edge of a control signal from the ECU 503, and the reset signal is a signal that transmits the falling edge of a control signal from the ECU 503. The set signal and the reset signal can also be said to be signals for generating a drive voltage signal for the switching element 501. For this reason, the set signal and the reset signal correspond to the "first signal."

[0017] More specifically, the low-voltage circuit 20 is configured to operate when a first voltage V1 is applied. The low-voltage circuit 20 is electrically connected to the ECU 503 and generates a set signal and a reset signal based on a control signal input from the ECU 503. For example, the low-voltage circuit 20 generates a set signal in response to a rising edge of the control signal, and generates a reset signal in response to a falling edge of the control signal. The low-voltage circuit 20 then transmits the generated set signal and reset signal to the high-voltage circuit 30.

[0018] The high-voltage circuit 30 is a circuit configured to operate when a second voltage V2 is applied to it. The high-voltage circuit 30 is a circuit electrically connected to the gate of the switching element 501, and generates a drive voltage signal for driving the switching element 501 based on the set signal and reset signal received from the low-voltage circuit 20, and applies the drive voltage signal to the gate of the switching element 501. In other words, it can be said that the high-voltage circuit 30 generates a drive voltage signal to be applied to the gate of the switching element 501 based on the first signal output from the low-voltage circuit 20. More specifically, the high-voltage circuit 30 generates a drive voltage signal that turns on the switching element 501 based on the set signal, and applies the drive voltage signal to the gate of the switching element 501. On the other hand, the high-voltage circuit 30 generates a drive voltage signal that turns off the switching element 501 based on the reset signal, and applies the drive voltage signal to the gate of the switching element 501. In this way, the gate driver 10 controls the on / off of the switching element 501.

[0019] The high-voltage circuit 30 includes, for example, an RS flip-flop circuit to which a set signal and a reset signal are input, and a driver unit that generates a drive voltage signal based on the output signal of the RS flip-flop circuit. However, the specific circuit configuration of the high-voltage circuit 30 can be changed as desired.

[0020] In the gate driver 10 of this embodiment, the low-voltage circuit 20 and the high-voltage circuit 30 are insulated from each other by the transformer 40. More specifically, the transformer 40 restricts the transmission of DC voltage between the low-voltage circuit 20 and the high-voltage circuit 30, while allowing the transmission of various signals such as set signals and reset signals.

[0021] In other words, the state in which the low-voltage circuit 20 and the high-voltage circuit 30 are insulated means that the transmission of DC voltage is blocked between the low-voltage circuit 20 and the high-voltage circuit 30, while the transmission of signals between the low-voltage circuit 20 and the high-voltage circuit 30 is permitted.

[0022] The withstand voltage of the gate driver 10 is, for example, 2500 Vrms or more and 7500 Vrms or less. The withstand voltage of the gate driver 10 of this embodiment is approximately 5000 Vrms. However, the specific value of the withstand voltage of the gate driver 10 is not limited to this and can be any value.

[0023] In this embodiment, the ground of the low-voltage circuit 20 and the ground of the high-voltage circuit 30 are provided independently. Hereinafter, the ground potential of the low-voltage circuit 20 will be referred to as a first reference potential, and the ground potential of the high-voltage circuit 30 will be referred to as a second reference potential. In this case, the first voltage V1 is a voltage derived from the first reference potential, and the second voltage V2 is a voltage derived from the second reference potential. The first voltage V1 is, for example, 4.5 V or more and 5.5 V or less, and the second voltage V2 is, for example, 9 V or more and 24 V or less.

[0024] The transformer 40 will be described in detail below. The gate driver 10 of this embodiment is equipped with two transformers 40 corresponding to the transmission of two types of signals from the low-voltage circuit 20 to the high-voltage circuit 30. More specifically, the gate driver 10 is equipped with a transformer 40 used to transmit a set signal and a transformer 40 used to transmit a reset signal. For ease of explanation, the transformer 40 used to transmit the set signal will be referred to as "transformer 40A" and the transformer 40 used to transmit the reset signal will be referred to as "transformer 40B" below.

[0025] The gate driver 10 includes a low-voltage signal line 21A that connects the low-voltage circuit 20 and the transformer 40A, and a low-voltage signal line 21B that connects the low-voltage circuit 20 and the transformer 40B. Therefore, the low-voltage signal line 21A transmits a set signal from the low-voltage circuit 20 to the transformer 40A. The low-voltage signal line 21B transmits a reset signal from the low-voltage circuit 20 to the transformer 40B.

[0026] The gate driver 10 includes a high-voltage signal line 31A that connects the transformer 40A and the high-voltage circuit 30, and a high-voltage signal line 31B that connects the transformer 40B and the high-voltage circuit 30. Therefore, the high-voltage signal line 31A transmits a set signal from the transformer 40A to the high-voltage circuit 30. The high-voltage signal line 31B transmits a reset signal from the transformer 40B to the high-voltage circuit 30.

[0027] Transformer 40A transmits a set signal from low-voltage circuit 20 to high-voltage circuit 30, while electrically insulating low-voltage circuit 20 from high-voltage circuit 30. The withstand voltage of transformer 40A is, for example, 2500 Vrms or more and 7500 Vrms or less. Alternatively, the withstand voltage of transformer 40A may be, for example, 2500 Vrms or more and 5700 Vrms or less.

[0028] The transformer 40A has a first coil 41A and a second coil 42A that is electrically insulated from and magnetically coupleable with the first coil 41A. The first coil 41A is connected to the low-voltage circuit 20 by the low-voltage signal line 21A, and is also connected to the ground of the low-voltage circuit 20. That is, a first end of the first coil 41A is electrically connected to the low-voltage circuit 20, and a second end of the first coil 41A is electrically connected to the ground of the low-voltage circuit 20. Therefore, the potential of the second end of the first coil 41A becomes a first reference potential. The first reference potential is, for example, 0 V.

[0029] The second coil 42A is connected to the high-voltage circuit 30 by the high-voltage signal line 31A, and is also connected to the ground of the high-voltage circuit 30. That is, a first end of the second coil 42A is electrically connected to the high-voltage circuit 30, and a second end of the second coil 42A is electrically connected to the ground of the high-voltage circuit 30. Therefore, the potential of the second end of the second coil 42A is the second reference potential. Because the ground of the high-voltage circuit 30 is connected to the source of the switching element 501, the second reference potential fluctuates as the inverter device 500 is driven, and may become, for example, 600 V or higher.

[0030] The transformer 40B transmits a reset signal from the low-voltage circuit 20 to the high-voltage circuit 30, while electrically insulating the low-voltage circuit 20 from the high-voltage circuit 30. The withstand voltage of the transformer 40B is the same as that of the transformer 40A. The transformer 40B has a first coil 41B and a second coil 42B that is electrically insulated from the first coil 41B and magnetically coupleable with the first coil 41B. Note that the connection configuration of the transformer 40B is similar to that of the transformer 40A, and therefore a detailed description thereof will be omitted. Here, in this embodiment, the first coils 41A and 41B correspond to the "first conductor," and the second coils 42A and 42B correspond to the "second conductor."

[0031] Fig. 2 shows an example of a plan view illustrating the internal configuration of the gate driver 10. Note that Fig. 1 shows a simplified circuit configuration of the gate driver 10, and therefore the number of external terminals of the gate driver 10 in Fig. 2 is greater than the number of external terminals of the gate driver 10 in Fig. 1. Here, the number of external terminals of the gate driver 10 refers to the number of external electrodes that can connect the gate driver 10 to external electronic components of the gate driver 10, such as the ECU 503 and switching elements 501 (see Fig. 1). Furthermore, the number of signal lines (the number of wires W, described later) that transmit signals from the low-voltage circuit 20 to the high-voltage circuit 30 in the gate driver 10 in Fig. 2 is greater than the number of signal lines in the gate driver 10 in Fig. 1.

[0032] 2, the gate driver 10 is a semiconductor device in which multiple semiconductor chips are packaged, and is mounted on, for example, a circuit board provided in an inverter device 500. Note that the switching elements 501 and 502 are mounted on a mounting board separate from the circuit board, and a cooler is attached to this mounting board.

[0033] The gate driver 10 is packaged in a small outline (SO) package, which is an SOP (Small Outline Package) in this embodiment. The gate driver 10 includes a low-voltage circuit chip 60, a high-voltage circuit chip 70, and a transformer chip 80 as semiconductor chips, a low-voltage lead frame 90 on which the low-voltage circuit chip 60 is mounted, a high-voltage lead frame 100 on which the high-voltage circuit chip 70 is mounted, and a molded resin 110 that seals portions of the lead frames 90 and 100 and the chips 60, 70, and 80. In this embodiment, the transformer chip 80 and the molded resin 110 correspond to an "insulation module" that insulates the low-voltage circuit 20 from the high-voltage circuit 30. In FIG. 2, the molded resin 110 is indicated by a two-dot chain line for the sake of convenience in explaining the internal structure of the gate driver 10. The package format of the gate driver 10 can be changed as desired.

[0034] The molded resin 110 is made of an electrically insulating material, such as black epoxy resin. The molded resin 110 is formed in the shape of a rectangular plate with its thickness in the z direction. The molded resin 110 has four resin side surfaces 111 to 114. More specifically, the molded resin 110 has resin side surfaces 111 and 112 as both end surfaces in the x direction and resin side surfaces 113 and 114 as both end surfaces in the y direction. The x and y directions are directions orthogonal to the z direction. The x and y directions are orthogonal to each other. In the following description, a plan view means a view from the z direction.

[0035] The low-voltage lead frame 90 and the high-voltage lead frame 100 are each made of a conductor, which in this embodiment is made of Cu (copper). Each of the lead frames 90, 100 is provided across the inside and outside of the molding resin 110.

[0036] The low-voltage lead frame 90 has a low-voltage die pad 91 disposed within the molded resin 110, and a plurality of low-voltage leads 92 disposed across the inside and outside of the molded resin 110. Each low-voltage lead 92 constitutes an external terminal that electrically connects to an external electronic device such as an ECU 503 (see FIG. 1).

[0037] In this embodiment, both the low-voltage circuit chip 60 and the transformer chip 80 are mounted on the low-voltage die pad 91. In plan view, the low-voltage die pad 91 is arranged so that its center in the y direction is closer to the resin side surface 113 than the center in the y direction of the molded resin 110. In this embodiment, the low-voltage die pad 91 is not exposed from the molded resin 110. In plan view, the low-voltage die pad 91 has a rectangular shape with its longer side in the x direction and its shorter side in the y direction.

[0038] The plurality of low-voltage leads 92 are arranged spaced apart from one another in the x direction. Of the plurality of low-voltage leads 92, the low-voltage leads 92 arranged at both ends in the x direction are each integrated with the low-voltage die pad 91. A portion of each low-voltage lead 92 protrudes outward from the resin side surface 113 of the molded resin 110.

[0039] The high-voltage lead frame 100 has a high-voltage die pad 101 disposed within a molded resin 110, and a plurality of high-voltage leads 102 disposed across the inside and outside of the molded resin 110. Each high-voltage lead 102 constitutes an external terminal that electrically connects to an external electronic device such as the gate of a switching element 501 (see FIG. 1).

[0040] The high-voltage die pad 101 has a high-voltage circuit chip 70 mounted thereon. In plan view, the high-voltage die pad 101 is disposed closer to the resin side surface 114 in the y direction than the low-voltage die pad 91. In this embodiment, the high-voltage die pad 101 is not exposed from the molded resin 110. In plan view, the high-voltage die pad 101 has a rectangular shape with its longer side oriented in the x direction and its shorter side oriented in the y direction.

[0041] The low-voltage die pad 91 and the high-voltage die pad 101 are arranged apart from each other in the y direction. Therefore, the y direction can also be said to be the arrangement direction of both die pads 91, 101. The y-direction dimensions of the low-voltage die pad 91 and the high-voltage die pad 101 are set depending on the size and number of semiconductor chips to be mounted. In this embodiment, the low-voltage circuit chip 60 and the transformer chip 80 are mounted on the low-voltage die pad 91, and the high-voltage circuit chip 70 is mounted on the high-voltage die pad 101, so the y-direction dimension of the low-voltage die pad 91 is larger than the y-direction dimension of the high-voltage die pad 101.

[0042] The multiple high-voltage leads 102 are arranged spaced apart from each other in the x direction. Of the multiple high-voltage leads 102, a pair of high-voltage leads 102 are integrated with the high-voltage die pad 101. A portion of each high-voltage lead 102 protrudes outward from the resin side surface 114 of the molded resin 110.

[0043] In this embodiment, the number of high-voltage leads 102 is the same as the number of low-voltage leads 92. As can be seen from Fig. 2, the plurality of low-voltage leads 92 and the plurality of high-voltage leads 102 are arranged in a direction (x direction) perpendicular to the arrangement direction (y direction) of the low-voltage die pads 91 and the high-voltage die pads 101. Note that the number of high-voltage leads 102 and the number of low-voltage leads 92 can each be changed arbitrarily.

[0044] In this embodiment, the low-voltage die pad 91 is supported by a pair of low-voltage leads 92 integrated with the low-voltage die pad 91, and the high-voltage die pad 101 is supported by a pair of high-voltage leads 102 integrated with the high-voltage die pad 101, so that each die pad 91, 101 does not have a suspension lead exposed from the resin side surfaces 111, 112. This allows for a large insulation distance between the low-voltage lead frame 90 and the high-voltage lead frame 100.

[0045] The low-voltage circuit chip 60, the high-voltage circuit chip 70, and the transformer chip 80 are arranged spaced apart from one another in the y direction. In the y direction, the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70 are arranged in this order from the low-voltage lead 92 to the high-voltage lead 102.

[0046] The low-voltage circuit chip 60 includes the low-voltage circuit 20 shown in FIG. 1. In plan view, the low-voltage circuit chip 60 has a rectangular shape with short and long sides. In plan view, the low-voltage circuit chip 60 is mounted on the low-voltage die pad 91 with its long sides aligned along the x direction and its short sides aligned along the y direction. The low-voltage circuit chip 60 has a chip main surface 60s and a chip back surface (not shown) that face opposite each other in the z direction. The chip back surface of the low-voltage circuit chip 60 is bonded to the low-voltage die pad 91 with a conductive bonding material such as solder or Ag (silver) paste.

[0047] A plurality of first electrode pads 61, a plurality of second electrode pads 62, and a plurality of third electrode pads 63 are formed on a chip main surface 60s of the low-voltage circuit chip 60. Each of the electrode pads 61 to 63 is electrically connected to the low-voltage circuit 20.

[0048] The multiple first electrode pads 61 are arranged on the chip main surface 60s closer to the low-voltage leads 92 than to the center of the chip main surface 60s in the y direction. The multiple first electrode pads 61 are arranged in the x direction. The multiple second electrode pads 62 are arranged at one of both ends of the chip main surface 60s in the y direction that is closer to the transformer chip 80. The multiple second electrode pads 62 are arranged in the x direction. The multiple third electrode pads 63 are arranged at both ends of the chip main surface 60s in the x direction.

[0049] The high-voltage circuit chip 70 includes the high-voltage circuit 30 shown in FIG. 1. In plan view, the high-voltage circuit chip 70 has a rectangular shape with short and long sides. In plan view, the high-voltage circuit chip 70 is mounted on the high-voltage die pad 101 with the long sides aligned along the x direction and the short sides aligned along the y direction. The high-voltage circuit chip 70 has a chip main surface 70s and a chip back surface (not shown) facing opposite sides in the z direction. The chip back surface of the high-voltage circuit chip 70 is bonded to the high-voltage die pad 101 with a conductive bonding material.

[0050] A plurality of first electrode pads 71, a plurality of second electrode pads 72, and a plurality of third electrode pads 73 are formed on a chip main surface 70s of the high-voltage circuit chip 70. Each of the electrode pads 71 ​​to 73 is electrically connected to the high-voltage circuit 30.

[0051] The multiple first electrode pads 71 ​​are arranged at the end closer to the transformer chip 80 of both end portions in the y direction of the chip main surface 70s. The multiple first electrode pads 71 ​​are arranged in the x direction. The multiple second electrode pads 72 are arranged at the end farther from the transformer chip 80 of both end portions in the y direction of the chip main surface 70s. In other words, the multiple second electrode pads 72 are arranged at the end closer to the high-voltage lead 102 of both end portions in the y direction of the chip main surface 70s. The multiple second electrode pads 72 are arranged in the x direction. The multiple third electrode pads 73 are arranged at both end portions in the x direction of the chip main surface 70s.

[0052] The transformer chip 80 includes the transformer 40 shown in Fig. 1. The shape of the transformer chip 80 in plan view is a rectangle having short and long sides. In this embodiment, the transformer chip 80 is mounted on the low-voltage die pad 91 so that the long sides are aligned in the x direction and the short sides are aligned in the y direction in plan view.

[0053] The transformer chip 80 is disposed adjacent to the low-voltage circuit chip 60 in the y direction. The transformer chip 80 is disposed closer to the high-voltage circuit chip 70 than the low-voltage circuit chip 60. In other words, the transformer chip 80 is disposed between the low-voltage circuit chip 60 and the high-voltage circuit chip 70 in the y direction.

[0054] The transformer chip 80 has a chip main surface 80s and a chip back surface 80r (see FIG. 7) facing opposite sides in the z direction. The chip back surface 80r of the transformer chip 80 is bonded to a low-voltage die pad 91 by a conductive bonding material SD (see FIG. 7).

[0055] 2, a plurality of first electrode pads 81 and a plurality of second electrode pads 82 are formed on a chip main surface 80s of the transformer chip 80. Here, in this embodiment, each first electrode pad 81 corresponds to a "first electrode," and each second electrode pad 82 corresponds to a "second electrode."

[0056] The multiple first electrode pads 81 are arranged, for example, at one of both ends in the y direction of the chip main surface 80s, which is closer to the low-voltage circuit chip 60. The multiple first electrode pads 81 are arranged in the x direction. The multiple second electrode pads 82 are arranged, for example, near the center in the y direction of the chip main surface 80s. The multiple second electrode pads 82 are arranged in the x direction. The transformers 40A and 40B are arranged near the center in the y direction of the chip main surface 80s in a plan view. As shown in FIG. 4, the multiple second electrode pads 82 and the transformers 40A and 40B are arranged in positions where they do not overlap each other in a plan view. The electrode pads 81 and 82 are electrically connected to the transformers 40A and 40B.

[0057] 2, in order to set the dielectric strength voltage of the gate driver 10 to a preset dielectric strength voltage, it is necessary to separate the low-voltage die pad 91 and the high-voltage die pad 101, which are closest to each other on the lead frames 90 and 100. Therefore, in a plan view, the distance between the high-voltage circuit chip 70 and the transformer chip 80 is greater than the distance between the low-voltage circuit chip 60 and the transformer chip 80.

[0058] A plurality of wires W are connected to each of the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70. Each wire W is a bonding wire formed by a wire bonding device and is made of a conductor such as Au (gold), Al (aluminum), or Cu.

[0059] The low-voltage circuit chip 60 is electrically connected to the low-voltage lead frame 90 by wires W. More specifically, the low-voltage circuit chip 60's first electrode pads 61 and third electrode pads 63 are connected to the low-voltage leads 92 by wires W. The low-voltage circuit chip 60's third electrode pads 63 are connected to a pair of low-voltage leads 92, among the low-voltage leads 92, that are integrated with the low-voltage die pad 91, by wires W. This electrically connects the low-voltage circuit 20 to the low-voltage leads 92 (external electrodes of the gate driver 10 that are electrically connected to the ECU 503). In this embodiment, the pair of low-voltage leads 92 that are integrated with the low-voltage die pad 91 form ground terminals, and the low-voltage circuit 20 and the low-voltage die pad 91 are electrically connected by wires W, so that the low-voltage die pad 91 has the same potential as the ground of the low-voltage circuit 20.

[0060] The high-voltage circuit chip 70 and the multiple high-voltage leads 102 of the high-voltage lead frame 100 are each electrically connected by a wire W. More specifically, the multiple second electrode pads 72 and multiple third electrode pads 73 of the high-voltage circuit chip 70 are connected to the high-voltage leads 102 by the wire W. This electrically connects the high-voltage circuit 30 and the multiple high-voltage leads 102 (external electrodes of the gate driver 10 that are electrically connected to the switching elements 501, etc.). In this embodiment, a pair of high-voltage leads 102 integrated with the high-voltage die pad 101 constitute ground terminals, and the high-voltage circuit 30 and the high-voltage die pad 101 are electrically connected by the wire W, so that the high-voltage die pad 101 has the same potential as the ground of the high-voltage circuit 30.

[0061] The transformer chip 80 is connected to both the low-voltage circuit chip 60 and the high-voltage circuit chip 70 by wires W. More specifically, the multiple first electrode pads 81 of the transformer chip 80 are connected to the multiple second electrode pads 62 of the low-voltage circuit chip 60 by wires W. The multiple second electrode pads 82 of the transformer chip 80 are connected to the multiple first electrode pads 71 ​​of the high-voltage circuit chip 70 by wires W.

[0062] Both the first coil 41A of the transformer 40A and the first coil 41B of the transformer 40B (see FIG. 1) are electrically connected to the ground of the low-voltage circuit 20 via a wire W, a low-voltage circuit chip 60, etc. Both the second coil 42A of the transformer 40A and the second coil 42B of the transformer 40B (see FIG. 1) are electrically connected to the ground of the high-voltage circuit 30 via a wire W, a high-voltage circuit chip 70, etc.

[0063] 3 to 9, an example of the configuration of the transformer chip 80 will be described. Note that the transformer 40B has the same configuration as the transformer 40A, and therefore its description will be omitted. In the following description, the direction from the chip back surface 80r of the transformer chip 80 toward the chip main surface 80s will be referred to as "upward," and the direction from the chip main surface 80s toward the chip back surface 80r will be referred to as "downward."

[0064] FIG. 4 is a plan view of the transformer chip 80, and for convenience of explanation, the transformers 40A and 40B, a shield electrode 86 and a dummy pattern 120, which will be described later, are indicated by dashed lines.

[0065] Figure 5 is a cross-sectional view of the transformer chip 80 taken along the xy plane at the z-direction position of the first coils 41A and 41B of each transformer 40AA, 40AB, 40BA, and 40BB, showing the connection relationship between the first coils 41A and 41B of each transformer 40AA, 40AB, 40BA, and 40BB. Figure 6 is a cross-sectional view of the transformer chip 80 taken along the xy plane at the z-direction position of the second coils 42A and 42B of each transformer 40AA, 40AB, 40BA, and 40BB, showing the connection relationship between the second coils 42A and 42B of each transformer 40AA, 40AB, 40BA, and 40BB. Note that hatching is omitted in Figures 5 and 6 for convenience.

[0066] 7 is a cross-sectional view of the transformer 40A of the transformer chip 80 and its surroundings taken along line 7-7 in FIG. 4. For convenience, FIG. 7 shows the transformer chip 80 sealed with the mold resin 110 of the gate driver 10. Also, in FIG. 7, some of the hatching has been omitted to make the drawing easier to read. FIGS. 8 and 9 are enlarged views of a portion of FIG. 7, and, like FIG. 7, some of the hatching has been omitted.

[0067] As shown in FIG. 4, the transformer chip 80 includes both transformers 40A and 40B. More specifically, both transformers 40A and 40B are integrated into a single chip. In other words, the transformer chip 80 is a semiconductor chip dedicated to both transformers 40A and 40B, separate from the low-voltage circuit chip 60 and the high-voltage circuit chip 70 (see FIG. 2 for both). The transformer chip 80 has four chip side surfaces 80a, 80b, 80c, and 80d that are perpendicular to both the chip main surface 80s and the chip back surface 80r. The chip side surfaces 80a to 80d are provided between the chip main surface 80s and the chip back surface 80r in the z direction. The chip side surfaces 80a and 80b form both end surfaces of the transformer chip 80 in the y direction, and the chip side surfaces 80c and 80d form both end surfaces of the transformer chip 80 in the x direction. In a plan view, the chip side surfaces 80a and 80b form the long sides of the transformer chip 80, and the chip side surfaces 80c and 80d form the short sides of the transformer chip 80. In this embodiment, the chip side surface 80a is closer to the high-voltage circuit chip 70 (see FIG. 2) than the chip side surface 80b, and the chip side surface 80b is closer to the low-voltage circuit chip 60 (see FIG. 2) than the chip side surface 80a.

[0068] As shown in FIG. 7, the transformer chip 80 has a substrate 84 and an insulating layer 85 formed on the substrate 84. The substrate 84 is made of, for example, a semiconductor substrate, and in this embodiment, is a substrate formed from a material containing Si (silicon). Note that a wide band gap semiconductor or a compound semiconductor may be used as the semiconductor substrate for the substrate 84. Furthermore, instead of a semiconductor substrate, an insulating substrate formed from a material containing glass may be used as the substrate 84.

[0069] The wide bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or more. The wide bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0070] The substrate 84 has a substrate main surface 84s and a substrate back surface 84r that face opposite to each other in the z direction. The substrate back surface 84r forms the chip back surface 80r of the transformer chip 80.

[0071] In this embodiment, a plurality of insulating layers 85 are stacked in the z direction on the substrate main surface 84s of the substrate 84. In other words, the z direction can be said to be the thickness direction of the insulating layers 85. The insulating layers 85 are formed on the substrate main surface 84s of the substrate 84. In this embodiment, the total thickness T1 of the plurality of insulating layers 85 is thicker than the thickness T2 of the substrate 84 (T1>T2). However, the number of stacked insulating layers 85 is set according to the required dielectric strength voltage of the transformer chip 80. Therefore, depending on the number of stacked insulating layers 85, the thickness T1 may be thinner than the thickness T2 (T1 <T2)。

[0072] The insulating layer 85 has a first insulating layer 85A and a second insulating layer 85B formed on the first insulating layer 85A. The first insulating layer 85A is, for example, an etching stopper layer and is made of SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), or the like. In this embodiment, the first insulating layer 85A is made of SiN. The second insulating layer 85B is, for example, an interlayer insulating layer and is made of SiO2 (silicon oxide). As shown in FIG. 7, the thickness of the second insulating layer 85B is thicker than the thickness of the first insulating layer 85A. The thickness of the first insulating layer 85A may be equal to or greater than 100 nm and less than 1000 nm. The thickness of the second insulating layer 85B may be equal to or greater than 1000 nm and less than 3000 nm. In this embodiment, the thickness of the first insulating layer 85A is, for example, approximately 300 nm, and the thickness of the second insulating layer 85B is, for example, approximately 2000 nm.

[0073] Both the bottommost insulating layer 85L in contact with the substrate main surface 84s of the substrate 84 and the topmost insulating layer 85U are made of the second insulating layer 85B. Therefore, the thicknesses of both the bottommost insulating layer 85L and the topmost insulating layer 85U are thinner than the other insulating layers 85. The thicknesses of both the bottommost insulating layer 85L and the topmost insulating layer 85U are equal to or greater than the thickness of the first insulating layer 85A and equal to or less than the thickness of the second insulating layer 85B.

[0074] The thicknesses of both the bottom insulating layer 85L and the top insulating layer 85U can be changed as desired. For example, the thicknesses of both the bottom insulating layer 85L and the top insulating layer 85U may be greater than the thickness of the second insulating layer 85B, or may be equal to or greater than the thickness of insulating layer 85 made up of first insulating layer 85A and second insulating layer 85B.

[0075] The outer surface of the uppermost insulating layer 85U is located more inward than the outer surfaces of the other insulating layers 85. For example, as shown in Fig. 7, the outer surface of the uppermost insulating layer 85U that faces the same side as the chip side surface 80a is located more inward than the chip side surface 80a in the y direction. The outer surface of the uppermost insulating layer 85U that faces the same side as the chip side surface 80b is located more inward than the chip side surface 80b in the y direction.

[0076] The transformer chip 80 includes a shield electrode 86 formed in the insulating layer 85. The shield electrode 86 prevents moisture from penetrating the insulating layer 85 and prevents cracks from occurring in the insulating layer 85. The shield electrode 86 is provided on the outer periphery of the insulating layer 85 (the outer periphery of the transformer chip 80) in a planar view. More specifically, as shown in FIGS. 4 to 6, the shield electrode 86 is provided spaced apart from the chip side surfaces 80a to 80d. In a planar view, the shield electrode 86 is formed in a strip shape and extends along the chip side surfaces 80a to 80d. In this embodiment, the shield electrode 86 has a rectangular ring shape in a planar view. The shield electrode 86 divides the insulating layer 85 into an inner region 87 and an outer region 88. In this embodiment, as shown in FIG. 7, the uppermost insulating layer 85U is formed to straddle the shield electrode 86 in a planar view. In other words, it can be said that the uppermost insulating layer 85U has the outer region 88.

[0077] As shown in FIG. 4, the inner region 87 is a region of the insulating layer 85 that is protected by the shield electrode 86. The inner region 87 has a rectangular shape in plan view, with its longer sides oriented in the x direction and its shorter sides oriented in the y direction. The outer region 88 is a rectangular ring-shaped region that surrounds the inner region 87 in plan view. The outer region 88 is a region between the shield electrode 86 and the chip side surfaces 80a to 80d in plan view. In other words, the outer region 88 is a rectangular ring-shaped region that includes the chip side surfaces 80a to 80d.

[0078] The material of the shield electrode 86 is appropriately selected from one or more of Ti (titanium), TiN (titanium nitride), Au, Ag, Cu, Al, and W (tungsten). As shown in FIG. 7 , the shield electrode 86 penetrates the insulating layers 85 in the z direction. More specifically, the shield electrode 86 is provided so as to overlap the coils 41A, 41B, 42A, and 42B of the transformers 40A and 40B when viewed from a direction perpendicular to the z direction. In this embodiment, the shield electrode 86 penetrates in the z direction from the insulating layer 85 that is two layers below the uppermost insulating layer 85U to the insulating layer 85 that is one layer above the lowermost insulating layer 85L. The lowermost insulating layer 85L is provided with a via 89 that penetrates the lowermost insulating layer 85L in the z direction. The via 89 is positioned so as to overlap the shield electrode 86 in a plan view and connects the shield electrode 86 to the substrate 84. This electrically connects the shield electrode 86 to the substrate 84. The via 89 may be formed of the same material as the shield electrode 86, for example.

[0079] Transformers 40A and 40B are embedded in the insulating layer 85. Transformers 40A and 40B are disposed in an inner region 87. As shown in FIG. 4, transformers 40A and 40B are aligned in the y direction and spaced apart in the x direction. In plan view, transformers 40A and 40B are arranged in a direction perpendicular to the arrangement of chips 60, 70, and 80. The transformer chip 80 of this embodiment includes two transformers 40A and two transformers 40B. For convenience, the two transformers near chip side surface 80c in the x direction are referred to as "transformer 40AA" and "transformer 40AB," and the two transformers near chip side surface 80d in the x direction are referred to as "transformer 40BA" and "transformer 40BB."

[0080] As shown in FIG. 4, the transformer 40AA, the transformer 40AB, the transformer 40BA, and the transformer 40BB are arranged in this order from the chip side surface 80c toward the chip side surface 80d in the x direction.

[0081] 7, the first coil 41A and the second coil 42A of the transformer 40AA are arranged opposite each other in the z direction with an insulating layer 85 interposed therebetween. In this embodiment, the first coil 41A and the second coil 42A are arranged opposite each other in the z direction with multiple insulating layers 85 interposed therebetween.

[0082] Each of the coils 41A, 42A is configured as a conductive layer embedded in one insulating layer 85. More specifically, the insulating layer 85X in which each of the coils 41A, 42A is embedded has a groove formed therein that penetrates both the first insulating layer 85A and the second insulating layer 85B in the z-direction. The conductive layer that constitutes each of the coils 41A, 42A is embedded in the groove of the insulating layer 85X. The insulating layer 85X in which each of the coils 41A, 42A is embedded is covered by an insulating layer 85 adjacent to the insulating layer 85X in the z-direction. As a result, each of the coils 41A, 42A can be said to be embedded in the insulating layer 85.

[0083] In the z direction, the second coil 42A is located farther from the substrate 84 than the first coil 41A. In other words, the second coil 42A is located higher than the first coil 41A. Furthermore, the first coil 41A is located closer to the substrate 84 than the second coil 42A. In this embodiment, the distance between the first coil 41A and the second coil 42A in the z direction is greater than the distance between the first coil 41A and the substrate main surface 84s of the substrate 84.

[0084] As shown in FIG. 4, the second coil 42A has an elliptical spiral shape in plan view. The first coil 41A has the same shape as the second coil 42A. The first coil 41A and the second coil 42A are formed with the same winding direction in plan view. In this embodiment, the number of turns of the first coil 41A is the same as the number of turns of the second coil 42A. Each of the coils 41A and 42A is made of one or more of Ti, TiN, Au, Ag, Cu, Al, and W, as appropriate. The configuration of the transformer 40AB is the same as that of the transformer 40AA, and therefore a description thereof will be omitted.

[0085] As shown in FIG. 4, in a plan view, the plurality of first electrode pads 81 and the plurality of second electrode pads 82 are each disposed within an inner region 87. As shown in FIG. 7, the electrode pads 81 and 82 are formed on an insulating layer 85 that is one layer below an uppermost insulating layer 85U. The uppermost insulating layer 85U is formed in a position aligned with the electrode pads 81 and 82. The electrode pads 81 and 82 can also be said to be embedded in the insulating layer 85. As shown in FIG. 7, in this embodiment, the electrode pads 81 and 82 are disposed at positions farther from the substrate 84 than the second coils 42A and 42B of the transformers 40A and 40B. In other words, the electrode pads 81 and 82 are located above the second coils 42A and 42B of the transformers 40A and 40B. In this embodiment, the distance between the first coil 41A and the second coil 42A is greater than the distance between the second coil 42A and each of the electrode pads 81 and 82 in the z direction.

[0086] The uppermost insulating layer 85U is formed so as to cover the outer peripheries of the electrode pads 81, 82. That is, as shown in Figures 8 and 9, the uppermost insulating layer 85U has first insulating layer openings 85Ua for exposing the first electrode pads 81 and second insulating layer openings 85Ub for exposing the second electrode pads 82. A plurality of first insulating layer openings 85Ua are provided corresponding to the plurality of pairs of first electrode pads 81, and a plurality of second insulating layer openings 85Ub are provided corresponding to the plurality of pairs of second electrode pads 82.

[0087] As shown in FIG. 4, in a plan view, the multiple first electrode pads 81 are arranged at positions aligned with the two transformers 40AA, 40AB and the two transformers 40BA, 40BB in the x direction, between the transformers 40AA and 40AB in the x direction, and between the transformers 40BA and 40BB in the x direction. The multiple first electrode pads 81 are arranged closer to the chip side surface 80b in the y direction than the transformers 40AA, 40AB, 40BA, and 40BB. In other words, the multiple first electrode pads 81 are arranged between the transformers 40AA, 40AB, 40BA, and 40BB in the y direction and the chip side surface 80b. In other words, the multiple first electrode pads 81 are arranged closer to the low-voltage lead 92 (see FIG. 2) than the transformers 40AA, 40AB, 40BA, and 40BB in a plan view. Hereinafter, for convenience, the multiple first electrode pads 81 from the chip side surface 80c toward the chip side surface 80d will be referred to as first electrode pad 81A, first electrode pad 81B, first electrode pad 81C, first electrode pad 81D, first electrode pad 81E, and first electrode pad 81F. Note that when describing matters common to the first electrode pads 81A to 81F, they will be described as first electrode pad 81.

[0088] The first electrode pad 81A is arranged at a position overlapping with the transformer 40AA when viewed from the y direction. The first electrode pad 81B is arranged at a position overlapping with a portion between the transformers 40AA and 40AB in the x direction when viewed from the y direction. The first electrode pad 81C is arranged at a position overlapping with the transformer 40AB when viewed from the y direction. The first electrode pad 81D is arranged at a position overlapping with the transformer 40BA when viewed from the y direction. The first electrode pad 81E is arranged at a position overlapping with a portion between the transformers 40BA and 40BB in the x direction when viewed from the y direction. The first electrode pad 81F is arranged at a position overlapping with the transformer 40BB when viewed from the y direction. Each of the first electrode pads 81A to 81F consists of a pair of electrode pads adjacent to each other in the x direction. The multiple first electrode pads 81A to 81F are arranged aligned with each other in the y direction and spaced apart from each other in the x direction.

[0089] In a plan view, the second electrode pads 82 are respectively arranged within each of the transformers 40AA, 40AB, 40BA, and 40BB, between the transformers 40AA and 40AB in the x-direction, and between the transformers 40BA and 40BB in the x-direction. The second electrode pads 82 are arranged in positions overlapping the transformers 40AA, 40AB, 40BA, and 40BB when viewed from the x-direction. Hereinafter, for convenience, the second electrode pads 82 from the chip side surface 80c toward the chip side surface 80d will be referred to as second electrode pad 82A, second electrode pad 82B, second electrode pad 82C, second electrode pad 82D, second electrode pad 82E, and second electrode pad 82F. When describing matters common to the second electrode pads 82A to 82F, they will be described as second electrode pad 82.

[0090] The second electrode pad 82A is arranged in an inner space formed by the elliptical spiral second coil 42A of the transformer 40AA. The second electrode pad 82B is arranged between the transformers 40AA and 40AB in the x direction. The second electrode pad 82C is arranged in an inner space formed by the elliptical spiral second coil 42A of the transformer 40AB. The second electrode pad 82D is arranged in an inner space formed by the elliptical spiral second coil 42B of the transformer 40BA. The second electrode pad 82E is arranged between the transformers 40BA and 40BB in the x direction. The second electrode pad 82F is arranged in an inner space formed by the elliptical spiral second coil 42B of the transformer 40BB. Each of the second electrode pads 82A to 82F consists of a pair of electrode pads adjacent to each other in the x direction. The second electrode pads 82A to 82F are arranged aligned with each other in the y direction and spaced apart from each other in the x direction.

[0091] 4, 5, and 7, the first electrode pads 81A-81F are individually electrically connected to the first coils 41A and 41B of the transformers 40AA, 40AB, 40BA, and 40BB. As shown in FIGS. 4, 6, and 7, the second electrode pads 82A-82F are individually electrically connected to the second coils 42A and 42B of the transformers 40AA, 40AB, 40BA, and 40BB.

[0092] 5 and 6, the transformer chip 80 includes connection wiring for individually connecting the electrode pads 81A-81F, 82A-82F to the coils 41A, 41B, 42A, and 42B of the transformers 40AA, 40AB, 40BA, and 40BB. In this embodiment, the connection wiring includes first connection wiring 131A-131F, second connection wiring 132A and 132B, third connection wiring 133A-133D, and fourth connection wiring 134A and 134B. The connection wirings 131A-131D, 132A, 132B, 133A-133D, and 134A and 134B are provided in the inner region 87 and are made of one or more of Ti, TiN, Au, Ag, Cu, Al, and W.

[0093] 4 and 5, the first connection wiring 131A is a wiring that connects the first electrode pad 81A and a first end of the first coil 41A of the transformer 40AA. The first connection wiring 131B is a wiring that connects the first electrode pad 81C and a first end of the first coil 41A of the transformer 40AB. The first connection wiring 131C is a wiring that connects the first electrode pad 81D and a first end of the first coil 41B of the transformer 40BA. The first connection wiring 131D is a wiring that connects the first electrode pad 81F and a first end of the first coil 41B of the transformer 40BB.

[0094] The second connection wiring 132A is a wiring that connects the first electrode pad 81B to both the second end of the first coil 41A of the transformer 40AA and the second end of the first coil 41A of the transformer 40AB. The second connection wiring 132B is a wiring that connects the first electrode pad 81E to both the second end of the first coil 41B of the transformer 40BA and the second end of the first coil 41B of the transformer 40BB.

[0095] The first connection wirings 131A to 131D have the same structure, and the second connection wirings 132A and 132B have the same structure. Therefore, in the following, the configuration of the first connection wiring 131A and the configuration of the second connection wiring 132A will be described, and detailed descriptions of the first connection wirings 131B to 131D and the second connection wiring 132B will be omitted.

[0096] As shown in FIG. 7, the first connection wiring 131A has a first wiring portion 135 extending in the z-direction so as to penetrate multiple insulating layers 85, a second wiring portion 136 extending in the y-direction, and a third wiring portion 137 connecting to a first end of the first coil 41A of the transformer 40AA.

[0097] The first wiring portion 135 is disposed at a position overlapping with the first electrode pad 81A in a plan view and is connected to the first electrode pad 81A. The first wiring portion 135 penetrates through the insulating layers 85, from the insulating layer 85 that is one layer below the uppermost insulating layer 85U to the insulating layer 85 that is two layers above the lowermost insulating layer 85L. The first wiring portion 135 has flat wiring portions provided at the same positions as the insulating layers 85X on which the coils 41A, 42A are provided, and a plurality of vias provided between the two wiring portions in the z direction, between the upper wiring portion and the first electrode pad 81A, and between the lower wiring portion and the second wiring portion 136.

[0098] The second wiring portion 136 is provided closer to the substrate 84 than the first wiring portion 135. The second wiring portion 136 is provided closer to the substrate 84 than the first coil 41A. In this embodiment, the second wiring portion 136 is provided in an insulating layer 85 that is one layer above the lowest insulating layer 85L among the multiple insulating layers 85. Of both x-direction ends of the second wiring portion 136, the end closer to the chip side surface 80b of the transformer chip 80 is provided at a position overlapping with the first wiring portion 135 in a plan view. The second wiring portion 136 is connected to the first wiring portion 135. Of both x-direction ends of the second wiring portion 136, the end closer to the chip side surface 80a of the transformer chip 80 is provided at a position overlapping with the first coil 41A of the transformer 40AA in a plan view.

[0099] The third wiring portion 137 is disposed at a position overlapping with the second electrode pad 82A in a plan view. The third wiring portion 137 has a coil connection wiring portion provided at the same position as the first coil 41A in the z direction, and a connection wiring portion that connects the coil connection wiring portion and the second wiring portion 136. The coil connection wiring portion is connected to a first end of the first coil 41A. The connection wiring portion is disposed at a position overlapping with the coil connection wiring portion in a plan view, and penetrates the insulating layer 85 in the z direction between the coil connection wiring portion and the second wiring portion 136.

[0100] 5, the second connection wiring 132A has the same configuration as the first connection wiring 131A. Unlike the first connection wiring 131A, the second connection wiring 132A has a third wiring portion 137 connected to a second end of the first coil 41A of the transformers 40AA and 40AB.

[0101] 4 and 6, the third connection wiring 133A is a wiring that connects the second electrode pad 82A and the first end of the second coil 42A of the transformer 40AA. The third connection wiring 133A is arranged at a position that overlaps the second electrode pad 82A in a plan view. The third connection wiring 133A is arranged closer to the chip side surface 80a of the transformer chip 80 in the y direction and aligned in the x direction with the third wiring portion 137 of the first connection wiring 131A in a plan view.

[0102] The third connection wiring 133B is a wiring that connects the second electrode pad 82C and a first end of the second coil 42A of the transformer 40AB. The third connection wiring 133B is arranged at a position that overlaps the second electrode pad 82C in a plan view. The third connection wiring 133B is arranged closer to the chip side surface 80a of the transformer chip 80 in the y direction and aligned in the x direction with the third wiring portion 137 of the first connection wiring 131B in a plan view.

[0103] The third connection wiring 133C is a wiring that connects the second electrode pad 82D and a first end of the second coil 42B of the transformer 40BA. The third connection wiring 133C is arranged at a position that overlaps the second electrode pad 82D in a plan view. The third connection wiring 133C is arranged closer to the chip side surface 80a of the transformer chip 80 in the y direction and aligned in the x direction with the third wiring portion 137 of the first connection wiring 131C in a plan view.

[0104] The third connection wiring 133D is a wiring that connects the second electrode pad 82F and a first end of the second coil 42B of the transformer 40BB. The third connection wiring 133D is arranged at a position that overlaps the second electrode pad 82F in a plan view. The third connection wiring 133C is arranged closer to the chip side surface 80a of the transformer chip 80 in the y direction and aligned in the x direction with the third wiring portion 137 of the first connection wiring 131D in a plan view.

[0105] The fourth connection wiring 134A is a wiring that connects the second electrode pad 82B with the second end of the second coil 42A of the transformer 40AA and the second end of the second coil 42A of the transformer 40AB. The fourth connection wiring 134A is arranged between the second coil 42A of the transformer 40AA and the second coil 42A of the transformer 40AB in the x direction. The fourth connection wiring 134A is arranged in a position that overlaps with the second coils 42A of the transformers 40AA and 40AB when viewed from the x direction.

[0106] The fourth connection wiring 134B is a wiring that connects the second electrode pad 82D to the second end of the second coil 42B of the transformer 40BA and the second end of the second coil 42B of the transformer 40BB. The fourth connection wiring 134B is arranged between the second coil 42B of the transformer 40BA and the second coil 42B of the transformer 40BB in the x direction. The fourth connection wiring 134B is arranged in a position that overlaps with the second coils 42B of the transformers 40BA and 40BB when viewed from the x direction.

[0107] As shown in FIGS. 4 and 6, in this embodiment, the transformer chip 80 includes a dummy pattern 120 provided around the second coils 42A and 42B of the transformers 40AA, 40AB, 40BA, and 40BB.

[0108] The dummy pattern 120 is provided in the inner region 87, and includes a first dummy pattern 121, a second dummy pattern 122, and a third dummy pattern 123. The material of each of the dummy patterns 121 to 123 is selected from one or more of Ti, TiN, Au, Ag, Cu, Al, and W, as appropriate.

[0109] In a planar view, the first dummy pattern 121 is provided in each of the region between the second coil 42A of transformer 40AA and the second coil 42A of transformer 40AB in the x-direction, the region between the second coil 42B of transformer 40BA and the second coil 42B of transformer 40BB in the x-direction, and the region between the second coil 42B of transformer 40AB and the second coil 42B of transformer 40BA in the x-direction.

[0110] The first dummy pattern 121 is electrically connected to the second coil 42B via the fourth connection wiring 134B. The first dummy pattern 121 may also be electrically connected to the second coil 42A. That is, the first dummy pattern 121 only needs to be electrically connected to at least one of the second coils 42A and 42B. Thus, the first dummy pattern 121 has the same potential as the second coils 42A and 42B. Therefore, as the second reference potential of the second coils 42A and 42B changes, the voltage of the first dummy pattern 121, like the second coil 42B, may sometimes be higher than the voltage of the first coil 41B. As shown in FIG. 6, the first dummy pattern 121 is formed in a pattern different from the second coils 42A and 42B.

[0111] Although not shown, the first dummy pattern 121 is arranged in a position aligned with the second coils 42A and 42B in the z direction. In other words, the first dummy pattern 121 is arranged in a position farther from the substrate 84 than the first coils 41A and 41B. In other words, it can be said that the dummy pattern 120 is provided around the coil of the transformers 40AA, 40AB, 40BA, and 40BB that is closer to the chip main surface 80s of the transformer chip 80.

[0112] The first dummy pattern 121 has the same voltage as the second coils 42A, 42B, thereby suppressing a voltage drop between the second coils 42A, 42B and the first dummy pattern 121. Therefore, electric field concentration on the second coils 42A, 42B can be suppressed.

[0113] 6, the third dummy pattern 123 is formed to surround the second coils 42A and 42B of the transformers 40AA, 40AB, 40BA, and 40BB in a plan view. The third dummy pattern 123 is electrically connected to the first dummy pattern 121. Therefore, similar to the first dummy pattern 121, the voltage of the third dummy pattern 123 may become higher than that of the first coil 41B as the second reference potential of the second coil 42B changes.

[0114] 7, the third dummy pattern 123 is arranged at a position aligned with the second coil 42A in the z direction. Although not shown, the third dummy pattern 123 is also arranged at a position aligned with the second coil 42B in the z direction. In other words, the third dummy pattern 123 is arranged at a position farther from the substrate 84 than the first coils 41A and 41B. In this way, the dummy patterns 121 to 123 are arranged at positions aligned with one another in the z direction.

[0115] The third dummy pattern 123 has the same voltage as the second coils 42A, 42B, thereby suppressing a voltage drop between the second coils 42A, 42B and the third dummy pattern 123. Therefore, electric field concentration on the second coils 42A, 42B can be suppressed.

[0116] In a plan view, the second dummy pattern 122 is formed so as to surround the third dummy pattern 123. The second dummy pattern 122 is independent from the second coils 42A and 42B. In other words, the second dummy pattern 122 is not electrically connected to the second coils 42A and 42B.

[0117] 7, the second dummy pattern 122 is arranged in a position aligned with the second coil 42A in the z direction. Although not shown, the second dummy pattern 122 is also arranged in a position aligned with the second coil 42B in the z direction. In other words, the second dummy pattern 122 is arranged in a position farther from the substrate 84 than the first coils 41A and 41B. The second dummy pattern 122 can suppress an increase in the electric field strength around the second coils 42A and 42B, and can also suppress electric field concentration on the second electrode pads 82A to 82F.

[0118] As shown in FIG. 7, the transformer chip 80 includes a passivation layer 150 that protects the insulating layer 85. The passivation layer 150 is formed on a surface 85s of the insulating layer 85. The surface 85s of the insulating layer 85 is the surface of the uppermost insulating layer 85U among the multiple insulating layers 85. The surface of the uppermost insulating layer 85U faces the same side as the substrate main surface 84s of the substrate 84. The passivation layer 150 is provided near the chip main surface 80s of the transformer chip 80. Therefore, it can be said that the dummy pattern 120 is provided around the coil (in this embodiment, the second coils 42A and 42B) of the first coils 41A and 41B and the second coils 42A and 42B that is located near the passivation layer 150.

[0119] The passivation layer 150 covers each electrode pad 81 and each electrode pad 82 so that a portion of each electrode pad 81 and each electrode pad 82 is exposed from the z direction. That is, the passivation layer 150 has first protective layer openings 151 that expose each electrode pad 81 and second protective layer openings 152 that expose each electrode pad 82. That is, the passivation layer 150 has a plurality of first protective layer openings 151 formed corresponding to the plurality of first electrode pads 81, and a plurality of second protective layer openings 152 formed corresponding to the plurality of second electrode pads 82. Each first protective layer opening 151 exposes both of a pair of first electrode pads 81 adjacent to each other in the x direction among the plurality of first electrode pads 81. Each second protective layer opening 152 exposes both of a pair of second electrode pads 82 adjacent to each other in the x direction among the plurality of second electrode pads 82.

[0120] 8, the first protective layer opening 151 is provided at a position overlapping the first electrode pad 81 in a plan view, and penetrates the passivation layer 150. The first protective layer opening 151 communicates with a first insulating layer opening 85Ua in the uppermost insulating layer 85U. A first inner surface constituting the first protective layer opening 151 is flush with, for example, the first inner surface constituting the first insulating layer opening 85Ua.

[0121] 9, the second protective layer opening 152 is provided at a position overlapping the second electrode pad 82 in a plan view, and penetrates the passivation layer 150. The second protective layer opening 152 communicates with the second insulating layer opening 85Ub in the uppermost insulating layer 85U. The second inner surface constituting the second protective layer opening 152 is flush with, for example, the second inner surface constituting the second insulating layer opening 85Ub.

[0122] As shown in FIG. 7 , the passivation layer 150 is formed in the inner region 87. The passivation layer 150 is disposed at a position overlapping the shield electrode 86 in a plan view. The passivation layer 150 slightly protrudes outward from the shield electrode 86 in a plan view. In other words, the passivation layer 150 is also formed in a portion of the outer region 88. In this embodiment, the passivation layer 150 covers the entire surface 85s of the uppermost insulating layer 85U. The outer surface of the passivation layer 150 is flush with the outer surface of the uppermost insulating layer 85U. For this reason, a step portion 88a is formed in the outer region 88 of the transformer chip 80. The step portion 88a is formed outward from the shield electrode 86 in a plan view.

[0123] The passivation layer 150 is formed of a material containing, for example, silicon nitride. Examples of materials containing silicon nitride include SiN and SiCN. In this embodiment, the passivation layer 150 is formed of a material containing SiN.

[0124] 8, the thickness TP of the passivation layer 150 is equal to or less than the thickness TR of the insulating layer 85. The thickness TP of the passivation layer 150 is less than the thickness TRU of the uppermost insulating layer 85U. Alternatively, the thickness TP of the passivation layer 150 may be equal to the thickness of the first insulating layer 85A.

[0125] As shown in FIGS. 8 and 9, the passivation layer 150 has a first raised portion 153 and a second raised portion 154. The first raised portion 153 covers the uppermost insulating layer 85U that covers the outer peripheries of a pair of first electrode pads 81 aligned in the x direction. The second raised portion 154 covers the uppermost insulating layer 85U that covers the outer peripheries of a pair of second electrode pads 82 aligned in the x direction. The first raised portion 153 is a portion that forms the first protective layer opening 151, and the second raised portion 154 is a portion that forms the second protective layer opening 152. In a plan view, the first raised portion 153 and the second raised portion 154 each have a rectangular shape with the long side extending in the x direction and the short side extending in the y direction.

[0126] 7, the transformer chip 80 includes a low dielectric layer 160 formed on a surface 150s of the passivation layer 150. In this embodiment, the low dielectric layer 160 is in contact with the passivation layer 150. Here, the surface 150s of the passivation layer 150 is the surface of the passivation layer 150 that faces the same side as the substrate main surface 84s of the substrate 84 in a plan view.

[0127] In this embodiment, the low dielectric layer 160 is formed over the entire surface 150s of the passivation layer 150 in a plan view. More specifically, the outer edge of the low dielectric layer 160 is aligned with the outer edge of the passivation layer 150 in a plan view. That is, as shown in FIG. 8 , the outer surface of the low dielectric layer 160 and the outer surface of the passivation layer 150 are flush with each other.

[0128] It can be said that the low dielectric layer 160 is interposed between the passivation layer 150 and the molding resin 110 in the z direction so that the passivation layer 150 and the molding resin 110 do not come into contact with each other. As shown in Fig. 8, the thickness TE of the low dielectric layer 160 is equal to or less than the thickness TP of the passivation layer 150. In this embodiment, the thickness TE of the low dielectric layer 160 is smaller than the thickness TP of the passivation layer 150.

[0129] It should be noted that the thickness TE of the low-k dielectric layer 160 can be changed as desired. In one example, the thickness TE of the low-k dielectric layer 160 may be greater than the thickness TP of the passivation layer 150. 8 and 9, the low-dielectric layer 160 is formed with first dielectric layer openings 161 at positions overlapping with the first protective layer openings 151 in a plan view, and second dielectric layer openings 162 at positions overlapping with the second protective layer openings 152 in a plan view. That is, the low-dielectric layer 160 is formed with a plurality of first dielectric layer openings 161 corresponding to the plurality of first protective layer openings 151, and a plurality of second dielectric layer openings 162 corresponding to the plurality of second protective layer openings 152. The first dielectric layer openings 161 communicate with the first protective layer openings 151, and the second dielectric layer openings 162 communicate with the second protective layer openings 152.

[0130] The first inner surface forming the first dielectric layer opening 161 is flush with the first inner surface forming the first protective layer opening 151. The second inner surface forming the second dielectric layer opening 162 is flush with the second inner surface forming the second protective layer opening 152.

[0131] As described above, in this embodiment, the transformer chip 80 includes a first opening 171 consisting of the first insulating layer opening 85Ua, the first protective layer opening 151, and the first dielectric layer opening 161, and a second opening 172 consisting of the second insulating layer opening 85Ub, the second protective layer opening 152, and the second dielectric layer opening 162. In this embodiment, the first opening 171 and the second opening 172 can be said to penetrate both the passivation layer 150 and the low-dielectric layer 160. Furthermore, the first opening 171 and the second opening 172 can be said to penetrate the uppermost insulating layer 85U. In other words, the first opening 171 is an opening that exposes the first electrode pad 81 from the z-direction, and the second opening 172 is an opening that exposes the second electrode pad 82 from the z-direction. A wire W (not shown in FIGS. 7 and 8) is connected to the first electrode pad 81 through the first opening 171. A wire W (not shown in FIGS. 7 and 9) is connected to the second electrode pad 82 through the second opening 172.

[0132] 8 and 9, the low dielectric layer 160 has a first raised portion 163 and a second raised portion 164. The first raised portion 163 covers the first raised portion 153 of the passivation layer 150. The second raised portion 164 covers the second raised portion 154.

[0133] In this way, since the first opening 171 is made up of the uppermost insulating layer 85U, the passivation layer 150, and the low dielectric layer 160, a first raised portion 173 that covers the outer peripheries of the pair of first electrode pads 81 aligned in the x direction is provided around the first opening 171. In other words, the first raised portion 173 is made up of the portion of the uppermost insulating layer 85U that covers the outer peripheries of the pair of first electrode pads 81, the first raised portion 153 of the passivation layer 150, and the first raised portion 163 of the low dielectric layer 160.

[0134] Because the second opening 172 is composed of the uppermost insulating layer 85U, the passivation layer 150, and the low dielectric layer 160, a second raised portion 174 that covers the outer peripheries of the pair of second electrode pads 82 aligned in the x direction is provided around the second opening 172. In other words, the second raised portion 174 is composed of the portion of the uppermost insulating layer 85U that covers the outer peripheries of the pair of second electrode pads 82, the second raised portion 154 of the passivation layer 150, and the second raised portion 164 of the low dielectric layer 160.

[0135] As shown in FIGS. 7 to 9, the transformer chip 80 includes a resin layer 180 formed on the low dielectric layer 160. The resin layer 180 is in contact with the low dielectric layer 160. The resin layer 180 is formed of a material containing, for example, polyimide (PI). The resin layer 180 is a layer that relieves stress between the mold resin 110 and the insulating layer 85 and between the mold resin 110 and the substrate 84. The outer surface of the resin layer 180 is flush with the outer surface of the low dielectric layer 160.

[0136] 8, the thickness TD of the resin layer 180 is thicker than the thickness TE of the low dielectric layer 160. In other words, the thickness TE of the low dielectric layer 160 is thinner than the thickness TD of the resin layer 180. The thickness TD of the resin layer 180 is thicker than the thickness TRU of the uppermost insulating layer 85U and thicker than the thickness TP of the passivation layer 150.

[0137] As shown in FIGS. 3 and 4 , the resin layer 180 is separated into an inner resin layer 181 and an outer resin layer 182 by a separation groove 183. In a plan view, the separation groove 183 is formed so as to surround the transformers 40AA, 40AB, 40BA, and 40BB. Therefore, the inner resin layer 181 includes a region overlapping with the transformers 40AA, 40AB, 40BA, and 40BB. More specifically, as shown in FIG. 7 , the inner resin layer 181 includes a region overlapping with the dummy pattern 120 in a plan view. The inner resin layer 181 is also formed so as to surround a pair of second electrode pads 82 adjacent to each other in the x direction in a plan view. The outer resin layer 182 includes an outer peripheral region of the low dielectric layer 160 in a plan view. The outer resin layer 182 is formed so as to surround a pair of first electrode pads 81 adjacent to each other in the x direction in a plan view. In addition, in the separation groove 183, the surface 160s of the low dielectric layer 160 is exposed in the z direction from the resin layer 180. The shape of the separation groove 183 in plan view is a rectangular ring shape with the long side direction being the x direction and the short side direction being the y direction. Here, in this embodiment, the separation groove 183 corresponds to a "groove exposing the surface of the low dielectric layer."

[0138] As described above, in this embodiment, a concave-convex structure 190 is provided in the region between the first electrode pad 81 and the second electrode pad 82 on the surface 160s of the low dielectric layer 160. The concave-convex structure 190 of this embodiment is made up of an inner resin layer 181, an outer resin layer 182, and a separation groove 183. In detail, the concave-convex structure 190 is made up of a bonding surface between the low dielectric layer 160 and the molded resin 110, and a bonding surface between the resin layer 180 and the molded resin 110. More specifically, the concave-convex structure 190 is made up of a bonding surface between the low dielectric layer 160 and the molded resin 110 provided in the opening 184, a bonding surface between the inner resin layer 181 and the molded resin 110, a bonding surface between the resin layer 180 and the low dielectric layer 160 and the molded resin 110 in the separation groove 183, and a bonding surface between the outer resin layer 182 and the molded resin 110.

[0139] Note that a plurality of separation grooves 183 may be provided, for example, spaced apart from each other. In this case, the number of projections and recesses in the projection-recess structure 190 increases, and the creepage distance between the first electrode pad 81 and the second electrode pad 82 also increases.

[0140] 8 and 9, the resin layer 180 has first resin layer openings 184 provided at positions overlapping with the first openings 171 in a plan view, and second resin layer openings 185 provided at positions overlapping with the second openings 172 in a plan view. In other words, the resin layer 180 has a plurality of first resin layer openings 184 corresponding to the plurality of first openings 171, and a plurality of second resin layer openings 185 corresponding to the plurality of second openings 172.

[0141] The opening area of ​​the first resin layer opening 184 is larger than the opening area of ​​the first opening 171. The first resin layer opening 184 accommodates the first raised portion 173. In plan view, the inner surface constituting the first resin layer opening 184 is located outward from the first raised portion 173. As a result, the first raised portion 173 is exposed from the resin layer 180 in the z direction. That is, in plan view, the portion of the surface 160s of the low dielectric layer 160 that is located within the first resin layer opening 184 is exposed in the z direction from the first resin layer opening 184. The portion of the surface 160s of the low dielectric layer 160 that is located within the first resin layer opening 184 includes the first raised portion 173 and a surrounding portion of the surface 160s of the low dielectric layer 160.

[0142] The opening area of ​​the second resin layer opening 185 is larger than the opening area of ​​the second opening 172. The second resin layer opening 185 accommodates the second raised portion 174. In plan view, the inner surface constituting the first resin layer opening 184 is located outward from the second raised portion 174. As a result, the second raised portion 174 is exposed from the resin layer 180 in the z direction. That is, in plan view, the portion of the surface 160s of the low dielectric layer 160 that is located within the second resin layer opening 185 is exposed in the z direction from the second resin layer opening 185. The portion of the surface 160s of the low dielectric layer 160 that is located within the second resin layer opening 185 includes the second raised portion 174 and a surrounding portion of the surface 160s of the low dielectric layer 160.

[0143] The first resin layer opening 184 communicates with the first dielectric layer opening 161, and the second resin layer opening 185 communicates with the second dielectric layer opening 162. That is, each first electrode pad 81 is exposed in the z direction to the transformer chip 80 through each first dielectric layer opening 161, each first protective layer opening 151, and each first resin layer opening 184. Each second electrode pad 82 is exposed in the z direction to the transformer chip 80 through each second dielectric layer opening 162, each second protective layer opening 152, and each second resin layer opening 185.

[0144] The mold resin 110 of the gate driver 10 covers the transformer chip 80. More specifically, as shown in FIG. 7 , the mold resin 110 is formed to cover the resin layer 180. The resin layer 180 is formed to cover the passivation layer 150, the low dielectric layer 160, and the side surfaces of the resin layer 180. The mold resin 110 fills the separation groove 183. As a result, the mold resin 110 contacts both the outer surface of the inner resin layer 181 and the inner surface of the outer resin layer 182 of the resin layer 180 that constitute the separation groove 183.

[0145] Furthermore, the mold resin 110 fills each of the first resin layer openings 184 and each of the second resin layer openings 185. Therefore, the mold resin 110 contacts the surface 160s of the low dielectric layer 160 in each of the first resin layer openings 184 and each of the second resin layer openings 185. The mold resin 110 fills each of the first resin layer openings 184 and each of the second resin layer openings 185. As a result, the mold resin 110 contacts each of the first inner surface of the resin layer 180 that constitutes each of the first resin layer openings 184 and each of the second resin layer openings 185.

[0146] Furthermore, the mold resin 110 fills into each of the first openings 171 and each of the second openings 172. As a result, the mold resin 110 contacts the first electrode pads 81 through the first openings 171 and contacts the second electrode pads 82 through the second openings 172.

[0147] In this embodiment, the molding resin 110 enters each of the first openings 171 and thereby contacts a pair of first electrode pads 81 exposed from each of the first openings 171. The molding resin 110 fills each of the first openings 171. As a result, within each of the first openings 171, the molding resin 110 contacts each of the first inner surfaces of the first insulating layer openings 85Ua, the first inner surface of the first protective layer openings 151, and the first inner surface of the first dielectric layer openings 161 that constitute each of the first openings 171.

[0148] In this embodiment, the molding resin 110 enters each of the second openings 172 and thereby contacts the pair of second electrode pads 82 exposed from each of the second openings 172. The molding resin 110 fills each of the second openings 172. As a result, within each of the second openings 172, the molding resin 110 contacts each of the second inner surfaces of the second insulating layer openings 85Ub, the second inner surface of the second protective layer openings 152, and the second inner surface of the second dielectric layer openings 162 that constitute each of the second openings 172.

[0149] Next, the relationship between the dielectric constants of the insulating layer 85, the passivation layer 150, the low-dielectric layer 160, the resin layer 180, and the molding resin 110 will be described. In this embodiment, the insulating layer 85 is made of a material containing SiO2, and therefore the dielectric constant of the insulating layer 85 is approximately 4.1. The passivation layer 150 is made of a material containing SiN, and therefore the dielectric constant of the passivation layer 150 is approximately 7.0. In other words, the dielectric constant of the passivation layer 150 is higher than the dielectric constant of the insulating layer 85.

[0150] In this embodiment, the resin layer 180 is made of a material containing polyimide, and therefore the dielectric constant of the resin layer 180 is about 2.9. In this embodiment, the mold resin 110 is made of a material containing epoxy resin, and therefore the mold resin 110 has a dielectric constant of about 3.9. In other words, the mold resin 110 has a lower dielectric constant than the passivation layer 150. The mold resin 110 has a higher dielectric constant than the resin layer 180.

[0151] The low-dielectric layer 160 has a lower dielectric constant than the passivation layer 150. For example, the low-dielectric layer 160 has a dielectric constant equal to or lower than that of the insulating layer 85. More specifically, the low-dielectric layer 160 has a lower dielectric constant than that of the first insulating layer 85A of the insulating layer 85. The low-dielectric layer 160 has a dielectric constant equal to or lower than that of the second insulating layer 85B of the insulating layer 85. The low-dielectric layer 160 may have a dielectric constant equal to or lower than that of the molding compound 110.

[0152] The low-dielectric layer 160 may be formed of, for example, a material containing SiO2. In this way, the low-dielectric layer 160 may be formed of the same material as the second insulating layer 85B of the insulating layer 85. The low-dielectric layer 160 may also have a lower dielectric constant than the insulating layer 85. The low-dielectric layer 160 may be formed of a low-k film. The low-k film may be appropriately selected from, for example, SiOC (carbon-doped silicon dioxide film), SiOF (fluorine-doped silicon dioxide film), porous film, etc. When the low-dielectric layer 160 is made of SiOC, the dielectric constant of the low-dielectric layer 160 is 2.5 or more and 3.0 or less. When the low-dielectric layer 160 is made of SiOF, the dielectric constant of the low-dielectric layer 160 is 3.4 or more and 3.8 or less. When the low-dielectric layer 160 is made of a porous film, the dielectric constant of the low-dielectric layer 160 is less than 2.5. In this way, by using a low-k film for the low-dielectric layer 160, the dielectric constant of the low-dielectric layer 160 can be made lower than that of the insulating layer 85 and the molding resin 110.

[0153] An example of a method for manufacturing the gate driver 10 of this embodiment will be outlined below. First, a low-voltage circuit chip 60, a high-voltage circuit chip 70, and a transformer chip 80 are prepared. A manufacturing method for the transformer chip 80 mainly includes the steps of preparing a substrate 84, forming an insulating layer 85 on the substrate 84, embedding a plurality of transformers 40 and a plurality of dummy patterns 120 in the insulating layer 85, forming a plurality of first electrode pads 81 and a plurality of second electrode pads 82, embedding a shield electrode 86, forming a passivation layer 150, forming a low-dielectric layer 160, forming each of the first openings 171 and each of the second openings 172, and forming a resin layer 180.

[0154] In the process of forming each of the first openings 171 and each of the second openings 172, a passivation layer 150 is laminated on the uppermost insulating layer 85U of the multiple insulating layers 85. Next, a low dielectric layer 160 is laminated on the passivation layer 150. Next, each of the first openings 171 and each of the second openings 172 is formed so as to penetrate each of the uppermost insulating layer 85U, the passivation layer 150, and the low dielectric layer 160 in the z direction.

[0155] In the step of forming the resin layer 180, the resin layer 180 is formed in a state where the first openings 171 and the second openings 172 are masked. Then, the masks on the first openings 171 and the second openings 172 are removed. Through the above steps, the transformer chip 80 is manufactured.

[0156] Next, a lead frame is prepared on which the low-voltage die pad 91 and low-voltage leads 92, and the high-voltage die pad 101 and high-voltage leads 102 are formed. In this process, the low-voltage leads 92 and high-voltage leads 102 are integrated with the lead frame.

[0157] Next, the low-voltage circuit chip 60 and the transformer chip 80 are, for example, die-bonded to the low-voltage die pad 91, and the high-voltage circuit chip 70 is, for example, die-bonded to the high-voltage die pad 101. Subsequently, using a wire bonding device, wires W are formed that connect the electrode pads 61, 63 of the low-voltage circuit chip 60 to the low-voltage leads 92, wires W that connect the second electrode pads 62 of the low-voltage circuit chip 60 to the first electrode pads 81 of the transformer chip 80, wires W that connect the second electrode pads 82 of the transformer chip 80 to the first electrode pads 71 ​​of the high-voltage circuit chip 70, and wires W that connect the electrode pads 72, 73 of the high-voltage circuit chip 70 to the high-voltage leads 102.

[0158] Next, a sealing layer is formed to seal at least the low-voltage die pad 91, the high-voltage die pad 101, the low-voltage circuit chip 60, the high-voltage circuit chip 70, the transformer chip 80, and the plurality of wires W. The sealing layer is made of, for example, black epoxy resin, and is formed by compression molding.

[0159] Next, the sealing layer and the lead frame are cut, thereby forming the molding resin 110, the low-voltage leads 92, and the high-voltage leads 102. Through the above steps, the gate driver 10 is manufactured.

[0160] (Operation of the first embodiment) The operation of the gate driver 10 of this embodiment will be described below. In the following description, a transformer chip having a configuration in which the low dielectric layer 160 is omitted from the transformer chip 80 of the gate driver 10 will be referred to as a transformer chip of a comparative example.

[0161] In the transformer chip of the comparative example, the passivation layer 150 has a portion exposed from the resin layer 180. That is, in the transformer chip of the comparative example, a portion is formed where the passivation layer 150 and the molded resin 110 come into contact with each other. When the transformer chip 80 is sealed with the molded resin 110, voids are formed in the molded resin 110 during the molding process. These voids may be located at the boundary between the molded resin 110 and the passivation layer 150. In this state, when a high voltage is applied to the transformer chip of the comparative example, partial discharge may occur through the void located at the boundary between the molded resin 110 and the passivation layer 150. This partial discharge may cause creeping discharge along the boundary between the molded resin 110 and the passivation layer 150. Regarding such discharges, the inventors of the present application have found that the higher the dielectric constant of the layer in contact with the molded resin 110, the lower the inception voltage of partial discharge and the more likely partial discharge and creeping discharge are to occur. In other words, in the transformer chip of the comparative example, the passivation layer 150 in contact with the molded resin 110 is made of a material containing SiN, and its dielectric constant is 7.0, which is higher than that of other layers, so the inception voltage of partial discharge is low and partial discharge and creeping discharge are more likely to occur.

[0162] Therefore, the inventors of the present application discovered that a structure in which the passivation layer 150 is not in contact with the mold resin 110 can be achieved by covering the passivation layer 150 with a layer having a lower dielectric constant than the passivation layer 150. In this embodiment, the transformer chip 80 includes a low-dielectric layer 160 covering the passivation layer 150. The low-dielectric layer 160 is a layer in contact with the mold resin 110. This prevents the mold resin 110 and the passivation layer 150 from coming into contact with each other. This prevents partial discharge and, ultimately, creeping discharge from occurring due to voids present at the boundary between the mold resin 110 and the passivation layer 150 when the mold resin 110 and the passivation layer 150 come into contact with each other. In addition, the low-dielectric layer 160 has a lower dielectric constant than the passivation layer 150. Therefore, the inception voltage of partial discharge at the boundary between the low dielectric layer 160 and the molded resin 110 is higher than the inception voltage of partial discharge at the boundary between the passivation layer 150 and the molded resin 110. Therefore, it is possible to suppress the occurrence of partial discharge, and in turn creeping discharge, due to voids existing at the boundary between the molded resin 110 and the low dielectric layer 160.

[0163] (Effects of the first embodiment) The gate driver 10 of this embodiment provides the following advantages. (1-1) The transformer chip 80 includes first coils 41A, 41B and second coils 42A, 42B, first electrode pads 81 connected to the first coils 41A, 41B, second electrode pads 82 provided at positions spaced apart from the first electrode pads 81 in a plan view and connected to the second coils 42A, 42B, a passivation layer 150 formed on a surface 85s of an insulating layer 85 to protect the insulating layer 85, and a low-dielectric layer 160 formed on a surface 150s of the passivation layer 150 and having a lower dielectric constant than the passivation layer 150. The low-dielectric layer 160 is covered with a mold resin 110.

[0164] According to this configuration, the low dielectric layer 160 is interposed between the passivation layer 150 and the molded resin 110, thereby preventing the passivation layer 150 from coming into contact with the molded resin 110. This prevents partial discharge and, ultimately, creeping discharge from occurring due to gaps present at the boundary between the molded resin 110 and the passivation layer 150. This improves the reliability of the transformer chip 80.

[0165] (1-2) The dielectric constant of the low dielectric layer 160 is equal to or lower than the dielectric constant of the molding resin 110 . According to this configuration, the inception voltage of partial discharge at the boundary between the low dielectric layer 160 and the molded resin 110 can be increased, thereby suppressing the occurrence of partial discharge, and ultimately creeping discharge, due to voids present at the boundary between the low dielectric layer 160 and the molded resin 110.

[0166] (1-3) The thickness TE of the low dielectric layer 160 is equal to or less than the thickness TP of the passivation layer 150. This configuration can prevent the size of the transformer chip 80 in the z direction from increasing.

[0167] (1-4) When the gate driver 10 is operating, a high voltage is applied to each second electrode pad 82 in the transformer chip 80, forming a high electric field around each second electrode pad 82. Therefore, although the occurrence of creeping discharge is suppressed by the low dielectric layer 160, creeping discharge is more likely to occur at the boundary between the low dielectric layer 160 and the mold resin 110 around each second electrode pad 82 than at other boundary areas. If a creeping discharge occurs and travels from the second electrode pad 82 to the first electrode pad 81, the second electrode pad 82 and the first electrode pad 81 may become electrically connected if the creeping distance between them is short.

[0168] Therefore, in this embodiment, an uneven structure 190 is provided between the first electrode pad 81 and the second electrode pad 82 on the surface 160s of the low dielectric layer 160. This allows a large creeping distance between the first electrode pad 81 and the second electrode pad 82. Therefore, even if creeping discharge occurs at the boundary between the low dielectric layer 160 and the mold resin 110, the first electrode pad 81 and the second electrode pad 82 are unlikely to become electrically connected.

[0169] (1-5) In plan view, a dummy pattern 120 is provided around the second coils 42A and 42B. With this configuration, the electric field concentration on the second coils 42A, 42B is alleviated, thereby suppressing the occurrence of partial discharges and, ultimately, creeping discharges due to gaps at the boundary between the low dielectric layer 160 and the molded resin 110 near the second coils 42A, 42B.

[0170] (1-6) The gate driver 10 includes a low-voltage circuit 20 configured to operate when a first voltage V1 is applied, a high-voltage circuit 30 configured to operate when a second voltage V2 higher than the first voltage V1 is applied, and a transformer chip 80. The low-voltage circuit 20 and the high-voltage circuit 30 are connected via the transformer chip 80, and are configured to transmit signals via the transformer chip 80. The transformer chip 80 includes first coils 41A, 41B and second coils 42A, 42B, a first electrode pad 81 connected to the first coils 41A, 41B, a second electrode pad 82 provided at a position spaced apart from the first electrode pad 81 in a plan view and connected to the second coils 42A, 42B, a passivation layer 150 formed on a surface 85s of an insulating layer 85 to protect the insulating layer 85, and a low-dielectric layer 160 formed on a surface 150s of the passivation layer 150 and having a lower dielectric constant than the surface 150s of the passivation layer 150. The low-dielectric layer 160 is covered with a molding resin 110. This configuration provides the same effect as in (1-1) above, thereby providing a highly reliable gate driver 10.

[0171] (1-7) Possible configurations of the gate driver 10 including the transformer 40 include, for example, a low-voltage circuit chip including the low-voltage circuit 20 and the transformer 40, or a high-voltage circuit chip including the high-voltage circuit 30 and the transformer 40. However, in these configurations, if the circuit configuration of the low-voltage circuit 20 or the high-voltage circuit 30 is to be changed, it is necessary to change the entire chip, which increases the cost of manufacturing multiple types of gate drivers.

[0172] In this regard, in this embodiment, the transformer 40 is included in a transformer chip 80, which is a chip independent of the low-voltage circuit chip 60 and the high-voltage circuit chip 70. In other words, a chip dedicated to the transformer 40 is provided. Therefore, a common transformer chip 80 can be used for different low-voltage circuits 20 and high-voltage circuits 30. This reduces costs when manufacturing multiple types of gate drivers 10 in which at least one of the low-voltage circuits 20 and the high-voltage circuits 30 is different.

[0173] [Second embodiment] A gate driver 10 of the second embodiment will be described with reference to Figure 10. The gate driver 10 of this embodiment differs from the gate driver 10 of the first embodiment in the shape of the low dielectric layer 160 of the transformer chip 80. In the following description, differences from the gate driver 10 of the first embodiment will be described in detail, and components common to the gate driver 10 of the first embodiment will be denoted by common reference numerals and will not be described again.

[0174] 10 , compared to the low dielectric layer 160 of the first embodiment, the low dielectric layer 160 of this embodiment further includes a first inner surface cover portion 165, a second inner surface cover portion 166, and an outer surface cover portion 167. Here, in this embodiment, the portion of the low dielectric layer 160 that covers the passivation layer 150 in plan view is defined as a main cover portion 168. In this embodiment, the low dielectric layer 160 is formed by integrating the first inner surface cover portion 165, the second inner surface cover portion 166, the outer surface cover portion 167, and the main cover portion 168.

[0175] In this embodiment, the first opening 171 consists of a first protective layer opening 151 in the passivation layer 150 and a first insulating layer opening 85Ua in the uppermost insulating layer 85U. The second opening 172 consists of a second protective layer opening 152 in the passivation layer 150 and a second insulating layer opening 85Ub in the uppermost insulating layer 85U. The uppermost insulating layer 85U has a first inner surface that constitutes the first insulating layer opening 85Ua and a second inner surface that constitutes the second insulating layer opening 85Ub. The passivation layer 150 has a first inner surface that constitutes the first protective layer opening 151 and a second inner surface that constitutes the second protective layer opening 152. Here, in this embodiment, the first inner surface of the first protective layer opening 151 corresponds to the "first inner surface of the first opening," and the second inner surface of the second protective layer opening 152 corresponds to the "second inner surface of the second opening."

[0176] The first inner surface cover portion 165 is formed on the first inner surface of the first protective layer opening 151. In other words, the first inner surface cover portion 165 covers the first inner surface of the first protective layer opening 151. In this embodiment, the tip surface of the first inner surface cover portion 165 contacts the first electrode pad 81. In other words, it can be said that the first inner surface cover portion 165 is formed on the first inner surface of the first opening 171. In this embodiment, the tip surface of the first inner surface cover portion 165 contacts the first electrode pad 81.

[0177] As described above, in this embodiment, the first dielectric layer opening 161 forms an opening that exposes the first electrode pad 81 from the z direction. The first dielectric layer opening 161 is formed by the first inner surface cover portion 165. Although not shown, a wire W is connected to the first electrode pad 81 through the first dielectric layer opening 161.

[0178] The second inner surface cover portion 166 is formed on the second inner surface of the second protective layer opening 152. In other words, the second inner surface cover portion 166 covers the second inner surface of the second protective layer opening 152. In this embodiment, the tip surface of the second inner surface cover portion 166 is in contact with the second electrode pad 82. In other words, it can be said that the second inner surface cover portion 166 is formed on the second inner surface of the second opening 172.

[0179] As described above, in this embodiment, the second dielectric layer opening 162 forms an opening that exposes the second electrode pad 82 from the z direction. The second dielectric layer opening 162 is formed by the second inner surface cover portion 166. Although not shown, a wire W is connected to the second electrode pad 82 through the second dielectric layer opening 162.

[0180] The outer surface cover portion 167 is formed on the outer surface of the passivation layer 150 located in the outer region 88. In other words, the outer surface cover portion 167 covers the outer surface of the passivation layer 150 located in the outer region 88. The outer surface of the passivation layer 150 is the surface that forms the step portion 88a. In other words, the outer surface cover portion 167 covers the entire outer surface of the passivation layer 150. For this reason, it can be said that the low dielectric layer 160 covers the end faces of the passivation layer 150.

[0181] In this manner, in this embodiment, the low dielectric layer 160 prevents the passivation layer 150 from coming into contact with the mold resin 110. This prevents a gap from being formed between the passivation layer 150 and the mold resin 110, thereby suppressing the occurrence of partial discharge due to the gap.

[0182] In this embodiment, the tip end surface of the outer surface cover portion 167 contacts the surface of the insulating layer 85 that is one layer below the uppermost insulating layer 85U among the multiple insulating layers 85. In other words, the outer surface cover portion 167 covers the entire outer surface of the uppermost insulating layer 85U.

[0183] An outline of an example of a manufacturing method for the gate driver 10 of this embodiment will be described. The manufacturing method for the gate driver 10 of this embodiment differs from the manufacturing method for the gate driver 10 of the first embodiment in the methods for forming the openings 171, 172 and the low dielectric layer 160 of the transformer chip 80. The methods for forming the openings 171, 172 and the low dielectric layer 160 of the transformer chip 80 will be described below.

[0184] In the process of forming each opening 171, 172 of the transformer chip 80, unlike the first embodiment, a passivation layer 150 is formed on the top insulating layer 85U, and then each opening 171, 172 is formed by penetrating the passivation layer 150.

[0185] Next, the low-dielectric layer 160 is formed on the passivation layer 150. In this case, a portion of the low-dielectric layer 160 is formed in each of the openings 171, 172. Subsequently, the low-dielectric layer 160 formed in each of the openings 171, 172 is removed so that the electrode pads 81, 82 are exposed in the z-direction. As a result, the first inner surface cover portion 165 and the second inner surface cover portion 166 are formed.

[0186] Furthermore, a portion of the low dielectric layer 160 is formed in the step portion 88a of the outer region 88. Next, the low dielectric layer 160 formed on the uppermost insulating layer 85 of the plurality of insulating layers 85, out of the low dielectric layer 160 formed in the step portion 88a, is removed. This forms the outer surface cover portion 167. Through the above steps, the low dielectric layer 160 is formed.

[0187] (Effects of the second embodiment) According to the gate driver 10 of this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0188] (2-1) The low-dielectric layer 160 is formed on both the first inner surface that constitutes the first opening 171 and the second inner surface that constitutes the second opening 172. The low-dielectric layer 160 covers the end face of the passivation layer 150.

[0189] According to this configuration, the passivation layer 150 constituting each of the openings 171, 172 and the outer surface of the passivation layer 150 are covered with the low dielectric layer 160, which further prevents the passivation layer 150 from coming into direct contact with the mold resin 110. Therefore, it is possible to further prevent partial discharge and creeping discharge from occurring when a high voltage is applied to the transformer chip 80.

[0190] [Third embodiment] A gate driver 10 of the third embodiment will be described with reference to FIGS. 11 to 13. The gate driver 10 of this embodiment differs from the gate driver 10 of the first embodiment in the insulating structure of the transformer. In the following description, differences from the gate driver 10 of the first embodiment will be described in detail, and components common to the gate driver 10 of the first embodiment will be given common reference numerals and will not be described again. For convenience, FIG. 13 shows the coils of each transformer, the shape of the dummy pattern, and the shield electrode simplified compared to the first embodiment, and omits the connection structure between each electrode pad and the coil.

[0191] 11, the gate driver 10 of this embodiment has a double-insulation structure using multiple transformers. That is, the transformer 40A has a first transformer 43A and a second transformer 44A connected in series. The transformer 40B has a first transformer 43B and a second transformer 44B connected in series. Because the transformers 40A and 40B each have a double-insulation structure, the withstand voltage of the gate driver 10 is higher than those of the first and second embodiments, for example, about 7500 Vrms.

[0192] The first transformer 43A is electrically connected to the low-voltage circuit 20. The first transformer 43A has a first coil 45A and a second coil 46A that is insulated from the first coil 45A and is magnetically coupleable with the first coil 45A.

[0193] The second transformer 44A is electrically connected to the high-voltage circuit 30. The second transformer 44A connects the first transformer 43A and the high-voltage circuit 30. The second transformer 44A has a first coil 47A and a second coil 48A that is insulated from the first coil 47A and is magnetically coupleable with the first coil 47A.

[0194] The first coil 45A is electrically connected to the low-voltage circuit 20 by the low-voltage signal line 21A, and is also connected to the ground of the low-voltage circuit 20. That is, a first end of the first coil 45A is electrically connected to the low-voltage circuit 20, and a second end of the first coil 45A is electrically connected to the ground of the low-voltage circuit 20. Therefore, the potential of the second end of the first coil 45A becomes a first reference potential. The first reference potential is, for example, 0 V.

[0195] The second coil 46A is connected to the first coil 47A of the second transformer 44A. In one example, the second coil 46A and the first coil 47A are connected to each other so as to be in an electrically floating state. That is, the first end of the second coil 46A is connected to the first end of the first coil 47A, and the second end of the second coil 46A is connected to the second end of the first coil 47A. In this way, the second coil 46A and the first coil 47A serve as relay coils that relay transmission of the set signal from the first coil 45A to the second coil 48A.

[0196] The second coil 48A is electrically connected to the high-voltage circuit 30 by the high-voltage signal line 31A, and is also connected to the ground of the high-voltage circuit 30. That is, a first end of the second coil 48A is connected to the high-voltage circuit 30, and a second end of the second coil 48A is connected to the ground of the high-voltage circuit 30. Therefore, the potential of the second end of the second coil 48A becomes the second reference potential. The second reference potential fluctuates as the inverter device 500 is driven, and becomes, for example, 600 V or higher.

[0197] Furthermore, the coils 45A and 46A of the first transformer 43A and the coils 47A and 48A of the second transformer 44A have an elliptical spiral shape in plan view, as in the first embodiment (see FIG. 12). The winding direction of the coils 45A and 46A of the first transformer 43A is opposite to the winding direction of the coils 47A and 48A of the second transformer 44A. The winding directions of the coils 45A, 46A, 47A, and 48A can be changed as desired. In one example, the winding direction of the coils 45A and 46A may be the same as the winding direction of the coils 47A and 48A.

[0198] The first transformer 43B of the transformer 40B has a first coil 45B electrically connected to the low-voltage circuit 20, and a second coil 46B insulated from and magnetically coupleable with the first coil 45B.

[0199] The second transformer 44B of the transformer 40B has a first coil 47B electrically connected to the high-voltage circuit 30, and a second coil 48B insulated from and magnetically coupled to the first coil 47B. The transformer 40B is similar to the transformer 40A, and therefore a detailed description thereof will be omitted.

[0200] Fig. 12 shows an example of a plan view illustrating the internal configuration of the gate driver 10. Note that Fig. 11 shows a simplified circuit configuration of the gate driver 10, and therefore the number of external terminals of the gate driver 10 in Fig. 12 is greater than the number of external terminals of the gate driver 10 in Fig. 11. Here, the number of external terminals of the gate driver 10 refers to the number of external electrodes that can connect the gate driver 10 to external electronic components of the gate driver 10, such as the ECU 503 and switching elements 501 (see Fig. 11). Furthermore, the number of signal lines (the number of wires W, described later) that transmit signals from the low-voltage circuit 20 to the high-voltage circuit 30 in the gate driver 10 in Fig. 12 is greater than the number of signal lines in the gate driver 10 in Fig. 11.

[0201] As shown in FIG. 12, the transformer chip 80 includes first transformers 43A and 43B and second transformers 44A and 44B. More specifically, these transformers 43A, 44A, 43B, and 44B are packaged together. In the transformer chip 80, the first transformer 43A and the second transformer 44A are aligned in the x direction but spaced apart in the y direction. The first transformer 43B and the second transformer 44B are aligned in the x direction but spaced apart in the y direction. The first transformer 43A and the first transformer 43B are aligned in the y direction but spaced apart in the x direction. The first transformer 43A and the second transformer 44A can also be said to be spaced apart in the direction in which the chips 60, 70, and 80 are arranged. The second transformers 44A and the second transformers 44B are aligned in the y direction but spaced apart in the x direction. It can also be said that the first transformer 43B and the second transformer 44B are arranged spaced apart from each other in the direction in which the chips 60, 70, and 80 are arranged.

[0202] The first transformers 43A and 43B are arranged closer to the low-voltage circuit chip 60 than the second transformers 44A and 44B of the transformer chip 80. As a result, the first transformers 43A and 43B, which are electrically connected to the low-voltage circuit chip 60, are arranged closer to the low-voltage circuit chip 60, thereby shortening the conductive paths between the low-voltage circuit 20 and the first transformers 43A and 43B.

[0203] The second transformers 44A, 44B are arranged closer to the high-voltage circuit chip 70 than the first transformers 43A, 43B of the transformer chip 80. As a result, the second transformers 44A, 44B, which are electrically connected to the high-voltage circuit chip 70, are arranged closer to the high-voltage circuit chip 70, thereby shortening the conductive path between the high-voltage circuit 30 and the second transformers 44A, 44B.

[0204] 12, the arrangement of the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70 and the connection by the wires W are the same as those in the first embodiment. The arrangement of the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70, and the low-voltage die pad 91 and the high-voltage die pad 101 are the same as those in the first embodiment.

[0205] An example of the internal structure of the transformer chip 80 will be described with reference to Figure 13. Figure 13 shows a schematic cross-sectional structure of the transformer 40A in the transformer chip 80. Note that the transformer 40B has the same configuration as the transformer 40A, and therefore detailed description thereof will be omitted. In the following description, the direction from the chip back surface 80r of the transformer chip 80 toward the chip main surface 80s will be referred to as "upward," and the direction from the chip main surface 80s toward the chip back surface 80r will be referred to as "downward."

[0206] 13, a first transformer 43A and a second transformer 44A are embedded in an insulating layer 85. The first transformer 43A and the second transformer 44A can also be said to be arranged spaced apart from each other in the direction in which the chips 60, 70, and 80 are arranged. Both the first transformer 43A and the second transformer 44A are disposed in an inner region 87 of the insulating layer 85.

[0207] The first coil 45A and the second coil 46A of the first transformer 43A are arranged opposite each other in the z direction with an insulating layer 85 interposed therebetween. In this embodiment, the first coil 45A and the second coil 46A are arranged opposite each other in the z direction with a plurality of insulating layers 85 interposed therebetween. Each of the coils 45A, 46A is configured as a conductive layer embedded in one insulating layer 85, similar to the first embodiment.

[0208] In the z direction, the second coil 46A is located farther from the substrate 84 than the first coil 45A. In other words, the second coil 46A is located higher than the first coil 45A. In addition, the first coil 45A can also be said to be disposed closer to the substrate 84 in the z direction than the second coil 46A.

[0209] The first coil 47A and the second coil 48A of the second transformer 44A are disposed opposite each other in the z direction with the insulating layer 85 interposed therebetween. Like the coils 45A and 46A, the coils 47A and 48A are configured as conductive layers embedded in one insulating layer 85. In the z direction, the first coil 47A is located farther from the substrate 84 than the second coil 48A. In other words, the first coil 47A is located higher than the second coil 48A. In addition, the second coil 48A is located closer to the substrate 84 in the z direction than the first coil 47A.

[0210] The positions of the first coils 45A, 47A and the second coils 46A, 48A within the transformer chip 80 are set so that the dielectric strength voltage of the transformer chip 80 becomes a preset dielectric strength voltage.

[0211] The distance D11 between the first coil 45A and the second coil 46A is greater than the distance D12 between the first coil 47A and the second coil 48A. This makes it possible to prevent dielectric breakdown caused by a short circuit between the first coil 45A and the second coil 46A. In one example, the distance D11 is at least twice the distance D12. However, the present invention is not limited to this, and the distance D11 may be less than twice the distance D12.

[0212] In this embodiment, the second coil 46A and the first coil 47A are aligned in the z direction. Meanwhile, the second coil 48A is located farther from the substrate 84 (i.e., higher) than the first coil 45A in the z direction. This makes the distance D11 greater than the distance D12.

[0213] In this case, when viewed from the y direction, the second coil 48A is disposed between the first coil 45A and the second coil 46A in the z direction. That is, the distance D14 between the second coil 48A and the substrate 84 is greater than the distance D13 between the first coil 45A and the substrate 84. This allows the distance D14 between the second coil 48A, to which a high voltage is likely to be applied, and the substrate 84 to be greater, thereby improving the dielectric strength of the transformer chip 80. In one example, the distance D14 is at least twice the distance D13. However, the present invention is not limited to this, and the distance D14 may be less than twice the distance D13.

[0214] Since the second coil 48A is electrically connected to the high-voltage die pad 101 (see FIG. 12), the second end of the second coil 48A may have a different potential from the substrate 84. For this reason, the second coil 48A and the substrate 84 must be insulated from each other. That is, by increasing the distance D14 between the second coil 48A and the substrate 84, the dielectric strength of the transformer chip 80 can be improved.

[0215] In one example, the distance D14 between the second coil 48A and the substrate 84 is equal to or greater than the distance D12 between the first coil 47A and the second coil 48A. This allows the distance D14 to be increased while preventing the z-direction dimension of the transformer chip 80 from increasing, thereby improving the dielectric strength of the transformer chip 80. Furthermore, since the voltage applied between the first coil 45A and the second coil 46A tends to be lower than the voltage applied between the second coil 48A and the substrate 84, the dielectric strength of the transformer chip 80 can be ensured even if the distance D12 is reduced.

[0216] In this embodiment, the distance D14 is greater than the distance D12. In one example, the distance D14 is equal to or greater than twice the distance D12. However, the present invention is not limited to this, and the distance D14 may be less than twice the distance D12.

[0217] In one example, the distance D14 between the second coil 48A and the substrate 84 is equal to or greater than the distance D11 between the first coil 45A and the second coil 46A. This allows the distance D14 between the second coil 48A, to which a high voltage is likely to be applied, and the substrate 84 to be increased, thereby improving the dielectric strength of the transformer chip 80. In this embodiment, the distance D14 is equal to the distance D11.

[0218] Due to the relationship between the distances D11 to D14, it can be said that the first coil 45A is closer to the substrate 84 than the second coil 48A. Because both the first coil 45A and the substrate 84 are electrically connected to the low-voltage die pad 91, the ground of the first coil 45A and the substrate 84 are at the same potential. Therefore, even if the first coil 45A is disposed near the substrate 84, a decrease in the dielectric strength of the transformer chip 80 can be suppressed. In this embodiment, the distance D13 between the first coil 45A and the substrate 84 is smaller than the distance D11 between the first coil 45A and the second coil 46A. The distance D13 is equal to or smaller than half the distance D11. However, the present invention is not limited to this, and the distance D13 may be greater than half the distance D11.

[0219] In one example, the distance D15 between the second coil 48A and the first coil 45A is equal to or greater than the distance D14 between the second coil 48A and the substrate 84. The distance D15 is the shortest distance between the second coil 48A and the first coil 45A. This makes it less likely that dielectric breakdown will occur due to a short circuit between the first coil 45A and the second coil 48A. This can improve the dielectric strength of the transformer chip 80.

[0220] In this embodiment, the distance D15 is equal to the distance D14. The distance D15 is equal to or greater than the distance D11. In this embodiment, the distance D14 is equal to the distance D11, so the distance D15 is equal to the distance D11.

[0221] The distance between the second coil 48A and the first coil 47A in the y direction is set in accordance with the distance D15 between the second coil 48A and the first coil 45A. Specifically, the central axis J1 of the first coil 45A and the central axis J2 of the second coil 46A coincide with each other, and the central axis J3 of the first coil 47A and the central axis J4 of the second coil 48A coincide with each other. Therefore, the positions of the first coil 45A and the second coil 48A in the x direction and the y direction are set in accordance with the setting of the distance D15. In a plan view, the positions of the second coil 46A and the first coil 47A in the x direction and the y direction are the same as the positions of the first coil 45A and the second coil 48A in the x direction and the y direction, and therefore the distance between the second coil 48A and the first coil 47A in the y direction is set.

[0222] Dummy patterns may be provided around the second coils 46A and 46B of the first transformer 43A and the second coils 48A and 48B of the second transformer 44A. This can suppress electric field concentration on the second coils 46A, 46B, 48A, and 48B. In the following description, the dummy patterns provided around the second coils 46A and 46B are referred to as dummy patterns 120A, and the dummy patterns provided around the second coils 48A and 48B are referred to as dummy patterns 120B. The configuration of these dummy patterns 120A and 120B is the same as the configuration of the dummy patterns 120 in the first embodiment. The relationship between the second coils 46B and 48B and the dummy patterns 120A and 120B is the same as the relationship between the second coils 46A and 48A and the dummy patterns 120A and 120B. Therefore, in the following description, the relationship between the second coils 46A, 48A and the dummy patterns 120A, 120B will be described, and a description of the relationship between the second coils 46B, 48B and the dummy patterns 120A, 120B will be omitted.

[0223] Dummy pattern 120A is aligned with second coil 46A in the z direction, and dummy pattern 120B is aligned with second coil 48A in the z direction. Therefore, distance D31 between dummy pattern 120A and first coil 45A in the z direction is greater than distance D12 between first coil 45A and second coil 46A. Distance D32 between dummy pattern 120B and substrate 84 in the z direction is equal to or greater than distance D12 between first coil 47A and second coil 48A in the z direction. In this embodiment, distance D32 is greater than distance D12.

[0224] Since the second coil 48A is disposed closer to the substrate 84 than the second coil 46A, the dummy pattern 120B is disposed closer to the substrate 84 than the dummy pattern 120A. Furthermore, since the second coil 48A is disposed farther from the substrate 84 than the first coil 45A, it can also be said that the dummy pattern 120B is disposed farther from the substrate 84 in the z direction than the first coil 45A. It can also be said that the dummy pattern 120B is disposed between the first coil 45A and the second coil 46A in the z direction.

[0225] The distance D15 between the first coil 45A and the second coil 48A is equal to or greater than the distance D32 between the dummy pattern 120B and the substrate 84 in the z direction. In this embodiment, the distance D15 is equal to the distance D32. Alternatively, the distance D15 may be equal to or greater than the distance D31 between the dummy pattern 120A and the first coil 45A in the z direction.

[0226] In this embodiment, the dummy pattern 120B is provided around the coil (second coil 48A) which is farther from the passivation layer 150 (chip main surface 80s) of the first coil 47A and the second coil 48A, but the position where the dummy pattern 120B is formed is not limited to this. For example, the dummy pattern 120B may be provided around the first coil 47A. In other words, the dummy pattern 120B may be provided around the coil (first coil 47A) which is closer to the passivation layer 150 (chip main surface 80s) of the first coil 47A and the second coil 48A.

[0227] A plurality of first electrode pads 81, a plurality of second electrode pads 82, and a plurality of connection wirings 83 are formed on an insulating layer 85 that is one layer below the uppermost insulating layer 85U among the plurality of insulating layers 85. Each connection wiring 83 is a wiring that connects the first transformer 43A (43B) and the second transformer 44A (44B) and is made of, for example, Al or Cu. Each connection wiring 83 is covered, for example, by the uppermost insulating layer 85U. Each first electrode pad 81 is arranged on the opposite side of the first transformer 43A from the second transformer 44A in the y direction. Each second electrode pad 82 is arranged on the opposite side of the second transformer 44A from the first transformer 43A in the y direction.

[0228] The multiple connection wirings 83 include a first connection wiring that connects the second coil 46A of the first transformer 43A and the first coil 47A of the second transformer 44A, and a second connection wiring that connects the second coil 46B of the first transformer 43B and the first coil 47B of the second transformer 44B. Therefore, compared to, for example, a configuration in which the second coil 46A and the first coil 47A are connected using a wire W and a configuration in which the second coil 46B and the first coil 47B are connected using a wire W, both the distance between the second coil 46A and the first coil 47A and the distance between the second coil 46B and the first coil 47B can be made smaller.

[0229] Similar to the first embodiment, a passivation layer 150, a low dielectric layer 160, and a resin layer 180 are laminated in this order on the uppermost insulating layer 85U. The passivation layer 150 is formed so as to cover all of the transformers 40A, 40B and the dummy patterns 120A, 120B in a planar view. As in the first embodiment, the low dielectric layer 160 is formed so as to cover the entire passivation layer 150 in a planar view. In other words, it can be said that the low dielectric layer 160 is formed so as to cover all of the transformers 40A, 40B, the dummy patterns 120A, 120B, and the connection wirings 83 in a planar view.

[0230] (Effects of the third embodiment) According to the gate driver 10 of this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0231] (3-1) The transformer 40A has a first transformer 43A and a second transformer 44A connected in series. The transformer 40B has a first transformer 43B and a second transformer 44B connected in series. With this configuration, the first transformer 43A and the second transformer 44A form a double-insulated structure between the low-voltage circuit 20 and the high-voltage circuit 30 on the signal line transmitting the set signal, and the first transformer 43B and the second transformer 44B form a double-insulated structure between the low-voltage circuit 20 and the high-voltage circuit 30 on the signal line transmitting the reset signal, thereby improving the withstand voltage of the gate driver 10.

[0232] [Fourth embodiment] A gate driver 10 of the third embodiment will be described with reference to Figures 14 and 15. The gate driver 10 of this embodiment differs from the gate driver 10 of the first embodiment in that the insulation structure using a transformer 40 has been changed to an insulation structure using a capacitor 50. In the following description, differences from the gate driver 10 of the first embodiment will be described in detail, and components common to the gate driver 10 of the first embodiment will be denoted by common reference numerals and will not be described again.

[0233] 14, as an insulating structure for electrically insulating the low-voltage circuit 20 and the high-voltage circuit 30, the capacitor 50 has a capacitor 50A connected to a signal line that transmits a set signal and a capacitor 50B connected to a signal line that transmits a reset signal. Both capacitors 50A and 50B are provided between the low-voltage circuit 20 and the high-voltage circuit 30.

[0234] Capacitor 50A has a first electrode plate 51A and a second electrode plate 52A, and capacitor 50B has a first electrode plate 51B and a second electrode plate 52B. The first electrode plate 51A of capacitor 50A is connected to low-voltage circuit 20 by low-voltage signal line 21A, and the second electrode plate 52A of capacitor 50A is connected to high-voltage circuit 30 by high-voltage signal line 31A. The first electrode plate 51B of capacitor 50B is connected to low-voltage circuit 20 by low-voltage signal line 21B, and the second electrode plate 52B of capacitor 50B is connected to high-voltage circuit 30 by high-voltage signal line 31B. In this way, the low-voltage circuit 20 and the high-voltage circuit 30 transmit a set signal via capacitor 50A, and transmit a reset signal via capacitor 50B.

[0235] In this embodiment, the gate driver 10 includes a low-voltage circuit chip 60, a capacitor chip 200 (see FIG. 15), and a high-voltage circuit chip 70 (see FIG. 2). Although not shown, both the low-voltage circuit chip 60 and the capacitor chip 200 are mounted on a low-voltage die pad 91 (see FIG. 15) of a low-voltage lead frame 90, and the high-voltage circuit chip 70 is mounted on a high-voltage die pad 101 (see FIG. 2) of a high-voltage lead frame 100. The layout of the low-voltage circuit chip 60, the capacitor chip 200, and the high-voltage circuit chip 70 is similar to the layout of the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70 in the first embodiment. That is, in this embodiment, the transformer chip 80 in the first embodiment is replaced with the capacitor chip 200.

[0236] 15, the capacitor chip 200 has a chip main surface 200s and a chip back surface 200r that face opposite to each other in the z direction. The chip back surface 200r of the capacitor chip 200 is bonded to the low-voltage die pad 91 by a conductive bonding material SD.

[0237] A plurality of first electrode pads 81 and a plurality of second electrode pads 82 are formed on the chip main surface 200s of the capacitor chip 200. Although not shown, the plurality of first electrode pads 81 are arranged at one of both ends in the y direction of the chip main surface 200s that is closer to the low-voltage circuit chip 60. The plurality of first electrode pads 81 are arranged in the x direction. The plurality of second electrode pads 82 are arranged at one of both ends in the y direction of the chip main surface 200s that is closer to the high-voltage circuit chip 70. The plurality of second electrode pads 82 are arranged in the x direction. In a plan view, the capacitors 50A and 50B are arranged between the plurality of first electrode pads 81 and the plurality of second electrode pads 82 in the y direction. The capacitors 50A and 50B are arranged aligned with each other in the y direction and spaced apart from each other in the x direction.

[0238] An example of the internal structure of the capacitor chip 200 will be described with reference to FIG. 15. FIG. 15 shows a schematic cross-sectional structure of a capacitor 50A. Note that since capacitor 50B has the same configuration as capacitor 50A, its description will be omitted. In the following description, the direction from the chip back surface 200r of the capacitor chip 200 toward the chip main surface 200s will be referred to as "upward," and the direction from the chip main surface 200s toward the chip back surface 200r will be referred to as "downward." Furthermore, in the capacitor chip 200, components common to those in the transformer chip 80 will be assigned common reference numerals, and their description will be omitted.

[0239] 15, first electrode plate 51A and second electrode plate 52A of capacitor 50A are disposed opposite each other in the z direction with insulating layer 85 interposed therebetween. Each of electrode plates 51A, 52A is configured as a conductive layer embedded in one insulating layer 85. That is, insulating layer 85 in which each of electrode plates 51A, 52A is embedded has openings formed therein that penetrate both first insulating layer 85A and second insulating layer 85B in the z direction. The conductive layers that constitute each of electrode plates 51A, 52A are embedded in the openings in insulating layer 85.

[0240] In the z direction, the second electrode plate 52A is located farther from the substrate 84 than the first electrode plate 51A. In other words, the second electrode plate 52A is located higher than the first electrode plate 51A. The first electrode plate 51A is connected to the first electrode pad 81 by a first connection wiring 131A. The second electrode plate 52A is connected to the second electrode pad 82 by a third connection wiring 133A.

[0241] As in the first embodiment, a passivation layer 150, a low dielectric layer 160, and a resin layer 180 are stacked in this order on the uppermost insulating layer 85U. The shapes of the passivation layer 150, the low dielectric layer 160, and the resin layer 180 are the same as in the first embodiment. As such, according to this embodiment, the same effects as in the first embodiment can be obtained.

[0242] [Example of change] The above embodiments are examples of possible forms of the isolation module and gate driver according to the present disclosure and are not intended to limit the forms. The isolation module and gate driver according to the present disclosure may take forms different from those illustrated in the above embodiments. Examples include forms in which part of the configuration of the above embodiments is replaced, modified, or omitted, or forms in which new configurations are added to the above embodiments. Furthermore, the following modified examples can be combined with each other as long as there is no technical contradiction. In the following modified examples, parts common to the above embodiments are assigned the same reference numerals as the above embodiments, and their description will be omitted.

[0243] In each embodiment, another insulating layer or low-dielectric layer may be interposed between the passivation layer 150 and the low-dielectric layer 160. In other words, the low-dielectric layer 160 may not be in contact with the passivation layer 150.

[0244] In the first to third embodiments, the resin layer 180 may be omitted from the transformer chip 80. This results in omitting the concave-convex structure 190 from the transformer chip 80. Similarly, in the fourth embodiment, the resin layer 180 may be omitted from the capacitor chip 200.

[0245] In each embodiment, the passivation layer 150 is not limited to a material containing silicon nitride, as long as it is a layer that can protect the insulating layer 85. However, the passivation layer 150 is made of a material with a higher dielectric constant than the low-k layer 160.

[0246] In each embodiment, the dielectric constant of the low-dielectric layer 160 may be higher than the dielectric constant of the molding resin 110 as long as it is lower than the dielectric constant of the passivation layer 150 . In the first and second embodiments, the arrangement of the transformers 40AA, 40AB, 40BA, and 40BB can be changed as desired. For example, the transformers 40AA, 40BA, 40AB, and 40BB may be arranged in this order from the chip side surface 80c toward the chip side surface 80d of the transformer chip 80.

[0247] In the first and second embodiments, the first dummy pattern 121 of the dummy pattern 120 is electrically connected to the second coil 42B. However, this is not limiting. For example, the first dummy pattern 121 may be provided independently of the second coils 42A and 42B. That is, the first dummy pattern 121 may not be electrically connected to the second coils 42A and 42B. Furthermore, in the first and second embodiments, the third dummy pattern 123 is electrically connected to the first dummy pattern 121. However, this is not limiting. For example, the third dummy pattern 123 may not be electrically connected to the first dummy pattern 121. The first transformer chip 80A may be configured so that a voltage higher than the voltage applied to the first coils 41A and 41B is applied to each of the dummy patterns 121 to 123. Note that the dummy patterns 120A and 120B of the third embodiment may also be modified in the same manner as the dummy pattern 120.

[0248] In the first to third embodiments, the configuration of the dummy patterns 120, 120A, and 120B can be changed as desired. For example, in the dummy patterns 120, 120A, and 120B, one or two of the first dummy pattern 121, the second dummy pattern 122, and the third dummy pattern 123 may be omitted. Furthermore, the dummy patterns 120, 120A, and 120B may be omitted from the transformer chip 80.

[0249] In the second embodiment, the first inner surface cover portion 165 of the low dielectric layer 160 may be spaced apart in the z direction from the first electrode pad 81. Furthermore, the second inner surface cover portion 166 of the low dielectric layer 160 may be spaced apart in the z direction from the second electrode pad 82.

[0250] In the second embodiment, the first inner surface cover portion 165 of the low dielectric layer 160 only needs to be formed on at least the first inner surface of the first protective layer opening 151 of the passivation layer 150, and does not need to be formed on, for example, the first inner surface of the first insulating layer opening 85Ua of the uppermost insulating layer 85U. Also, the second inner surface cover portion 166 of the low dielectric layer 160 only needs to be formed on at least the second inner surface of the second protective layer opening 152 of the passivation layer 150, and does not need to be formed on, for example, the second inner surface of the second insulating layer opening 85Ub of the uppermost insulating layer 85U.

[0251] In the second embodiment, one or two of the first inner cover portion 165, the second inner cover portion 166, and the outer surface cover portion 167 may be omitted from the low dielectric layer 160. In the third embodiment, the gate driver 10 may include a first transformer chip 80A and a second transformer chip 80B instead of the transformer chip 80. That is, as shown in FIG. 16 , the gate driver 10 includes a low-voltage circuit chip 60, a high-voltage circuit chip 70, a first transformer chip 80A, and a second transformer chip 80B. The low-voltage circuit chip 60, the high-voltage circuit chip 70, the first transformer chip 80A, and the second transformer chip 80B are arranged at a distance from each other in the y direction. It can also be said that these chips 60, 70, 80A, and 80B are arranged in the arrangement direction of the low-voltage die pad 91 and the high-voltage die pad 101.

[0252] In the illustrated example, the low-voltage circuit chip 60, the first transformer chip 80A, the second transformer chip 80B, and the high-voltage circuit chip 70 are arranged in this order from the low-voltage lead 92 toward the high-voltage lead 102. In other words, in a plan view, each of the transformer chips 80A and 80B is disposed between the low-voltage circuit chip 60 and the high-voltage circuit chip 70.

[0253] In the illustrated example, both the low-voltage circuit chip 60 and the first transformer chip 80A are mounted on a low-voltage die pad 91 of a low-voltage lead frame 90. Both the high-voltage circuit chip 70 and the second transformer chip 80B are mounted on a high-voltage die pad 101 of a high-voltage lead frame 100.

[0254] The first transformer chip 80A includes the first transformer 43A of the transformer 40A and the first transformer 43B of the transformer 40B, and more specifically, both transformers 43A and 43B are packaged together. In other words, the first transformer chip 80A includes one of the transformers 40A and 40B that is arranged closer to the low-voltage circuit 20 than the high-voltage circuit 30 in terms of the circuit.

[0255] The second transformer chip 80B includes the second transformer 44A of the transformer 40A and the second transformer 44B of the transformer 40B, and more specifically, both transformers 44A and 44B are packaged together. In other words, the second transformer chip 80B includes one of the transformers 40A and 40B that is arranged closer to the high-voltage circuit 30 than the low-voltage circuit 20 in terms of the circuit.

[0256] In the illustrated example, the configuration of the first transformer chip 80A is similar to that of the transformer chip 80 of the first embodiment. The second transformer chip 80B differs from the configuration of the transformer chip 80 of the first embodiment in the arrangement of the coils 47A, 47B, 48A, and 48B and the arrangement of the coils 47A, 47B, 48A, and 48B and the electrode pads 81 and 82.

[0257] More specifically, the multiple first electrode pads 81 of the second transformer chip 80B are arranged near the center in the y direction of the chip main surface 80s of the second transformer chip 80B. The multiple second electrode pads 82 of the second transformer chip 80B are arranged at one of both end portions in the y direction of the chip main surface 80s of the second transformer chip 80B that is closer to the high-voltage circuit chip 70.

[0258] Although not shown, in the second transformer chip 80B, the first coils 47A and 47B are arranged at positions farther from the substrate 84 than the second coils 48A and 48B. In other words, the second coils 48A and 48B are arranged closer to the substrate 84 than the first coils 47A and 47B. The first coils 47A and 47B are individually and electrically connected to the multiple first electrode pads 81 of the second transformer chip 80B. The second coils 48A and 48B are individually and electrically connected to the multiple second electrode pads 82 of the second transformer chip 80B.

[0259] The low-voltage circuit chip 60 and the first transformer chip 80A are connected by a wire W. More specifically, the second electrode pad 62 of the low-voltage circuit chip 60 and the first electrode pad 81 of the first transformer chip 80A are connected by the wire W. As a result, the low-voltage circuit 20 and the first coil 45A of the first transformer 43A (see FIG. 11) are electrically connected, and the low-voltage circuit 20 and the first coil 45B of the first transformer 43B (see FIG. 11) are electrically connected.

[0260] The first transformer chip 80A and the second transformer chip 80B are connected by a wire W. More specifically, the second electrode pad 82 of the first transformer chip 80A and the first electrode pad 81 of the second transformer chip 80B are connected by the wire W. This electrically connects the second coil 46A of the first transformer 43A to the first coil 47A of the second transformer 44A, and electrically connects the second coil 46B of the first transformer 43B to the first coil 47B of the second transformer 44B.

[0261] The second transformer chip 80B and the high-voltage circuit chip 70 are connected by a wire W. More specifically, the second electrode pad 82 of the second transformer chip 80B and the first electrode pad 71 of the high-voltage circuit chip 70 are connected by the wire W. This electrically connects the second coil 48A of the second transformer 44A (see FIG. 11) to the high-voltage circuit 30, and electrically connects the second coil 48B of the second transformer 44B (see FIG. 11) to the high-voltage circuit 30.

[0262] In the third and fourth embodiments, the shape of the low-dielectric layer 160 can be changed as desired. In one example, the low-dielectric layer 160 may have the same shape as the low-dielectric layer 160 in the second embodiment. In the first to third embodiments, the low-voltage circuit 20 and the transformer 40 are formed as separate chips, but this is not limiting. The transformer 40 and the low-voltage circuit 20 may be mounted on a single chip. This chip is covered with mold resin 110. Therefore, the low-dielectric layer 160 provided on the chip is covered with mold resin 110. In one example, the low-voltage circuit 20 may be formed on the substrate 84 of the transformer chip 80. The transformer chip 80 is covered with mold resin 110. Similarly, in the fourth embodiment, the capacitor 50 and the low-voltage circuit 20 may be mounted on a single chip. In other words, the insulating module and the low-voltage circuit 20 may be mounted on a single chip.

[0263] In the first to third embodiments, the high-voltage circuit 30 and the transformer 40 are formed as separate chips, but this is not limited to this. The transformer 40 and the high-voltage circuit 30 may be mounted on a single chip. This chip is covered with mold resin 110. Therefore, the low-dielectric layer 160 provided on the chip is covered with mold resin 110. In one example, the high-voltage circuit 30 may be formed on the substrate 84 of the transformer chip 80. In this case, the transformer chip 80 is mounted on the high-voltage die pad 101. The transformer chip 80 is covered with mold resin 110. Similarly, in the fourth embodiment, the capacitor 50 and the high-voltage circuit 30 may be mounted on a single chip. In other words, the insulating module and the high-voltage circuit 30 may be mounted on a single chip.

[0264] In the first to third embodiments, the gate driver 10 may include an insulating module that houses the transformer 40 in a single package. The insulating module includes a transformer chip 80 and a molded resin 110 that seals the transformer chip 80. The insulating module may further include a die pad on which the transformer chip 80 is mounted, multiple leads, and wires that connect the multiple leads to the transformer chip 80. The molded resin 110 seals at least the transformer chip 80, the die pad, and the wires. The multiple leads are electrically connectable to both the low-voltage circuit 20 and the high-voltage circuit 30. Similarly, in the fourth embodiment, the gate driver 10 may include an insulating module that houses the capacitor 50 in a single package. That is, the insulating module includes an insulating chip and a molded resin that seals the insulating chip. This insulating module is used to insulate the low-voltage circuit 20 and the high-voltage circuit 30 included in the gate driver 10.

[0265] In the first to third embodiments, the gate driver 10 may include a low-voltage circuit unit that houses the low-voltage circuit 20 and the transformer 40 in a single package. The low-voltage circuit unit may include a low-voltage circuit chip 60, a transformer chip 80, and a molding resin 110 that seals the low-voltage circuit chip 60 and the transformer chip 80. The low-voltage circuit unit may further include a die pad, a plurality of first leads, first wires that connect the plurality of first leads to the low-voltage circuit chip 60, a plurality of second leads, and second wires that connect the plurality of second leads to the transformer chip 80. The molding resin 110 seals at least the low-voltage circuit chip 60, the transformer chip 80, the die pad, and each wire. The plurality of first leads can be electrically connected to, for example, the ECU 503, and the plurality of second leads can be electrically connected to the high-voltage circuit 30. Similarly, in the fourth embodiment, the gate driver 10 may include a low-voltage circuit unit that houses the low-voltage circuit 20 and the capacitor 50 in a single package. That is, the low-voltage circuit unit may include a low-voltage circuit chip 60, an insulating module, and a mold resin 110 that seals both the low-voltage circuit chip 60 and the insulating module.

[0266] In the first to third embodiments, the gate driver 10 may include a high-voltage circuit unit in which the high-voltage circuit 30 and the transformer 40 are housed in a single package. The high-voltage circuit unit may include a high-voltage circuit chip 70, a transformer chip 80, and a molded resin 110 that seals both the high-voltage circuit chip 70 and the transformer chip 80. The high-voltage circuit unit may further include a die pad, multiple first leads, first wires connecting the multiple first leads to the high-voltage circuit chip 70, multiple second leads, and second wires connecting the multiple second leads to the transformer chip 80. The molded resin 110 seals at least the high-voltage circuit chip 70, the transformer chip 80, the die pad, and each wire. The multiple first leads can be electrically connected to the source of the switching element 501, for example, and the multiple second leads can be electrically connected to the low-voltage circuit 20. Similarly, in the fourth embodiment, the gate driver 10 may include a high-voltage circuit unit in which the high-voltage circuit 30 and the capacitor 50 are housed in a single package. That is, the high-voltage circuit unit only needs to include the high-voltage circuit chip 70, the insulating module, and the mold resin 110 that seals both the high-voltage circuit chip 70 and the insulating module.

[0267] In each embodiment, the gate driver 10 may transmit a signal from the high-voltage circuit 30 to the low-voltage circuit 20 via an insulating module. As an example, a configuration will be described in which a signal path for transmitting a signal from the high-voltage circuit 30 to the low-voltage circuit 20 is added to the gate driver 10 of the first embodiment, as shown in Fig. 17 .

[0268] As shown in FIG. 17, the gate driver 10 includes a transformer 40C for transmitting a signal from the high-voltage circuit 30 to the low-voltage circuit 20. The transformer 40C transmits a signal from the high-voltage circuit 30 to the low-voltage circuit 20, while insulating the high-voltage circuit 30 from the low-voltage circuit 20. This signal is, for example, an abnormality detection signal that is output when an abnormality in the switching element 501 is detected. Examples of abnormalities in the switching element 501 include an abnormality in which the temperature of the switching element 501 rises excessively (temperature abnormality), an abnormality in which an excessively large current flows through the switching element 501 (overcurrent), and an abnormality in which an excessively high voltage is applied to the switching element 501 (overvoltage). In other words, when an abnormal temperature, overcurrent, overvoltage, or the like is detected in the switching element 501, the gate driver 10 transmits an abnormality detection signal from the high-voltage circuit 30 to the low-voltage circuit 20 via the transformer 40C.

[0269] The transformer 40C has the same configuration as the transformers 40A and 40B, and includes a first coil 41C and a second coil 42C. The first coil 41C is connected to a low-voltage signal line 21C connected to the low-voltage circuit 20, and is also connected to the ground of the low-voltage circuit 20. The second coil 42C is connected to a high-voltage signal line 31C connected to the high-voltage circuit 30, and is also connected to the ground of the high-voltage circuit 30. A signal output from the high-voltage circuit 30 is transmitted to the low-voltage circuit 20 via the transformer 40C.

[0270] 17, signals are transmitted in both directions between the low-voltage circuit 20 and the high-voltage circuit 30. These signals include a first signal transmitted from the low-voltage circuit 20 to the high-voltage circuit 30, and a second signal transmitted from the high-voltage circuit 30 to the low-voltage circuit 20. The first signal is transmitted from the low-voltage circuit 20 to the high-voltage circuit 30 via the first coil 41A (41B) and then the second coil 42A (42B). The second signal is transmitted from the high-voltage circuit 30 to the low-voltage circuit 20 via the second coil 42C and then the first coil 41C.

[0271] The term "on" used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Therefore, the expression "A is formed on B" is intended to mean that, in this embodiment, A may be in contact with B and disposed directly on B, but as a variant, A may be disposed above B without contacting B. In other words, the term "on" does not exclude a structure in which another member is formed between A and B.

[0272] The z-direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the z-direction described herein being "up" and "down" of the vertical direction. For example, the x-direction may be the vertical direction, or the y-direction may be the vertical direction.

[0273] The statement "at least one of A and B" in this specification should be understood to mean "A only, or B only, or both A and B." [Note] The technical ideas that can be understood from the above-described embodiments and modified examples are described below. Note that the reference numerals of the components of the embodiments corresponding to the components described in each appendix are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0274] (Appendix 1) First conductors (41A, 41B / 51A, 51B) and second conductors (42A, 42B / 52A, 52B) embedded in an insulating layer (85) and arranged opposite to each other with a gap in the thickness direction (z direction) of the insulating layer (85); a first electrode (81) connected to the first conductor (41A, 41B / 51A, 51B); a second electrode (82) provided at a position spaced apart from the first electrode (81) when viewed from the thickness direction (z direction) of the insulating layer (85) and connected to the second conductors (42A, 42B / 52A, 52B); a passivation layer (150) formed on the surface (85s) of the insulating layer (85); a low dielectric layer (160) formed on the surface (150s) of the passivation layer (150) and having a dielectric constant lower than that of the passivation layer (150); and a molding compound (110) covering the low dielectric layer (160).

[0275] (Appendix 2) The passivation layer (150) is formed from a material including silicon nitride. 1. An isolation module as defined in claim 1.

[0276] (Appendix 3) The dielectric constant of the low dielectric layer (160) is equal to or lower than the dielectric constant of the molding resin (110). 1. An isolation module as defined in claim 1 or 2.

[0277] (Appendix 4) The thickness (TE) of the low dielectric layer (160) is equal to or less than the thickness (TP) of the passivation layer (150). 4. The insulating module according to any one of claims 1 to 3.

[0278] (Appendix 5) a first opening (171) penetrating both the passivation layer (150) and the low dielectric layer (160) is formed at a position in the passivation layer (150) and the low dielectric layer (160) that overlaps with the first electrode (81) when viewed in the thickness direction (z direction) of the insulating layer (85); a second opening (172) penetrating both the passivation layer (150) and the low dielectric layer (160) is formed at a position in the passivation layer (150) and the low dielectric layer (160) that overlaps with the second electrode (82) when viewed in the thickness direction (z direction) of the insulating layer (85); The molding resin (110) is in contact with the first electrode (81) through the first opening (171) and is in contact with the second electrode (82) through the second opening (172). 5. The insulating module according to any one of claims 1 to 4.

[0279] (Appendix 6) a first opening (171) penetrating the passivation layer (150) is formed at a position in the passivation layer (150) that overlaps with the first electrode (81) when viewed from the thickness direction (z direction) of the insulating layer (85); a second opening (172) penetrating the passivation layer (150) is formed at a position in the passivation layer (150) that overlaps with the second electrode (82) when viewed from the thickness direction (z direction) of the insulating layer (85); The low dielectric layer (160 / 165, 166) is formed on both a first inner surface constituting the first opening (171) and a second inner surface constituting the second opening (172), The low dielectric layer (160 / 167) covers the edge of the passivation layer (150). 5. The insulating module according to any one of claims 1 to 4.

[0280] (Appendix 7) a resin layer (180) having a groove (183) exposing the surface (160s) of the low dielectric layer (160) is provided on the surface (160s) of the low dielectric layer (160); The region between the first electrode (81) and the second electrode (82) on the surface (160s) of the low dielectric layer (160) is provided with an uneven structure (190) formed by the bonding surface between the mold resin (110) and the resin layer (180) and the bonding surface between the mold resin (110) and the low dielectric layer (160). 7. The insulating module according to any one of appendices 1 to 6.

[0281] (Appendix 8) the first conductor is a first coil (41A, 41B), the second conductor is a second coil (42A, 42B), The first coils (41A, 41B) and the second coils (42A, 42B) constitute a transformer (40 / 40A, 40B). An insulating module according to any one of appendices 1 to 7.

[0282] (Appendix 9) A dummy pattern (120) is provided around the coil (42A, 42B) of the first coil (41A, 41B) and the second coil (42A, 42B) that is arranged near the passivation layer (150). 10. The isolation module of claim 9.

[0283] (Appendix 10) the first conductor is a first electrode plate (51A, 51B), the second conductor is a second electrode plate (52A, 52B), The first electrode plates (51A, 51B) and the second electrode plates (52A, 52B) form a capacitor (50 / 50A, 50B). An insulating module according to any one of appendices 1 to 7.

[0284] (Appendix 11) A gate driver (10) that applies a drive voltage signal to the gate of a switching element (501), a low-voltage circuit (20) configured to operate when a first voltage (V1) is applied; a high-voltage circuit (30) configured to operate when a second voltage (V2) higher than the first voltage (V1) is applied; an insulating module (80, 110); the low-voltage circuit (20) and the high-voltage circuit (30) are connected via the insulating module (80, 110) and are configured to transmit signals via the insulating module (80, 110); The insulating module (80, 110) First conductors (41A, 41B / 51A, 51B) and second conductors (42A, 42B / 51A, 51B) embedded in an insulating layer (85) and arranged opposite to each other with a gap in the thickness direction (z direction) of the insulating layer (85); a first electrode (81) connected to the first conductor (41A, 41B / 51A, 51B); a second electrode (82) provided at a position spaced apart from the first electrode (81) when viewed from the thickness direction (z direction) of the insulating layer (85) and connected to the second conductors (42A, 42B / 52A, 52B); a passivation layer (150) formed on the surface (85s) of the insulating layer (85) to protect the insulating layer (85); a low dielectric layer (160) formed on the surface (150s) of the passivation layer (150) and having a dielectric constant lower than that of the passivation layer (150); a molding compound (110) that covers the low dielectric layer (160).

[0285] (Appendix 12) the signal includes a first signal; the first signal output from the low-voltage circuit (20) is transmitted to the high-voltage circuit (30) via the insulating module (80, 110); The high-voltage circuit (30) generates the drive voltage signal based on the first signal from the low-voltage circuit (20). 12. The gate driver of claim 11.

[0286] (Appendix 13) the signal includes a second signal; The second signal output from the high-voltage circuit (30) is transmitted to the low-voltage circuit (20) via the insulating module (80, 110). 13. The gate driver of claim 12.

[0287] (Appendix 14) The insulating module (80, 110) and the low-voltage circuit (20) are mounted on a single chip. 14. The gate driver according to any one of claims 11 to 13.

[0288] (Appendix 15) The insulating module (80, 110) and the high-voltage circuit (30) are mounted on a single chip. 14. The gate driver according to any one of claims 11 to 13.

[0289] (Appendix 16) the transformer (40 / 40A, 40B) includes a first transformer (43A, 43B) and a second transformer (44A, 44B) connected in series with each other; the first transformers (43A, 43B) are connected to the low-voltage circuit (20); The second transformers (44A, 44B) are connected to both the first transformers (43A, 43B) and the high-voltage circuit (30). 10. The isolation module of claim 8. [Explanation of symbols]

[0290] 10...Gate driver 20...Low voltage circuit 30...High voltage circuit 40, 40A, 40B, 40AA, 40AB, 40BA, 40BB, 40C...transformers 41A, 41B...First coil (first conductor) 42A, 42B...Second coil (second conductor) 43A, 43B...First transformer 44A, 44B...Second transformer 45A, 45B, 47A, 47B...First coil (first conductor) 46A, 46B, 48A, 48B...Second coil (second conductor) 80...Transformer chip 50, 50A, 50B...capacitors 51A, 51B...First electrode plate (first conductor) 52A, 52B...Second electrode plate (second conductor) 81, 81A to 81F...First electrode pads (first electrodes) 82, 82A to 82F...Second electrode pads (second electrodes) 85...insulating layer 85s…Surface 110...Mold resin 120, 120A, 120B...Dummy patterns 150...passivation layer 150s…Surface 160...Low dielectric layer 160s…Surface 171...First opening 172...Second opening 180...Resin layer 190…Uneven structure 200...Capacitor chip 501, 502...Switching elements

Claims

1. a first conductor and a second conductor embedded in an insulating layer and disposed opposite to each other and spaced apart in a thickness direction of the insulating layer; a first electrode connected to the first conductor; a second electrode provided at a position spaced apart from the first electrode when viewed in a thickness direction of the insulating layer and connected to the second conductor; a passivation layer formed on the surface of the insulating layer; a low-k layer formed on a surface of the passivation layer and having a dielectric constant lower than that of the passivation layer; a resin layer formed on the surface of the low dielectric layer; a molding resin covering the low dielectric layer and the resin layer; Equipped with a first opening penetrating through both the passivation layer and the low dielectric layer is formed at a position in the passivation layer and the low dielectric layer that overlaps with the first electrode when viewed in a thickness direction of the insulating layer; a second opening portion that penetrates both the passivation layer and the low dielectric layer is formed at a position in the passivation layer and the low dielectric layer that overlaps with the second electrode when viewed in a thickness direction of the insulating layer; the low dielectric layer includes a first region that is disposed at a position spaced apart from the first opening and in which the resin layer and the molding resin are disposed in this order in a thickness direction of the insulating layer, and a second region that is located between the first opening and the first region and is directly covered by the molding resin; the low dielectric layer includes a third region that is disposed at a position spaced apart from the second opening and in which the resin layer and the molding resin are disposed in this order in the thickness direction of the insulating layer, and a fourth region that is located between the second opening and the third region and is directly covered by the molding resin. Isolation module.

2. The passivation layer is formed from a material including silicon nitride. The isolation module of claim 1 .

3. The dielectric constant of the low dielectric layer is equal to or lower than the dielectric constant of the molding resin. The insulating module according to claim 1 or 2.

4. The thickness of the low dielectric layer is equal to or less than the thickness of the passivation layer. The insulating module according to any one of claims 1 to 3.

5. The molded resin contacts the first electrode through the first opening and contacts the second electrode through the second opening. The insulating module according to any one of claims 1 to 4.

6. The low dielectric layer is formed on both a first inner surface constituting the first opening and a second inner surface constituting the second opening, The low-dielectric layer covers the end surface of the passivation layer. The insulating module according to any one of claims 1 to 4.

7. a resin layer having a groove exposing the surface of the low dielectric layer is provided on the surface of the low dielectric layer; In a region between the first electrode and the second electrode on the surface of the low dielectric layer, an uneven structure is provided which is formed by a bonding surface between the molding resin and the resin layer and a bonding surface between the molding resin and the low dielectric layer. The insulating module according to any one of claims 1 to 6.

8. the first conductor is a first coil, the second conductor is a second coil, The first coil and the second coil form a transformer. The insulating module according to any one of claims 1 to 7.

9. A dummy pattern is provided around the coil of the first coil and the second coil that is disposed near the passivation layer. The isolation module of claim 8 .

10. the first conductor is a first electrode plate; the second conductor is a second electrode plate; The first electrode plate and the second electrode plate form a capacitor. The insulating module according to any one of claims 1 to 7.

11. A gate driver that applies a drive voltage signal to a gate of a switching element, a low-voltage circuit configured to operate when a first voltage is applied; a high-voltage circuit configured to operate when a second voltage higher than the first voltage is applied; an isolation module; Equipped with the low-voltage circuit and the high-voltage circuit are connected via the isolation module and configured to transmit signals via the isolation module; The insulation module includes: a first conductor and a second conductor embedded in an insulating layer and disposed opposite to each other and spaced apart in a thickness direction of the insulating layer; a first electrode connected to the first conductor; a second electrode provided at a position spaced apart from the first electrode when viewed in a thickness direction of the insulating layer and connected to the second conductor; a passivation layer formed on the surface of the insulating layer to protect the insulating layer; a low-k layer formed on a surface of the passivation layer and having a dielectric constant lower than that of the passivation layer; a resin layer formed on the surface of the low dielectric layer; a molding resin covering the low dielectric layer and the resin layer; Equipped with a first opening penetrating through both the passivation layer and the low dielectric layer is formed at a position in the passivation layer and the low dielectric layer that overlaps with the first electrode when viewed in a thickness direction of the insulating layer; a second opening portion that penetrates both the passivation layer and the low dielectric layer is formed at a position in the passivation layer and the low dielectric layer that overlaps with the second electrode when viewed in a thickness direction of the insulating layer; the low dielectric layer includes a first region that is disposed at a position spaced apart from the first opening and in which the resin layer and the molding resin are disposed in this order in a thickness direction of the insulating layer, and a second region that is located between the first opening and the first region and is directly covered by the molding resin; the low dielectric layer includes a third region that is disposed at a position spaced apart from the second opening and in which the resin layer and the molding resin are disposed in this order in the thickness direction of the insulating layer, and a fourth region that is located between the second opening and the third region and is directly covered by the molding resin. Gate driver.

12. the signal includes a first signal; The first signal output from the low-voltage circuit is is transmitted to the high-voltage circuit via The high-voltage circuit generates the drive voltage signal based on the first signal from the low-voltage circuit. The gate driver of claim 11 .

13. the signal includes a second signal; The second signal output from the high-voltage circuit is transmitted to the low-voltage circuit via the isolation module. The gate driver of claim 12 .

14. The isolation module and the low-voltage circuit are mounted on a single chip. The gate driver according to any one of claims 11 to 13.

15. The isolation module and the high-voltage circuit are mounted on a single chip. The gate driver according to any one of claims 11 to 13.

16. A first conductor and a second conductor embedded in an insulating layer and arranged opposite each other and spaced apart in the thickness direction of the insulating layer; a first electrode connected to the first conductor; a second electrode provided at a position spaced apart from the first electrode when viewed in a thickness direction of the insulating layer and connected to the second conductor; a three-layer laminate including at least a silicon oxide layer and a silicon nitride layer formed on the surface of the insulating layer so as to cover the insulating layer; a resin layer formed on the surface of the laminate; a molding resin formed on the surface of the resin layer; Equipped with a first opening penetrating the laminate is formed at a position overlapping the first electrode when viewed from a thickness direction of the insulating layer; a second opening portion that penetrates the laminate body and is formed at a position that overlaps the second electrode when viewed from the thickness direction of the insulating layer; an outer periphery of the first electrode and an outer periphery of the second electrode are inclined with respect to a thickness direction of the insulating layer, the laminate includes a first raised portion covering the outer periphery of the first electrode and a second raised portion covering the outer periphery of the second electrode, the first raised portion and the second raised portion are exposed from the resin layer. Isolation module.

17. A first conductor and a second conductor embedded in an insulating layer and arranged opposite each other and spaced apart in the thickness direction of the insulating layer; a first electrode connected to the first conductor; a second electrode provided at a position spaced apart from the first electrode when viewed in a thickness direction of the insulating layer and connected to the second conductor; a passivation layer formed on the surface of the insulating layer; a low-k layer formed on a surface of the passivation layer and having a dielectric constant lower than that of the passivation layer; a molding resin covering the low dielectric layer; Equipped with the thickness of the low dielectric layer is equal to or less than the thickness of the passivation layer; Isolation module.

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