Switching control device, switching power supply device and power supply system

Abstract

The switching control device according to one embodiment of the present invention is applied to a switching power supply device and is provided with a control circuit for controlling each of the switching operations of a plurality of switching elements included in at least either an inverter circuit or a rectifying / smoothing circuit. The control circuit sets, on the basis of the detection result of the current flowing through the capacitance component between the gate and drain of a first switching element in an OFF-state among the plurality of switching elements, a timing at which the first switching element switches from the OFF-state to an ON-state after a second switching element among the plurality of switching elements switches from the ON-state to the OFF-state and makes the transition to a delay time.

Description

[Technical Field]

[0001] The present invention relates to a switching power supply device that performs voltage conversion using a switching element, a switching control device applied to such a switching power supply device, and a power supply system equipped with such a switching power supply device. [Background technology]

[0002] Various DC-DC converters have been proposed and put into practical use as examples of switching power supply devices (see, for example, Patent Document 1). This type of DC-DC converter generally includes an inverter circuit including a switching element, a power conversion transformer, and a rectifying and smoothing circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4929856 Summary of the Invention

[0004] However, in switching power supply devices such as DC-DC converters, it is generally required to reduce power loss (to achieve high efficiency). It is desirable to provide a switching control device, a switching power supply device, and a power supply system that can reduce power loss.

[0005] A switching control device according to one embodiment of the present invention is a control device applied to a switching power supply device including a transformer having a primary winding and a secondary winding, an inverter circuit arranged between an input terminal pair to which an input voltage is input and the primary winding, and a rectifying and smoothing circuit arranged between an output terminal pair to which an output voltage is output and the secondary winding, and includes a control circuit that controls the switching operations of a plurality of switching elements included in at least one of the inverter circuit and the rectifying and smoothing circuit. The control circuit controls a current flowing through a gate-drain capacitance component of a first switching element in an off state among the plurality of switching elements. Using detection timing After a second switching element among the plurality of switching elements is switched from an on state to an off state and a delay time is entered, Before the voltage between the source and drain of the first switching element reaches its lowest point, the event of the voltage reaching its lowest point is detected, and at the time when this event is detected, The timing at which the first switching element switches from an OFF state to an ON state is set.

[0006] A switching power supply device according to one embodiment of the present invention includes the input terminal pair, the output terminal pair, the transformer, the inverter circuit, the rectifying and smoothing circuit, and the switching control device according to the embodiment of the present invention.

[0007] A power supply system according to an embodiment of the present invention includes the switching power supply device according to the embodiment of the present invention described above, and a power supply that supplies the input voltage to the input terminal pair.

[0008] According to the switching control device, switching power supply device, and power supply system according to an embodiment of the present invention, it is possible to reduce power loss. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a circuit diagram illustrating a schematic configuration example of a switching power supply device according to an embodiment of the present invention. [Figure 2] 2 is a circuit diagram illustrating a detailed configuration example of a control circuit shown in FIG. 1. [Figure 3] 2 is a timing chart illustrating an example of the operation of the switching power supply device shown in FIG. [Figure 4] FIG. 10 is a diagram illustrating an example of conduction characteristics of a transistor. [Figure 5] FIG. 10 is a timing diagram for explaining a dead time in an ideal state. [Figure 6] FIG. 10 is a timing diagram for explaining a dead time when a circuit delay time occurs. [Figure 7] 5A to 5C are timing diagrams illustrating examples of waveforms of detection currents and the like according to the embodiment. [Figure 8] 8 is a timing chart showing an enlarged view of a portion of the waveform example shown in FIG. 7. [Figure 9] FIG. 4 is a timing diagram illustrating an example of control of a switching operation according to an embodiment. [Figure 10] 10 is a circuit diagram illustrating an example of the configuration of a control circuit according to Modification 1. FIG. [Figure 11] 10 is a circuit diagram illustrating an example of the configuration of a control circuit according to Modification 2. FIG. [Figure 12] 10 is a circuit diagram illustrating an example of the configuration of a control circuit according to Modification 3. FIG. [Figure 13] 10 is a timing diagram illustrating an example of waveforms of a detected voltage and the like according to Modification 3. FIG. [Figure 14] 10 is a timing diagram schematically illustrating an example of control of a switching operation according to Modification 4. FIG. [Figure 15] FIG. 11 is a circuit diagram illustrating a schematic configuration example of a switching power supply device according to Modification 5. [Figure 16] FIG. 13 is a circuit diagram illustrating a schematic configuration example of a switching power supply device according to a sixth modification. [Figure 17] FIG. 13 is a circuit diagram illustrating a schematic configuration example of a switching power supply device according to a seventh modification. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The description will be made in the following order: 1. Embodiment (Example of using a center-tap rectifier circuit) 2. Variations Modification 1 (another circuit configuration example of the gate drive circuit in the control circuit) Modifications 2 and 3 (Examples of indirect detection of detection current) Modification 4 (Example of Switchable Control Method for Switching Operation) Modification 5 (Example of using a bridge-type rectifier circuit) Modifications 6 and 7 (Examples of Synchronous Rectification Circuits) 3. Other Modifications

[0011] <1. Embodiment> [composition] FIG. 1 is a circuit diagram showing an example of the schematic configuration of a switching power supply (switching power supply 1) according to an embodiment of the present invention. This switching power supply 1 functions as a DC-DC converter that converts a DC input voltage Vin supplied from a DC input power source 10 (e.g., a battery) into a DC output voltage Vout and supplies power to a load 9. Examples of this load 9 include an electronic device and a battery. As will be described below, this switching power supply 1 is a so-called "(isolated half-bridge) LLC resonant type" DC-DC converter. The voltage conversion mode in switching power supply 1 may be either up-conversion (step-up) or down-conversion (step-down).

[0012] Here, the DC input voltage Vin corresponds to a specific example of the "input voltage" in the present invention, and the DC output voltage Vout corresponds to a specific example of the "output voltage" in the present invention. Furthermore, the DC input power supply 10 corresponds to a specific example of the "power supply" in the present invention, and a system including this DC input power supply 10 and the switching power supply device 1 corresponds to a specific example of the "power supply system" in the present invention.

[0013] The switching power supply 1 includes two input terminals T1 and T2, two output terminals T3 and T4, an inverter circuit 2, a transformer 3, a rectifying and smoothing circuit 4, and a control circuit 7. A DC input voltage Vin is input between the input terminals T1 and T2, and a DC output voltage Vout is output between the output terminals T3 and T4. In the example shown in Fig. 1, the primary-side low-voltage line L1L is connected to ground GND.

[0014] Here, the input terminals T1 and T2 correspond to a specific example of an "input terminal pair" in the present invention, and the output terminals T3 and T4 correspond to a specific example of an "output terminal pair" in the present invention. Also, the control circuit 7 corresponds to a specific example of a "switching control device" in the present invention.

[0015] Note that, for example, an input smoothing capacitor may be arranged between the primary-side high-voltage line L1H connected to the input terminal T1 and the primary-side low-voltage line L1L connected to the input terminal T2. Specifically, at a position between the inverter circuit 2 (described later) and the input terminals T1 and T2, a first end (one end) of the input smoothing capacitor may be connected to the primary-side high-voltage line L1H, and a second end (the other end) of the input smoothing capacitor may be connected to the primary-side low-voltage line L1L. Such an input smoothing capacitor is a capacitor for smoothing the DC input voltage Vin input from the input terminals T1 and T2.

[0016] (A. Inverter circuit 2) The inverter circuit 2 is disposed between input terminals T1, T2 and a primary winding 31 of a transformer 3, which will be described later. The inverter circuit 2 includes two switching elements S1, S2, a resonant inductor Lr, and a resonant capacitor Cr, and is a so-called "half-bridge" inverter circuit. The resonant inductor Lr may be formed by a leakage inductance in the transformer 3, which will be described later, or may be provided separately from such a leakage inductance.

[0017] Here, the above-described switching elements S1 and S2 each correspond to a specific example of "plurality of switching elements" in the present invention. Furthermore, switching element S2 corresponds to a specific example of "first switching element" in the present invention, and switching element S1 corresponds to a specific example of "second switching element" in the present invention.

[0018] As the switching elements S1 and S2, various switching elements are used, such as a field effect transistor (MOS-FET; Metal Oxide Semiconductor-Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), a HEMT (High Electron Mobility Transistor) = HFET (Heterostructure Field-Effect Transistor), etc. An example of a HEMT is a GaN (gallium nitride) transistor.

[0019] In the example shown in Fig. 1, the switching elements S1 and S2 are each configured with a transistor made of a MOS-FET or a HEMT. In this way, when a MOS-FET or a HEMT is used as the switching elements S1 and S2, the capacitor and diode (not shown in Fig. 1) connected in parallel to each switching element S1 and S2 can be configured with the parasitic capacitance or parasitic diode of the MOS-FET or HEMT, respectively.

[0020] In this inverter circuit 2, two switching elements S1 and S2 are connected in series in this order between input terminals T1 and T2 (between the primary high-voltage line L1H and the primary low-voltage line L1L). Specifically, the switching element S1 is arranged between the primary high-voltage line L1H and a connection point P1, and the switching element S2 is arranged between the connection point P1 and the primary low-voltage line L1L.

[0021] Furthermore, the resonant inductor Lr and resonant capacitor Cr in the inverter circuit 2 and a primary winding 31 in the transformer 3, which will be described later, are connected in series with each other between the connection point P1 and the primary low-voltage line L1L. Specifically, in the example of Fig. 1, a first end (one end) of the resonant capacitor Cr is connected to the connection point P1, and a second end (the other end) of the resonant capacitor Cr is connected to a first end (one end) of the resonant inductor Lr. Furthermore, the second end (the other end) of the resonant inductor Lr is connected to one end of the primary winding 31, and the other end of the primary winding 31 is connected to the primary low-voltage line L1L.

[0022] In the inverter circuit 2 configured as described above, the switching elements S1 and S2 perform switching operations (ON / OFF operations) in accordance with drive signals SG1 and SG2 supplied from a drive circuit 5 in a control circuit 7, which will be described later, to achieve the following: That is, the DC input voltage Vin applied between the input terminals T1 and T2 is converted into an AC voltage and output to the transformer 3 (primary winding 31).

[0023] (B.Trans 3) The transformer 3 has one primary winding 31 and two secondary windings 321 and 322.

[0024] In the primary winding 31, a first end (one end) of the primary winding 31 is connected to a second end (other end) of the above-mentioned resonant inductor Lr, and a second end (other end) of the primary winding 31 is connected to the above-mentioned primary low-voltage line L1L.

[0025] In the secondary winding 321, a first end of the secondary winding 321 is connected to the cathode of a rectifier diode 41 (described later) via a connection line L21 (described later), and a second end of the secondary winding 321 is connected to a center tap P6 in the rectifier smoothing circuit 4 (described later). In the secondary winding 322, a first end of the secondary winding 322 is connected to the cathode of a rectifier diode 42 (described later) via a connection line L22 (described later), and a second end of the secondary winding 322 is connected to the center tap P6. In other words, the second ends of the secondary windings 321 and 322 are commonly connected to the center tap P6.

[0026] The transformer 3 converts the voltage generated by the inverter circuit 2 (a rectangular pulse wave voltage input to the primary winding 31 of the transformer 3) and outputs an AC voltage from each end of the secondary windings 321, 322. In this case, the degree of voltage conversion of the DC output voltage Vout relative to the DC input voltage Vin is determined by the turns ratio between the primary winding 31 and the secondary windings 321, 322 and the switching period Tsw (switching frequency fsw=1 / Tsw) described later.

[0027] (C. Rectifier smoothing circuit 4) The rectifying and smoothing circuit 4 has two rectifying diodes 41 and 42 and one output smoothing capacitor Cout. Specifically, the rectifying and smoothing circuit 4 includes a rectifying circuit having the rectifying diodes 41 and 42, and a smoothing circuit having the output smoothing capacitor Cout.

[0028] The above-described rectifier circuit is a so-called "center-tapped" rectifier circuit. That is, the anodes of rectifier diodes 41 and 42 are each connected to the ground line LG, the cathode of rectifier diode 41 is connected to the first end of secondary winding 321 via connection line L21, and the cathode of rectifier diode 42 is connected to the first end of secondary winding 322 via connection line L22. As described above, the second ends of secondary windings 321 and 322 are commonly connected to center tap P6, which is connected to output terminal T3 via output line LO. The ground line LG is connected to output terminal T4.

[0029] In the smoothing circuit described above, an output smoothing capacitor Cout is connected between the output line LO and the ground line LG (between the output terminals T3 and T4). That is, a first terminal of the output smoothing capacitor Cout is connected to the output line LO, and a second terminal of the output smoothing capacitor Cout is connected to the ground line LG.

[0030] In the rectifying / smoothing circuit 4 configured as described above, a rectifying circuit including rectifying diodes 41 and 42 rectifies and outputs the AC voltage output from the transformer 3. Furthermore, a smoothing circuit including an output smoothing capacitor Cout smoothes the voltage rectified by the rectifying circuit to generate a DC output voltage Vout. The DC output current Iout (load current) flows to the load 9 described above due to the DC output voltage Vout generated in this manner, and power is supplied to the load 9 from the output terminals T3 and T4.

[0031] (D. Control circuit 7) The control circuit 7 is a circuit that controls the switching power supply device 1. As shown in Fig. 1, the control circuit 7 has a current detector 6 that detects a current Igd2 (detected current) that will be described later.

[0032] 2 is a circuit diagram showing a detailed configuration example of the control circuit 7 together with the inverter circuit 2. As shown in FIG. 2, the control circuit 7 has a drive circuit 5 including two gate drive circuits 51 and 52. The above-mentioned current detector 6 is disposed within the gate drive circuit 52.

[0033] FIG. 3 is a timing diagram showing an example of the operation of the switching power supply 1 (examples of waveforms of various voltages and currents). Specifically, FIG. 3(A) shows an example waveform of the drive signal SG1 (the gate-source voltage Vgs1 of the switching element S1; shown in FIG. 1), and FIG. 3(B) shows an example waveform of the drive signal SG2 (the gate-source voltage Vgs2 of the switching element S2; shown in FIG. 1). Also, FIG. 3(C) shows an example waveform of the drain-source voltage Vds2 (shown in FIG. 1) of the switching element S2, and FIG. 3(D) shows an example waveform of the drain-source current Ids2 (shown in FIG. 1) of the switching element S2. In FIG. 3, the horizontal axis represents time t, and this also applies to the subsequent timing diagrams. Also shown in FIG. 3 is the switching period Tsw (=1 / fsw) of the switching power supply 1.

[0034] The above-mentioned drive circuit 5 (gate drive circuits 51, 52) and current detector 6 will be described in detail below with reference to FIGS.

[0035] 1 and 2, the drive circuit 5 is a circuit that performs switching drive and controls the operations of the switching elements S1 and S2 in the inverter circuit 2. Specifically, the drive circuit 5 controls the switching operations (on / off operations) of the switching elements S1 and S2 by individually supplying drive signals SG1 and SG2 to the switching elements S1 and S2, respectively.

[0036] 2, a gate drive circuit 51 in the drive circuit 5 controls the operation of the switching element S1 by supplying a drive signal SG1 to the gate of the switching element S1 via a resistor element R1. The resistor element R1 is connected between one output terminal of the gate drive circuit 51 and the gate of the switching element S1, and the other output terminal of the gate drive circuit 51 is connected to the connection point P1 in the inverter circuit 2.

[0037] Similarly, as shown in FIG. 2, the gate drive circuit 52 in the drive circuit 5 controls the operation of the switching element S2 by supplying a drive signal SG2 to the gate of the switching element S2 via a resistor R2. In the example shown in FIG. 2, the gate drive circuit 52 includes a drive circuit 520, two drive transistors 521 and 522, and the current detector 6. The drain of the drive transistor 521 is connected to a power supply VD, the gate is connected to one output terminal of the drive circuit 520, and the source is connected to the drain of the drive transistor 522 and one end of the resistor R2. The gate of the drive transistor 522 is connected to the other output terminal of the drive circuit 520, and the current detector 6 is disposed between the drain of the drive transistor 522 and ground GND. The other end of the resistor R2 is connected to the gate of the switching element S2. With this configuration, the drive circuit 520 controls the operation of the drive transistors 521 and 522 to generate the drive signal SG2.

[0038] As shown in FIG. 2, the current detector 6 is connected to the drive transistor 522 within the control circuit 7 (the gate drive circuit 52 in the drive circuit 5). As shown in FIGS. 1 and 2, the current detector 6 is a circuit that detects (directly detects) the current Igd2 flowing through a predetermined path. As shown in FIG. 2, the current Igd2 flows via the gate-drain capacitance Cdg2 of the switching element S2 (in the off state). As shown by the solid line in FIG. 2, the current Igd2 is a loop current that flows through the capacitance Cdg2, the resonant capacitor Cr and resonant inductor Lr in the inverter circuit 2, the primary winding 31 of the transformer 3, ground GND, the current detector 6, the drive transistor 522, and the resistor R2, in that order. Furthermore, the current Igd2 flows in conjunction with the resonant current (shown by the dashed line in FIG. 2) flowing through the inverter circuit 2. The capacitance component Cdg2 is configured using, for example, a parasitic capacitance in the switching element S2 or an external capacitor for the switching element S2.

[0039] Such a current detector 6 includes, for example, a resistor element or a Hall element, etc. In the example shown in Fig. 2, the current detector 6 is disposed on the source side of the drive transistor 522, but the current detector 6 may also be disposed on the drain side of the drive transistor 522, for example.

[0040] Here, the above-mentioned drive circuit 5 is configured to perform switching frequency control when controlling the switching operation of each of the switching elements S1 and S2 (performing switching drive), i.e., PFM (Pulse Frequency Modulation) control is performed on the drive signals SG1 and SG2.

[0041] The drive circuit 5 performs the above-described switching drive so that the switching elements S1 and S2 each perform a switching operation at a fixed duty ratio and a variable switching frequency fsw. If the on-periods of the switching elements S1 and S2 are represented as Ton1 and Ton2, respectively, the duty ratios of the switching elements S1 and S2 can be expressed as (Ton1 / Tsw) and (Ton2 / Tsw) using the switching cycle Tsw (=1 / fsw). Both of these (Ton1 / Tsw) and (Ton2 / Tsw) are less than 50%, and a dead time Td (described below) is provided between the on-periods Ton1 and Ton2 to prevent short-circuit damage due to simultaneous on-periods.

[0042] Here, when performing the above-described switching drive, the control circuit 7 (drive circuit 5) also performs the following control based on the detection result of the current Igd2 by the above-described current detector 6. That is, the control circuit 7 (as needed) sets the length of the dead time Td (the timing of switching the switching element S2 from the OFF state to the ON state, which will be described below) as a delay time, based on the detection result of the current Igd2. That is, the control circuit 7 uses the dead time Td thus set to control the switching operation of the switching element S2.

[0043] As shown in FIG. 3, the dead time Td is the period from when the switching element S1 switches from the on state (Vgs1=5V, for example) to the off state (Vgs1=0V) to when the switching element S2 switches from the off state to the on state. In other words, the dead time Td is the period during which both the switching elements S1 and S2 are set to the off state. Note that the on state of the switching elements mentioned above means the gate-on state of the switching elements, and the same applies hereinafter.

[0044] In this way, the control circuit 7 sets the timing for switching element S2 from the off state to the on state after switching element S1 switches from the on state to the off state and transitions to the dead time Td based on the detection result of current Igd2.

[0045] Such a dead time Td corresponds to a specific example of the "delay time" in the present invention.

[0046] Also, for example, Fig. 3 As shown in Fig. 3, the control circuit 7 performs switching operation in the next switching cycle Tsw during the dead time Td (for example, the dead time Td' shown in Fig. 3) set in this manner. At this time, the control circuit 7, as will be described in detail later, controls the dead time Td so that it is shortened to near 0 (zero).

[0047] The method for setting such dead time Td (the timing at which the switching element S2 is switched to the ON state) will be described in detail later (FIGS. 5 to 9).

[0048] [Operation, Actions and Effects] (A.Basic movement) In this switching power supply device 1, a DC input voltage Vin supplied from a DC input power supply 10 via input terminals T1 and T2 is switched by switching elements S1 and S2 in inverter circuit 2 to generate a rectangular pulse wave voltage. This rectangular pulse wave voltage is supplied to primary winding 31 of transformer 3 and transformed in transformer 3, so that a transformed AC voltage is output from secondary windings 321 and 322.

[0049] In the rectifying and smoothing circuit 4, the AC voltage output from the transformer 3 (the transformed AC voltage described above) is rectified by rectifying diodes 41 and 42 in the rectifying circuit, and then smoothed by an output smoothing capacitor Cout in the smoothing circuit. As a result, a DC output voltage Vout is output from output terminals T3 and T4. This DC output voltage Vout causes a DC output current Iout to flow to the load 9, and power is supplied to the load 9.

[0050] (B. Transistor conduction characteristics) However, conventional general switching power supply devices that use transistors as switching elements have the following problems.

[0051] That is, during the aforementioned dead time Td, a reverse voltage drop of, for example, 2 V or more occurs between the drain and source of the transistor serving as the switching element. This reverse voltage and the drain current flowing through the transistor result in conduction loss in the switching element. In particular, when the aforementioned GaN transistor is used as the switching element, the aforementioned reverse voltage drop becomes large, as shown in Figure 4 below, and therefore the aforementioned conduction loss also becomes large.

[0052] Figure 4 shows an example of the conduction characteristics of a typical transistor (an example of the relationship between the drain-source voltage Vds and the drain-source current Ids in the case of the GaN transistor described above). Note that this example of Figure 4 shows such conduction characteristics for gate-source voltages Vgs = -3V, -2V, 0V, 2V, and 6V.

[0053] First, although such GaN transistors do not have a built-in body diode in their device structure, they have a pseudo-body diode during circuit operation. This pseudo-body diode operates when the gate of the GaN transistor is off and the voltage Vds described above becomes negative, causing the gate-drain voltage Vgd to become positive, exceeding a certain threshold and causing the channel to conduct. Therefore, in this GaN transistor, the forward drop voltage VF of the body diode is approximately 2V, which is higher than the 0.7V VF of a silicon MOS-FET.

[0054] Furthermore, when the voltage Vgs in a GaN transistor is negative, the VF becomes even larger, as shown in Figure 4. Because this VF is large, the period during which the pseudo body diode is conductive is long, and if the current Ids is large, even larger conduction losses occur.

[0055] Here, conduction of the body diode or pseudo-body diode in a switching element occurs immediately before the gate of the switching element is turned on when synchronous rectification or zero voltage switching (ZVS) is performed.

[0056] Also, just before the switching element is turned on, it is ideal to turn on the gate at the same time as the voltage Vds becomes negative. Specifically, in the case of the switching power supply device 1 of this embodiment, as shown in Fig. 5, it can be said that it is ideal for the switching element S2 to be switched from the off state to the on state by the drive signal SG2 (the above-mentioned voltage Vgs2) at the timing t1 when the above-mentioned voltage Vds2<0.

[0057] On the other hand, if the switching element is turned on too early, the charge accumulated in the output capacitance Coss of the switching element may be short-circuited when the element is turned on, resulting in power loss, or the timing of the turn-on may overlap with the on period of another switching element, causing a through current to flow.

[0058] Conversely, if the turn-on is too delayed, the conduction period of the body diode or pseudo-body diode will be longer. Specifically, as shown in FIG. 6, in the case of the switching power supply device 1 of this embodiment, if the timing (timing t2) at which the drive signal SG2 (voltage Vgs2) switches the switching element S2 from the OFF state to the ON state is too late, relative to the timing t1 at which the voltage Vds2 becomes less than 0, the following will occur. That is, in this case, as described above, the conduction period of the body diode or pseudo-body diode will be longer, and the power loss due to such conduction will increase, as shown by symbol P10 in FIG. 6, for example.

[0059] In addition, just before the switching element turns on, the voltage Vds drops rapidly, causing current to flow to the gate of the switching element through the feedback capacitance, which can cause the voltage Vgs to become negative. For example, in a GaN transistor, a negative voltage Vgs increases VF, which increases power loss due to conduction of the pseudo-body diode.

[0060] Furthermore, the appropriate turn-on timing differs depending on the operating conditions of the switching power supply (input voltage, load, etc.) and variations in constants such as parasitic capacitance and inductance. Therefore, to avoid a fatal increase in power loss due to premature turn-on, as well as surges and noise, it is desirable to set the turn-on timing later than ideal.

[0061] However, there is a risk that the dead time Td will be long due to the existence of, for example, the circuit delay time Tcd shown in FIG. 6 (for example, the delay time in the control circuit 7 due to the delay in detecting the current Igd2 in the current detector 6 or the delay in the response time in the drive circuit 5). That is, as shown in FIG. 5, for example, ideally, it is desirable that the switching element S2 be turned on almost simultaneously with the timing t1 at which it is detected that the voltage Vds2<0 (circuit delay time Tcd≈0). However, in reality, for example, as shown in FIG. 6, the existence of the circuit delay time Tcd described above will result in a long dead time Td, which will lead to increased power loss.

[0062] Incidentally, such a circuit delay time Tcd is generally at most several tens of nanoseconds, but due to the recent trend toward higher frequencies in control circuits (drive circuits), it has become a time that cannot be ignored. Specifically, when operating at 1 MHz, for example, even if the circuit delay time Tcd is about 50 nanoseconds, the power loss due to such a circuit delay time Tcd can amount to as much as 30% of the total power loss in the switching element.

[0063] In this way, in a conventional general switching power supply device that uses a transistor as a switching element, there is a risk of increased power loss due to the generation of reverse voltage in the switching element, etc. Therefore, it can be said that it is necessary to appropriately set the turn-on timing of the switching element, etc., and minimize the dead time Td.

[0064] Incidentally, to reduce the cost, versatility, and speed of switching power supplies, it is important to avoid high-voltage (high-withstand-voltage) processes in the detector used to set the dead time Td. The reason for this is that while directly detecting the voltage Vds to set the dead time Td would reduce the circuit delay time Tcd, this voltage Vds is very high (e.g., approximately 400 V). Therefore, directly detecting this voltage Vds would require a high-voltage process in the detector. In this case, a voltage division technique using a resistive element could be considered, but even in this case, the withstand voltage of the resistive element and power loss in the resistive element would ultimately become problems. Furthermore, a blocking technique using a diode could also be considered, but even in this case, the withstand voltage of the diode would ultimately become a problem. In addition, in these cases, the high impedance of the resistive element and the parasitic capacitance of the detector and diode increase the time constant, ultimately resulting in an increase in the circuit delay time.

[0065] (C. Operation Example of This Embodiment) Therefore, in the switching power supply device 1 of the present embodiment, the detection result of the current Igd2 described above is used to set the switching timing of the switching element S2 described above in advance (at a previous stage described below), as will be described in detail below, in the control circuit 7. In other words, the control circuit 7 sets the timing of switching the switching element S2 from the OFF state to the ON state after the transition to the dead time Td, based on the detection result of the current Igd2 described above (the current flowing via the gate-drain capacitance component Cdg2 of the switching element S2 in the OFF state).

[0066] FIG. 7 is a timing diagram showing waveform examples of the current Igd2 (detection current) and the like according to this embodiment. FIG. 8 is a timing diagram showing an enlarged version of a portion of the waveform example shown in FIG. 7. Specifically, FIGS. 7 and 8 respectively show waveform examples of the drive signals SG1 and SG2, voltage Vgs2, current Igd2, voltage Vds2, and current Ids2 described above. FIG. 9 is a timing diagram showing a control example of the switching operation according to this embodiment (an example of setting the dead time Td described above).

[0067] First, when the drive signal SG1 transitions to the off state (dropping to 0 V), the voltage Vds2 across the switching element S2 begins to drop. At this time, the aforementioned gate-drain capacitance Cdg2 of the switching element S2 causes the aforementioned current Igd2 (current flowing via the capacitance Cdg2 of the switching element S2 in the off state) to flow, lowering the voltage Vds2 across the switching element S2. Furthermore, as shown by reference symbol P11 in FIG. 7 and reference symbol P11a among reference symbols P11a and P11b in FIG. 8, this current Igd2 tends to increase before the voltage Vds2 reaches its lowest point. Therefore, by using the detection of this current Ids2 as a trigger, it is possible to detect the event (event) of the voltage Vds2 reaching its lowest point. Furthermore, since the gate terminal of the switching element S2 has a breakdown voltage of only a few tens of volts, the high-voltage process described above is not required to detect the current Igd2.

[0068] Therefore, in this embodiment, the control circuit 7 utilizes the detection result of the current Igd2 to set the timing of the dead time Td (the timing at which the switching element S2 is switched to the ON state) as follows.

[0069] That is, the control circuit 7 uses the detection timing of the current Igd2 to detect in advance the event that the voltage Vds2 of the switching element S2 reaches its lowest point after the transition to the dead time Td, before the voltage Vds2 reaches its lowest point. Then, at the point when the control circuit 7 detects in advance such an event, it sets in advance the timing at which the switching element S2 will switch from the OFF state to the ON state.

[0070] 9, when Vds2<0 (timing t1) and the current detector 6 detects that the current Igd2 is equal to or greater than the predetermined threshold current Ith (Igd2≧Ith) (timing t0) before the voltage Vds2 reaches its lowest point, the following occurs: That is, the control circuit 7 detects in advance that the voltage Vds2 has reached its lowest point, and sets the timing for switching the switching element S2 from the OFF state to the ON state earlier (before the timing t1) at the time of the detection of this event (timing t0). Specifically, the control circuit 7 sets the drive signal SG2 for the switching element S2 so that it transitions from the OFF state (Vgs2=0 V) to the ON state (Vgs2=5 V, for example). As a result, for example, as shown in Figure 9, after the aforementioned actual circuit delay time Tcd (shown in Figure 9) has elapsed, the drive signal SG2 actually transitions to the ON state, and the switching element S2 transitions from the OFF state to the ON state (the dead time Td ends).

[0071] In this way, the control circuit 7 uses the detection timing of the current Igd2 to set the timing of switching the switching element S2 to the on state in advance, thereby performing the following control. That is, as shown in FIG. 9, for example, the control circuit 7 reduces the circuit delay time Tcd from the detection of the current Igd2 to the switching of the switching element S2 to the on state, thereby shortening the dead time Td. In detail, by reducing and adjusting the circuit delay time Tcd in this way, the control circuit 7 shortens the dead time Td to near 0 (zero). This prevents the increase in power loss caused by the aforementioned increase in the circuit delay time Tcd, as shown by reference symbol P10 in FIG. 9, for example.

[0072] (D. Actions and Effects) In this manner, in this embodiment, the timing of switching the switching element S2 from the OFF state to the ON state after the transition to the dead time Td is set based on the detection result of the current Igd2 described above, resulting in the following: That is, as described above, since the event of the voltage Vds2 of the switching element S2 reaching its lowest point can be detected in advance before the voltage Vds2 reaches its lowest point, the circuit delay time Tcd described above can be substantially shortened. This shortens the dead time Td and reduces the conduction loss (in the body diode described above) in the switching element S2. As a result, in this embodiment, it is possible to suppress power loss in the switching power supply device 1 (achieve high efficiency).

[0073] In the present embodiment, the switching timing of the switching element S2 is set based on the detection result of the current Igd2. However, for example, the switching timing of the switching element S1 (from the OFF state to the ON state) may be set based on the detection result of the current Igd1, as follows. That is, instead of the current Igd2 (current flowing via the gate-drain capacitance component Cdg2 of the switching element S2 in the OFF state), for example, the following current Igd1 may be detected by a current detector separately provided in the gate drive circuit 51. This current Igd1 is a current flowing via the gate-drain capacitance component Cdg2 of the switching element S1 (in the OFF state) (as well as the gate drive circuit 51 and the resistor R1), as shown by the dashed line in FIG. 2 . Note that the capacitance component Cdg1, like the capacitance component Cdg2, may be configured using, for example, a parasitic capacitance in the switching element S1 or an external capacitor for the switching element S1. Even with this configuration, it is possible to obtain essentially the same effects as in the present embodiment.

[0074] In particular, when GaN transistors are used as the switching elements S1 and S2, the reverse voltage drop is large as described above, which leads to the following: In other words, in this case, the effect of suppressing power loss in the switching power supply device 1 due to the reduction in conduction loss in the switching elements S1 and S2 described above is particularly large.

[0075] Furthermore, in this embodiment, when detecting the current Igd2, the high-voltage process (high-voltage elements) as described above is not required (this can be achieved using only low-voltage elements), which makes it possible to reduce the cost, make the switching power supply device 1 more versatile, and increase its speed.

[0076] Furthermore, in this embodiment, the rectifier circuit in the rectifying and smoothing circuit 4 is a so-called "center tap type" rectifier circuit, which results in the following: The number of rectifier elements is reduced to two (rectifier diodes 41 and 42), which makes it possible to reduce the size, loss, and cost of the rectifier circuit.

[0077] <2. Modifications> Next, modifications of the above embodiment (Modifications 1 to 7) will be described. Note that, in the following, the same components as those in the embodiment will be given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0078] [Variation 1] (composition) FIG. 10 is a circuit diagram showing an example of the configuration of a control circuit (control circuit 7A) in a switching power supply device (switching power supply device 1A) according to Modification 1, together with an inverter circuit 2.

[0079] As in the embodiment, a system including DC input power supply 10 and switching power supply device 1A corresponds to a specific example of a "power supply system" in the present invention. Also, the above-described control circuit 7A corresponds to a specific example of a "switching control device" in the present invention.

[0080] The switching power supply 1A of this modification 1 corresponds to the switching power supply 1 of the embodiment (see FIG. 1) in which a control circuit 7A is provided instead of the control circuit 7, and the other configurations are similar. Also, this control circuit 7A corresponds to the control circuit 7 of the embodiment (see FIG. 2) in which a drive circuit 5A including gate drive circuits 51 and 52A is provided instead of the drive circuit 5 including gate drive circuits 51 and 52, and the other configurations are similar.

[0081] In the gate drive circuit 52A described above, as shown in FIG. 10, the output from the drive circuit 520 is separated into an output terminal on the source side (on the drive transistor 521 side) and an output terminal on the sink side (on the drive transistor 522 side). Specifically, unlike the gate drive circuit 52 shown in FIG. 2, in this gate drive circuit 52A, the source of the drive transistor 521 is connected to the gate of the switching element S2 via a resistor element R2a. Also, the drain of the drive transistor 522 is connected to the gate of the switching element S2 via a current detector 6 and a resistor element R2b. In other words, in this gate drive circuit 52A, unlike the gate drive circuit 52, the current detector 6 is arranged on the drain side of the drive transistor 522, not on the source side.

[0082] In this first modification, the current detector 6 detects the current Igd2 shown by the solid line in Fig. 10. This current Igd2 is a loop current that passes through the aforementioned capacitance component Cdg2 in the switching element S2, the resonant capacitor Cr and resonant inductor Lr in the inverter circuit 2, the primary winding 31 of the transformer 3, the ground GND, the drive transistor 522, the current detector 6, and the resistor element R2b, in that order. As in the case of Fig. 2, the current Igd2 is a current that flows in conjunction with the resonant current (shown by the dashed line in Fig. 10) flowing in the inverter circuit 2.

[0083] 2, instead of setting the switching timing of the switching element S2 based on the detection result of the current Igd2, for example, the following may be done. That is, for example, the switching timing of the switching element S1 (from the OFF state to the ON state) may be set based on the detection result of the current Igd1 described above, as shown by the dashed line in FIG. 10. This also applies to the cases of FIGS. 11 and 12 described later.

[0084] (Actions and Effects) The switching power supply device 1A of the first modification configured as above basically operates in the same manner as the switching power supply device 1 of the embodiment, and can therefore achieve the same effects. In the first modification, for example, the gate drive circuit 51 may also have the same configuration as the gate drive circuit 52A described above.

[0085] [Variation 2] (composition) FIG. 11 is a circuit diagram showing an example of the configuration of a control circuit (control circuit 7B) in a switching power supply device (switching power supply device 1B) according to Modification 2, together with an inverter circuit 2.

[0086] As in the embodiment, a system including DC input power supply 10 and switching power supply device 1B corresponds to a specific example of a "power supply system" in the present invention. Also, the above-described control circuit 7B corresponds to a specific example of a "switching control device" in the present invention.

[0087] The switching power supply device 1B of this modified example 2 corresponds to the switching power supply device 1 of the embodiment (see FIG. 1) in which a control circuit 7B is provided instead of the control circuit 7, and the other configurations are similar. Also, this control circuit 7B corresponds to the control circuit 7 of the embodiment (see FIG. 2) in which a drive circuit 5B including gate drive circuits 51, 52B is provided instead of the drive circuit 5 including gate drive circuits 51, 52, and the other configurations are similar.

[0088] 11, in the gate drive circuit 52B described above, unlike the gate drive circuit 52 shown in Fig. 2, the current detector 6 is configured to indirectly (rather than directly) detect the current Igd2 described above. Specifically, in the example of Fig. 11, the current detector 6 detects the voltage VR2 across the resistor element R2 connected to the gate of the switching element S2, and derives the current Igd2 based on this voltage VR2, thereby indirectly detecting the current Igd2.

[0089] (Actions and Effects) The switching power supply device 1B of the second modification configured as above basically operates in the same manner as the switching power supply device 1 of the embodiment, and can therefore achieve the same effects. In the second modification, for example, the gate drive circuit 51 may also have the same configuration as the gate drive circuit 52B described above.

[0090] [Variation 3] (composition) FIG. 12 is a circuit diagram showing an example of the configuration of a control circuit (control circuit 7C) in a switching power supply device (switching power supply device 1C) according to Modification 3, together with an inverter circuit 2.

[0091] As in the embodiment, a system including DC input power supply 10 and switching power supply device 1C corresponds to a specific example of a "power supply system" in the present invention. Also, the above-described control circuit 7C corresponds to a specific example of a "switching control device" in the present invention.

[0092] The switching power supply device 1C of this modification 3 corresponds to the switching power supply device 1 (see FIG. 1) of the embodiment in which a control circuit 7C is provided instead of the control circuit 7, and the other configurations are similar. Also, this control circuit 7C corresponds to the control circuit 7 (see FIG. 2) of the embodiment in which a drive circuit 5C including gate drive circuits 51 and 52C is provided instead of the drive circuit 5 including gate drive circuits 51 and 52, and the other configurations are similar.

[0093] The gate drive circuit 52C also has the same structure as the gate drive circuit 52 shown in FIG. B Similarly, the current detector 6 indirectly (rather than directly) detects the current Igd2 (see FIG. 12). Specifically, in the example of FIG. 12, the current detector 6 indirectly detects the current Igd2 by detecting the gate-source voltage Vgs2 of the switching element S2.

[0094] Here, for example, as shown in FIG. 13 (a timing diagram similar to FIG. 8 described above), when the current Igd2 increases (see symbol P11a), the following occurs. That is, due to the resistor element R2 being connected to the gate of the switching element S2, a negative potential is generated in the voltage Vgs2 as the current Igd2 increases (see symbol P12a), which can be detected by the current detector 6. Therefore, the control circuit 7C (drive circuit 5C) detects and triggers the voltage Vgs2 to become negative, thereby enabling the dead time Td (the timing at which the switching element S2 switches to the on state) to be set in the same manner as in the embodiment.

[0095] (Actions and Effects) The switching power supply device 1C of the third modification configured as above basically operates in the same manner as the switching power supply device 1 of the embodiment, and can therefore achieve the same effects. In the third modification, for example, the gate drive circuit 51 may also have the same configuration as the gate drive circuit 52C described above.

[0096] [Variation 4] (composition) FIG. 14 is a timing diagram that schematically illustrates an example of control of the switching operation by a control circuit (control circuit 7D) in a switching power supply device (switching power supply device 1D) according to Modification 4.

[0097] As in the embodiment, a system including DC input power supply 10 and switching power supply device 1D corresponds to a specific example of a "power supply system" in the present invention. Also, the above-described control circuit 7D corresponds to a specific example of a "switching control device" in the present invention.

[0098] The switching power supply device 1D of the fourth modification corresponds to the switching power supply device 1 (see FIG. 1) of the embodiment, except that a control circuit 7D is provided instead of the control circuit 7, and the other configurations are the same.

[0099] As shown in Figure 14, for example, this control circuit 7D is configured to switch between two types of control CTL1 and CTL2 depending on the detection status of the aforementioned current Igd2 (or depending on the switching setting from the user, etc.) (see symbol P20).

[0100] As will be explained in detail below, in the control CTL1 (first control), the control circuit 7D sets the timing (dead time Td) at which the switching element S2 switches to the on state based on the detection result of the current Igd2, as explained above. On the other hand, in the control CTL2 (second control), the control circuit 7D always sets a fixed timing (dead time Td) at which the switching element S2 switches to the on state, as in the conventional case.

[0101] The reason why two types of control CTL1 and CTL2 are switched and executed in this way depending on the detection status of the current Igd2 is that there may be cases where the current Igd2 cannot be detected properly, depending on, for example, the load conditions, input conditions, etc. In other words, by skillfully combining the method of timing-setting the dead time Td (control CTL1) as explained above and the conventional method of always fixing the dead time Td (control CTL2), it is possible to avoid problems with setting the dead time Td due to poor detection of the current Igd2.

[0102] Specifically, in the example of control CTL1 shown in FIG. 14, first, during the detection period of current Igd2 (the period when Igd2 ≥ Ith), the drive signal SdA becomes an on state ("H (high)" state). Incidentally, the transition timing (timing t2) to the on state ("H" state) of the other drive signal SdB is fixed at all times as before and corresponds to the switching timing of the switching element S2 to the on state. And in this control CTL1, as described above, the control circuit 7D uses the detection time point (timing t0) of this current Igd2 as a trigger, and after the elapse of the circuit delay time Tcd described above (at timing t3), the switching element S2 will switch to the on state at any time (see FIG. 14). That is, in this control CTL1, the control circuit 7D uses the transition timing of the drive signal SdA to the on state among the two drive signals SdA and SdB described above (as a trigger) to set the switching timing of the switching element S2 to the on state.

[0103] On the other hand, in the example of control CTL2 shown in FIG. 14, as shown in FIG. 14, even in a situation where the magnitude of the current Igd2 is insufficient and does not reach the threshold current Ith (remaining in the state of Igd2 < Ith), the following occurs. That is, in this situation, the above-described drive signal SdA remains in an off state ("L (low)" state). Therefore, in this control CTL2, the control circuit 7D uses the transition timing of the drive signal SdB to the on state among the two drive signals SdA and SdB described above (as a trigger) to set the switching timing of the switching element S2 to the on state (the always-fixed timing t2) (see FIG. 14).

[0104] (Operation and Effect) In the switching power supply device 1 of the modification 4 having such a configuration D basically, by the same operation as the switching power supply device 1 of the embodiment, the same effects can be obtained.

[0105] Furthermore, in particular, in this modification 4, as described above, two types of control CTL1 and CTL2 are switched between depending on the detection status of the current Igd2, resulting in the following: That is, for example, as described above, it is possible to avoid a problem in setting the dead time Td (the timing at which the switching element S2 switches to the ON state) caused by a detection failure of the current Igd2, and it is possible to build a more robust system.

[0106] [Variation 5] (composition) FIG. 15 is a circuit diagram showing an example of the schematic configuration of a switching power supply device (switching power supply device 1E) according to Modification 5.

[0107] As in the embodiment, a system including the DC input power supply 10 and this switching power supply device 1E corresponds to a specific example of the "power supply system" of the present invention.

[0108] This variant 5 This switching power supply 1E corresponds to the switching power supply 1 of the embodiment (see FIG. 1) in which a transformer 3E and a rectifying / smoothing circuit 4E are provided instead of the transformer 3 and the rectifying / smoothing circuit 4, and the other configurations are similar. Note that, as shown in FIG. 15, for example, in this switching power supply 1E, any of the control circuits 7A to 7D described in Modifications 1 to 4 may be provided in place of the control circuit 7.

[0109] The transformer 3E has one primary winding 31 and one secondary winding 32. That is, while the transformer 3 has two secondary windings 321 and 322, the transformer 3E has only one secondary winding 32. A first end of the secondary winding 32 is connected to a connection point P7 in a rectifying and smoothing circuit 4E (described later), and a second end of the secondary winding 32 is connected to a connection point P8 in the rectifying and smoothing circuit 4E.

[0110] Like the transformer 3, the transformer 3E converts the voltage (voltage converted into a rectangular pulse wave) generated by the inverter circuit 2 into an AC voltage, and outputs the AC voltage from the end of the secondary winding 32. In this case, the degree of voltage conversion of the DC output voltage Vout relative to the DC input voltage Vin is determined by the turns ratio between the primary winding 31 and the secondary winding 32, and the switching frequency fsw described above.

[0111] The rectifying and smoothing circuit 4E has four rectifying diodes 41 to 44 and one output smoothing capacitor Cout. Specifically, the rectifying and smoothing circuit 4E includes a rectifying circuit having the rectifying diodes 41 to 44 and a smoothing circuit having the output smoothing capacitor Cout. In other words, the rectifying and smoothing circuit 4E has a modified rectifying circuit configuration in the rectifying and smoothing circuit 4.

[0112] The rectifier circuit of this modification 5 is a so-called "bridge type" rectifier circuit, unlike the rectifier circuit of the embodiment (a so-called "center-tap type" rectifier circuit). That is, the cathodes of rectifier diodes 41 and 43 are each connected to output line LO, and the anode of rectifier diode 41 is connected to the cathode of rectifier diode 42 and the aforementioned first end of secondary winding 32 at connection point P7. Furthermore, the anodes of rectifier diodes 42 and 44 are each connected to ground line LG, and the cathode of rectifier diode 44 is connected to the anode of rectifier diode 43 and the aforementioned second end of secondary winding 32 at connection point P8.

[0113] In the rectifying / smoothing circuit 4E configured as above, similarly to the rectifying / smoothing circuit 4, the rectifying circuit configured to include rectifying diodes 41 to 44 rectifies the AC voltage output from the transformer 3E and outputs the rectified voltage.

[0114] (Actions and Effects) The switching power supply device 1E of the fifth modification configured as described above also basically operates in the same manner as the switching power supply devices 1 and 1A to 1D described so far, and can therefore obtain the same effects.

[0115] Furthermore, in particular, in this modification 5, the rectifier circuit in the rectifying and smoothing circuit 4E is a bridge-type rectifier circuit, so that the number of windings (number of secondary windings) in the transformer 3E is reduced to one (secondary winding 32) compared to, for example, the embodiment. As a result, it is possible to reduce the size and loss of the transformer 3E.

[0116] [Variations 6 and 7] The switching power supply devices (switching power supply devices 1F, 1G) according to Modifications 6 and 7 are each configured such that the rectifier circuits in the rectifying and smoothing circuits 4, 4E in the embodiment and Modifications 1 to 5 described above are replaced with so-called synchronous rectifier circuits, as will be described below. In addition, since such synchronous rectifier circuits are provided, the switching power supply devices 1F, 1G according to Modifications 6 and 7 are each provided with control circuits 7F, 7G, which will be described later, instead of the control circuits 7, 7A to 7D in the embodiment and Modifications 1 to 5.

[0117] (Configuration of Modification 6) Specifically, FIG. 16 is a circuit diagram showing an example of the schematic configuration of a switching power supply device 1F according to the sixth modification.

[0118] As in the embodiment, a system including the DC input power supply 10 and this switching power supply device 1F corresponds to a specific example of the "power supply system" of the present invention.

[0119] The switching power supply device 1F of this variant example 6 corresponds to the switching power supply device 1 of the embodiment, in which a rectifying and smoothing circuit 4F and a control circuit 7F are provided instead of the rectifying and smoothing circuit 4 and the control circuit 7, respectively, and the other configurations are similar.

[0120] In the synchronous rectifier circuit (rectifier smoothing circuit 4F) of this modification 6, as shown in FIG. 16, the rectifier diodes 41 and 42 described in the embodiment are each configured with MOS-FETs (MOS transistors M9 and M10) as switching elements. In this synchronous rectifier circuit, the MOS transistors M9 and M10 themselves are controlled to be turned on (perform synchronous rectification) in synchronization with the period during which the parasitic diodes of the MOS transistors M9 and M10 are conductive. Specifically, in this modification 6, a drive circuit 5 in a control circuit 7F (described later) uses drive signals SG9 and SG10 to control the on / off operation of the MOS transistors M9 and M10 (see FIG. 16).

[0121] Each of these MOS transistors M9 and M10 corresponds to a specific example of a "switching element that performs synchronous rectification" in the present invention.

[0122] Furthermore, the control circuit 7F of this modification 6 basically has the same configuration as the control circuits 7, 7A to 7D in the embodiment and modifications 1 to 5. However, the control circuit 7F differs from the control circuits 7, 7A to 7D in the following way.

[0123] That is, first, in the control circuits 7, 7A to 7D, the two switching elements S2, S1 (corresponding to the "first and second switching elements" in the present invention) for which the dead time Td is set are both switching elements arranged in the inverter circuit 2. In contrast, in the control circuit 7F, at least one of the two switching elements (corresponding to the "first and second switching elements" in the present invention) for which the dead time Td is set is a switching element that performs synchronous rectification (at least one of the above-mentioned MOS transistors M9, M10) arranged in the above-mentioned rectifying smoothing circuit 4F.

[0124] Specifically, in the control circuit 7F, the two switching elements for which the dead time Td (the timing at which the switching elements described above are switched to the on state) are set are as shown in (a) or (b) below. (a) One of the switching elements S1 and S2 and one of the MOS transistors M9 and M10 are the two switching elements for which the dead time Td is set. (b) MOS transistors M9 and M10 are two switching elements for which the dead time Td is set.

[0125] Incidentally, the above-mentioned "two switching elements to be set" (corresponding to "first and second switching elements" in the present invention) can be, for example, as follows: That is, when one switching element (corresponding to "second switching element" in the present invention) transitions from an on state to an off state, the other switching element that is (already) in an off state corresponds to the switching element (corresponding to "first switching element" in the present invention) for which the switching timing is to be set. Therefore, for example, it can be said that the other switching element that transitions from an on state to an off state together with the transition of one switching element from an on state to an off state does not correspond to the above-mentioned switching element for which the switching timing is to be set.

[0126] Then, for one of these two switching elements (corresponding to the "first switching element" in the present invention), the control circuit 7F sets a dead time Td (the timing at which the above-mentioned switching element switches to the on state) in the same manner as in the embodiment and modifications 1 to 5. Then, the control circuit 7F uses the dead time Td thus set to control the switching operations of a plurality of switching elements (switching elements S1, S2 and MOS transistors M9, M10) including the above-mentioned two switching elements.

[0127] At this time, examples of currents to be detected by the current detector 6 include the aforementioned current Igd2 (or the aforementioned current Igd1), as well as the following current Igd9 (or current Igd10), as shown in FIG. 16.

[0128] Current Igd9 (shown by a solid arrow in FIG. 16): a current that flows via a capacitance component Cdg9 between the gate and drain of the MOS transistor M9 (a loop current that passes through, in addition to this capacitance component Cdg9, the secondary winding 321 in the rectifying smoothing circuit 4F, the output smoothing capacitor Cout, the ground GND, and the current detector 6 in the control circuit 7F, in that order). Current Igd10: a current that flows via a capacitance component between the gate and drain of the MOS transistor M10 (a loop current that flows in this order through the secondary winding 322 in the rectifying smoothing circuit 4F, the output smoothing capacitor Cout, the ground GND, and the current detector 6 in the control circuit 7F, in addition to this capacitance component)

[0129] Such a control circuit 7F corresponds to a specific example of a "switching control device" in the present invention. In addition, in this modification 6, the above-mentioned switching elements S1, S2 and MOS transistors M9, M10 each correspond to a specific example of a "plurality of switching elements" in the present invention. Furthermore, any two of these switching elements S1, S2 and MOS transistors M9, M10 (the above-mentioned two switching elements) correspond to a specific example of a "first switching element" and a "second switching element" in the present invention.

[0130] (Configuration of Modification 7) FIG. 17 is a circuit diagram showing a schematic configuration example of a switching power supply device 1G according to the seventh modification.

[0131] As in the embodiment, a system including the DC input power supply 10 and this switching power supply device 1G corresponds to a specific example of the "power supply system" of the present invention.

[0132] The switching power supply device 1G of this variant 7 corresponds to the switching power supply device 1E of variant 5, except that the rectifying and smoothing circuit 4E and the control circuit 7 are replaced by a rectifying and smoothing circuit 4G and a control circuit 7G, respectively, and the other configurations are similar.

[0133] In the synchronous rectifier circuit (rectifier smoothing circuit 4G) of this modification 7, as shown in FIG. 17, the rectifier diodes 41-44 described in modification 5 are each configured with a MOS-FET (MOS transistors M11-M14) serving as a switching element. Similarly to the synchronous rectifier circuit of modification 6, the synchronous rectifier circuit of modification 7 also controls the MOS transistors M11-M14 themselves to be turned on (perform synchronous rectification) in synchronization with the period during which the parasitic diode of each MOS transistor M11-M14 is conductive. Specifically, in modification 7, a drive circuit 5 in a control circuit 7G (described later) uses drive signals SG11-SG14 to control the on / off operation of each MOS transistor M11-M14 (see FIG. 17).

[0134] Each of these MOS transistors M11 to M14 corresponds to a specific example of a "switching element that performs synchronous rectification" in the present invention.

[0135] Furthermore, the control circuit 7G of this modified example 7 basically has the same configuration as the control circuits 7, 7A to 7D in the embodiment and modified examples 1 to 5. However, unlike the control circuits 7, 7A to 7D, this control circuit 7G has the following configuration, similar to the control circuit 7F described in modified example 6.

[0136] That is, in the control circuit 7G, at least one of the two switching elements (corresponding to the "first and second switching elements" in the present invention) for which the dead time Td is set is a switching element that performs synchronous rectification (at least one of the above-mentioned MOS transistors M11 to M14) arranged in the above-mentioned rectifying smoothing circuit 4G.

[0137] Specifically, in the control circuit 7G, the two switching elements for which the dead time Td (the timing at which the aforementioned switching elements switch to the on state) is set are as shown in (c) or (d) below. (c) One of the switching elements S1 and S2 and one of the MOS transistors M11 to M14 are the two switching elements for which the dead time Td is set. (d) Two of the MOS transistors M11 to M14 are two switching elements for which the dead time Td is set.

[0138] Incidentally, the above-mentioned "two switching elements to be set" (corresponding to "first and second switching elements" in the present invention) are the same as those in the sixth modification example, for example.

[0139] The control circuit 7G sets a dead time Td (the timing at which the above-mentioned switching element switches to the on state) for one of these two switching elements (corresponding to the "first switching element" in the present invention) in the same manner as in the embodiment and modifications 1 to 6. The control circuit 7G then uses the dead time Td thus set to control the switching operations of a plurality of switching elements (switching elements S1, S2 and MOS transistors M11 to M14) including the above-mentioned two switching elements.

[0140] 17, examples of currents to be detected by the current detector 6 include the above-mentioned current Igd2 (or the above-mentioned current Igd1), as well as the following current Igd11 (or currents Igd12 to Igd14). That is, like the above-mentioned currents Igd9 and Igd10, the currents Igd11 to Igd14 are currents that flow via the gate-drain capacitance components of the MOS transistors M11 to M14, respectively.

[0141] Such a control circuit 7G corresponds to a specific example of a "switching control device" in the present invention. In addition, in this modification 7, the above-mentioned switching elements S1, S2 and MOS transistors M11 to M14 each correspond to a specific example of a "plurality of switching elements" in the present invention. Furthermore, any two of these switching elements S1, S2 and MOS transistors M11 to M14 (the above-mentioned two switching elements) correspond to a specific example of a "first switching element" and a "second switching element" in the present invention.

[0142] (Actions and Effects of Modifications 6 and 7) The switching power supply devices 1F and 1G of the sixth and seventh modifications configured as described above also basically have the same functions as the switching power supply devices 1, 1A to 1E described so far, and can therefore achieve the same effects.

[0143] Furthermore, in particular, in these modifications 6 and 7, each of the multiple rectifier elements (rectifier diodes) in the rectifier circuit is configured as a switching element, and this rectifier circuit is configured as a synchronous rectifier circuit, as follows: That is, such a synchronous rectifier circuit reduces conduction loss during rectification, making it possible to achieve a smaller rectifier circuit and lower loss. Incidentally, examples of such switching elements include, in addition to the above-mentioned MOS-FET, the above-mentioned HEMT, an IGBT or a bipolar transistor with a diode added in parallel, etc.

[0144] <3. Other Modifications> Although the present invention has been described above by way of embodiments and modifications, the present invention is not limited to these embodiments and can be modified in various ways.

[0145] For example, in the above embodiments, specific configurations of the inverter circuit have been described, but the present invention is not limited to the examples of the above embodiments, and for example, an inverter circuit with another configuration may be used. Specifically, for example, the arrangement of the resonant inductor Lr, the resonant capacitor Cr, and the primary winding 31, which are connected in series with each other, is not limited to the arrangement described in the above embodiments, and these three components may be arranged in any order. Furthermore, in the above embodiments, an example of a so-called "half-bridge" inverter circuit has been described, but the present invention is not limited to this example, and for example, a so-called "full-bridge" inverter circuit may be used.

[0146] Furthermore, in the above embodiments, the configuration of the transformer (primary winding and secondary winding) has been specifically described, but the present invention is not limited to the examples of the above embodiments, and for example, a transformer (primary winding and secondary winding) with a different configuration may be used.

[0147] Furthermore, in the above embodiments, the configuration of the rectifying and smoothing circuit (rectifying circuit and smoothing circuit) has been specifically described, but the present invention is not limited to the above examples of the embodiments, and for example, a rectifying and smoothing circuit (rectifying circuit and smoothing circuit) with a different configuration may be used. Furthermore, in the above embodiments, the configuration of the current detector has been specifically described, but the present invention is not limited to the above examples of the embodiments, and for example, a current detector with a different configuration may be used. Furthermore, such a current detector may not be provided inside the control circuit (switching control device) or the switching power supply device as described in the above examples, but may be provided outside these control circuits or the switching power supply device, for example.

[0148] In addition, in the above embodiments, specific methods for controlling the operation of each switching element (switching drive) by a drive circuit have been given and explained, but the present invention is not limited to the examples of the above embodiments, and other methods may be used as switching drive methods.

[0149] Furthermore, in the above embodiments, a DC-DC converter has been described as an example of a switching power supply device according to the present invention, but the present invention can also be applied to other types of switching power supply devices, such as an AC-DC converter.

[0150] Furthermore, the configuration examples described so far may be applied in any combination.

Claims

1. A control device applied to a switching power supply device including: a transformer having a primary winding and a secondary winding; an inverter circuit arranged between an input terminal pair to which an input voltage is input and the primary winding; and a rectifying and smoothing circuit arranged between an output terminal pair to which an output voltage is output and the secondary winding, a control circuit that controls switching operations of a plurality of switching elements included in at least one of the inverter circuit and the rectifying and smoothing circuit, The control circuit utilizing the detection timing of a current flowing through a capacitance component between the gate and the drain of a first switching element in an off state among the plurality of switching elements, detecting an event of a voltage between the source and drain of the first switching element reaching a lowest point after a second switching element of the plurality of switching elements has switched from an on state to an off state and a delay time has begun, before the voltage reaches a lowest point; At the time when the event is detected, a timing for switching the first switching element from an off state to an on state is set. Switching control device.

2. The control circuit The timing of switching in the first switching element is set by utilizing the timing of detecting the current, A circuit delay time from the detection of the current to the switching of the first switching element to an on state is reduced, thereby shortening the delay time. The switching control device according to claim 1 .

3. The control circuit reduces the circuit delay time, thereby shortening the delay time to near 0 (zero). The switching control device according to claim 2 .

4. The control circuit a first control for setting the switching timing of the first switching element based on the detection result of the current; a second control for always setting the switching timing of the first switching element to a fixed value; are switched and executed depending on the detection status of the current.

4. The switching control device according to claim 1.

5. The device further includes a current detector that directly or indirectly detects the current.

5. The switching control device according to claim 1.

6. The current detector is connected to a drive transistor in the control circuit. The switching control device according to claim 5 .

7. The capacitance component between the gate and the drain of the first switching element is The parasitic capacitance of the first switching element or an external capacitor is used.

7. The switching control device according to claim 1.

8. The first and second switching elements are both switching elements disposed within the inverter circuit. The switching control device according to any one of claims 1 to 7.

9. At least one of the first and second switching elements is disposed in the rectifying and smoothing circuit and is a switching element that performs synchronous rectification. The switching control device according to any one of claims 1 to 7.

10. A switching control device according to any one of claims 1 to 9; the input terminal pair, the output terminal pair, the transformer, the inverter circuit, and the rectifying and smoothing circuit; A switching power supply device comprising:

11. The switching power supply device according to claim 10; a power supply that supplies the input voltage to the input terminal pair; A power supply system comprising:

Images