Semiconductor Devices

Abstract

To provide a semiconductor device having high storage capacity per unit area.SOLUTION: A semiconductor device includes a first memory cell, and a second memory cell provided thereon. The first memory cell includes first and second transistors, and a first capacitor element. The second memory cell includes third and fourth transistors, and a second capacitor element. A gate of the first transistor is connected to one of a source and a drain of the second transistor and to one electrode of the first capacitor element. A gate of the third transistor is connected to one of a source and a drain of the fourth transistor and to one electrode of the second capacitor element. One of a source and a drain of the first transistor is connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.SELECTED DRAWING: None

Description

[Technical Field]

[0001] The present invention relates to, for example, a transistor and a semiconductor device. For example, the present invention relates to a method for manufacturing a transistor and a semiconductor device. The present invention relates to a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a processor, and an electronic device. The present invention also relates to a manufacturing method of a display device, a liquid crystal display device, a light emitting device, a storage device, and an electronic device. The present invention also relates to a display device, a liquid crystal display device, a light emitting device, a storage device, and a method for driving electronic equipment.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. One aspect of the invention is a process, machine, manufacture, or composition of matter. It concerns the matter of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, including display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, semiconductor circuits, and The electronic equipment may include semiconductor devices. [Background technology]

[0004] Silicon (Si)-based transistors and oxide semiconductors (Oxide S) By combining transistors that use an OS (semiconductor) as the semiconductor layer, Semiconductor devices that enable data reading and writing are attracting attention (see Patent Document 1). ).

[0005] In recent years, with the increase in the amount of data handled, semiconductor devices with larger storage capacities have become increasingly popular. To increase the storage capacity per unit area, memory cells must be stacked. It is effective to form the memory cells in layers (see Patent Document 2). This makes it possible to increase the storage capacity per unit area in accordance with the number of stacked memory cells. do. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 2011-119674 [Patent Document 2] Patent Publication No. 2011-66417 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a semiconductor device having a large storage capacity per unit area. One of the objects of the present invention is to provide a semiconductor device having a novel structure in which memory cells are stacked. Another object is to provide a method for driving a semiconductor device having a novel structure.

[0008] Another object of the present invention is to provide a module including the semiconductor device. It is another object of the present invention to provide an electronic device including the semiconductor device or the module. Another object is to provide a novel semiconductor device. One of the objectives is to provide a novel electronic device. do.

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0010] One aspect of the present invention is a memory cell including a first memory cell and a second memory cell provided on the first memory cell. a first memory cell including a first transistor and a second transistor; , a first capacitance element, and the second memory cell has a third transistor and a fourth transistor. a gate of the first transistor and a second capacitance element, the source or drain of the first transistor is electrically connected to the source of the second transistor. Alternatively, one of the drains is electrically connected to one of the electrodes of the first capacitor element, and the third transistor The gate of the fourth transistor is electrically connected to one of the source and drain of the fourth transistor. One of the source and drain of the fourth transistor is connected to one of the electrodes of the second capacitor. and one of the source and drain of the first transistor is electrically connected to the third transistor. a first transistor electrically connected to one of the source and drain of the first transistor, and a second transistor The fourth transistor includes an oxide semiconductor, and the first transistor and the third transistor include an oxide semiconductor. the channel length direction of the second transistor and the channel length direction of the fourth transistor are The semiconductor device is characterized by being substantially vertical.

[0011] Another embodiment of the present invention is a semiconductor memory device including a first memory cell provided over a substrate and a first memory cell. a second memory cell disposed on the cell, the first memory cell including a first transistor; the second memory cell has a third transistor and a first capacitance element; a first transistor, a fourth transistor, and a second capacitance element, The gate of the first transistor is electrically connected to one of the source and drain of the second transistor. One of the source and drain of the second transistor is connected to one of the electrodes of the first capacitor. The gate of the third transistor is electrically connected to the source or drain of the fourth transistor. One of the source and drain of the fourth transistor is electrically connected to , electrically connected to one of the electrodes of the second capacitor element, and One of the drains is electrically connected to one of the source and drain of the third transistor. The second transistor and the fourth transistor include an oxide semiconductor. The first and second transistors have channel lengths that are substantially perpendicular to the upper surface of the substrate. This is a semiconductor device.

[0012] Another embodiment of the present invention is a semiconductor memory device including a first memory cell provided over a substrate and a first memory cell. a second memory cell disposed on the cell, the first memory cell including a first transistor; the second memory cell has a third transistor and a first capacitance element; a first transistor, a fourth transistor, and a second capacitance element, The gate of the first transistor is electrically connected to one of the source and drain of the second transistor. One of the source and drain of the second transistor is connected to one of the electrodes of the first capacitor. The gate of the third transistor is electrically connected to the source or drain of the fourth transistor. One of the source and drain of the fourth transistor is electrically connected to , electrically connected to one of the electrodes of the second capacitor element, and One of the drains is electrically connected to one of the source and drain of the third transistor. The second transistor and the fourth transistor include an oxide semiconductor. The first and second transistors are parts of semiconductors extending substantially perpendicularly to the top surface of the substrate. The semiconductor device is characterized by having:

[0013] In another aspect of the present invention, a semiconductor device is provided that extends substantially perpendicularly to the upper surface of a substrate. In another aspect of the present invention, a crystalline silicon film is formed on the upper surface of the substrate. The elongated semiconductor is preferably cylindrical.

[0014] Another aspect of the present invention is a memory cell array including a plurality of memory cells arranged in a first direction. a plurality of first wirings and a plurality of second wirings, The second wiring is provided so as to extend in a second direction substantially perpendicular to the first direction, and the memory cell array has a plurality of memory cell strings arranged in a second direction, and The cell string is provided so as to extend in a third direction that is substantially perpendicular to the first direction and the second direction. The memory cell string includes a plurality of memory cells and a third non-volatile memory cell extending in a third direction. to fifth wirings, and the memory cell includes a first transistor, a second transistor, and a capacitance element, and a channel length direction of the first transistor is approximately parallel to the third direction. The second transistor includes an oxide semiconductor, and the gate of the first transistor is connected to the second a second transistor electrically connected to one of the source and drain of the first transistor; One of the source and drain is electrically connected to one of the electrodes of the capacitor element. In one of the cell strings, the plurality of memory cells are connected to each other by the source of the first transistor. The source or drain of the first transistor is electrically connected to the other of the source or drain of the second transistor. The source or drain of the first transistor of the memory cell at one end of the memory cell string is connected to the One of the drains is electrically connected to the third wiring, and the other end of the memory cell string is electrically connected to the third wiring. The other of the source and the drain of the first transistor of the cell is electrically connected to a fourth wiring. The other of the source and drain of the second transistor of the plurality of memory cells is connected to a fifth wiring. and in one of the plurality of memory cell arrays, the capacitance of the memory cells in the same row is The other electrode of the element is electrically connected to one of the plurality of first wirings, and a gate of the second transistor is electrically connected to one of the plurality of second wirings; This is a semiconductor device.

[0015] Another embodiment of the present invention is a semiconductor device in which multiple write operations are performed in a write operation. one of the plurality of memory cell arrays is selected and connected to a second transistor via one of the plurality of second wirings; is turned on, a write potential is applied to the plurality of fifth wirings, and a write potential is applied to one of the plurality of second wirings. The second transistor is turned off, data corresponding to the write potential is held, and the read In this operation, one of the plurality of memory cell arrays is selected and a signal is transmitted via one of the plurality of first wirings. A first potential is applied to the other electrode of the capacitor element, and a first wiring in a row different from one of the plurality of first wirings is applied. A second potential different from the first potential is applied to the other electrode of the capacitance element via a line to The transistor is turned on, a readout potential is applied to the third wiring, and data is read from the change in the readout potential. The present invention relates to a method for driving a semiconductor device, and a method for reading out data from the semiconductor device.

[0016] Another embodiment of the present invention is a memory device including the above-described semiconductor device. [Effects of the Invention]

[0017] It is possible to provide a semiconductor device having a large memory capacity per unit area. It is possible to provide a semiconductor device having a novel structure in which recells are stacked. It is possible to provide a method for driving the semiconductor device.

[0018] Alternatively, a module having the semiconductor device can be provided. It is possible to provide a device or an electronic device having the module. A conductor device may be provided, or a novel module may be provided. Alternatively, a novel electronic device can be provided.

[0019] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description. The above is self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other effects. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 3]FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 5] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 6] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 7] 10 is a timing chart illustrating a method for driving a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A and 1B are schematic diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 10] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 11] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 13] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21]1A and 1B are diagrams illustrating structural analysis of a CAAC-OS and a single-crystal oxide semiconductor by XRD, and a selected-area electron diffraction pattern of a CAAC-OS. [Figure 22] Cross-sectional TEM image of CAAC-OS, as well as planar TEM image and its image analysis. [Figure 23] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 24] Cross-sectional TEM image of a-like OS. [Figure 25] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 26] FIG. 1 is a schematic diagram of a memory device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description, and various modifications in form and details can be easily made by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same symbols are used It is used in common among different drawings. When referring to the same thing, the hatch pattern is used in the same way. In some cases, no particular symbol is given.

[0022] The configurations shown in the following embodiments may be applied or combined as appropriate with other configurations shown in the embodiments. Combinations, substitutions, etc. can be made to form one embodiment of the present invention.

[0023] In the drawings, the size, thickness of the film (layer), or area is exaggerated for clarity. This may be the case.

[0024] In this specification, the terms "film" and "layer" are interchangeable. It is possible to do this.

[0025] Also, voltage is a voltage between a certain potential and a reference potential (for example, ground potential (GND) or source potential Therefore, voltage can be replaced with potential. Generally, potential (voltage) is relative, and the magnitude is relative to a reference potential. Therefore, even if it is described as "ground potential", The potential is not necessarily 0V. For example, the lowest potential in a circuit may be the "ground potential." Or, the intermediate potential in the circuit may be the "ground potential." In this case, the positive potential and the negative potential are defined based on that potential.

[0026] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. It does not indicate the layer order. Therefore, for example, "first" should not be changed to "second" or "third." In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers The term and the ordinal number used to identify an aspect of the present invention may not match.

[0027] In this specification, "A and B are connected" means that "A and B are directly connected." In addition to the above, it also includes things that are electrically connected. Being connected means that there is an object that has some kind of electrical effect between A and B. A means a device that enables the transmission and reception of electrical signals between A and B.

[0028] In this specification, the source of a transistor is a semiconductor film that functions as an active layer. The source electrode is a part of the semiconductor film. The drain of the transistor is a drain region that is a part of the semiconductor film, or The term "gate" refers to the gate electrode connected to the semiconductor film.

[0029] The source and drain of a transistor are determined by the conductivity type of the transistor and the terminals. The name changes depending on the level of the potential applied. Generally, n-channel transistors In a capacitor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. In addition, in a p-channel transistor, the terminal to which a low potential is applied is called the drive The terminal to which the high potential is applied is called the drain, and the terminal to which the high potential is applied is called the source. Explain the connection relationship of a transistor, assuming that the source and drain are fixed. However, in reality, the names of source and drain are interchanged according to the above potential relationship. Bad.

[0030] Unless otherwise specified, in this specification, the off-state current refers to the current when a transistor is in an off state. The off-state refers to the drain current when the n-channel transistor is turned on, unless otherwise specified. In a transistor, the potential difference between the gate and source (V GS ) is lower than the threshold voltage (Vth) In the p-channel transistor, V GS is higher than Vth. For example, , the off-state current of an n-channel transistor is V GS When Vth is lower than The off-state current of a transistor is V GS It may depend on So, the off-state current of the transistor is 10 -21A or less means that the off-state current of the transistor is Flow is 10 -21 V below A GS It may be said that there exists a value of

[0031] The off-state current of a transistor is determined by the potential difference between the drain and source (V DS ) depends on In this specification, the off-state current is V unless otherwise specified. DS The absolute value of is 0 .1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 1 It may represent the off-state current at 2V, 16V, or 20V. V that guarantees the reliability of semiconductor devices containing DS , or the transistor V used in semiconductor devices, etc. DS The term "off-state current" may also refer to the off-state current at

[0032] Even when written as "semiconductor," if the conductivity is sufficiently low, it may be called an "insulator." In addition, the boundary between "semiconductors" and "insulators" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein is also used to refer to "insulator" Similarly, the term "insulator" used in this specification can be interpreted as "semiconductor." It can sometimes be rephrased as "body."

[0033] Also, even if a material is written as a "semiconductor," if the conductivity is sufficiently high, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein is not necessarily a "conductor" Similarly, the term "conductor" used in this specification can be interpreted as "semiconductor." It can sometimes be rephrased as "body."

[0034] The impurities in a semiconductor refer to, for example, anything other than the main component that constitutes the semiconductor. Elements present at concentrations of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the conductor and carrier movement The semiconductor may be an oxide semiconductor, and the crystallinity may decrease. In the case of a conductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1, Group elements, 13th group elements, 14th group elements, 15th group elements, and transition metals other than the main component. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, In the case of oxide semiconductors, impurities such as hydrogen can cause In addition, when the semiconductor is silicon, the characteristics of the semiconductor The impurities that change the value of the valence band include, for example, oxygen, group 1 elements excluding hydrogen, group 2 elements, and group 1 elements. These include Group 3 elements and Group 15 elements.

[0035] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source The distance between the drain electrode and the drain region is called the distance between the In the transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one value, the maximum value, in the region where the channel is formed. , the minimum or average value.

[0036] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the gate electrode overlaps with the electrode (the area where current flows) forms a channel. The length of the region where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. In the detailed description, the channel width is any one value, the maximum value in the region where the channel is formed. , the minimum or average value.

[0037] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width shown in the figure becomes larger, and the effect becomes non-negligible. For example, in transistors with a fine, three-dimensional structure, the side surface of the semiconductor In this case, the ratio of the channel region formed in the top view may be increased. The effective channel width of the channel is actually formed rather than the apparent channel width shown. will be larger.

[0038] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width if the channel conditions are not precisely known. .

[0039] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length is the length of the part where the source and drain face each other in the overlapping region. The above channel width is called "Surrounded Channel Width (SCW)". In this specification, it is simply referred to as the channel width. In some cases, it may refer to the enclosed channel width or apparent channel width. In this specification, when simply referring to a channel width, it may refer to an effective channel width. The channel length, channel width, effective channel width, apparent channel width, and The width of the interstitial channel can be determined by acquiring a cross-sectional TEM image and analyzing the image. Thus, the value can be determined.

[0040] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0041] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to a state in which two lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0042] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0043] (Embodiment 1) In this embodiment, a circuit configuration and operation of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIGS. 1 to 7.

[0044] <Memory Cell> First, the circuit configuration and operation of a memory cell of a semiconductor device, which will be described later, will be explained with reference to FIG. 1A and 1B. Here, FIG. 1A shows the circuit of a memory cell 10. FIG. 1(B) is an example of a circuit diagram showing the configuration in a plan view, and FIG. 1(B) is a three-dimensional view of a semiconductor device to be described later. 1 is an example of a circuit diagram showing a three-dimensional representation of the circuit configuration of a memory cell 10 in accordance with the configuration.

[0045] In the memory cell 10 shown in FIGS. 1A and 1B, the wiring SL and the transistor 1 The source electrode (or drain electrode) of the transistor 1 is electrically connected to the wiring RBL. The drain electrode (or source electrode) of 11 is electrically connected. and the source electrode (or drain electrode) of the transistor 12 are electrically connected, and the wiring WW L and the gate electrode of transistor 12 are electrically connected. The gate electrode of the transistor 11 and the drain electrode (or source electrode) of the transistor 12 are connected to the capacitance element 1 The wiring RWL and the other electrode of the capacitance element 14 are electrically connected. is connected.

[0046] Here, the transistor 12 is, for example, a transistor using an oxide semiconductor. As will be described in detail later, a transistor including an oxide semiconductor has a low off-state current Therefore, when the transistor 12 is turned off, This allows the potential of the gate electrode of the transistor 11 to be maintained for an extremely long period of time. By providing the capacitor 14, the gate electrode of the transistor 11 This makes it easier to hold the charge given to the layer, and also makes it easier to read out the held information.

[0047] The transistor 11 is not particularly limited. From the viewpoint of this, for example, a transformer using polycrystalline silicon or single crystal silicon is It is preferable to use a transistor with a high switching speed, such as a MOSFET.

[0048] In the memory cell 10 shown in FIGS. 1A and 1B, the gate electrode of the transistor 11 By taking advantage of the feature that the potential can be maintained, information can be written, stored, and read as follows: It is possible to issue.

[0049] First, writing and holding of information will be described. First, the potential of the wiring WWL is set as follows: The transistor 12 is turned on by applying a potential that turns the transistor 12 on. As a result, the potential of the wiring WBL is The gate electrode of the transistor 11 and one electrode of the capacitor 14 are electrically connected. Node FN, that is, the gate of transistor 11. A predetermined charge is applied to the electrode (writing). Here, two different potentials are applied. Charge (hereinafter, the charge that gives the low potential is called charge Q L , the charge that gives the high potential is the charge Q H (That is, Any of the three or more different potentials can be applied. Then, the potential of the wiring WWL is applied to the transistor By setting the potential at which the transistor 12 is turned off, the transistor The charge given to the gate electrode of the transistor 11 is held (retained).

[0050] Since the off-state current of the transistor 12 is extremely small, the voltage of the gate electrode of the transistor 11 is The load is held for a long period of time.

[0051] Next, reading of information will be described. When a predetermined potential (constant potential) is applied to the wiring SL, In this state, when an appropriate potential (read potential) is applied to the wiring RWL, the gate of the transistor 11 The wiring RBL takes on different potentials depending on the amount of charge held in the electrode. If the transistor 11 is an n-channel type, then the gate electrode of the transistor 11 is connected to Q H is given The apparent threshold voltage V th_H is connected to the gate electrode of transistor 11. L is given The apparent threshold voltage V th_L This is because the The threshold voltage of the switch is the voltage at which the transistor 11 is switched from the "off state" to the "on state" or This refers to the potential of the wiring RWL required to change from the "on state" to the "off state." Therefore, the potential of the wiring RWL is Vth_H and V th_L By setting the potential between V0, The charge applied to the gate electrode of the transistor 11 can be determined. For example, TeQ H is given, the potential of the wiring RWL is V0 (>V th_H ) then, Tiger Transistor 11 is in the "ON state." Q L When the potential of the wiring RWL is V 0( <V th_L ), the transistor 11 remains in the "off state." If transistor 11 is a p-channel type, Q L is given, it is "on" Then, Q H If the wiring RBL By observing the potential, the stored information can be read out.

[0052] When memory cells are arranged in a matrix, the information of the desired memory cell is In this way, it is necessary to read only the information of a specific memory cell. To prevent other memory cells from reading information, a transistor is placed between each memory cell. When the memory cells 11 are connected in series, the memory cells that are not the object of reading are For the wiring RWL, the transistor 11 is in the "ON state" regardless of the state of the gate electrode. The potential at which V th_L In this case, the wiring R WL to V th_L When a larger potential is applied, the transistor 11 A potential is applied to the gate electrode of the transistor 11 so that the transistor 11 is in the "on state." The node FN can be turned on independently of the data stored in the node FN.

[0053] Next, the rewriting of information will be explained. That is, the potential of the wiring WWL is changed by turning on the transistor 12. This turns on the transistor 12 by setting the potential of the wiring WBL ( A potential related to new information is applied to the gate electrode of the transistor 11 and the capacitor 14. After that, the potential of the wiring WWL is set to a potential that turns off the transistor 12. By turning off the transistor 12, the gate electrode of the transistor 11 is The charge related to the information is given.

[0054] In this way, the semiconductor device according to the disclosed invention can directly write information again. Therefore, when erasing flash memory, This eliminates the need to extract charge from the floating gate using the high voltage required for This makes it possible to suppress a decrease in the operating speed. In other words, high-speed operation of the semiconductor device is realized. do.

[0055] The drain electrode (or source electrode) of the transistor 12 and the The node FN, to which the gate electrode and one electrode of the capacitor 14 are electrically connected, is a nonvolatile The floating gate of a floating gate transistor used as a memory element When the transistor 12 is off, the node FN is connected to the insulator. The node FN can be considered as being buried, and charge is held in the node FN. The off-state current of the transistor 12 is 100,000 times that of a transistor made of a silicon semiconductor. Because the charge stored in node FN is less than one-fifth of the In other words, the transistor 12 using an oxide semiconductor can store information without power supply. It is possible to realize a storage device capable of long-term retention.

[0056] For example, if the off-state current of the transistor 12 at room temperature (25° C.) is 10 zA (1 zA (zepto)), ampere) is 1 x 10 -21 A) or less, and the capacitance value of the capacitance element 14 is about 10 fF. If so, at least 10 4 It is possible to hold data for more than 10 seconds. It goes without saying that this varies depending on the transistor characteristics and capacitance value.

[0057] In addition, in the memory cell 10 shown in this embodiment, a conventional floating gate type The problem of deterioration of the gate insulating film (tunnel insulating film) that has been pointed out in transistors In other words, there is no problem with injecting electrons into the floating gate, which has been a problem in the past. This solves the problem of deterioration of the gate insulating film during writing. This means that there is no limit to the number of times. The high voltage required for writing and erasing data in a conventional transistor is also unnecessary.

[0058] In the memory cell 10, the node FN is connected to a floating gate of a flash memory or the like. The floating gate of the present embodiment functions in the same way as the floating gate of a gate-type transistor. FN has fundamentally different characteristics from floating gates such as flash memory. In flash memory, the potential applied to the control gate is high, so the potential In order not to affect the floating gates of adjacent cells, the spacing between cells is This is one of the factors that hinders the high integration of semiconductor devices. The reason for this is the flash effect, which generates a tunnel current by applying a high electric field. This is due to the fundamental principles of memory.

[0059] On the other hand, the semiconductor device according to this embodiment has a transistor switch using an oxide semiconductor. It operates by switching and does not use the principle of charge injection by tunnel current as described above. That is, unlike flash memory, a high electric field for injecting charges is not required. Therefore, there is no need to consider the influence of the high electric field caused by the control gate on adjacent cells. This makes it easier to achieve high integration.

[0060] In order to increase the memory capacity of a semiconductor device, in addition to high integration, a method of multi-level data storage is also required. For example, it is possible to write three or more levels of information into each memory cell. This allows for a larger memory capacity than when writing binary (1-bit) information. For example, the charge Q L , a charge Q that gives a high potential H In addition By applying a charge Q that gives another potential to the gate electrode of the transistor 11, multi-values ​​are realized. Multi-valued data can be expressed as, for example, 4-valued (2 bits), 8-valued (3 bits), It is sufficient to be able to hold data such as 16 values ​​(4 bits), 16 values ​​(4 bits), etc.

[0061] The above explanation is for n-type transistors (n-channel transistors) that use electrons as carriers. This is about using a transistor that uses holes as carriers instead of an n-type transistor. Alternatively, a p-type transistor may be used.

[0062] In the memory cell array described later, the memory cell 10 has a transistor as shown in FIG. The channel length direction of the transistor 11, the channel length direction of the transistor 12, the wiring SL, the wiring R It is preferable that the wiring BL, the wiring WBL, the wiring RWL and the wiring WWL are arranged to intersect three-dimensionally. It's nice.

[0063] The channel length direction of the transistor 11 and the channel length direction of the transistor 12 are approximately perpendicular to each other. It is also preferable that the transistor is disposed on the upper surface of the substrate on which the memory cell 10 is provided. The channel length direction of the transistor 11 is approximately perpendicular, and the channel length direction of the transistor 12 is approximately parallel. It is preferable that there is.

[0064] In addition, the wiring WWL and the wiring RWL are approximately It is preferable that the wiring is perpendicular to the upper surface of the substrate on which the memory cell 10 is provided. RBL, wiring SL and wiring WBL are approximately perpendicular, and wiring WWL and wiring RWL are approximately parallel. It is preferable that there is.

[0065] By configuring the memory cell 10 in this way, as will be described later, a plurality of memory cells 1 0 can be stacked in series with each transistor 11 This increases the storage capacity per unit area according to the number of stacked memory cells 10. It is possible to provide a semiconductor device that can

[0066] As described above, the transistor 11 is arranged so that the channel length direction is perpendicular to the upper surface of the substrate. By configuring the circuit so that the gate electrode surrounds the semiconductor, and the source and drain are Vertical transistors (SGTs) are placed above and below the transistor. The minimum processing size can be easily reduced. F, the area occupied by a standard planar transistor is 8F. 2 whereas, SGT occupies 4 floors 2 This further reduces the storage capacity per unit area. The amount can be increased.

[0067] <Memory Cell Array> Next, a more specific circuit configuration and operation using the circuit shown in Figure 1 will be explained in Figure 2. The description will be made with reference to FIG.

[0068] A three-dimensional memory cell array 40, a selection transistor array 50, a drive circuit 51, and a read A block circuit of a semiconductor device having a read circuit 52, a drive circuit 53, and a drive circuit 54. An example of the path diagram is shown in Figure 2. In the following, as shown in Figure 2, the x-axis, y-axis, and z-axis For convenience, an orthogonal coordinate system consisting of the following will be set and explained.

[0069] Also, since the diagram in Figure 2 is somewhat complicated, the 3D memory cell array is shown in Figure 3. 4 shows an example of a block circuit diagram of only the three-dimensional memory cell array 40. An example of a block circuit diagram of the included two-dimensional memory cell array 30 [1] is shown. 4 shows an example of a block circuit diagram of a two-dimensional memory cell array 30 [1]. Some of the z-axis configurations are represented pseudo-on the xy plane. A transistor array 50, a drive circuit 51, a read circuit 52, a drive circuit 53, and a drive circuit 5 shows an example of a block circuit diagram of the circuit 54.

[0070] A selection transistor array 50, a drive circuit 51, a read circuit 52, a drive circuit 53, and The drive circuit 54 is formed on a substrate surface that is approximately parallel to the xz plane. A three-dimensional memory cell array 40 is formed on the substrate 50 .

[0071] The three-dimensional memory cell array 40 is composed of m1×m2×m3 (m1, m2, and m3 are natural numbers) It has memory cells 10, m1 in the x-axis direction, m2 in the y-axis direction, and m3 in the z-axis direction. The memory cells 10 are arranged in a rectangular parallelepiped shape. Coordinates are added to the memory cells 10 (1,1,1) to (m1,m2,m3). There are cases where this happens.

[0072] As shown in FIG. 3, the three-dimensional memory cell array 40 is provided extending in the y-axis direction. The m1 × m3 wirings SL, wirings RBL and wirings WBL are arranged in the x-axis direction. The wiring RWL and the wiring WWL are arranged in a total of m2 × m3. The wiring SL is assigned coordinates in the x-axis direction and the z-axis direction, and the wiring SL[1,1] to [m1,m3 Similarly, the wiring RBL[1,1] to [m1,m3], the wiring W It may be expressed as BL[1,1] to [m1,m3]. The line RWL is assigned coordinates in the y-axis and z-axis directions, and the wiring RWL[1,1] to [m2,m3 Similarly, the wiring WWL[1,1] to [m2,m3] This may be indicated.

[0073] The three-dimensional memory cell array 40 is composed of m3 two-dimensional memories arranged in the z-axis direction. As shown in FIG. 2, the two-dimensional memory cell array 30 The coordinates in the z-axis direction are added to the two-dimensional memory cell arrays 30[1] to [m3]. This may occur.

[0074] Each two-dimensional memory cell array 30 is made up of m1 memory cells arranged in the x-axis direction. As shown in FIG. 2, the memory cell string 20 is The memory cell strings 20[1,1] to [m1, The memory cell strings 20 are arranged in the y-axis direction. Each of the two-dimensional memory cell arrays 3 has m2 memory cells 10. 0 is composed of m1 memory cell strings 20, so the two-dimensional memory cell array 3 In the example shown in FIG. 0, m1 memory cells 10 are arranged in the x-axis direction and m2 memory cells 10 are arranged in the y-axis direction in a matrix. This means that...

[0075] As shown in FIG. 1B, the memory cell 10 includes a transistor 11, a transistor 12, and a and a capacitance element 14, and However, as shown in FIGS. 2 to 4, each memory cell string 20 is electrically connected to The constituent memory cells 10 are connected in series in the y-axis direction in the transistors 11. Therefore, memory cell (i1,1,i3) (i1 is a natural number between 1 and m1, and i3 is a natural number between 1 and m1) ) is connected to the wiring RBL[ In addition, only memory cells (i1, m2, i3) are connected to other memory cells. The other memory cells 10 are connected to the wiring SL[i1, i3] without going through the memory cell 10. The wiring RBL and the wiring SL and electrically connected to each other.

[0076] Here, taking the two-dimensional memory cell array 30[1] shown in FIG. 4 as an example, The structure of the two-dimensional memory cell array 30 [1] shown in FIG. wirings SL[1,1] to [m1,1] and m1 wirings RBL[1,1] to [m1 ,1], m1 wirings WBL[1,1] to [m1,1], and m2 wirings RWL[1 ,1] to [m2,1], m2 wires WWL[1,1] to [m2,1], and m1× The memory cells 10 (1,1,1) to (m1,m2,1) are arranged in a matrix of m2. ) and.

[0077] In the following, the matrix wiring and memory cells of the two-dimensional memory cell array 30 are For example, the same two-dimensional memory cell array 30 In this case, a plurality of memory cells 10 having the same y coordinate are referred to as memory cells 10 in the same row. In the same two-dimensional memory cell array 30, the x coordinates are the same. A plurality of memory cells 10 (which can also be said to constitute the same memory cell string 20) can be expressed as the memory cells 10 in the same column. In the following, the two-dimensional memory cell shown in Fig. 4 etc. In the Array 30, the rows are called the 1st row, 2nd row, ... 2nd row from the bottom, and the columns are called the 2nd row from the left. These are called the first column, second column, ... m1st column.

[0078] The wiring SL[i1,1] is connected to the corresponding transistor of the memory cell 10(i1,m2,1). The wiring RBL[i1,1] is electrically connected to the source electrode of the transistor 11. The drain electrode of the corresponding transistor 11 of the memory cell 10 (i1,1,1) is electrically connected to the drain electrode of the corresponding transistor 11. To be continued.

[0079] The wiring WBL[i1,1] is connected to the memory cells 10(i1,1,1) to (i The source electrodes of the corresponding transistors 12 (m1, m2, 1) are electrically connected to the source electrodes of the corresponding transistors 12. In other words, the source electrodes of the transistors 12 of the memory cells 10 in the same column are connected to the wiring WB Electrically connected to L.

[0080] The wiring RWL[i2,1] (i2 is a natural number between 1 and m2) is In addition to the electrodes of the corresponding capacitance elements 14 of the resistors 10(1,i2,1) to (m1,i2,1), In other words, the electrodes of the capacitors 14 of the memory cells 10 in the same row are electrically connected to each other. The other one is electrically connected to the wiring RWL in the same row.

[0081] The wiring WWL[i2,1] is connected to the memory cells 10(1,i2,1) to (m 1, i2, 1) are electrically connected to the gate electrodes of the corresponding transistors 12. In other words, the gate electrodes of the transistors 12 of the memory cells 10 in the same row are connected to the wiring W Electrically connected to L.

[0082] Memory cell 10(i1,i 2A ,1)(i 2A denotes a natural number between 1 and m2-1. The source electrode of the transistor 11 of the memory cell 10 (i1,i 2A +1,1) Tiger In other words, in the same column, the drain electrodes of the transistors 11 are electrically connected to the drain electrodes of the transistors 11. The memory cells 10 are connected to each other by the source electrode of the transistor 11 and the drain of the transistor 11. The input electrode is electrically connected to the output electrode.

[0083] In this way, between the wiring SL[i1,1] and the wiring RBL[i1,1], transistor 1 1, the memory cells 10 (i1,1,1) to (i1,m2,1) connected in series Thus, a memory cell string 20[i1,1] is formed.

[0084] In this way, the memory cell string 20 includes a plurality of memory cells 10, The transistors 11 can be stacked so that they are connected in series. The ring 20 has a storage capacity of the memory cell string 20 that varies depending on the number of stacked memory cells 10. Therefore, the number of memory cells 20 can be increased. The dimensional memory cell array 40 has a memory capacity per unit area that varies depending on the number of stacked memory cells 10. The capacity can be increased.

[0085] Here, the structure of the selection transistor array 50 shown in FIG. The transistor array 50 is made up of m1×m3 select transistor cells 6 arranged in a matrix. 0, m1 wires RBL and WBL extending in the z-axis direction, and The selection transistor has m3 wirings SG1 and SG2 extending in the direction of the arrow. The select transistor cell 60 is assigned coordinates on the xz plane, and the select transistor cell 60(1,1) In addition, the wiring RBL and wiring WBL are in the x-axis direction. The coordinates are given as wiring RBL[1] to [m1], wiring WBL[1] to [m1], etc. In addition, the wiring SG1 and wiring SG2 are given coordinates in the z-axis direction, and the wiring S The wirings may be indicated as G1[1] to [m3], and wirings SG2[1] to [m3].

[0086] Each select transistor cell 60 includes a transistor 61 and a transistor 62 . In the select transistor cell 60(i1, i3), the wiring RBL[i1] and the transistor The drain electrodes (or source electrodes) of the memory cell strings [ The wiring RBL[i1,i3] and the source electrode (or drain) of the transistor 61 The wiring SG1[i3] and the gate electrode of the transistor 61 are electrically connected. In the select transistor cells 60 (i1, i3), the The line WBL[i1] and the drain electrode (or source electrode) of the transistor 62 are electrically connected. The wiring WBL[i1,i3] of the memory cell string [i1,i3] and the transistor The source electrode (or drain electrode) of the capacitor 62 is electrically connected to the wiring SG2 [i3]. The gate electrodes of the transistors 62 are electrically connected.

[0087] In this way, each selection transistor cell 60 is set corresponding to each memory cell string 20. The wiring RBL[i1] and the wiring RBL[i1,1] to [i1,m3] are connected. The on state is selected by the transistor 61 of each selection transistor cell 60, and the wiring WBL[i1] and the wiring WBL[i1,1] to [i1,m3] are connected to each of the select transistor cells 6 0 can be selected by transistor 62.

[0088] As shown in FIG. 5, a drive circuit 51 and a read circuit 52 are arranged around the selection transistor array 50. The drive circuit 51 is provided with a wiring RBL[1] to [m1] are connected to the wirings WBL[1] to [m1]. The wirings RBL[1] to [m1] are also connected to the read circuit 52. Although not shown, the driving circuit 53 includes wirings RWL[1,1] to [m2,m3] and wirings WW L[1,1] to [m2,m3] are connected to the driving circuit 54. 1[1] to [m3] are connected to wiring SG2[1] to [m3].

[0089] An example of a readout circuit that can be used for the readout circuit 52 will be described below with reference to FIG. FIG. 6(A) shows a schematic diagram of the readout circuit. It has a transistor and a sense amplifier circuit.

[0090] When reading, terminal A is connected to the wiring RBL to which the memory cell to be read is connected. A bias potential Vbias is applied to the gate electrode of the transistor, and The potential of the electrode is controlled.

[0091] The memory cell 10 exhibits different electrical resistances depending on the data stored therein. When the transistor 11 of the selected memory cell 10 is in an on state, it is in a low resistance state. When the transistor 11 of the selected memory cell 10 is in an off state, the memory cell 10 is in a high resistance state.

[0092] When the memory cell is in a high resistance state, the potential at terminal A becomes higher than the reference potential Vref, and the sensor The amplifier outputs a potential (data "0") corresponding to the potential of terminal A. When the resistance is low, the potential of terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit outputs a potential (data "1") corresponding to the potential of terminal A.

[0093] Thus, by using the read circuit, data can be read from the memory cell. Note that the read circuit shown in this embodiment is an example. Other known circuits may also be used. Further, the read circuit may have a precharge circuit. Instead of the reference potential Vref, it may be configured to be connected to a reference memory cell.

[0094] Fig. 6(B) shows a differential sense amplifier, which is an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the difference between Vin(+) and Vin(-). If Vin(+) > Vin(-), Vout is generally a High output; if Vin(+) < Vin(-), Vout is generally a Low output.

[0095] Fig. 6(C) shows a latch-type sense amplifier, which is an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, signal Sp is set to High, signal Sn is set to Low, and the power supply potential (Vdd) is cut off. Then, the potentials for comparison are applied to V1 and V2. After that, when signal Sp is set to Low and signal Sn is set to High and the power supply potential (Vdd) is supplied, if the potentials for comparison V1in and V2in are in the relationship V1in > V2in, the output of V1 is High and the output of V2 is Low; if they are in the relationship V1in < V2in, the output of V1 is Low and the output of V2 is High. Using such a relationship, the difference between V1in and V2in can be amplified.

[0096] In the above, the drive circuit 51, the read circuit 52, the drive circuit 53, and the drive circuit 54 are provided independently for each function, but the semiconductor device shown in this embodiment The present invention is not limited to this, and a plurality of circuits may be integrated into one circuit. A circuit 51, a read circuit 52, a drive circuit 53, a drive circuit 54, and circuits connected to each circuit. The wiring arrangement is not limited to the configuration shown in FIG. 5, and may be set appropriately according to the semiconductor device. stomach.

[0097] In addition, the wirings SL[1,1] to [m1,m3] are provided separately in FIG. However, the present invention is not limited to this configuration. For example, a plurality of wirings SL may be electrically connected. Alternatively, all the wirings SL may be electrically connected. 1, m3] is connected to a low power supply potential that supplies, for example, ground potential GND or 0V. Just leave it there.

[0098] In the semiconductor device shown in FIG. 2, a three-dimensional memory cell is provided on the select transistor array 50. The semiconductor device shown in this embodiment is configured to have a memory cell array 40. For example, a selection transistor array may be provided on the three-dimensional memory cell array 40. In this case, the transistor of the select transistor cell 60 The transistor 61 and the transistor 62 are made of, for example, an oxide semiconductor, similar to the transistor 12. It is sufficient to set it up.

[0099] In addition, peripheral circuits such as a drive circuit 51, a read circuit 52, a drive circuit 53, and a drive circuit 54 are A part of the circuit may be provided under the three-dimensional memory cell array 40. For example, A readout circuit may be provided in a matrix corresponding to the ring 20. In this case, the readout circuit and the selection transistor cell 60 are stacked in a matrix. That's fine.

[0100] Data writing, retention, and reading are basically the same as in Figure 1. In the three-dimensional memory cell array 40, first, the two-dimensional memory cell array 30[1] After selecting one of [m1] to [m2], data is written or read. , writing and reading data in the two-dimensional memory cell arrays 30[1] to [m3] This is done at least row by row. In other words, the specific write operation is as follows: In this example, the node FN is set to a potential V2 (a potential lower than the power supply potential VDD). This section explains the case where either the reference potential GND (sometimes expressed as 0V) is applied. However, the relationship of the potential applied to the node FN is not limited to this. When the reference potential GND is applied to the node FN, the data retained is data "1". The data held when this happens is data "0." Also, the reference potential GND is applied to the wiring SL. This shall be the case.

[0101] In writing data, first, one of the two-dimensional memory cell arrays 30 is selected. In selecting the two-dimensional memory cell array 30, the potential of the corresponding wiring SG2 is set to V1 (for example, For example, a transistor 62 electrically connected to the wiring is turned on as a power supply voltage Vdd. Lines WBL[1] to [m1] and the wiring WB included in the selected two-dimensional memory cell array 30 At this time, the potential of the unselected wiring SG2 is set to GND (0V), and the wiring Lines WBL[1] to [m1] and wiring WB included in the unselected two-dimensional memory cell array 30 L is in a non-conductive state.

[0102] Next, in the selected two-dimensional memory cell array 30, the memory cells in the row to be written are The potential of the wiring WWL connected to 10 is set to V3 (a potential higher than V2, for example, VDD). The transistor 12 of the memory cell 10 is turned on. The memory cell 10 stores data "0". When writing, GND is applied to the wiring WBL as a write potential, and When data "1" is written, a potential V2 is applied to the wiring WBL as a write potential. Here, the potential of the wiring WWL is V3, so the potential V2 can be applied to the node FN. It is possible.

[0103] To retain data, the potential of the wiring WWL connected to the memory cell 10 to be retained is set to GND. This is done by turning off the transistor 12 of the memory cell 10. When the potential of WWL is fixed to GND, the potential of node FN is fixed to the potential at the time of writing. That is, when the potential V2, which is data "1", is applied to the node FN, The potential of node FN becomes V2, and if GND, which is data "0", is applied to node FN, The potential of the FN terminal is GND.

[0104] In addition, since GND is given to the wiring WWL, either data "1" or data "0" can be written. Even if a deviation is written, the transistor 12 is in an off state. Since the off-state current is extremely small, the charge in the gate electrode of the transistor 11 remains constant for a long time. In this way, the node FN of the memory cell 10 to be held is set to the write potential. The corresponding data can be retained.

[0105] In reading data, first, one of the two-dimensional memory cell arrays 30 is selected. In selecting the two-dimensional memory cell array 30, the potential of the corresponding wiring SG1 is set to V1 (for example, For example, a transistor 61 electrically connected to the wiring is turned on as a power supply voltage Vdd. Lines RBL[1] to [m1] and the wiring RB included in the selected two-dimensional memory cell array 30 At this time, the potential of the unselected wiring SG1 is set to GND (0V), and the wiring Lines RBL[1] to [m1] and wiring RB included in the unselected two-dimensional memory cell array 30 L is in a non-conductive state.

[0106] Next, in the selected two-dimensional memory cell array 30, the memory cells in the row to be read are The potential of the wiring RWL connected to 10 is set to GND, and the other electrode of the capacitor 14 connected to The potential of the line connected to the memory cells 10 in the row that is not the target for reading is set to GND. The potential of the line RWL is set to V5 (for example, VDD), and the other potential of the electrode of the capacitance element 14 connected to the line RWL is set to V6 (for example, VDD). Let the place be V5.

[0107] If the potential of the wiring RWL connected to the memory cell 10 in the row to be read is GND, then A potential V2 representing data "1" is applied to the node FN of the memory cell 10 to be read. On the other hand, when the node FN has data "0", the transistor 11 is turned on. If the GND is applied, the transistor 11 is in an off state.

[0108] In addition, the potential of the wiring RWL connected to the memory cells 10 in the row that is not the target for reading is set to V5 Then, if data "1" is written to the memory cell 10 that is not the target for reading, In both cases where data "0" is written, the transistor 11 is in the ON state.

[0109] A read potential (for example, VDD) is applied to the wiring RBL. When the transistor 11 of the cell 10 is in the on state, the wiring RBL and the wiring SL are electrically connected. In response to this, the potential of the wiring RBL drops. When the switch 11 is in the off state, the wiring RBL and the wiring SL are not electrically connected. In this way, the read potential of the wiring RBL is maintained. The data in the target memory cell can then be read.

[0110] As a driving method, it is preferable to provide a batch erase operation for data for each block. For example, the two-dimensional memory cell array 30 may be one block. The two-dimensional memory cell array 30 to be erased is selected in the same manner as in the data write. The wiring WWL connected to the two-dimensional memory cell array 30 is turned on. This allows one block of data to be erased at once.

[0111] FIG. 7 shows an example of a timing chart relating to the detailed operation of the semiconductor device shown in FIG. The timing chart shown in FIG. 7 shows the simultaneous erasure of the two-dimensional memory cell array 30[1], Writing the first row of the two-dimensional memory cell array 30[1] and the two-dimensional memory cell array 30 This shows the relationship between the potentials of each wiring when reading the first row of [1]. The collective erasure of the two-dimensional memory cell array 30[1] is performed by This is the operation to erase the data written in modules 10 (1,1,1) through (m1,m2,1). The first row of the two-dimensional memory cell array 30[1] is written in the two-dimensional memory cell array 30. Data "1" is written to the memory cell in the first row and first column of [1], and the other columns of the first row ( This is the operation of writing data "0" to the memory cells in the second to m1th columns. The first row of the cell array 30[1] is read from the first row of the two-dimensional memory cell array 30[1]. This is the operation to read out the data written in the first row and first column. The data "1" is stored in the memory cell of the first row, and the data "2" is stored in the memory cells of the other columns (the second column to the m1th column) of the first row. The data "0" is stored.

[0112] It is assumed that the read circuit 52 is provided with the read circuit shown in FIG. 6(A). do.

[0113] In the batch erase of the two-dimensional memory cell array 30[1], first, By applying a potential V1, the transistors of the select transistor cells 60(1,1) to (m1,1) are turned on. The switch 62 is turned on, and the wirings WBL[1] to [m1] are connected to the corresponding wirings WBL[1,1 ] to [m1,1] are connected to GND. Then, the transistors 62 of the select transistor cells 60(1, 2) to (m1, m3) are turned on. and the wirings WBL[1] to [m1] are switched to the corresponding wirings WBL[1,2] to [m In this way, the two-dimensional memory is set as the target for the batch erase operation. Select the memory cell array 30[1].

[0114] In the two-dimensional memory cell array 30[1], the wiring WWL[1,1] to the wiring WWL[ m2,1] to turn on the transistors 12 in the first row to the m2-th row. At the same time, the wirings WBL[1] to [m1] are connected to GND, and the nodes F Set the potential of N to GND.

[0115] The wiring WW electrically connected to the two-dimensional memory cell arrays 30[2] to [m3] L[1,2] to [m2,m3] are connected to GND, and memory cells 10(1,1,2) to ( The potential of the node FN of each of the nodes m1, m2, and m3 is maintained.

[0116] In writing the first row of the two-dimensional memory cell array 30[1], first, The two-dimensional memory cell is used as the target for the write operation in the same manner as the bulk erase of the array 30[1]. Select Array 30 [1].

[0117] In the two-dimensional memory cell array 30[1], a potential V3 is applied to the wiring WWL[1,1]. The transistors 12 in the first row are turned on, and the wirings WWL[2,1] to [m2,1] are turned on. The transistors 12 in the second row to the m2th row are turned off by using GND. A potential V2 is applied to WBL[1], and the wirings WBL[2] to [m1] are set to GND. The wiring RWL[1,1] to [m2,1] should be set to GND.

[0118] As a result, the node of the memory cell 10 in the first row and first column of the two-dimensional memory cell array 30[1] The potential V2 is applied to the node FN, that is, the data "1" is written. , 0V is applied to the nodes FN in the first row, second column to the m1-th column of the two-dimensional memory cell array 30[1]. is given, that is, data "0" is written.

[0119] As with the collective erasure of the two-dimensional memory cell array 30[1], Wiring WWL[1,2] to [m2,m3] electrically connected to I30[2] to [m3] ] is set to GND, and the nodes F The potential of N is maintained.

[0120] In the first row readout of the two-dimensional memory cell array 30[1], first, the wiring SG1[ 1] is applied with a potential V1 to activate the transistors of the select transistor cells 60(1,1) to (m1,1). The transistor 61 is turned on, and the wirings RBL[1] to [m1] are connected to the corresponding wirings RBL[ 1,1] to [m1,1]. Also, the wiring SG1[2] to [m3] are connected to the G As ND, the transistors 6 of the select transistor cells 60(1, 2) to (m1, m3) 1 is turned off, and the wirings RBL[1] to [m1] are connected to the corresponding wirings RBL[1,2] to In this way, the two read operations are performed. 3. Select the 3-dimensional memory cell array 30[1].

[0121] In the two-dimensional memory cell array 30[1], the memory cell 10 in the first row to be read The wiring RWL[1,1] connected to is set to GND. A potential V4 is applied to the wiring RWL[2,1] to [m2,1] connected to the cell 10. The transistor 11 of the memory cell 10 is turned on.

[0122] Here, the bias potential Vbias of the read circuit shown in FIG. 6A is changed from the potential Vdd to G The wiring RBL is connected to a wiring to which a power supply potential Vdd is supplied as ND.

[0123] As a result, the memory cell 10 (1,1,1) in which data "1" is written is The wiring RBL[1] connected to the wiring SL[1,1] is electrically connected to the wiring SL[1,1], and the potential drops. , the memory cells 10(2,1,1) to (m) in which data “0” is written The wirings RBL[2] to [m1] connected to the wirings SL[2,1] to [ m1,1] and is therefore non-conductive, so the potential is Vdd.

[0124] The wiring WWL[1,1] to [m2,m3] are connected to GND, and the memory cell 10 (1 , 1, 1) to (m1, m2, m3) hold the potentials of the nodes FN.

[0125] The above explanation is for the case where an n-type transistor using electrons as carriers is used. However, instead of an n-type transistor, a p-type transistor that uses holes as carriers is used. In this case, the operation of the transistor is reversed, so the applied potential can be set appropriately. That's fine.

[0126] In the above-described method for driving a semiconductor device, binary (1-bit) data is stored in a memory cell. The above explanation was given for the case of writing data, but it is also possible to write three or more levels of information into one memory cell. For example, a memory cell may be configured to store four values ​​(2 bits), eight values ​​(3 bits), or ), 16-value (4-bit) data, etc. may be held.

[0127] In the semiconductor device described in this embodiment, the off-state current of a transistor including an oxide semiconductor is Because it is extremely small, it can be used to retain memory contents for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the refresh operation is shortened. Since the frequency can be reduced to an extremely low level, power consumption can be reduced significantly. In addition, even if there is no power supply (however, it is desirable that the potential is fixed), Even if the memory card is used, it is possible to retain the stored contents for a long period of time.

[0128] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem of element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. Therefore, the problem of deterioration of the gate insulating layer due to electron extraction does not occur. In the semiconductor device according to the present invention, the rewritable circuit which has been a problem in the conventional nonvolatile memory is There is no limit to the number of transistors, and reliability is dramatically improved. Since information is written depending on the state, high-speed operation can be easily achieved.

[0129] Furthermore, transistors using materials other than oxide semiconductors can operate at sufficiently high speeds. Therefore, by using this in combination with a transistor using an oxide semiconductor, It is possible to sufficiently ensure high speed of the operation of the semiconductor device (for example, the operation of reading information). In addition, transistors using materials other than oxide semiconductors can be used in various applications where high-speed operation is required. It is possible to suitably realize the various circuits (logic circuits, drive circuits, etc.).

[0130] In this way, transistors using materials other than oxide semiconductors (or, more broadly, transistors using sufficiently high transistors that can operate at high speed) and transistors that use oxide semiconductors (or, in a broader sense, By integrating a transistor with a sufficiently low off-state current, It is possible to realize a semiconductor device having the above structure.

[0131] Furthermore, in the semiconductor device shown in this embodiment, by stacking memory cells, The memory capacity per unit area can be increased according to the number of layers. In addition, the memory cell can achieve the above-mentioned excellent characteristics, and furthermore, it has the same characteristics as conventional memories. It is possible to provide a semiconductor device having a memory capacity per unit area as large as or larger than that of the conventional semiconductor device. In addition, in the semiconductor device described in this embodiment mode, memory cells are stacked as described above to form a unit. By increasing the storage capacity per area, it is possible to achieve 1TB or more, 5TB or more, It will also be possible to provide storage devices with storage capacities of 10TB or more.

[0132] As described above, the configurations, methods, etc. shown in this embodiment may be different from the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combinations.

[0133] (Embodiment 2) In this embodiment, the structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. This will be explained using:

[0134] <Memory cell configuration> First, the configuration of the memory cell 10 shown in the previous embodiment will be explained using FIGS. 8(A) to 8(C). and explain.

[0135] The memory cell 10 shown in FIGS. 8A to 8C includes a transistor 11, a transistor 12 and a capacitor element 14. FIG. 8(A) is a top view of the memory cell 10. FIG. 8(B) 8(A) is a cross-sectional view corresponding to the dashed line A1-A2 in FIG. 8(A), and FIG. 8(C) is a cross-sectional view corresponding to the dashed line A1-A2 in FIG. This is a cross-sectional view corresponding to the dashed line A3-A4 in the area indicated by the dashed line A1-A2. The dashed line A3 indicates the structure of the transistor 12 in the channel length direction. The region indicated by -A4 shows the structure of the transistor 12 in the channel width direction. The channel length direction of the transistor 12 is the direction of the source (source region or source electrode) The direction in which carriers move between the drain and the drain (drain region or drain electrode) The channel width direction of the transistor 12 is the channel width direction in a plane parallel to the substrate. It means the direction perpendicular to the longitudinal direction.

[0136] Here, the semiconductor material of the transistor 11 and the semiconductor material of the transistor 12 are different materials. For example, the semiconductor material of the transistor 11 is preferably a material other than an oxide semiconductor. The semiconductor material is a semiconductor material (such as silicon), and the semiconductor material of the transistor 12 is an oxide semiconductor. A transistor using a material other than an oxide semiconductor, such as polycrystalline silicon, can be On the other hand, transistors using oxide semiconductors have the following characteristics: It allows for long-term charge retention.

[0137] Note that the above transistors are all n-channel transistors. However, it goes without saying that p-channel transistors can also be used. The technical essence of the present invention is to provide a semiconductor device that can sufficiently suppress the off-state current, such as an oxide semiconductor, in order to retain data. The advantage of using semiconductor materials for the transistor 12 is that they can be reduced to a low level. The specific configuration of the semiconductor device, such as the materials used in the device and the structure of the semiconductor device, is shown here. There is no need to limit it to anything.

[0138] The transistor 11 includes a conductor 108b, an insulator 132, a semiconductor 134, and an insulator 135. The insulator 132, the semiconductor 134, and the insulator 136 are insulator 104, conductive The conductive body 108b, the insulator 116, and the insulator 118 are formed in cylindrical openings. The insulator 132 is formed in a cylindrical shape in contact with the inner wall of the opening, and the semiconductor 134 is The insulator 136 is formed in a cylindrical shape inside the semiconductor 134. The insulator 132, the semiconductor 134, and the insulator 136 form the memory cell 10. The semiconductor 134 is formed to extend substantially perpendicular to the upper surface of the substrate on which it is provided. The insulator 136 is not provided inside the insulator 132, and the columnar semiconductor 134 is provided inside the insulator 132. It may also be possible to use the following.

[0139] Here, the conductor 108b functions as the gate of the transistor 11, and the insulator 13 2 functions as a gate insulating film of the transistor 11, and the semiconductor 134 functions as a gate insulating film of the transistor 11. The active layer 11 functions as a source and a drain. The region 134a overlapping the body 108b functions as a channel forming region of the transistor 11, The region 134b that does not overlap with the conductor 108b serves as the source or drain of the transistor 11. It works like this.

[0140] In this way, the transistor 11 is configured such that the region 134 a of the semiconductor 134 is surrounded by the insulator 132 The SGT is formed with a conductor 108b functioning as a gate electrode, surrounding the gate electrode. In the semiconductor 134 of the transistor 11, the channel is formed at the same height as the conductor 108b. Region 134a, which functions as a forming region, is located above and below conductor 108b. The region 134b that functions as the drain is located in the transistor 11. The length of the channel of the transistor 11 is approximately the same as the film thickness of the conductor 108b. The direction is approximately perpendicular to the upper surface of the substrate on which the memory cells 10 are provided. As shown in FIG. 8(B), the channel length direction of the transistor 11 is The channel width of the transistor 11 is approximately perpendicular to the longitudinal direction of the cylindrical semiconductor 13. It will be roughly the same length as the circumference of 4.

[0141] In a standard planar transistor, the gate electrode, source electrode, and The drain electrode is formed and the occupied area is 8F 2 On the other hand, the SGT type In the transistor 11, when viewed from above, other structures are formed inside the gate electrode, and the occupied The area is 4 floors 2 In this way, the area occupied by the transistor 11 is very small. This reduces the area occupied by the memory cell 10 and The storage capacity per unit area of ​​the semiconductor device can be increased.

[0142] In addition, as in the case of the transistor 11 in FIG. 8, the source electrode and the drain electrode are not explicitly provided. However, for convenience, such a state may be included in the term "transistor." .

[0143] In addition, the opening in which the transistor 11 is provided has a circular top surface in FIG. However, the present invention is not limited to this. For example, the upper surface may be elliptical, triangular, or quadrilateral. The shape may be a polygon, such as a square. In the case of a polygon, the corners may be rounded. In addition, the insulator 132 and the semiconductor 134 may be formed in accordance with the shape of the upper surface of the opening. The shape of the upper surface of the insulator 136 may also change. 70 side) of the opening perpendicular to the y axis, the y The cross-sectional area perpendicular to the axis may be narrowed.

[0144] The transistor 12 includes an insulator 106a formed on the insulator 104 and an insulator 106b formed on the insulator 106. a semiconductor 106b formed in contact with at least a portion of the upper surface of a; and an insulator 106c formed in contact with at least a part of the semiconductor 106b. The conductors 108a and 108b are formed on the insulating layer 106c. 12 and the insulator 112, and at least a portion of the conductor 108a and the conductor 108b are formed on the insulator 112. and a conductor 114 formed between the insulators 106a and 106b. An insulator 116 is formed on the semiconductor 106b, the conductor 108a, and the conductor 108b. An insulator 118 is formed over the edge 116 .

[0145] The transistor 12 has an opening in the insulator 118 that reaches the semiconductor 106b. The insulator 106c, the insulator 112, and the conductor 114 are embedded in the mouth. Furthermore, the opening separates the conductor 108a and the conductor 108b. The transistor 12 has a conductor 114 that functions as a gate electrode and is surrounded by an insulator 118 or the like. The opening is formed in a self-aligned manner to fill the opening. Therefore, TGSA s-channel FET (Trench Gate Self A It can also be called a light s-channel FET.

[0146] In the transistor 12, the insulator 118, the insulator 106c, the insulator 112, and the conductor 11 The upper surfaces of the insulators 117 and 14 are roughly flush with each other and are provided flat. 06c, because the top surfaces of the insulator 112 and the conductor 114 are flattened by a CMP method or the like. As a result, the area where the conductor 114 overlaps with the conductors 108a and 108b is almost Since almost no gate-source and gate-drain This can reduce the parasitic capacitance that occurs between the two.

[0147] As shown in FIG. 8C, the insulator 106c is a semiconductor 106a. It is preferable that the semiconductor 10 is provided so as to cover the side surface of the semiconductor 10b in the channel width direction. 6b in the vicinity of the side end portion in the channel width direction, A continuous junction is formed between the low-resistance region 109a and the low-resistance region 109b, and the defect level density is reduced. Even if the on-current becomes easier to flow by providing the low-resistance region 109b, the semiconductor 106b The side edges in the channel width direction do not become parasitic channels, and stable electrical characteristics can be obtained. Cut.

[0148] Here, the conductor 108a functions as either the source or the drain of the transistor 12. The conductor 108b functions as the other of the source and drain of the transistor 12. The insulator 112 functions as a gate insulating film of the transistor 12, and the conductor 11 4 functions as the gate of the transistor 12 .

[0149] In addition, in FIGS. 8(B) and 8(C), the ends of the insulator 106a and the semiconductor 106b are roughly The insulator 106a and the semiconductor 106b are formed to coincide with each other. The configuration of the semiconductor device shown is not limited to this.

[0150] In addition, the circles provided on the insulator 104, the conductor 108a, the insulator 116, and the insulator 118 A cylindrical conductor 120 is formed in the columnar opening. The conductor 120 is electrically connected to the substrate 108a on which the memory cell 10 is provided. The conductor 120 is formed in a cylindrical shape and extends substantially perpendicular to the upper surface of the conductor 120. Alternatively, the opening of the conductor 120 may be filled with an insulator.

[0151] In addition, the opening in which the conductor 120 is provided has a circular upper surface in FIG. However, the present invention is not limited to this, and the upper surface may be elliptical, triangular, or rectangular. In the case of a polygonal shape, the corners may be rounded. The shape of the upper surface of the conductor 120 may also be changed in accordance with the shape of the upper surface of the opening. In addition, the cross-sectional area of ​​the opening may be smaller than that of the opening on the upper side (the insulator 170 side). The cross-sectional area of ​​the opening on one side (the semiconductor substrate 150 side) may be narrower.

[0152] The capacitance element 14 includes a conductor 108b, an insulator 116, and a conductor 122. The conductor 108b functions as one of the electrodes of the capacitor 14, and the conductor 122 functions as one of the electrodes of the capacitor 14. The insulator 116 functions as the dielectric of the capacitor element 14. It is sufficient that the conductive material 108b and the conductive material 122 are formed in the overlapping area. That's fine.

[0153] As described above, the conductor 108b functions as the gate of the transistor 11 and In the capacitor 12, it functions as either a source or a drain, and in the capacitor 14, it functions as one of the electrodes. That is, the conductor 108b functions as the node FN shown in FIGS. 1A and 1B, the wiring WBL is a conductor 120, and the wiring WWL is a conductor. The wiring RWL corresponds to the conductor 122. The semiconductor 134 is provided in an elongated manner. and is electrically connected to the conductor corresponding to the wiring SL and the conductor corresponding to the wiring RBL. .

[0154] Here, the insulator 104, the insulator 106a, the insulator 106c, the insulator 112, the insulator 11 6, the insulators 118, 132 and 136 may also be referred to as insulating films or insulating layers. In addition, the conductor 108a, the conductor 108b, the conductor 114, the conductor 120, and the conductor The semiconductor 106b and the semiconductor 13 can also be called a conductive film or a conductive layer. 4 can also be called a semiconductor film or semiconductor layer.

[0155] As will be described in detail later, when the insulator 106a and the insulator 106c are used alone, In some cases, materials may be used that can function as conductors, semiconductors, or insulators. However, when a transistor is formed by stacking the semiconductor 106b, electrons 106b, the vicinity of the interface between the semiconductor 106b and the insulator 106a, and the vicinity of the interface between the semiconductor 106b and the insulator 106a. The insulators 106a and 106c flow near the interface of the transistor. Therefore, in this specification and the like, the insulator 1 The semiconductor 106a and the insulator 106c are not described as conductors and semiconductors, but as insulators. do.

[0156] <Transistor 11 Semiconductor> The detailed configuration of the semiconductor 134 will be described below.

[0157] The semiconductor 134 may be, for example, crystalline silicon such as polycrystalline silicon or single crystal silicon. However, it is not limited to this, and microcrystalline silicon and amorphous silicon can also be used. The material is not limited to silicon, and may be germanium, silicon carbide, silicon dioxide, or the like. Indium germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. Also, a semiconductor that can be used for the semiconductor 106b, which will be described later, may be used.

[0158] When polycrystalline silicon is used as the semiconductor 134, the thickness of the semiconductor 134 should be thin. For example, it is preferably 20 nm or less, more preferably 10 nm or less. This makes it possible to suppress variations in the characteristics of the transistor 11.

[0159] In addition, when polycrystalline silicon or the like is used as the semiconductor 134, hydrogen is supplied to the semiconductor 134. The dangling bonds in the semiconductor 134 may be terminated by supplying a terminating agent.

[0160] In addition, the semiconductor 134 is doped with impurities that give it p-type conductivity or impurities that give it n-type conductivity. Impurities that impart p-type conductivity include, for example, boron. The impurity that gives n-type conductivity is boron (B) or aluminum (Al). For example, phosphorus or arsenic may be used.

[0161] <Transistor 11 insulator> The detailed configurations of the insulators 132 and 136 will be described below.

[0162] The insulator 132 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium Insulators containing aluminum, zirconium, lanthanum, neodymium, hafnium or tantalum are used alone. For example, the insulator 112 may be made of aluminum oxide, Magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide For example, tantalum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used. In the above, silicon nitride oxide is a material whose composition contains more nitrogen than oxygen. Silicon oxynitride is a material whose composition contains more oxygen than nitrogen. Point.

[0163] The insulator 132 has the effect of blocking hydrogen, water, alkali metals, alkaline earth metals, etc. As such an insulator, for example, a nitride insulating film may be used. The nitride insulating film can be formed of silicon nitride, silicon nitride oxide, aluminum nitride, or the like. Instead of the nitride insulating film, oxygen, hydrogen, water, etc. An oxide insulating film having a blocking effect may be provided. Aluminum, aluminum oxynitride, gallium oxide, gallium oxynitride, yttria Examples include yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

[0164] In particular, when the dangling bonds of the semiconductor 134 are terminated with hydrogen, the insulator 132 is hydrogen, If the semiconductor 106b has a water blocking effect, the hydrogen will diffuse and be taken up by the semiconductor 106b. As will be described in detail later, the oxide used in the semiconductor 106b If hydrogen is absorbed into the semiconductor, the electrical characteristics of the transistor 12 may be degraded. That is, the insulator 132 has the effect of blocking hydrogen and water. This allows the electrical characteristics of the transistor 12 to be stabilized.

[0165] As the insulator 136, an insulator that can basically be used as the insulator 132 is used. However, when the dangling bonds of the semiconductor 134 are terminated with hydrogen, the insulator In this case, hydrogen is supplied to the semiconductor 134 by adding hydrogen to the insulator 136. For example, silicon nitride containing hydrogen may be used as the insulating film.

[0166] <Transistor 12 semiconductor> The detailed configuration of the semiconductor 106b will be described below. The detailed configurations of the insulators 106a and 106c as well as the insulators 106b will be described below.

[0167] The semiconductor 106b is, for example, an oxide semiconductor containing indium. For example, when indium is contained, the carrier mobility (electron mobility) increases. The body 106b preferably contains the element M. The element M is preferably Ti, Ga, Y, Zr , La, Ce, Nd, Sn or Hf, where the element M is the aforementioned element The element M may have a bond energy with oxygen of, for example, For example, the bond energy with oxygen is higher than that of indium. Alternatively, the element M may have a function of increasing the energy gap of the oxide semiconductor, for example. The semiconductor 106b preferably contains zinc. If lead is included, crystallization may occur more easily.

[0168] However, the semiconductor 106b is not limited to an oxide semiconductor containing indium. 06b does not contain indium, such as zinc tin oxide, gallium tin oxide, etc. Oxide semiconductors containing zinc, oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. It's okay if there is.

[0169] For example, the insulators 106a and 106c are made of oxygen other than the oxygen that constitutes the semiconductor 106b. The semiconductor 106b is an oxide semiconductor composed of one or more of the elements other than oxygen. Since the insulators 106a and 106c are made of one or more of the elements, the insulators 10 At the interface between the semiconductor 106a and the semiconductor 106b, and at the interface between the semiconductor 106b and the insulator 106c Therefore, defect levels are less likely to be formed.

[0170] The insulator 106a, the semiconductor 106b, and the insulator 106c contain at least indium. When the insulator 106a is an In-M-Zn oxide, the sum of In and M is preferably When the atomic percentage is 100, it is preferable that In is less than 50 atomic percent and M is less than 50. atomic %, more preferably In is less than 25 atomic % and M is 75 atomic % When the semiconductor 106b is an In-M-Zn oxide, I When the sum of n and M is 100 atomic %, In is preferably 25 atomic %. %, and M is less than 75 atomic %, and more preferably In is 34 atomic % The insulator 106c is In-M-Zn. In the case of oxides, when the sum of In and M is 100 atomic %, In is preferably 50 atomic %, M is higher than 50 atomic %, and more preferably In is 2 5 atomic % or less, and M is higher than 75 atomic %. However, the same oxide as the insulator 106a may be used. In some cases, the insulator 106c does not need to contain indium. 106a and / or the insulator 106c is gallium oxide or Ga-Zn oxide, It should be noted that the respective components included in the insulator 106a, the semiconductor 106b, and the insulator 106c may be The atomic numbers of elements do not have to be in a simple integer ratio.

[0171] For example, when the insulator 106a or the insulator 106 A typical example of the atomic ratio of the metal elements in the target used in c is In:M:Zn=1:2. :4, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1 :3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:3, In:M:Zn =1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4:6, In:M: Zn=1:6:3, In:M:Zn=1:6:4, In:M:Zn=1:6:5, In: M:Zn=1:6:6, In:M:Zn=1:6:7, In:M:Zn=1:6:8, I n:M:Zn=1:6:9, In:M:Zn=1:10:1, etc. The atomic ratio of the metal elements in the target used for 6a or insulator 106c is M:Zn=10: It can also be set to 1.

[0172] In addition, for example, when a film is formed by sputtering, the substrate used for the semiconductor 106b is Typical examples of atomic ratios of metal elements in the get are In:M:Zn=1:1:1, In:M :Zn=1:1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1: 2.3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn= Examples include 4:2:4.1, In:M:Zn=5:1:6, and In:M:Zn=5:1:7. In particular, as a sputtering target, the atomic ratio of In:Ga:Zn=4:2:4.1 When using the above, the atomic ratio of the semiconductor 106b to be formed is In:Ga:Zn=4:2:3. It may be nearby.

[0173] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the insulator 106c preferably contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and More preferably, it is 90% or more.

[0174] The semiconductor 106b is made of, for example, an oxide with a large energy gap. The energy gap of 6b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2. The value is preferably 8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less. The energy gap of the insulator 106a is larger than the energy gap of the semiconductor 106b. The energy gap of the insulator 106c is larger than that of the semiconductor 106b. Bigger than a cup.

[0175] The semiconductor 106b is an oxide having a larger electron affinity than the insulator 106a or the insulator 106c. For example, the semiconductor 106b is made of a material having a higher conductivity than the insulators 106a and 106c. The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less. 5 or less, more preferably, an oxide having a larger energy level than the above by 0.15 eV or more and 0.4 eV or less. , electron affinity is the energy difference between the vacuum level and the bottom of the conduction band. The energy level of the conduction band minimum of the semiconductor 106a or the insulator 106c is It is closer to the vacuum level than the energy level at the lower band edge.

[0176] At this time, when a gate voltage is applied, the insulator 106a, the semiconductor 106b, and the insulator 106 A channel is formed in the semiconductor 106b having a large electron affinity among the semiconductors 106a and 106b. When a voltage is applied to the insulator 106a, the insulator 106a is electrically connected to the semiconductor 106b. Current may also flow near the interface between 6c and semiconductor 106b.

[0177] As described above, when the insulators 106a and 106c are used alone, they are not conductive or semi-conductive. It consists of a material that can function as either a conductor or an insulator. When a transistor is formed by stacking the semiconductor 106b and the semiconductor 106, electrons are transferred through the semiconductor 106b and the semiconductor 106. The flow passes through the vicinity of the interface between the semiconductor 106b and the insulator 106a, and the vicinity of the interface between the semiconductor 106b and the insulator 106c. The insulators 106a and 106c do not function as the channel of the transistor. Therefore, in this specification and the like, the insulator 106a and the insulator 10 6c will not be described as a semiconductor but as an insulator. The insulator 106c is described as an insulator because it is a transistor compared to the semiconductor 106b. Since the function of the insulating material is similar to that of an insulator, the insulating material 106a or the insulating material 106c is In some cases, a material that can be used for the semiconductor 106b may be used.

[0178] Here, there is a gap between the insulator 106a and the semiconductor 106b. In addition, there may be a mixed region between the semiconductor 106b and the insulator 106c. , the semiconductor 106b and the insulator 106c may have a mixed region. Therefore, the level density of the insulator 106a, the semiconductor 106b, and the insulator 106c is In the laminate, the energy changes continuously near each interface (also known as continuous junction). The band diagram is as follows. The interface between the semiconductor 106c and the semiconductor 106b may not be clearly distinguishable.

[0179] At this time, the electrons are not in the insulator 106a and the insulator 106c but in the semiconductor 106b. As described above, the electrons move mainly through the interface between the insulator 106a and the semiconductor 106b. and the defect state density at the interface between the semiconductor 106b and the insulator 106c. By lowering the concentration, the movement of electrons in the semiconductor 106b is less hindered, The on-state current of the transistor can be increased.

[0180] In addition, the on-current of the transistor can be increased by reducing the factors that hinder the movement of electrons. For example, if there are no factors that hinder the movement of electrons, electrons can move efficiently. It is estimated that the electron movement is slower when, for example, the physical unevenness of the channel formation region is large. is also inhibited.

[0181] In order to increase the on-current of the transistor, for example, The square of the surface (the surface to be formed, here the upper surface of the insulator 106a) in the range of 1 μm×1 μm Root Mean Square (RMS) roughness less than 1 nm, preferably is less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in the area of ​​1 μm × 1 μm is 1n less than 0.6 nm, more preferably less than 0.5 nm, and The maximum height difference (PV) in the area of ​​1 μm x 1 μm should be less than 0.4 nm. ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, More preferably, it should be less than 7 nm. RMS roughness, Ra and PV are - Using a scanning probe microscope system SPA-500 manufactured by Nano Technology Co., Ltd. It can be measured.

[0182] In addition, in order to increase the on-state current of the transistor, the thickness of the insulator 106c is preferably as small as possible. The thickness of the insulator 106c is preferably smaller than the thickness of the insulator 106a. For example, the thickness is less than 10 nm, preferably 5 nm or less, More preferably, the insulator 106c has a region of 3 nm or less. 06c is a semiconductor 106b in which a channel is formed, and is formed by introducing oxygen other than oxygen constituting the adjacent insulator. It has the function of blocking elements (hydrogen, silicon, etc.) from entering. It is preferable that the insulator 106c has a certain thickness, for example, 0.3 nm or more. , preferably 1 nm or more, more preferably 2 nm or more insulator 10 Just use 6c.

[0183] In order to improve reliability, it is preferable that the insulator 106a is thick. 0 nm or more, preferably 20 nm or more, more preferably 40 nm or more, and more preferably The insulator 106a may have a region with a thickness of 60 nm or more. By thickening the insulator 106a, a channel is formed from the interface between the adjacent insulator and the insulator 106a. The distance to the semiconductor 106b can be increased, but the productivity of the semiconductor device decreases. Therefore, for example, it is set to 200 nm or less, preferably 120 nm or less, and more preferably The insulating layer 106a may have a region with a thickness of 80 nm or less.

[0184] Silicon in an oxide semiconductor may act as a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the semiconductor 106b, the more preferable. b and the insulator 106a, for example, by secondary ion mass spectroscopy (SIMS). 1×10 16 ato ms / cm 3 More than 1×10 19 atoms / cm 3 Less than 1 × 10 16 ato ms / cm 3 5x10 or more 18 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 Over 2×10 18 atoms / cm 3 The region with the following silicon concentration In addition, a 1×1 0 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below, preferably 1 x 1 0 16 atoms / cm 3 5x10 or more 18 atoms / cm 3 More preferably, 1×10 16 atoms / cm 3 Over 2×10 18 atoms / cm 3 Silicon concentration below It has a range of degrees.

[0185] In addition, in order to reduce the hydrogen concentration in the semiconductor 106b, the insulator 106a and the insulator 10 It is preferable to reduce the hydrogen concentration in the insulator 106a and the insulator 106c. In S, 1×10 16 atoms / cm 3 Over 2×10 20 atoms / cm 3 below , preferably 1 x 10 16 atoms / cm 3 5x10 or more 19 atoms / cm 3 below , more preferably 1 × 10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 5x10 or more 18 atoms / cm 3 The hydrogen concentration in the semiconductor 106b is reduced. Therefore, it is preferable to reduce the nitrogen concentration in the insulators 106a and 106c. The 106a and the insulator 106c have a SIMS resolution of 1×10 15 atoms / cm 3 5x10 or more 19 atoms / cm 3 Less than 1 × 10 15 atoms / cm 3 5x10 or more 18 atoms / cm 3 Less than 1×10, more preferably 15 atoms / c m 3 More than 1×10 18 atoms / cm 3 or less, more preferably 1 × 10 15 atom s / cm 3 5x10 or more 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0186] The insulator 106a, the semiconductor 106b, and the insulator 106c shown in this embodiment, particularly the semiconductor 106b is an oxide semiconductor having a low impurity concentration and a low density of defect states (few oxygen vacancies). and can be called a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. A highly intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources, Therefore, a channel region can be formed in the oxide semiconductor. The transistors used in this study have electrical characteristics in which the threshold voltage is negative (also known as normally-on). In addition, oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic are The defect level density is low in the silicon dioxide, so the trap level density may also be low. Intrinsic or substantially highly purified intrinsic oxide semiconductors have a significantly small off-state current and a high channel density. The width W is 1×10 6Even if the device has a channel length L of 10 μm, the source electrode and drain When the voltage between the drain electrodes (drain voltage) is in the range of 1V to 10V, the off-state current is below the measurement limit of the body parameter analyzer, i.e., 1 × 10 -13 A characteristic of A or less It is possible.

[0187] Therefore, the channel region is formed in the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The transistors in which this region is formed have small fluctuations in electrical characteristics and are highly reliable. Note that charges trapped in the trap states of the oxide semiconductor do not disappear until It takes a long time for the charge to dissipate, and it may behave as if it were a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor with a high density of drop states has Impurities include hydrogen, nitrogen, alkali metals, or alkalis. These include lithium-earth metals.

[0188] The hydrogen contained in the insulator 106a, the semiconductor 106b, and the insulator 106c bonds with metal atoms. The lattice from which oxygen is released (or the part from which oxygen is released) reacts with the oxygen to form water. When hydrogen enters the oxygen vacancy, electrons, which act as carriers, are generated. In addition, some of the hydrogen atoms may bond with oxygen atoms that bond with metal atoms, forming carriers. In particular, hydrogen trapped in oxygen vacancies can cause the band structure of semiconductors to change. Therefore, the oxide semiconductor containing hydrogen may have a shallow donor level. A transistor using a conductor tends to have a normally-on characteristic. a) It is preferable that the semiconductor 106b and the insulator 106c have as little hydrogen as possible. Specifically, in the insulator 106a, the semiconductor 106b, and the insulator 106c, SIM The hydrogen concentration obtained by S analysis is 2 × 10 20 atoms / cm 3 Below, preferably 5 x10 19 atoms / cm 3 Less than 1×10, more preferably 19 atoms / cm 3 Below Bottom, 5×10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Less than or equal to 5 × 10 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 The following applies.

[0189] In addition, in the insulator 106a, the semiconductor 106b, and the insulator 106c, SIMS analysis The concentration of alkali metal or alkaline earth metal obtained by 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 The following are alkali metals and When alkaline earth metals bond with oxide semiconductors, they can generate carriers. Therefore, the insulator 106a and the semiconductor 10 6b and the insulator 106c. preferable.

[0190] Furthermore, when nitrogen is contained in the insulator 106a, the semiconductor 106b, and the insulator 106c, Electrons, which act as carriers, are generated, increasing the carrier density and making it easier to become n-type. A transistor using an oxide semiconductor film containing such a metal oxide tends to be normally on. Therefore, it is preferable that nitrogen be reduced as much as possible in the oxide semiconductor film. For example, the nitrogen concentration obtained by SIMS analysis is 5×10 18 atoms / cm 3 below It is preferable to do so.

[0191] Here, as shown in FIG. 8B, the conductor 108a such as the semiconductor 106b or the conductor 1 The low resistance region 109a and the low resistance region 08b are in contact with each other (shown by the dotted line in FIG. 8B). The low resistance region 109a and the low resistance region 109b are mainly The semiconductor 106b is then exposed to the conductor 108a or the conductor 108b. Alternatively, the conductive material contained in the conductor 108a or the conductor 108b may be an element in the semiconductor 106b. Such low resistance regions 109a and 109b are formed by bonding. is formed, the conductor 108a or the conductor 108b contacts the semiconductor 106b. Since the resistance can be reduced, the on-current of the transistor 12 can be increased. Cut.

[0192] As shown in FIG. 8B, the semiconductor 106b is made up of a conductor 108a and a conductor 108b. There is a region between the conductive layers 108a and 108b that is thinner than the region where the conductive layers 108a and 108b overlap. This is because when the conductor 108a and the conductor 108b are formed, the semiconductor 106b The upper surface of the semiconductor 106b is formed by removing a part of the upper surface of the conductor 10. When the conductors to be the low resistance regions 8a and 108b are formed, the low resistance regions 109a and 109b are formed. In this way, a region with low resistance similar to the region 109b may be formed. b, by removing the region located between the conductors 108a and 108b. It is possible to prevent a channel from being formed in a low-resistance region on the top surface of the semiconductor 106b. In the following drawings, even if thin film thickness areas are not shown in enlarged views, the same There may be a region where the film is thin.

[0193] The above-described three-layer structure of the insulator 106a, the semiconductor 106b, and the insulator 106c is an example. For example, a two-layer structure in which either the insulator 106a or the insulator 106c is not provided may be used. Alternatively, a single-layer structure without the insulator 106a or the insulator 106c may be used. Alternatively, the semiconductor 106 may be exemplified as an insulator 106a, a semiconductor 106b, or an insulator 106c. As an n-layer structure (n is an integer of 4 or more) having either an insulating material, a semiconductor material, or a conductor material That's fine.

[0194] <Insulators and conductors of transistor 12> The components of the transistor 12 other than the semiconductor will be described in detail below.

[0195] The insulator 104 preferably contains a small amount of water or hydrogen. The insulator 104 is preferably an insulator having excess oxygen. Examples of suitable elements include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, and silicon. Cr, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, Insulators containing lanthanum, neodymium, hafnium or tantalum, either in single or multilayer configurations For example, the insulator 104 may be aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, Hafnium oxide or tantalum oxide may be used. Preferably, silicon oxide or oxide Silicon nitride is used.

[0196] The insulator 104 is preferably an insulator with excess oxygen. By providing the semiconductor 104, the insulator 104 is connected to the insulator 106a, the semiconductor 106b, and the insulator 10 Oxygen can be supplied to the oxide semiconductor insulator 106. a) Oxygen vacancies that cause defects in the semiconductor 106b and the insulator 106c can be reduced. This allows the insulator 106a, the semiconductor 106b, and the insulator 106c to have a low defect level density and a stable The oxide semiconductor can have stable characteristics.

[0197] In this specification and the like, excess oxygen refers to oxygen contained in excess of the stoichiometric composition. Alternatively, the excess oxygen refers to oxygen that is released by heating, for example. This refers to oxygen released from a film or layer. Excess oxygen may be released, for example, by moving inside the film or layer. The movement of excess oxygen can occur between atoms in the film or layer, or between oxygen atoms that make up the film or layer. In some cases, the two move in a domino effect, replacing each other.

[0198] The insulator 104 having excess oxygen has a temperature of 10 In the surface temperature range of 0°C to 700°C or 100°C to 500°C, the oxygen molecules The amount of desorption is 1.0×10 14 molecules / cm 2 Over 1.0 x 10 16 molec ules / cm 2 It is preferable that the value is less than 1.0 × 10 15 molecules / c m 2 Over 5.0 x 10 15 molecules / cm 2 It is more preferable that:

[0199] Regarding the method for measuring the amount of released molecules using TDS analysis, the amount of released oxygen is as follows: will be explained.

[0200] The total amount of gas released when the measurement sample is subjected to TDS analysis is calculated by the integral value of the ion intensity of the released gas. By comparison with a standard sample, the total amount of gas released can be calculated.

[0201] For example, the TDS analysis results of a silicon substrate containing a specified density of hydrogen as a standard sample, and From the TDS analysis results of the measurement sample, the amount of oxygen molecules released from the measurement sample (N O2 ) is shown below Here, the gas detected at a mass-to-charge ratio of 32 obtained by TDS analysis can be calculated using the formula: Assume that all of the charge is from oxygen molecules. For example, the mass-to-charge ratio of CH3OH is 32. It is not considered here as it is unlikely to exist. Oxygen molecules containing oxygen atoms with mass numbers 17 and 18 also occur in nature. It is not taken into consideration because its abundance is extremely small.

[0202] N O2 =N H2 / S H2 ×S O2 ×α

[0203] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is the standard This is the integrated value of the ion intensity when the sample is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 Let's say S O2 is the integral value of the ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ion intensity in TDS analysis. Details of the above formula For details, see Japanese Patent Application Laid-Open No. 6-275697. A thermal desorption analyzer EMD-WA1000S / W manufactured by Kagaku Co., Ltd. was used as a standard sample. Measurements are made using a silicon substrate containing a fixed amount of hydrogen atoms.

[0204] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The atomic ratio can be calculated from the ionization rate of oxygen molecules. Since it includes the ionization rate of the molecules, evaluating the amount of released oxygen molecules can be used to estimate the amount of released oxygen atoms. It is also possible to estimate.

[0205] In addition, N O2 is the amount of released oxygen molecules. The amount of released oxygen atoms is This is twice the amount of offspring released.

[0206] Alternatively, insulators that release oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to peroxide radicals is 5×10 17 spins / cm 3 Insulators containing peroxide radicals can be analyzed by electron spin resonance (E In SR (Electron Spin Resonance), the g value is around 2.01. It may also have an asymmetric signal.

[0207] The amount of water or hydrogen contained in the insulator 104 is preferably small. The body 104 has a temperature of 100°C or higher and 700°C or lower or 100°C or higher and 500°C or lower by TDS analysis. In the range of surface temperatures below, the number of water molecules desorbed is 1.0 × 10 13 molecules / cm 2 Over 1.4 x 10 16 molecules / cm 2 Below, 1.0 x 10 13 mol ecules / cm 2 Over 4.0 x 10 15 molecules / cm 2 Below, one more .0×10 13 molecules / cm 2 Over 2.0 x 10 15 molecules / cm 2 Furthermore, it is preferable that the temperature is between 100°C and 700°C by TDS analysis. or in the surface temperature range of 100°C to 500°C, the amount of hydrogen molecules desorbed is 1.0 × 10 1 3 molecules / cm 2 Over 1.2 x 10 15 molecules / cm 2 below, Furthermore, 1.0×10 13 molecules / cm 2 Over 9.0 x 10 14 molecu les / cm 2 It is preferable that the following be true:

[0208] As mentioned above, it is preferable that the upper or lower surface of the semiconductor 106b is highly flat. Therefore, the upper surface of the insulator 104 is subjected to chemical mechanical polishing (CMP). To improve the flatness, a flattening process is performed using methods such as the CAL Polishing. Good too.

[0209] The conductor 108a and the conductor 108b are the source electrode or It functions as either a drain electrode or a gate electrode.

[0210] The conductor 108a and the conductor 108b may include, for example, boron, nitrogen, oxygen, fluorine, Silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, Zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium Conductors containing one or more of aluminum, tin, tantalum and tungsten are used in a single layer or multilayer. For example, alloys or compounds may be used, and conductors containing aluminum, copper, Conductors containing copper and manganese, conductors containing indium, tin and oxygen Conductors containing titanium and nitrogen, etc. may also be used.

[0211] The insulator 112 functions as a gate insulating film of the transistor 12. The insulator 112 may be an insulator having excess oxygen, similar to the insulator 104. By providing the insulating layer 112, the insulating layer 106a, the semiconductor layer 106b, and the insulating layer 106c can supply oxygen to

[0212] The insulator 112 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium Insulators containing aluminum, zirconium, lanthanum, neodymium, hafnium or tantalum are used alone. For example, the insulator 112 may be made of aluminum oxide, Magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide For example, tantalum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used.

[0213] The conductor 114 functions as a gate electrode of the transistor 12. Any conductor that can be used for the conductors 108a and 108b may be used.

[0214] Here, as shown in FIG. 8C, the semiconductor 106b The semiconductor can be electrically surrounded by an electric field generated by a conductor. The structure of the transistor that surrounds it is called the surrounded channel (s-channel Therefore, the entire semiconductor 106b (top, bottom and side surfaces) is covered with a thin film. In the s-channel structure, a channel is formed between the source and drain of the transistor. A large current can be passed through the transistor, and the current (on-state current) when the transistor is conducting can be increased.

[0215] When the transistor has an s-channel structure, the side surface of the semiconductor 106b is Therefore, the thicker the semiconductor 106b, the larger the channel region. That is, the thicker the semiconductor 106b, the higher the on-current of the transistor. In addition, the thicker the semiconductor 106b, the greater the proportion of the region with high carrier controllability. For example, the subthreshold swing value can be reduced to 10 nm or more. Preferably, it is 20 nm or more, more preferably 30 nm or more, and even more preferably 50 nm or more. However, the productivity of the semiconductor device may be reduced. Therefore, for example, it is set to 300 nm or less, preferably 200 nm or less, and more preferably In this case, the semiconductor 106b may have a region with a thickness of 150 nm or less.

[0216] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device having the transistor The device can be a highly integrated, high density semiconductor device. The transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. Preferably, the transistor has a channel width of 20 nm or less. or 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. It has a region.

[0217] The insulator 116 serves not only as a dielectric for the capacitor 14 but also as a protective insulator for the transistor 12. It is preferable that the insulator 116 also functions as an insulating film. The thickness of the insulator 116 can be at least 20 nm or 200 nm. It is preferably formed in contact with the upper surface of the insulator 104 .

[0218] The insulator 116 may be, for example, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in single or double layers. The insulator 116 may be made of oxygen, hydrogen, water, alkali metals, alkaline earth metals, or the like. It is preferable that the insulating material has an effect of blocking metals, etc. Examples of such insulating materials include The nitride insulating film may be made of silicon nitride, oxynitride, or the like. Silicon nitride, aluminum nitride, aluminum oxide nitride, etc. Alternatively, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided. Examples of the oxide insulating film include aluminum oxide, aluminum oxynitride, gallium oxide, and oxide Gallium nitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride Funium, etc.

[0219] Here, the insulator 116 is preferably formed by sputtering. It is more preferable to carry out the sputtering method in an atmosphere containing By forming the insulator 116, the surface of the insulator 104 (insulator 1 After the film 16 is formed, oxygen is added to the vicinity of the interface between the insulator 104 and the insulator 116 .

[0220] The insulator 116 is an insulator that is less permeable to oxygen than the insulator 104, and blocks oxygen. By providing such an insulator 116, When oxygen is supplied from the body 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c, Therefore, the oxygen can be prevented from being released to the outside above the insulator 116.

[0221] Aluminum oxide has a film that is resistant to both impurities such as hydrogen and moisture, and oxygen. It is preferable to apply it to the insulator 116 because it has a high blocking effect of preventing transmission.

[0222] The insulator 118 functions as an interlayer insulating film. Any insulator that can be used as the insulating layer may be used.

[0223] The conductor 120 is electrically connected to the source or drain electrode of the transistor 12. The conductor 120 functions as a wiring. The conductor 120 may be a conductor such as phosphorus. A semiconductor such as polycrystalline silicon doped with impurities may also be used.

[0224] The conductor 122 functions as the other electrode of the capacitor. Any conductor that can be used for the conductors 108a and 108b may be used.

[0225] The above-described structure provides the transistor 12 with stable electrical characteristics. Alternatively, it is possible to provide a transistor 12 with a small leakage current when it is not conducting. Alternatively, it is possible to provide a transistor 12 having high frequency characteristics. Alternatively, the transistor 12 can be provided with normally-off electrical characteristics. Alternatively, a transistor 12 with a small subthreshold swing value can be provided. It is possible to provide a highly reliable transistor. By using the transistor 12 in the memory cell 10, the stored contents can be retained for a longer period of time. Therefore, it is possible to provide a semiconductor device that can

[0226] <Memory cell array configuration> Next, an example of the configuration of the three-dimensional memory cell array shown in the above embodiment will be described with reference to FIGS. 11 will be used to explain.

[0227] As part of the three-dimensional memory cell array, the memory cells of the two-dimensional memory cell array 30[1] The structures of modules 10 (1,1,1) to (1,4,4) are shown in Figs. 9 to 11 as examples. 9 is a three-dimensional schematic diagram of memory cells 10 (1,1,1) to (1,4,4). In FIG. 9, a Cartesian coordinate system consisting of x-axis, y-axis, and z-axis is set for convenience, as in FIG. 2. Here, the upper surface of the substrate on which the three-dimensional memory cell array is provided is approximately in the xz plane. The y-axis is parallel to the substrate, and the y-axis is approximately perpendicular to the upper surface of the substrate. 10 (for example, the insulator 106c, the insulator 112, etc.) are omitted. do.

[0228] FIG. 10 is a top view of the memory cells 10(1,4,1) to (1,4,4). 10A is a cross-sectional view corresponding to the dashed line B1-B2 of FIG. 10, and shows the memory cell 10 (1,1, 11(B) corresponds to the dashed line B3-B4 in FIG. 1A and 1B are corresponding cross-sectional views corresponding to memory cells 10(1,4,1) through (1,4,4). In the region indicated by the dashed line B1-B2, the transistor 12 has a channel length direction. In the region indicated by the dashed line B3-B4, the memory cell 10 (1 1, 4, 1) to (1, 4, 4) show the structure of the transistor 12 in the channel width direction. are.

[0229] The structure of each memory cell 10 is similar, and the description of the structure of the memory cell 10 above is to be referred to. However, the memory cells 10 formed on the same plane (for example, FIG. 2 In the memory cells 10(1,1,1) to (m1,1,m3), etc., shown in FIG. The insulators 116 and 118 may be integral with each other.

[0230] As shown in FIG. 11A, the insulator 132, the semiconductor 134, and the insulator 136 are arranged in a direction parallel to the y-axis. The memory cells 10 (1,1,1) to (1,4, 1) are shared. That is, in the memory cells 10 arranged in the y-axis direction, The insulator 132, the semiconductor 134, and the insulator 136 are shared. The region 134b that functions as the source or drain of the transistor 11 in the y-axis direction In other words, the memory cells 10 are adjacent to each other in the y-axis direction. In the memory cell 10, the transistors 11 are electrically connected in series. There are.

[0231] In this way, one memory cell is formed by the insulator 132, the semiconductor 134, and the insulator 136. The transistors 11 included in the transistor string 20 are formed together. If the transistor 11 is formed of a standard planar transistor, However, the structure required the formation of plugs and wiring. By using SGT as 11, the source of multiple transistors 11 can be self-aligned. and the drain are connected in series.

[0232] In the semiconductor 134 of the uppermost memory cell 10, the upper surface of the semiconductor 134 and A conductor electrically connected to the low power supply potential line is formed so as to contact the wiring SL. Also, the transistor 6 in the semiconductor 134 of the memory cell 10 at the bottom The connection with 1 will be described later.

[0233] As shown in FIG. 11(A), the conductor 120 is elongated in a direction substantially parallel to the y-axis. It is shared by memory cells 10(1,1,1) to (1,4,1). In other words, the conductor 120 is shared among the memory cells 10 arranged in the y-axis direction. The conductor 120 is connected to the source or drain of the transistor 12 in the memory cell 10. It is electrically connected to the other and functions as the wiring WBL shown in FIG. 2 and the like.

[0234] In the conductor 120 of the uppermost memory cell 10, the upper surface of the conductor 120 is a wiring. It is preferable to cover it with an insulator so that it does not come into contact with the conductor that functions as the SL. In addition, the connection between the conductor 120 of the memory cell 10 at the bottom and the transistor 62 is More details will be provided later.

[0235] 10 and 11(B), the conductor 114 is oriented in a direction substantially parallel to the x-axis. The memory cells 10(1,4,1) to 10(1,4,4) are formed in an elongated manner. That is, in the memory cells 10 arranged in the x-axis direction, the conductors 114 are shared. The conductor 114 is provided as the gate of the transistor 11 in the memory cell 10. It also functions as the wiring WWL shown in FIG. 2. In the three-dimensional memory cell array 40 shown in FIG. 11, the insulator 106c and the insulator 112 are also The pattern is formed in the same manner as the conductor 114. Therefore, the memory cells arranged in the x-axis direction In 10, the insulator 106c and the insulator 112 are also shared. For example, the conductors 114 and the insulators 112 are arranged in the memory cells 10 in the x-axis direction. The insulator 106c is shared by the memory cells 10 arranged in the x-axis direction. Alternatively, each memory cell 10 may be patterned in an island shape.

[0236] As shown in FIG. 10, the conductor 122 is formed to extend in a direction substantially parallel to the x-axis. It is shared by memory cells 10(1,4,1) to (1,4,4). That is, the conductor 122 is shared among the memory cells 10 arranged in the x-axis direction. The electrode 122 also functions as the other electrode of the capacitor 14 in the memory cell 10. , and has the function of the wiring RWL shown in FIG. 2 and the like.

[0237] With the above-described configuration, the memory cells 10 are stacked in a direction perpendicular to the upper surface of the substrate. In this way, a three-dimensional memory cell array can be provided. By providing the layers in this way, the storage capacity per unit area can be increased according to the number of layers. The memory cell includes two transistors and one capacitance element, Because there are a relatively large number of elements, the memory capacity per unit area is smaller than that of conventional memory. In contrast, by using the semiconductor device described in this embodiment mode, In addition to these excellent characteristics, it has a density per unit area that is equal to or better than that of conventional memory. A semiconductor device with a large storage capacity can be provided. In this device, memory cells can be stacked to increase the storage capacity per unit area. This allows for storage of 1TB or more, 5TB or more, or 10TB or more. It is also possible to provide a storage device.

[0238] <Configuration of selection transistor array> Next, one of the configurations of the transistors included in the select transistor array shown in the above embodiment will be described. An example will be described with reference to FIGS.

[0239] 12(A) and 12(B) show the transistors provided in the selection transistor array 50 shown in FIG. 12A is a cross-sectional view of the transistor 61. The cross-section C1-C2 shown in FIG. 12B is a cross-sectional view of the transistor 61. The figure shows a cross section in the channel width direction.

[0240] The transistor 61 shown in FIGS. 12A and 12B is a transistor using a semiconductor substrate 150. The transistor 61 is formed by a region 172a in the semiconductor substrate 150 and a region 172b in the semiconductor substrate 150. 0, an area 172b, an insulator 162a, and a conductor 154a. Although not shown, a configuration in which a sidewall insulator is provided in contact with the side surface of the conductor 154a is also possible. In addition, when a sidewall insulator is provided in contact with the side surface of the conductor 154a, the region In the region 172a and the region 172b, the sidewall insulator is overlapped with the region This can result in regions with lower impurity concentrations than regions that do not overlap with the sidewall insulator. .

[0241] In transistor 61, regions 172a and 172b are the source and drain regions. The insulator 162a functions as a gate insulator. The conductor 154a also functions as a gate electrode. The resistance of the channel formation region can be controlled by the potential applied to the conductive material 154a. That is, the potential applied to the conductor 154a causes a voltage between the region 172a and the region 172b. Conduction and non-conduction can be controlled.

[0242] The semiconductor substrate 150 may be, for example, a single semiconductor substrate such as silicon or germanium. or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide A semiconductor substrate made of lead, gallium oxide, or the like may be used. Preferably, the semiconductor substrate 150 A single crystal silicon substrate is used as the substrate.

[0243] The semiconductor substrate 150 is a semiconductor substrate containing impurities that impart p-type conductivity. However, a semiconductor substrate containing impurities that impart n-type conductivity is used as the semiconductor substrate 150. In this case, the region that will become the transistor 61 is given a p-type conductivity. Alternatively, the semiconductor substrate 150 may be an i-type. No.

[0244] Note that the substrate used for the semiconductor device shown in this embodiment mode is not limited to a semiconductor substrate. For example, when forming an active layer such as a transistor 61 by film formation, an insulating substrate Alternatively, a conductive substrate or the like can be used. An example of an insulating substrate is a glass substrate. , quartz substrate, sapphire substrate, stabilized zirconia substrate (yttria stabilized zirconia substrate In addition, there are semiconductor substrates that have an insulating region inside the semiconductor substrate. Even if a substrate, such as an SOI (Silicon On Insulator) substrate, is used, Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. , a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a semiconductor substrate in which a conductor or an insulator is provided and a substrate in which a semiconductor or an insulator is provided on a conductive substrate. The substrate may have elements mounted thereon. The elements include a capacitance element, a resistance element, a switch element, a light-emitting element, a memory element, and the like.

[0245] In addition, a flexible substrate that can withstand the heat treatment during transistor fabrication can be used as the substrate. As a method for providing a transistor on a flexible substrate, a method for providing a transistor on a non-flexible substrate is also available. There is also a method in which a transistor is fabricated on a substrate, and then the transistor is peeled off and transferred to a flexible substrate. In that case, a peeling layer may be provided between the non-flexible substrate and the transistor. The substrate may be a sheet, film, or foil containing woven fibers. The substrate may be stretchable. The substrate may also be designed to retain its original shape when the bending or pulling is stopped. Alternatively, the substrate may have a property of not returning to its original shape. The thickness is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less. More preferably, the thickness is 15 μm or more and 300 μm or less. Furthermore, by making the substrate thinner, it is possible to reduce the extension even when glass is used. If the material has shrinkage or the property of returning to its original shape when bending or pulling is stopped, Therefore, in order to reduce the impact that may be applied to the semiconductor device on the board when it is dropped, etc. That is, a robust semiconductor device can be provided.

[0246] The regions 172a and 172b are regions containing impurities that impart n-type conductivity. In this way, the transistor 61 constitutes an n-channel transistor.

[0247] The transistor 61 is separated from adjacent transistors by a region 160 or the like. The region 160 is an insulating region.

[0248] The semiconductor device shown in FIGS. 12A and 12B includes an insulator 132, a semiconductor 134, and an insulator 135. 36, insulator 164, insulator 166, insulator 168, insulator 170, and conductor 1 80a, conductor 180b, conductor 178a, conductor 178b, conductor 176a, , and the conductor 174a. Here, the insulator 132, the semiconductor 134, and the insulator 136 are formed in the above-mentioned three-dimensional memory cell array 40.

[0249] The insulator 164 is formed on the transistor 61. The insulator 166 is formed on the insulator 162. 64. Insulator 168 is formed on insulator 166. Body 170 is formed on insulator 168 .

[0250] Insulators 164, 166, 168, and 170 extend to region 172a. The opening has a cylindrical shape, and the opening contains an insulator 132, a semiconductor 134, and an insulator 135. The insulator 132 is formed in a cylindrical shape in contact with the inner wall of the opening, and is a semiconductor. The insulator 134 is cylindrically formed inside the insulator 132, and the insulator 136 is the semiconductor 134. The insulator 132, the semiconductor 134, and the insulator 136 are formed in a cylindrical shape on the inside. The insulating film 154 is formed to extend substantially perpendicular to the upper surface of the substrate 150 .

[0251] An opening is formed in at least a part of the bottom surface of the insulator 132, and the semiconductor The semiconductor 134 is in contact with the region 172a. corresponds to any one of the wirings RBL[1,1] to [m1,m3] shown in FIG. The region 172a functions as the source region or the drain region of the transistor 61. By adopting the above-mentioned configuration, the wiring RBL at the bottom of the memory cell string The source region or drain region of the transistor 61 of the selected transistor cell 60 is electrically connected to the can be effectively connected.

[0252] Additionally, insulator 164 has an opening that reaches region 172b and an opening that reaches conductor 154a. The openings are filled with a conductor 180a and a conductor 180b, respectively. Furthermore, the insulator 166 has an opening that reaches the conductor 180a and an opening that reaches the conductor 180b. The openings are provided with conductors 178a and 178b, respectively. The insulator 168 has an opening that reaches the conductor 178a. The opening is filled with a conductor 176a. 6a, and a conductor 174a is embedded in the opening.

[0253] Here, the conductor 174a functions as the source region or the drain region of the transistor 61. The wiring RBL[1] to [m1] shown in FIG. ]. The conductor 178b functions as the gate of the transistor 61. It is electrically connected to the conductor 154a that functions as the wiring SG1 shown in FIG. The data is read out through the wiring SG1 and the transistor 61 thus formed. In this case, any one of the two-dimensional memory cell arrays 30[1] to [m3] can be selected. Cut.

[0254] The insulators 164, 166, 168 and 170 may be, for example, boron. element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing hafnium or tantalum may be used in single or multilayer configurations.

[0255] One or more of the insulators 164, 166, 168, and 170 may be formed of a material such as hydrogen. It is preferable to have an insulator that has the function of blocking impurities and oxygen. Impurities such as hydrogen and acids are present in the layer below the transistors 12 included in the memory cell array 40. By disposing an insulator that has the function of blocking the element, the electrical The characteristics can be stabilized.

[0256] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include fluorine, Uron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium Insulators containing titanium, hafnium or tantalum may be used in single or multilayer configurations.

[0257] Conductor 180a, conductor 180b, conductor 178a, conductor 178b, conductor 176a The conductor 174a may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, Aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, Yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum Conductors containing one or more of zinc and tungsten may be used in a single layer or a multilayer. For example, the conductor may be an alloy or compound, such as an aluminum-containing conductor, a copper-containing conductor, or a titanium-containing conductor. Conductors, conductors containing copper and manganese, conductors containing indium, tin and oxygen, Conductors containing titanium and nitrogen may also be used.

[0258] 12(C) and 12(D) show transistors provided in the selection transistor array 50 shown in FIG. 12C is a cross-sectional view of the transistor 62. The cross-section C5-C6 shown in FIG. 12(D) is a cross section of the transistor 6. 2 shows a cross section in the channel width direction.

[0259] The semiconductor device shown in FIGS. 12C and 12D includes an insulator 132, a semiconductor 134, and an insulating layer. 12 except that instead of the conductive body 136, the conductive body 120 is formed. The structure of the semiconductor device shown in (A) and (B) is the same as that of the semiconductor device shown in (A). 50, region 172d in semiconductor substrate 150, insulator 162b, and conductive The region 172c and the region 172d are the same as the region 172a and the region 172b. The insulator 162b has the structure of the insulator 162a, and the conductor 154b has the structure of the conductor 154b. The configuration of the electric body 154a can be taken into consideration.

[0260] In addition, the conductor 180c, the conductor 180d, the conductor 178c, the conductor 178d, and the conductor 1 76b and conductor 174b are conductors 180a, 180b, 178a, and conductor The structures of the conductor 178b, the conductor 176a, and the conductor 174a can be taken into consideration.

[0261] Insulators 164, 166, 168, and 170 extend to region 172c. The conductive material 120 is a cylindrical opening. The conductor 120 is formed in a cylindrical shape in contact with the inner wall of the opening. The conductors shown in FIGS. 120 corresponds to any one of the wirings WBL[1,1] to [m1,m3] shown in FIG. region 172c functions as the source or drain region of transistor 62. By adopting the above-described configuration, the transistor 1 of the memory cell 10 The wiring WBL electrically connected to the transistor 62 of the selection transistor cell 60 is The source region or the drain region can be electrically connected.

[0262] Additionally, the conductor 174b functions as the source or drain region of the transistor 62. 5 and the wiring WBL[1] to [m1] shown in FIG. Conductor 178d also functions as the gate of transistor 62. The wiring SG2 shown in FIG. 5 is electrically connected to the conductor 154b. When data is written, the signal is input to the wiring SG2 and the transistor 62. In this case, any one of the two-dimensional memory cell arrays 30[1] to [m3] can be selected. do.

[0263] The semiconductor devices shown in FIGS. 13(A), 13(B), 13(C), and 13(D) are the same as those shown in FIG. 12(B) and 12(C)(D) The only difference is the structure of the capacitor 62. The semiconductor device shown in FIG. 12(A), (B) and FIG. 12(C)(D) The description of the body device can be taken into consideration. Specifically, Figures 13(A)(B) and 13(C) In the semiconductor device shown in (D), the transistor 61 or the transistor 62 is a fin type. The transistor 61 or the transistor 62 is a fin type. As a result, the effective channel width of the transistor 61 or the transistor 6 2. The on-state characteristics of the gate electrode can be improved by increasing the contribution of the electric field of the gate electrode. Therefore, the off characteristics of the transistor 61 or the transistor 62 can be improved. can.

[0264] <Modification of memory cell> A modification of the transistor 12 will be described below with reference to FIG. 8B and 8C, a cross-sectional view of the transistor 12 in the channel length direction and a 1 is a cross-sectional view of the transistor 12 in the channel width direction.

[0265] The memory cell 10a shown in FIGS. 14(A) and 14(B) is mainly a transistor 12a. The transistor 12a is different from the transistor 12 in that the transistor 12a has an insulator 119, an insulator 118, and an insulator 119 below the insulator 104. An insulator 101, an insulator 107, a conductor 102, an insulator 103 and an insulator 105 are formed. The transistor 101 is formed on the insulator 119. An insulator 107 is formed on the insulator 101, and a conductor 102 is formed in the opening of the insulator 107. The insulator 105 is formed on the insulator 107 and the conductor 102. Then, the insulator 103 is formed on the insulator 105, and the insulator 104 is formed on the insulator 103. It is formed.

[0266] The insulator 119 may be an insulator that can be used as the insulator 104. .

[0267] The insulator 101 is an insulator that has the function of blocking hydrogen or water. The hydrogen and water in the insulator provided near the semiconductor 106a, the semiconductor 106b, and the insulator 106c are converted into oxides. Carriers are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c, which also function as semiconductors. This may cause a decrease in the reliability of the transistor 12. In particular, the memory cell 10(1,1,1) provided at the bottom of the three-dimensional memory cell array 40 1 to (m1,1, m3) are the closest to the selection transistor array 50 and are therefore isolated. It is more effective to provide the insulating body 101. When a semiconductor element is provided, hydrogen is used to terminate the dangling bonds of the semiconductor element. The hydrogen may diffuse to the transistor 12. By providing an insulator 101 having a function of blocking water, the transistor 12 is This can prevent hydrogen or water from diffusing from the layer, thereby improving the reliability of the transistor 12. can.

[0268] In addition, the insulator 101 preferably has a function of blocking oxygen. By blocking oxygen diffusing from the insulator 104, Oxygen can be effectively supplied to the semiconductor 106a, the insulator 106b, and the semiconductor 106c.

[0269] The insulator 101 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium oxynitride or the like can be used. This allows the film to function as an insulating film that blocks the diffusion of oxygen, hydrogen, or water. The insulator 101 may be made of, for example, silicon nitride or silicon nitride oxide. By using these as the insulator 101, the diffusion of hydrogen and water can be blocked. It can function as an insulating film that exhibits a blocking effect.

[0270] At least a portion of the conductor 102 is located in a region sandwiched between the conductors 108a and 108b. The conductor 102 preferably overlaps with the semiconductor 106b in the By providing such a conductor 102, the transistor The threshold voltage of 12 can be controlled. , the voltage applied to the gate (conductor 114) of transistor 12 is low, e.g. When the applied voltage is 0 V or less, the transistor 12 can be prevented from being turned on. In other words, the electrical characteristics of the transistor 12 are shifted more in the normally-off direction. The conductor 102 can be used as the conductor 114. A conductor may be used.

[0271] The length of the conductor 102 in the channel length direction is the length of the semiconductor 106b in the channel length direction. It is preferable that the conductive material 102 is larger than the semiconductor 106b, and that the conductive material 102 covers the lower surface of the semiconductor 106b. By providing the conductor 102, the electric field generated in the memory cell provided below is 102, the electric field is shielded, and the influence of the electric field on the semiconductor 106b can be suppressed. .

[0272] The insulator 107 may be an insulator that can be used as the insulator 104. The upper surfaces of the insulator 107 and the conductor 102 are planarized by a CMP method or the like. It is preferable to improve the flatness by using a conductive layer that functions as a back gate. Even if the body 102 is provided, the flatness of the surface on which the semiconductor 106b is formed is not impaired. This improves the mobility of the electrons and increases the on-state current of the transistor 12. The step on the surface of the insulator 104 caused by the shape of the conductor 102 is eliminated, so that the conductor 1 Between the drain and the conductor 102, one of the drains 108a and 108b is an insulator 108. This reduces the leakage current that occurs through the step portion of the transistor. The off-state current of the transistor 12 can be reduced.

[0273] The insulator 105 may be an insulator that can be used as the insulator 104. .

[0274] The insulator 103 preferably has a function of blocking oxygen. By providing 103, the conductor 102 is prevented from extracting oxygen from the insulator 104. As a result, the insulator 104 is transferred to the insulator 106a, the semiconductor 106b, and the insulator 106c. Oxygen can be effectively supplied to the insulating layer 106c. This reduces the amount of oxygen extracted from the insulator 104, and Oxygen can be supplied more effectively to the insulator 106a, the semiconductor 106b, and the insulator 106c. can.

[0275] The insulator 103 may be boron, aluminum, silicon, scandium, titanium, or gallium. Sodium, yttrium, zirconium, indium, lanthanum, cerium, neodymium, halide An oxide or nitride containing hafnium or thallium is used. Preferably, hafnium oxide is used. Aluminum or aluminum oxide is used.

[0276] In the insulators 105, 103, and 104, the insulator 103 traps electrons. It is preferable that the insulator 105 and the insulator 104 have a function of suppressing the emission of electrons. When the insulator 103 has the function of trapping electrons, the electrons trapped in the insulator 103 behave like fixed negative charges. Therefore, the insulator 103 functions as a floating gate.

[0277] However, the memory cell 10a is not limited to the configuration shown in FIGS. 14(A) and 14(B). For example, the insulators 107, 105, and 104 are not provided, and the insulator 104 is a conductor. It may be configured to protrude in accordance with the shape of the insulator 102, or a configuration without the insulator 101 may be used. It may also be composed.

[0278] The memory cell 10b shown in FIGS. 14(C) and 14(D) is mainly a transistor 12b. The transistor 12b is different from the transistor 12 in that the insulators 106c and 112 are semiconductor. The insulating layer 11 is formed to cover the conductive body 106b, the conductive body 108a, and the conductive body 108b. 117 is formed on the insulator 112 and the conductor 114, and the insulator 117 is formed on the insulator 117. The transistor 12 differs from the transistor 12 in that a transistor 8 is formed.

[0279] The capacitance element 14b uses the insulator 112 and the insulator 106c as dielectrics. The capacitor element 14 differs from the capacitor element 14 in that it has a capacitance of 1.5 V.

[0280] The insulator 117 may be an insulator that can be used for the insulator 116. Here, the insulator 117 is preferably formed by sputtering. It is more preferable to perform the sputtering under an insulating atmosphere. By forming the insulator 117, the surface of the insulator 112 (insulator 117) After the film formation, oxygen is added to the vicinity of the interface between the insulator 112 and the insulator 117 .

[0281] The insulator 117 is an insulator that is less permeable to oxygen than the insulator 112, and blocks oxygen. By providing such an insulator 117, When oxygen is supplied from the body 112 to the insulator 106a, the semiconductor 106b, and the insulator 106c, This can prevent the oxygen from being released to the outside above the insulator 112. Aluminum oxide makes the membrane permeable to both impurities such as hydrogen and moisture, and oxygen. It is preferable to apply it to the insulator 117 because it has a high blocking effect without being affected by light.

[0282] However, the memory cell 10b is not limited to the configuration shown in FIGS. 14(C) and 14(D). For example, a part of the insulator 106 or the insulator 112 may be patterned.

[0283] The memory cell 10c shown in FIGS. 14(E) and 14(F) is mainly a transistor 12c. The transistor 12c is different from the transistor 12 in that the conductor 108a and the conductor 108b are insulated. The insulating layer 118 is formed on the semiconductor 106b and is in contact with the semiconductor 106b through an opening formed in the insulating layer 118. In this respect, the insulator 137 is formed on the conductor 108a and the conductor 108b, and the insulator 13 7, and an insulator 138 is formed on the insulator 137 and the conductor 122. The insulator 117 is formed to cover the insulator 106c and the like, and the conductive The side edges of the body 114 and the insulator 112 are generally aligned. The transistor 12 is different from the transistor 12. The low resistance regions 109a and 109b functioning as source and drain regions are used as gates. This is a gate-last method in which the gate is formed before the formation of the functional conductor 114. In the transistor manufacturing process, the source region or the drain region of the transistor 12c is The low resistance regions 109a and 109b functioning as a gate are formed in the shape of the conductor 114. This is a gate-first method in which the gate is formed after growth.

[0284] In the transistor 12c, the low resistance region 109a and the low resistance region 109b are made of an insulator. The low resistance region 109a and the low resistance region 117 include at least one of the elements included in the low resistance region 109a and the low resistance region 117. A part of the semiconductor 106b overlaps with the conductor 114 (channel formation region). It is preferable that the area is approximately in contact with or overlaps with a part of the area.

[0285] In addition, the low resistance region 109a and the low resistance region 109b are formed by using an element contained in the insulator 117. Since the semiconductor 106b is doped with Zn, the low resistance region 109a and the low resistance region 109b of the semiconductor 106b are not SIMS analysis is more sensitive to the area of ​​the semiconductor 106b than to the area of ​​the semiconductor 106c that overlaps the conductor 114. This results in a higher concentration of the element.

[0286] The elements added to the low resistance region 109a and the low resistance region 109b include, for example, boron. element, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, Zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum or tungsten These elements are relatively easy to form oxides, and the oxides are semiconductors. Therefore, the semiconductor 106a, the semiconductor 106b, or the insulator 106c can function as a semiconductor or an insulator. For example, the low resistance region 109a and the low resistance region 109b are preferably added to the low resistance region 109c. b contains 1×10 14 / cm 2 Over 2×10 16 / cm 2 It is preferred to include the following: In addition, the low resistance region 109a and the low resistance region 109b in the insulator 106c are preferably insulated. The region other than the low resistance region 109a and the low resistance region 109b of the insulator 106c (for example, an insulating region The concentration of the above elements is higher in the region (region overlapping with the conductor 114 of the body 106c) than in the region (region overlapping with the conductor 114 of the body 106c).

[0287] The low resistance regions 109a and 109b contain nitrogen, thereby forming n-type Therefore, the low resistance region 109a and the low resistance region 109b of the semiconductor 106b can be b (for example, the area of ​​the semiconductor 106b overlapping with the conductor 114) The nitrogen concentration obtained by analysis is higher.

[0288] By forming such low resistance regions 109a and 109b, a conductive The semiconductor 108a or the conductor 108b and the insulator 106a, the semiconductor 106b or the insulator 106c. Since the contact resistance of the transistor 12c can be reduced, the on-current of the transistor 12c can be increased. It is possible.

[0289] In the transistor 12c, the semiconductor 106b is connected to the insulator 106a and the insulator 106c. Therefore, the side edge of the semiconductor 106b, in particular The vicinity of the side end in the channel width direction is provided in contact with the insulator 106a and the insulator 106c. As a result, the insulator 106a or the insulating material 106b is in contact with the semiconductor 106b in the vicinity of the side edge of the semiconductor 106b. A continuous junction is formed between the layer 106c and the substrate 106, and the defect level density is reduced. Even if the on-current becomes easier to flow by providing the low-resistance region 109a and the low-resistance region 109b, The side edge of the semiconductor 106b in the channel width direction does not become a parasitic channel, resulting in stable electrical characteristics. can be obtained.

[0290] Furthermore, the capacitance element 14c is a capacitance element in that an insulator 137 is used as a dielectric. The insulators 137 and 138 are different from the insulator 118. Any suitable insulator may be used.

[0291] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0292] (Embodiment 3) In this embodiment, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. This will be explained using FIG.

[0293] In the following, the A1-A2 cross section of the memory cells 10 constituting the three-dimensional memory cell array 40 will be referred to as A method for fabricating the three-dimensional memory cell array 40 will be described with attention to the plane and the A3-A4 cross section. Although only one memory cell 10 is shown in the figure, memory cells formed on the same plane 10 (for example, memory cells 10(1,1,1) to (m1,1,m3) shown in FIG. 2) can be made simultaneously.

[0294] First, a substrate on which the selection transistor array 50 is formed is prepared. The transistor array 50 is made of an insulator 1 shown in FIGS. 12(A), 12(B), 12(C), and 12(D). 32, semiconductor 134, insulator 136, and conductor 120 before being formed. The select transistor array 50 may be fabricated by any known method.

[0295] First, the insulator 104 is formed. The insulator 104 may be any of the above-described insulators.

[0296] The insulator 104 is formed by a sputtering method, a chemical vapor deposition (CVD) method, or the like. Vapor Deposition method, Molecular Beam Epitaxy (MBE) Laser Beam Epitaxy (PLD) or Pulsed Laser Deposition (PLD) Atomic Layer Deposition (ALD) This can be done using a method such as ferroelectric deposition.

[0297] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be further classified into the VD method, which uses light, and the Photo CVD method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0298] In order to reduce the amount of water or hydrogen contained in the insulator 104, the substrate is heated. It is preferable to perform film formation.

[0299] In addition, it is preferable that the upper or lower surface of the semiconductor 106b to be formed later has high flatness. Therefore, the top surface of the insulator 104 is subjected to a planarization process such as CMP to improve the planarity. That's fine.

[0300] Next, heat treatment is preferably performed. By the heat treatment, water in the insulator 104, Alternatively, hydrogen can be further reduced. Also, by making the insulator 104 have excess oxygen, The heat treatment is carried out at a temperature of 250°C or higher and 650°C or lower, preferably 450°C or lower. The heating temperature is preferably from 520°C to 570°C. The treatment is in an inert gas atmosphere or an oxidizing gas of 10 ppm or more, 1% or more, or 10% The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out under an inert atmosphere. After heat treatment in an oxidizing gas atmosphere, an oxidizing gas of 10 ppm or less is added to compensate for the oxygen that has been removed. The heat treatment may be carried out in an atmosphere containing 1% or more or 10% or more of the above. The crystallinity of the insulator 126a and the semiconductor 126b can be improved, and impurities such as hydrogen and water can be removed. Heat treatment can be performed using an RTA device that uses lamp heating. Heat treatment using an RTA device takes less time than using a furnace, so it is suitable for increasing productivity. It is effective for.

[0301] In addition, in accordance with the configuration of the selection transistor array 50, a relatively low temperature range (for example, For example, it may be preferable to heat the material at a temperature in the range of about 350° C. to 445° C.

[0302] Next, an insulator that will become the insulator 106a in a later step is formed. Any insulator or semiconductor that can be used as the insulator 106a may be used. The film formation of the substrate is done by sputtering, CVD, MBE, PLD, ALD, etc. This can be done using

[0303] Next, a semiconductor film is formed that will become the semiconductor 106b in a later step. Any semiconductor that can be used as the semiconductor 106b may be used. Sputtering, CVD, MBE, PLD, ALD, etc. The formation of the insulator film that will become the insulator 106a and the formation of the semiconductor film that will become the semiconductor 106b can be performed. By performing the film formation and the deposition in succession without exposing to the atmosphere, impurities are prevented from being mixed into the film and the interface. can be reduced.

[0304] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the insulator 106a and the semiconductor In some cases, the hydrogen concentration in the insulator 106a and the insulator 106b can be reduced. The heat treatment may be performed at 250° C. or higher than 650°C, preferably higher than 450°C and lower than 600°C, and more preferably higher than 520°C. The heat treatment can be carried out at a temperature of 570°C or less. The heat treatment is carried out in an atmosphere containing more than ppm, more than 1%, or more than 10%. Alternatively, the heat treatment may be carried out in an inert gas atmosphere, followed by absorbing the desorbed oxygen. To compensate for this, heat treatment is carried out in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. The crystallinity of the insulator 106a and the semiconductor 106b can be improved by heat treatment. The heating process can be performed by lamp heating or by removing impurities such as hydrogen and water. An RTA device can also be used. Heat treatment with an RTA device is shorter than that with a furnace. This is effective in increasing productivity because it only takes a short time. When CAAC-OS is used as a fluorine-containing compound, the peak intensity increases by heat treatment. The full width of the value is reduced, which means that the crystallinity of the CAAC-OS is increased by the heat treatment.

[0305] In addition, in accordance with the configuration of the selection transistor array 50, a relatively low temperature range (for example, For example, it may be preferable to heat the material at a temperature in the range of about 350° C. to 445° C.

[0306] The heat treatment converts the insulator 104 into the insulator 106a and the semiconductor 106 In this way, oxygen can be supplied to the semiconductor that becomes the insulator 106a. By supplying oxygen to the semiconductor that will become the semiconductor 106b and reducing oxygen vacancies, A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor having a low density of recess states can be obtained. Cut.

[0307] Further, high density plasma treatment may be performed. High density plasma is generated by using microwaves. In the high-density plasma treatment, for example, an oxidizing gas such as oxygen or nitrous oxide is used. Alternatively, a mixture of an oxidizing gas and a rare gas such as He, Ar, Kr, or Xe can be used. A mixed gas may be used. In the high density plasma treatment, a bias may be applied to the substrate. This allows oxygen ions in the plasma to be drawn to the substrate. The plasma treatment may be performed while heating the substrate. When performing plasma treatment, the same effect can be obtained at a temperature lower than that of the heat treatment. The high-density plasma treatment may be performed before forming the insulator that will become the insulator 106a, or after forming the insulator. This may be performed before the formation of the insulator 116 or before the formation of the insulator 106c.

[0308] Next, a resist or the like is formed on the insulator that will become the insulator 106a and the semiconductor that will become the semiconductor 106b. Then, the resist is used to process the insulator 106a and the semiconductor 106b. (See Figures 15(A) and 15(B)). When simply saying that a resist is formed, This also includes the case where an anti-reflection layer is formed underneath.

[0309] The resist is removed after the object is processed by etching or other methods. For this purpose, plasma treatment and / or wet etching are used. Plasma ashing is suitable for this purpose. If the removal of resist, etc. is insufficient, Hydrofluoric acid and / or ozone at a concentration of 1% by volume or more but not exceeding 1% by volume Residual resist may be removed using rinsing water or the like.

[0310] Next, heat treatment is preferably performed. By the heat treatment, water in the insulator 104, Alternatively, hydrogen can be further reduced. The temperature is preferably 450°C or higher and 600°C or lower, and more preferably 520°C or higher and 570°C or lower. The heat treatment is preferably carried out in an inert gas atmosphere. The heat treatment may be carried out in an atmosphere containing the metal. The heat treatment may be carried out under reduced pressure. After heat treatment in an active gas atmosphere, oxidizing gas is added at 10 ppm to compensate for the oxygen that has been removed. The heat treatment may be carried out in an atmosphere containing 1% or more or 10% or more of fluorine. An RTA device using a pump can also be used. Heat treatment using an RTA device is more efficient than using a furnace. This is effective in increasing productivity as it takes only a short time.

[0311] In addition, in accordance with the configuration of the selection transistor array 50, a relatively low temperature range (for example, For example, it may be preferable to heat the material at a temperature in the range of about 350° C. to 445° C.

[0312] Next, a conductor is formed as a film, a resist or the like is formed on the conductor, and the resist or the like is used to form a film. The conductor 108 is formed by processing the conductor 108 (see FIGS. 15(C) and 15(D)). The conductors that can be used as the conductors 108a and 108b described above are The conductor used for the conductor 108 can be formed by a sputtering method, a CVD method, or the like. The method can be carried out by using a method such as MBE, PLD, or ALD.

[0313] Next, the insulator 116 is formed. As the insulator 116, any of the above insulators may be used. The insulator 116 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. This can be done using methods such as the

[0314] The insulator 116 is preferably formed by using plasma, and is preferably formed by sputtering. It is more preferable to use a sputtering method in an oxygen-containing atmosphere. It is more preferable to do this.

[0315] The sputtering method uses a direct current (DC) power supply for the sputtering power supply. Current sputtering method, and pulsed DC sputtering method, which applies a bias in a pulsed manner. RF (Radio Frequency) sputtering method, which uses a high frequency power supply for sputtering. A sputtering method may also be used. A magnetron having a magnet mechanism inside the chamber may also be used. bias sputtering, which applies voltage to the substrate during film formation; reactive A reactive sputtering method performed in a gas atmosphere may also be used. The oxygen gas flow rate and film formation power for sputtering may be adjusted depending on the amount of oxygen. The amount may be determined appropriately depending on the amount added, etc.

[0316] By forming the insulator 116 by sputtering, the insulator 116 is formed simultaneously with the film formation. Oxygen is added near the surface of insulator 104 (the interface between insulator 104 and insulator 116 after insulator 116 is formed). Here, oxygen is added to the insulator 104 as, for example, oxygen radicals. The state in which oxygen is added is not limited to this. The oxygen may be an oxygen atom or an oxygen ion. The oxygen may be added to the insulator 104 in the above state. In some cases, oxygen is contained in excess of the stoichiometric composition, and in this case, the oxygen is called excess oxygen. You can also do this.

[0317] Next, a conductor is formed as a film, a resist or the like is formed on the conductor, and the resist or the like is used to form a film. The conductive material 122 is formed by processing the conductive material 122 (see FIGS. 15(E) and 15(F)). The conductor may be any of the conductors that can be used as the conductor 122 described above. The conductive material used for the conductive material 122 is formed by sputtering, CVD, MBE or P This can be done using the LD method, ALD method, or the like.

[0318] Next, a resist or the like is formed on the conductor 128, and the resist or the like is used to process the conductor. The conductive body 108a and the conductive body 108b are formed.

[0319] Next, an insulator that will become the insulator 118 is formed. The insulator serving as the insulator 118 can be formed by a sputtering method, a CV method, or the like. This can be done using the D method, MBE method, PLD method, ALD method, or the like.

[0320] Next, a resist or the like is formed on the insulator that will become the insulator 118. The insulating layer 118a, the conductor 108a, and the conductor 108b are formed (FIG. 16(A)). )(B). ).

[0321] In addition, in a region of the semiconductor 106b in contact with the conductor 108a and the conductor 108b, A resistive region 109a and a low resistive region 109b may be formed. b is a portion between the conductor 108a and the conductor 108b that overlaps the conductor 108a and the conductor 108b. This is because the conductor 108a and the conductor 108b may have a region with a thinner film thickness than the region with a thinner film thickness. When forming 08b, it is formed by removing a part of the upper surface of semiconductor 106b.

[0322] Here, the capacitance element 14 having the conductor 108b, the insulator 116, and the conductor 122 is formed. will be done.

[0323] Next, an insulator 106d that will become the insulator 106c in a later step is formed. For example, an insulator or a semiconductor that can be used as the insulator 106c described above may be used. The insulator 106d may be formed by sputtering, CVD, MBE, or PLD. Before forming the insulator 106d, the semiconductor 10 The surface of the substrate 6b may be etched. For example, the surface of the substrate 6b may be etched using a plasma containing a rare gas. After that, the insulator 106d is formed continuously without being exposed to the atmosphere. By forming a film, the inclusion of impurities at the interface between the semiconductor 106b and the insulator 106c is reduced. Impurities present at the interface between films tend to diffuse more easily than impurities within the film. Therefore, by reducing the amount of impurities mixed in, the transistor can be made stable. It is possible to impart excellent electrical properties.

[0324] Next, an insulator 112a that will become the insulator 112 in a later step is formed. For the insulating layer 112, any insulating material that can be used as the insulating layer 112 may be used. The film of a is formed by the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. The formation of the insulator 106d and the formation of the insulator 112a can be performed simultaneously. By performing this process continuously without exposing the film to air, it is possible to reduce the inclusion of impurities in the film and at the interface. This can be done.

[0325] Next, a conductor 114a that will become the conductor 114 in a later step is formed (FIGS. 16(C) and 16(D)). The conductor 114a is a conductor that can be used as the conductor 114 described above. The conductor 114a can be formed by a sputtering method, a CVD method, an MBE method, or the like. Alternatively, the PLD method, the ALD method, or the like can be used. By continuously performing the above steps without exposing the conductive material 114a to the atmosphere, the conductive material 114b is formed in the film and at the boundary. This can reduce the amount of impurities that get mixed into the surface.

[0326] Next, the conductor 114a is polished until the insulator 118a is exposed. 114, insulator 112, insulator 106c and insulator 118 are formed (FIG. 16(E)( 1F). The conductor 114 and the insulator 112 are the gate of the transistor 12. The conductor 114 and the gate insulator are formed by the above-described method. The insulating layer 112 can be formed in a self-aligned manner.

[0327] The insulators 118, 106c, and 11 are the same as the insulator 116. 2 and the conductor 114, and oxygen may be added to the insulator 118.

[0328] Next, it is preferable to perform heat treatment. By performing heat treatment, the insulator 104 (or The oxygen added to the insulator 106a, the semiconductor 106b, and the insulating layer 118 is diffused. The heat treatment can be performed at a temperature of 250° C. or higher and 650° C. or lower, preferably The heat treatment may be carried out at a temperature of 350°C or higher and 450°C or lower. The heat treatment is carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of reactive gas. Heat treatment may be carried out under pressure. Heat treatment may also be carried out using an RTA device with lamp heating. .

[0329] The temperature of this heat treatment is preferably lower than that of the heat treatment performed after the formation of the semiconductor 126b. The temperature difference between the heat treatment after the semiconductor 126b deposition and the heat treatment after the semiconductor 126b deposition is 20°C or more and 150°C or less, preferably 4 The temperature is set to 0° C. or higher and 100° C. or lower. This allows excess oxygen (oxygen) to be released from the insulator 104 and the like. ) can be suppressed from being released. In the case where the heat treatment for the insulating layer 118 can be performed by the heat treatment for the insulating layer 118 during the film formation, In some cases, this may not be necessary (when equivalent heating is performed in the deposition of the film).

[0330] The heat treatment converts the oxygen added to the insulator 104 (or the insulator 118) into an insulating material. The insulator 116 is more permeable to oxygen than the insulator 104. It is an insulator that does not easily allow oxygen to pass through, and functions as a barrier film that blocks oxygen. Since the insulator 116 is formed on the insulator 104, oxygen diffusing through the insulator 104 is insulated. The diffusion does not occur upward in the insulator 104, but occurs mainly in the lateral or downward direction in the insulator 104.

[0331] The oxygen diffusing through the insulator 104 is transferred to the insulators 106a, 106c, and the semiconductor 106. At this time, an insulator having a function of blocking oxygen is provided under the insulator 104. By providing the insulating layer 104 at the upper surface of the insulating layer 104, oxygen diffused into the insulating layer 104 can be easily transported to a lower layer than the insulating layer 104. It is possible to prevent the diffusion of the insulator 116. When forming the insulator 118, oxygen is also contained in the insulators 106a, 106c, and and semiconductor 106b.

[0332] In this way, the insulator 106a, the insulator 106c and the semiconductor 106b, especially the semiconductor 106b, Oxygen can be effectively supplied to the region where the channel is formed in O6b. Oxygen is supplied to the insulator 106a, the insulator 106c, and the semiconductor 106b, and oxygen vacancies are reduced. By this, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor with a low density of defect states can be obtained. It may be a conductor.

[0333] In this manner, the transistor 12 and the capacitor element 14 of the memory cell 10 can be formed. By repeating the above steps, a metal oxide film having a transistor 12 and a capacitor element 14 formed thereon can be obtained. The memory cell 10 can be formed by stacking the transistor 12 and the capacitance element 14. After stacking the memory cells 10, the conductors 120 and the transistors of the three-dimensional memory cell array 40 are The transistors 11 are formed in a lump.

[0334] The manufacturing method of the conductor 120 and the transistor 11 will be described below with reference to FIGS. 17 to 20. In the following description, the memory cells 10 are stacked in two stages, and the cross section of FIG. (C)(D) shows a cross section along D3-D4 corresponding to the vicinity of the conductor 120, and (B) shows a cross section along D3-D4 corresponding to the vicinity of the conductor 120. Attention is now focused on the D5-D6 cross section corresponding to the vicinity of the transistor 11.

[0335] First, a method for forming the conductor 120 will be described with reference to FIG.

[0336] First, a resist or the like is formed on the topmost memory cell 10, and then, using the resist or the like, An opening 17 extending from the top memory cell 10 to the region 172c of the select transistor cell 60 1 (see FIGS. 17(A) and 17(B)). The opening 171 is In the present embodiment, at least the insulator 104, the conductor 108a, the insulator 116, and the insulator 11 8, and in the select transistor array 50, at least the semiconductor substrate 150 Region 172a is formed in insulator 164, insulator 166, insulator 168, and insulator 170. do.

[0337] The opening 171 is formed to extend in a direction substantially perpendicular to the upper surface of the substrate, and has a very small aspect ratio. Therefore, the opening 171 is formed by etching in a direction substantially perpendicular to the upper surface of the substrate. It is preferable to use anisotropic etching, which has a fast etching rate. For example, dry etching When forming the opening 171, the region 172 of the semiconductor substrate 150 A part of c may be over-etched, forming a recess on the surface of the semiconductor substrate 150. .

[0338] Next, the conductor 120 is formed in the opening 171 (see FIGS. 17(C) and 17(D)). The body 120 may be any conductor that can be used as the conductor 120 described above. As described above, the opening 171 has a very high aspect ratio, and therefore, it is difficult to form the opening 171 by an ALD method or a CVD method. It is preferable to form the conductor 120 by using a method such as CVD. It is preferable to form the film by using the OCVD method or the MCVD method.

[0339] In the uppermost memory cell 10, the upper surface of the conductor 120 is insulated so as not to be exposed. It is preferable to cover it with your body.

[0340] Next, a method for forming the transistor 11 will be described with reference to FIGS. 18 to 20. .

[0341] First, a resist or the like is formed on the topmost memory cell 10, and then, using the resist or the like, An opening 18 extending from the top memory cell 10 to the region 172a of the select transistor cell 60 1a (see FIGS. 18(A) and 18(B)). The opening 181a is also formed in the same manner as the opening 171. In the two-dimensional memory cell array 40, at least an insulator 104, a conductor 108a, an insulating 116 and an insulator 118, and in the select transistor array 50, at least In addition, the region 172a of the semiconductor substrate 150, the insulators 164, 166, 168, and It is formed on an insulator 170 .

[0342] The opening 181a is formed to extend in a direction substantially perpendicular to the upper surface of the substrate, and has a very narrow aspect ratio. Therefore, the opening 181a is also formed on the upper surface of the substrate in the same manner as the opening 171. It is preferable to use anisotropic etching, in which the etching proceeds at a high rate in the substantially perpendicular direction. For example, dry etching may be used. In this case, a portion of the region 172a of the semiconductor substrate 150 is over-etched, and the surface of the semiconductor substrate 150 is exposed. A depression may form on the surface.

[0343] Next, the insulator 132 is formed in contact with the inner wall of the opening 181a (see FIGS. 18(C) and (D)). The insulator 132 may be any of the insulators that can be used as the insulator 132 described above. As described above, the opening 181a has a very high aspect ratio, and therefore, it is possible to form the opening 181a by the ALD method or the It is preferable to form the insulator 132 by using a CVD method or the like. Since it functions as a gate insulating film for the transistor 11, it is preferable that the film thickness be highly uniform. Therefore, the ALD method is preferable in terms of high film thickness controllability.

[0344] Next, an opening 181b reaching the region 172a is formed in the bottom of the insulator 132 (FIG. 19( The opening 181b is formed in at least a part of the bottom surface of the insulator 132. Therefore, the diameter of opening 181b is often smaller than that of opening 181a.

[0345] Here, the opening 181b is formed by removing the insulator 132 formed on the sidewall of the opening 181a. It is necessary to remove at least a part of the bottom surface of the insulator 132 without removing the opening. The opening 181b is also formed in the same manner as the opening 181a, by forming an opening in a direction substantially perpendicular to the upper surface of the substrate. It is preferable to use anisotropic etching, which has a fast etching rate. When forming the opening 181b, the area of ​​the semiconductor substrate 150 A portion of the region 172a is over-etched to form a further recess in the surface of the semiconductor substrate 150. This may be the case.

[0346] Next, a semiconductor 134 is formed inside the insulator 132 (see FIGS. 19(C) and (D)). As the semiconductor 134, the semiconductor that can be used as the semiconductor 134 described above may be used. Here, the semiconductor 134 is provided in contact with the region 172a.

[0347] As described above, the opening 181a has a very high aspect ratio, and therefore, it can be formed by the ALD method, the CVD method, or the like. It is preferable to form the semiconductor 134 by using an epitaxial method or the like. The method can be used to form a semiconductor 134, such as monocrystalline silicon or polycrystalline silicon. After the amorphous silicon film is formed, it can be hardened by heat treatment or the like. Alternatively, the semiconductor 134 may be made of polycrystalline silicon by crystallizing the silicon.

[0348] When the semiconductor 134 is made of polycrystalline silicon, it is preferable to make the film thickness of the semiconductor 134 thin. For example, it is preferable to set the thickness to 20 nm or less, and more preferably 10 nm or less. By making the semiconductor 134 have such a film thickness, the characteristics of the transistor 11 can be reduced. This can reduce the risk of injury.

[0349] When forming the semiconductor 134, impurities that impart p-type conductivity or n-type conductivity are added. The semiconductor 134 may be deposited so that it contains impurities that impart a type.

[0350] Next, an insulator 136 is formed inside the semiconductor 134 (see FIGS. 20(A) and (B)). As the insulator 136, the semiconductor that can be used as the insulator 136 described above may be used. The insulator 136 is preferably formed by ALD or CVD. .

[0351] When polycrystalline silicon is used for the semiconductor 134, the insulator 136 contains hydrogen. The dangling bonds in the semiconductor 134 may be terminated by heat treatment or the like. At this time, an insulator having a blocking effect on hydrogen, water, etc. is used as the insulator 132. This prevents hydrogen from diffusing out during heat treatment and more effectively binds the semiconductor 134. Gring bonds can be terminated.

[0352] 19(A) and 19(B), a cylindrical Alternatively, a semiconductor 134 having a shape similar to that of a semiconductor film 134 may be formed (see FIGS. 20(C) and (D)).

[0353] In the uppermost memory cell 10, a conductor is provided so as to contact the upper surface of the semiconductor 134. It is preferable to form a film so that the conductor is electrically connected to the low power supply potential.

[0354] In this way, the conductor 108b, the insulator 132, the semiconductor 134, and the insulator 136 are formed. A vertical transistor 11 can be formed by using the above method. By fabricating the transistor 11, a plurality of transistors included in the three-dimensional memory cell array 40 can be Therefore, the transistor 11 can be manufactured in a very simple process. This allows shortening of the takt time and improving productivity.

[0355] Through the above steps, a semiconductor device according to one embodiment of the present invention can be manufactured.

[0356] By using the above manufacturing method, a semiconductor device with a large storage capacity per unit area can be manufactured. Alternatively, a semiconductor device having a novel structure in which memory cells are stacked can be provided. It is possible.

[0357] As described above, the configurations, methods, etc. shown in this embodiment may be different from the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combinations.

[0358] (Fourth embodiment) In this embodiment, the oxide semiconductor included in the semiconductor device of one embodiment of the present invention will be described in detail. The following explains this.

[0359] <Oxide semiconductor structure> The structure of an oxide semiconductor will be described below.

[0360] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- like oxide semiconductor) and amorphous oxide semiconductor be.

[0361] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxides. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductor, and nc-OS.

[0362] Amorphous structures are generally isotropic and have no heterogeneous structure, and the arrangement of atoms is in a metastable state. The positions are not fixed, the bond angles are flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0363] That is, a stable oxide semiconductor is completely amorphous. s) It cannot be called an oxide semiconductor. Also, it is not isotropic (for example, a periodic structure in a small area) An oxide semiconductor having an amorphous structure cannot be called a completely amorphous oxide semiconductor. ike OS is not isotropic, but has an unstable structure with voids. In terms of instability, a-like OS is similar in physical properties to amorphous oxide semiconductors. stomach.

[0364] <caac-os> First, let me explain about CAAC-OS.

[0365] CAAC-OS is an oxide having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0366] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystal structure was analyzed by the out-of-plane method. As shown in FIG. 21(A), a peak appears at a diffraction angle (2θ) of approximately 31°. The peak is attributed to the (009) plane of the InGaZnO4 crystal, so it is In this case, the crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). It can be confirmed that the direction is perpendicular to the surface, or approximately perpendicular to the upper surface. In addition to the peak around 2θ of 36°, a peak may also appear around 2θ of 36°. The nearby peak is due to a crystal structure classified into the space group Fd-3m. It is preferable that the C-OS does not exhibit such a peak.

[0367] On the other hand, in-pl, X-rays are incident on the CAAC-OS from a direction parallel to the surface to be formed. When structural analysis is performed using the ane method, a peak appears at 2θ around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. And, 2θ is fixed at around 56°. The sample is then rotated around the normal vector of the sample surface as the axis (φ axis) for analysis (φ scan). Even if this is done, no clear peak appears as shown in Figure 21(B). When 2θ is fixed at around 56° and φ is scanned for ZnO4, the As shown, six peaks attributable to the crystal plane equivalent to the (110) plane are observed. Structural analysis using XRD revealed that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0368] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the process was performed parallel to the surface on which the CAAC-OS was formed. When an electron beam with a probe diameter of 300 nm is incident, a diffraction pattern ( This diffraction pattern may contain I The spots due to the (009) plane of the nGaZnO4 crystal are included. Diffraction also shows that the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is formed On the other hand, for the same sample, the direction of the sample surface is perpendicular to the sample surface. The diffraction pattern when an electron beam with a probe diameter of 300 nm was incident perpendicularly to the ) is shown. From Figure 21(E), a ring-shaped diffraction pattern is confirmed. Electron diffraction using an electron beam with a beam diameter of 300 nm also revealed that the pea contained in CAAC-OS It can be seen that the a-axis and b-axis of the lattice do not have any orientation. The first ring is due to the (010) and (100) planes of the InGaZnO4 crystal. The second ring in Figure 21(E) is thought to be due to the (110) plane. It is thought that...

[0369] In addition, a transmission electron microscope (TEM) Combined analysis of bright-field images and diffraction patterns of CAAC-OS using a microscope When observing the image (also called a high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain boundaries), are not clearly visible. It may not be possible to clearly identify the boundary. It can be said that C-OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0370] Figure 22(A) shows a high-resolution image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image is shown. For high-resolution TEM observation, spherical aberration correction (SCA) was used. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. Therefore, it can be observed.

[0371] From Figure 22(A), it is possible to confirm the pellet, which is the region where metal atoms are arranged in layers. The size of a single pellet can be over 1 nm or over 3 nm. Therefore, the pellets can be called nanocrystals (nc). CAAC-OS can also be used as a C-Axis Aligned Navigator (CANC). The pellets can also be called oxide semiconductors with CAA It reflects the unevenness of the surface on which the C-OS is formed or the top surface, and the unevenness of the surface on which the CAAC-OS is formed or It is parallel to the top surface.

[0372] 22(B) and 22(C) show CAA images observed from a direction approximately perpendicular to the sample surface. Figures 22(D) and 22(E) show Cs-corrected high-resolution TEM images of the C-OS surface. 22(B) and 22(C) are processed images, respectively. First, the processing method of FIG. 22(B) is performed using a fast Fourier transform (FFT). Then, the FFT image is obtained by Fourier Transform (FFT). In the acquired FFT image, the origin is used as the reference point, and the -1 to 5.0 nm -1 The range between Next, the masked FFT image is subjected to inverse fast Fourier transform (IFFT) : Inverse Fast Fourier Transform) processing The image thus obtained is called an FFT filtered image. The filtered image is an image in which periodic components are extracted from a Cs-corrected high-resolution TEM image. This shows the child array.

[0373] In Figure 22(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area indicated by the broken line is the connection between the pellets. The broken line indicates the hexagonal shape of the pellet. The shape of the let is not limited to a regular hexagon, but is often a non-regular hexagon.

[0374] In FIG. 22(E), a point is drawn between an area with a uniform lattice arrangement and an area with a different uniform lattice arrangement. The lattice orientation is shown by the dotted line, and the lattice orientation is shown by the dotted line. If you connect the grid points around the dotted line, you will get a distorted hexagon. Shapes such as pentagons and / or heptagons can be formed. In other words, by distorting the lattice arrangement, This indicates that the formation of grain boundaries is suppressed. The atomic arrangement is not dense in the plane direction, and the bond distance between atoms is reduced by substitution of metal elements. This is thought to be because the distortion can be tolerated by changing the distance between the substrate and the substrate.

[0375] As described above, the CAAC-OS has a c-axis orientation and is Multiple pellets (nanocrystals) are connected to form a distorted crystal structure. AAC-OS, CAA crystal(c-axis-aligned abp It can also be called an oxide semiconductor with lane-anchored crystals. Cut.

[0376] CAAC-OS is an oxide semiconductor with high crystallinity. CAAC-OS is designed to be free from impurities and defects. It can also be said to be an oxide semiconductor with few defects (such as oxygen vacancies).

[0377] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more oxidative than metal elements that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0378] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 traps hydrogen and becomes a carrier generation source.

[0379] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. There is. Specifically, 8×10 11 pieces / cm 3 Less than 1 x 10 11 / cm 3 less than , and more preferably 1 × 10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 The above Such an oxide semiconductor can be obtained by using a high-purity pure oxide semiconductor. CAAC-OS is a highly pure or substantially highly pure intrinsic oxide semiconductor. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0380] <nc-os> Next, we will explain nc-OS.

[0381] We will explain the analysis of nc-OS by XRD. However, when structural analysis was performed using the out-of-plane method, no peaks indicating orientation appeared. That is, the crystals of the nc-OS do not have any orientation.

[0382] For example, an nc-OS having InGaZnO4 crystals was thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region of m, the A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in 3(A) was observed. In addition, the diffraction pattern ( The nanobeam electron diffraction pattern is shown in Figure 23(B). Therefore, the nc-OS probe diameter is 50 nm. However, when an electron beam with a probe diameter of 1 nm is incident, the order is not observed. Order is confirmed by injecting light.

[0383] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 23(C), an electron diffraction pattern was observed in which the spots were arranged in a substantially regular hexagonal shape. Therefore, it is possible to assume that the nc-OS is ordered in the range of thickness less than 10 nm. It can be seen that the crystals have highly ordered regions, i.e., crystals. Therefore, there are some areas where a regular electron diffraction pattern is not observed.

[0384] FIG. 23(D) shows the Cs-corrected height of the cross section of the nc-OS observed from a direction approximately parallel to the surface on which the film is formed. The nc-OS is shown in the high-resolution TEM image, with the areas indicated by the auxiliary lines. How to identify the crystal areas and areas where no clear crystal areas can be identified The crystal parts contained in the nc-OS have a size of 1 nm to 10 nm. The size of the crystal part is often between 1 nm and 3 nm. An oxide semiconductor with a size of greater than 10 nm and less than 100 nm is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). It is sometimes called a polycrystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries cannot be clearly identified in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, the crystalline part of nc-OS may be referred to as pellets below.

[0385] In this way, nc-OS can be used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. In the case of the SiO2 film, there is no regularity in the crystal orientation between different pellets. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. In some cases, it may be difficult to distinguish them from solid oxide semiconductors.

[0386] In addition, since there is no regularity in the crystal orientation between the pellets (nanocrystals), nc-OS , oxidation with RANC (Random Aligned nanocrystals) semiconductors or NANC (Non-Aligned nanocrystals) The oxide semiconductor may also be called an oxide semiconductor.

[0387] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0388] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a semiconductor.

[0389] Figure 24 shows a high-resolution cross-sectional TEM image of the a-like OS. is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. B) is 4.3 x 10 8 e - / nm 2 electrons (e - ) a-like OS after irradiation High-resolution cross-sectional TEM images are shown in Figures 24(A) and 24(B). It can be seen that striped bright regions extending in the vertical direction are observed in S from the start of electron irradiation. It can also be seen that the shape of the bright regions changes after electron irradiation. It is assumed to be a density region.

[0390] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0391] As samples, a-like OS, nc-OS, and CAAC-OS were prepared. Both samples are In-Ga-Zn oxides.

[0392] First, high-resolution cross-sectional TEM images of each sample are acquired. All of the materials have crystalline parts.

[0393] The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn It is known that the structure has a total of nine layers, six of which are -O layers, stacked in layers along the c-axis. The distance between these adjacent layers is determined by the lattice spacing (also called the d value) of the (009) plane. The value is about the same, and is calculated to be 0.29 nm from crystal structure analysis. In the following, the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less is referred to as InGaZ. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0394] Figure 25 shows an example of investigating the average size of the crystal parts (22 to 30 locations) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. e The crystal part of the OS grows in size according to the cumulative amount of electron irradiation used to obtain the TEM image. From Figure 25, it can be seen that in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that was left behind (also called the initial nucleus) is filled with electrons (e - ) cumulative exposure is 4.2 × 10 8 e - / nm 2 On the other hand, it can be seen that the size of the crystals grows to about 1.9 nm in the case of n For c-OS and CAAC-OS, the cumulative electron irradiation dose was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of 1000 to 10000. Therefore, the size of the crystalline parts of nc-OS and CAAC-OS is constant regardless of the cumulative electron irradiation dose. , and are approximately 1.3 nm and 1.8 nm, respectively. The Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. The conditions were an acceleration voltage of 300 kV and a current density of 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter of the region was set to 230 nm.

[0395] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in nc-OS and CAAC-OS, the growth of the crystals by electron irradiation is almost nonexistent. In other words, a-like OS is not seen in comparison with nc-OS and CAAC-OS. , it is clear that this is an unstable structure.

[0396] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal of the same composition. The density of the nc-OS is 78.6% or more and less than 92.3% of that of the nc-OS. The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0397] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0398] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By combining these, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density corresponding to a single crystal of a desired composition is calculated based on the ratio of the single crystals of different compositions combined. However, the density can be estimated by using as few types of single crystals as possible. It is preferable to estimate them together.

[0399] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the above-mentioned compounds.

[0400] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0401] (Embodiment 5) This embodiment mode will describe an application example of a memory device using the semiconductor device described in the above embodiment. The semiconductor device described in the above embodiment can be used in various electronic devices (for example, Terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video playback devices, and navigation systems. Here, the computer refers to a tablet computer, a notebook computer, or This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device according to the above embodiment may be used in a memory card (for example, D card), USB memory, SSD (Solid State Drive) and other removable media This is applied to removable storage devices. Figure 26 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. It is processed into a flash memory and used in various storage devices and removable memory.

[0402] 26A is a schematic diagram of a USB memory. The USB memory 1100 is a housing 1101. 1102, a USB connector 1103, and a substrate 1104. 4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110 5, controller chip 1106 is attached. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 105 or the like.

[0403] Figure 26(B) is a schematic diagram of the external appearance of an SD card, and Figure 26(C) is a schematic diagram of the internal structure of an SD card. The SD card 1110 is a schematic diagram of the structure. The SD card 1110 comprises a housing 1111, a connector 1112, and a base. The substrate 1113 is housed in a housing 1111. For example, 13 has a memory chip 1114 and a controller chip 1115 attached thereto. By providing a memory chip 1114 on the back side of the substrate 1113, the SD card 1110 The capacity can be increased. In addition, a wireless chip having a wireless communication function can be installed on the substrate 1113. This allows the host device and the SD card 1110 to communicate wirelessly. This allows data to be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be incorporated into the chip 1114 or the like.

[0404] FIG. 26(D) is a schematic diagram of the external appearance of the SSD, and FIG. 26(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a board 1153. The substrate 1153 is housed in the housing 1151. For example, the substrate 1153 has a memory The memory chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DRAM chip may be used. A memory chip 1154 is also provided on the back side of the substrate 1153. By providing the memory chip 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the chip 1154 or the like. [Explanation of symbols]

[0405] 10 memory cells 10a memory cell 10b memory cell 10c memory cell 11 Transistor 12 transistors 12a transistor 12b transistor 12c transistor 14 Capacitor element 14b Capacitor element 14c Capacitor 20 memory cell strings 24 transistors 30 Two-dimensional memory cell array 40 3D Memory Cell Array 50 Selective transistor array 51 Drive circuit 52 circuits 53 Drive circuit 54 Drive circuit 60 Select transistor cell 61 Transistor 62 transistors 101 Insulator 102 Conductors 103 Insulator 104 Insulator 105 Insulator 106 Insulator 106a Insulator 106b Semiconductors 106c Insulator 106d Insulator 107 Insulators 108 Conductors 108a Conductor 108b Conductor 109a Low resistance area 109b Low resistance region 112 Insulator 112a Insulator 114 Conductors 114a Conductor 116 Insulator 117 Insulators 118 Insulator 118a Insulator 119 Insulator 120 Conductors 122 Conductors 126a Insulator 126b Semiconductors 128 Conductors 132 Insulator 134 Semiconductors 134a area 134b area 136 Insulator 137 Insulators 138 Insulator 150 Semiconductor substrate 154a Conductor 154b Conductor 160 areas 162a Insulator 162b Insulator 164 Insulators 166 Insulators 168 Insulator 170 Insulators 171 Aperture 172a area 172b area 172c area 172d area 174a Conductors 174b Conductors 176a Conductor 176b Conductor 178a Electric conductor 178b Conductor 178c conductor 178d conductor 180a Conductor 180b conductor 180c conductor 180d conductor 181a aperture 181b aperture 1100 USB memory 1101 Case 1102 Cap 1103 USB connector 1104 Circuit Board 1105 memory chip 1106 controller chip 1110 SD card 1111 Case 1112 Connector 1113 PCB 1114 memory chip 1115 controller chip 1150 SSD 1151 Case 1152 Connector 1153 PCB 1154 memory chip 1155 memory chip 1156 controller chip

Claims

1. having a memory cell above a substrate; the memory cell includes a first transistor, a second transistor, and a capacitance element; the first transistor includes a cylindrical semiconductor having a height in a direction perpendicular to an upper surface of the substrate and a first conductive layer; the cylindrical semiconductor has a channel forming region; the first conductive layer has a function as a gate electrode of the first transistor, a function as one of electrodes of the capacitor, and a function as one of a source electrode and a drain electrode of the second transistor; the second transistor includes an oxide semiconductor layer, an insulating layer, and a second conductive layer; the oxide semiconductor layer has a channel formation region, the insulating layer has a region located above the oxide semiconductor layer and functions as a gate insulating layer of the second transistor; the second conductive layer functions as a gate electrode of the second transistor, the first conductive layer has a region in contact with the oxide semiconductor layer through an opening provided in the insulating layer.

2. In claim 1, the second transistor has a third conductive layer; the third conductive layer has a region functioning as the other of the source electrode and the drain electrode, The semiconductor device, wherein the third conductive layer has a region in contact with a cylindrical conductor having a height in a direction perpendicular to the upper surface of the substrate.

Images